JP2004134493A - Ceramic circuit board - Google Patents

Ceramic circuit board Download PDF

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Publication number
JP2004134493A
JP2004134493A JP2002295937A JP2002295937A JP2004134493A JP 2004134493 A JP2004134493 A JP 2004134493A JP 2002295937 A JP2002295937 A JP 2002295937A JP 2002295937 A JP2002295937 A JP 2002295937A JP 2004134493 A JP2004134493 A JP 2004134493A
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JP
Japan
Prior art keywords
metal
ceramic
circuit board
layer
metal circuit
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JP2002295937A
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Japanese (ja)
Inventor
Norio Nakayama
中山 憲隆
Takao Shirai
白井 隆雄
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Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2002295937A priority Critical patent/JP2004134493A/en
Publication of JP2004134493A publication Critical patent/JP2004134493A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic circuit board which is capable of markedly increasing a metal circuit layer in wiring density and current-carrying capacity and improving the functions and reliability of a high-power transistor, a power module, and a semiconductor device. <P>SOLUTION: The ceramic circuit board 1a composed of a ceramic board 2 and the metal circuit layer 4 bonded on the surface of the ceramic board 2 in one piece, is characterized in that, if the width and height of the metal circuit layer 4 are represented by W and H, respectively, the aspect ratio or the H/W ratio of the metal circuit layer 4 is 1 or more 1. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、主として高出力トランジスタやパワーモジュール等の実装に使用されたり、半導体装置に搭載されるセラミックス回路基板に係り、特に金属回路層による配線密度を高め通電容量を大幅に増大させることが可能であり、高出力トランジスタやパワーモジュール、半導体装置の機能および信頼性を向上させることが可能なセラミックス回路基板に関する。
【0002】
【従来の技術】
従来からアルミナ(Al)焼結体などのように絶縁性に優れたセラミックス基板の表面に、導電性を有する銅などの金属回路板をろう材や接着剤やメタライズ金属層で一体に接合したセラミックス回路基板がパワートランジスターモジュール用基板やスイッチング電源モジュール用基板として広く普及している。
【0003】
しかしながら上記セラミックス回路基板においては、金属回路板とセラミックス基板との間に、Ti,Zr,Hfなどの活性金属を含有するろう材や接着剤やメタライズ層のような介在物が存在するため、両者間の熱抵抗が大きくなり、金属回路板上に設けられた半導体素子の発熱を系外に迅速に放熱させることが困難であるという短所があった。
【0004】
このような問題点を解消するため、近年、上記ろう材や接着剤やメタライズ層を使用せずに、所定形状に打ち抜いた金属回路板をセラミックス基板上に接触配置させて加熱するだけで直接接合する方法も普及している。具体的には、セラミックス基板とCu板とを直接接合するDBC法(Direct Bonding Copper法)やセラミックス基板とAl板とを直接接合するDBA法(Direct Bonding Aluminum法)が採用されている。
【0005】
すなわち、直接接合法は、セラミックスと金属板とを、ろう材層や接着剤層やメタライズ層などの接合層を介在させずに直接的に接合する方法である。この直接接合法では金属中あるいは金属表面に存在する結合剤(銅の場合は酸素)と金属との共晶液相が生成されて両部材が直接的に接合される。
【0006】
また前記のように、金属回路板とセラミックス基板との間に、Ti,Zr,Hfなどの活性金属を含有するろう材層を形成し、このろう材層を介して金属回路板とセラミックス基板とを一体に接合する活性金属法も多用されており、優れた接合強度を実現している。
【0007】
図2は従来のセラミックス回路基板1の構成例を示す断面図である。セラミックス基板2の材質としては、アルミナ(Al),ジルコニア(ZrO),ムライト等の酸化物系セラミックス焼結体や窒化アルミニウム(AlN)などの窒化物系焼結体が使用される。図2は結合剤としての酸素を含有しない銅からなる金属回路板3をAl基板2の表面に直接接合したセラミックス回路基板1を示す。
【0008】
このセラミックス回路基板1をパワーモジュールとして使用する場合には、Al基板2の表面側に金属回路板3としての銅回路板が直接接合される一方、背面側に裏銅板としての銅板も同様に直接接合され、さらに表面側の銅回路板3の所定位置に図示しない半田層を介して半導体素子が一体に接合された構造を形成する。
【0009】
なお、上記直接接合法(DBC法)は、Alなどの酸化物系セラミックスについてのみ直接適用可能であり、窒化アルミニウム(AlN)基板や窒化けい素(Si)基板などの非酸化物系セラミックス基板にそのまま適用しても、基板に対する濡れ性が低いため、金属回路板の充分な接合強度が得られない。
【0010】
そこで、非酸化物系セラミックス基板を使用する場合には、予めセラミックス基板表面に酸化物層を形成し、基板に対する濡れ性を高める必要がある。この場合、金属回路板の接合操作前に、予めAlN基板を酸化性雰囲気中で加熱処理することにより、AlN基板の全表面に酸化物層(Al皮膜)が形成される。
【0011】
上記直接接合法により金属回路板をセラミックス基板に接合したセラミックス回路基板によれば、接合界面部にろう材や接着剤層が介在しないため、両部材間の熱抵抗が小さく放熱姓に優れた回路基板が得られる。また、セラミックスと金属との間にMo板等を介在させないような単純構造であるため、小型高実装化が可能であり、さらに作業工程も短縮できる等の長所を有している。
【0012】
また金属板を回路状に形成して金属回路板とする方法としては、前記のように、接合前にパンチングプレス等で金属板を所定形状に打ち抜いて回路形成する方法や金属板をセラミックス基板に接合後にエッチング処理することにより回路形成する方法が一般的に採用されている。
【0013】
【発明が解決しようとする課題】
近年になって、高出力トランジスタ、パワーモジュールや半導体装置の高出力化,高機能化,高信頼性化,小型化を求める技術的要請はさらに高まり、以前に増してより通電容量が高く、高精細な回路パターンを有するセラミックス回路基板の需要が大幅に増大している。
【0014】
しかしながら、上記従来のセラミックス回路基板において、金属板とセラミックス基板とを接合する前に金属板に回路形成し、調製した微細な金属回路板をセラミックス基板に接合する場合には、所定の回路パターンの形状を維持しながら多数の微細な金属回路板をセラミックス基板の所定位置に安定した状態で接合することが極めて困難であった。特に金属回路板の幅に対する高さの比で定義されるアスペクト比が1以上であるような幅に比べて高さが高い金属回路層を安定的にかつ高い位置精度で正確に接合することは実質上不可能であった。
【0015】
一方、金属板をセラミックス基板に接合した後にエッチング法により回路形成する場合においては、金属板の厚さ方向のみならず水平方向も同時にエッチング液の侵食を受けるため、形成できる金属回路層の高さが制限されることになる。つまり、金属板の厚さが0.5mmであれば、隣接する金属回路層の隙間(ピッチ)も0.5mmと荒くなり、精細な金属回路層は形成できない。特に金属回路層の幅に対する高さの比で定義されるアスペクト比が1以上であるような幅に比べて高さが高い金属回路層を高い形状精度で調製することは全く不可能であった。
【0016】
そのため、従来のセラミックス回路基板においては、図2に示すように各金属回路板3,3の断面形状は、セラミックス基板2の平面方向に延びる幅を有する形状に限定されてしまうため、特に金属回路板3の幅Wに対する高さHの比で定義されるアスペクト比が1以上であるような幅Wに比べて高さHが大きい金属回路層を形成することは不可能であり、上記アスペクト比は概略0.01から0.8程度の範囲であった。具体的に最小幅の金属回路板の幅寸法Wは0.5mm程度であり、高さ寸法Hは0.3mm程度でアスペクト比が0.6程度で最大値になっているものが大部分である。その結果、セラミックス基板の単位表面積あたりに形成できる金属回路層は少なく配線密度の向上が困難であり、また通電容量を増大させて半導体装置の高出力化、高機能化および小型化を図ることが困難であるという問題点があった。
【0017】
本発明は上記問題点を解決するために成されたものであり、特に金属回路層による配線密度を高め通電容量を大幅に増大させることが可能であり、高出力トランジスタやパワーモジュール、半導体装置の機能および信頼性を向上させることが可能なセラミックス回路基板を提供することを目的とする。
【0018】
【課題を解決するための手段】
上記目的を達成するため、本発明者らは微細な回路幅と十分な高さを有する金属回路層を高精度で安定した状態で形成する方法を鋭意検討した。その結果、セラミックス基板上に所定の回路パターンに沿って金属ろう材層を形成した後、さらにセラミックス基板全面にレジストを厚く塗布し、回路パターンに相当する部位のレジストを除去し、この除去した部位に金属めっきを電鋳法で施工したときに、幅に対する高さの比(アスペクト比)が高いファインピッチの金属回路層が高い形状精度で安定した状態で初めて形成できるという知見を得た。
【0019】
本発明は上記知見に基づいて完成されたものである。すなわち、本発明に係るセラミックス回路基板は、セラミックス基板の少なくとも一方の表面上に金属回路層を一体に接合したセラミックス回路基板において、上記金属回路層の幅に対する高さの比であるアスペクト比が1以上であることを特徴とする。
【0020】
上記金属回路層の幅に対する高さの比であるアスペクト比が1未満である場合にはセラミックス基板の単位面積当たりにおける金属回路層の配置数が少なくなり、配線密度を十分に高めることが困難になる。上記アスペクト比を大きくするほど金属回路層の断面積を大きくでき通電容量を高めることが可能になる。
【0021】
しかしながら、過度にアスペクト比を高めると金属回路層の構造強度が低下しやすいため、金属回路層の幅寸法によっても異なるが上記アスペクト比は5以下とされる。より好ましいアスペクト比は1.2〜2.5の範囲である。具体的に金属回路層の幅寸法Wは0.3〜0.5mmの範囲が好適である一方、金属回路層の高さ寸法Hは1〜1.5mmの範囲が好適である。
【0022】
また上記セラミックス回路基板において、前記金属回路層が銅またはアルミニウムから成ることが好ましい。すなわち、上記金属回路層を構成する金属としては、銅,アルミニウム,鉄,ニッケル,クロム,銀,モリブデン,コバルトの単体またはその合金など、金属ろう材層との濡れ性が良好であり、めっき法を適用できる金属であれば特に限定されないが、特に導電性および価格の観点から銅,アルミニウムまたはその合金が好ましい。
【0023】
さらに上記セラミックス回路基板において、前記金属回路層とセラミックス基板との間に、Ag,Cu,TiおよびZrの少なくとも1種を含有する金属ろう材層を設け、この金属ろう材層を介して上記金属回路層とセラミックス基板とを一体に接合することが好ましい。上記金属ろう材層により金属回路層とセラミックス基板との接合強度を高めることが可能であり、耐久性および信頼性に優れたセラミックス回路基板が得られる。
【0024】
上記のような活性金属法による接合法は、例えばTi,Zr,Hf,Nb等から選択された少なくとも1種の活性金属を含む金属ろう材層を介して、セラミックス基板と金属回路層とを接合する方法である。用いる活性金属含有ろう材の組成としては、例えばAg−Cuの共晶組成(72wt%Ag−28wt%Cu)もしくはその近傍組成のAg−Cu系ろう材やCu系ろう材を主体とし、これに1〜10重量%のTi,Zr,Hf,Nb等から選択された少なくとも1種の活性金属を添加した組成等が例示できる。なお、活性金属含有ろう材にInのような低融点金属を添加して用いることもできる。
【0025】
さらに上記セラミックス回路基板において、前記セラミックス基板が窒化アルミニウム,窒化けい素,アルミナおよびアルミナとジルコニアとの化合物(通称:アルジル)のいずれかから構成されていることが好ましい。
【0026】
すなわち本発明に係るセラミックス回路基板に使用されるセラミックス基板としては、特に限定されるものではなく、回路基板に要求される強度、放熱性(熱伝導率),誘電率,破壊電圧等の電気的特性に応じて選択される。具体的には、酸化アルミニウム(アルミナ:Al)等の酸化物系セラミックス基板の他に、窒化アルミニウム(AlN),窒化けい素(Si),窒化チタン(TiN)等の窒化物、炭化けい素(SiC),炭化チタン(TiC)等の炭化物、またはほう化ランタン等のほう化物等の非酸化物系セラミックス基板でもよい。これらのセラミックス基板には酸化イットリウムなどの焼結助剤等が含有されていてもよい。
【0027】
また上記セラミックス回路基板において、前記金属回路層の表面上に、Ni,AgおよびAuの少なくとも1種からなるめっき層を形成することが好ましい。上記めっき層の厚さは1〜5μm程度で十分である。上記めっき層を形成することにより、金属回路層の耐食性を大幅に高めることができ、セラミックス回路基板の耐久性および信頼性を大幅に改善することができる。
【0028】
本発明に係るセラミックス回路基板は、例えば以下の手順で製造することができる。すなわち、まずセラミックス基板表面上に金属ろう材ペーストをスクリーン印刷法等により印刷し、セラミックス基板上に所定の回路パターン状の金属ろう材層を形成する。
【0029】
ここで金属ろう材層のセラミックス基板に対する接合強度を高めるために、印刷されたろう材の接合条件に合った条件、すなわち温度700〜900℃で10分間〜1時間程度の熱処理を実施すると良い。なお、この金属ろう材層を当初セラミックス基板の全面に形成しておき、金属回路層を形成した後に回路パターン以外のろう材層を除去しても良い。
【0030】
次に、最終的に形成される金属回路層の厚さ以上の厚さとなるようにセラミックス基板表面にフォトレジストを塗布しレジスト膜を形成する。しかる後に、フォト・リソグラフィー法等により、金属回路層形成部位のレジスト膜を除去し配線パターンに沿った空隙部を形成する。この時、レジスト膜表面方向から空隙部の底部に形成した金属ろう材層が直接観察できるように、空隙部の幅よりも深さが大きい配線パターン状の空隙部を形成する。
【0031】
次に、金属ろう材層を構成する金属に対して良好な濡れ性を有する金属を、上記空隙部にめっき法により所定厚さまで堆積充填せしめて金属回路層を形成する。しかる後に、金属回路層以外の部位に残留していたレジスト膜を剥離溶解液で除去することにより、幅に対する高さの比(アスペクト比)が高く形状精度に優れた金属回路層が一体に接合したセラミックス回路基板が安定した状態で製造することが可能になる。
【0032】
上記構成に係るセラミックス回路基板によれば、幅に対する高さの比(アスペクト比)が高い金属回路層が高い形状精度で安定した状態で形成されているため、セラミックス基板上における金属回路層の配線密度を高めることができ、高精細な金属回路層にもかかわらず通電容量を大幅に増大させることが可能であり、高出力トランジスタやパワーモジュール、半導体装置の機能および信頼性を向上させることが可能になる。
【0033】
【発明の実施の形態】
次に本発明に係るセラミックス回路基板の実施形態について添付図面を参照して具体的に説明する。
【0034】
図3(a)に示すように、厚さ0.635mmのアルミナ(Al)基板,窒化けい素(Si)基板,厚さ0.9mmの窒化アルミニウム(AlN)基板,厚さ0.9mmのアルミナ−ジルコニア化合物基板をセラミックス基板2として用意し、各セラミックス基板2表面にスクリーン印刷法を使用してろう材ペーストを印刷して、図3(b)に示すように、幅が0.2mmである所定の回路状パターンを有する金属ろう材層5を形成した。なお、上記ろう材ペーストとしてはBAg−18(Ag/Cu/Sn系ろう材)組成を適用した。
【0035】
さらに、ろう材ペーストを印刷した各セラミックス基板2を、真空度1×10−4Tоrr以下の加熱炉内において温度800℃で15分間熱処理を実施することにより、各金属ろう材層5のセラミックス基板2に対する接合強度を高めた。
【0036】
この後、図3(c)に示すように、金属ろう材層5を形成したセラミックス基板2表面に、紫外線硬化型のフォトレジストを塗布することにより、厚さ0.5mmのフォトレジスト膜6を形成した。次に、上記回路状パターン以外の部位については所望の配線パターン形状に応じて選択的に紫外線照射を実施して照射部のレジスト膜を硬化せしめる一方、上記配線パターン部分のレジスト膜については所定の洗浄液で洗浄することにより、図3(d)に示すように、配線パターンに沿った空隙部7を形成した。
【0037】
次に、上記空隙部7を形成したセラミックス基板に対して電気めっき処理を実施することにより、図3(e)に示すように、フォトレジスト膜6の厚さ(0.5mm)に相当する高さHを有する金属回路層(銅回路層)4を形成した。しかる後に、図3(f)に示すように、硬化済みのレジスト膜6を所定の剥離液で洗浄して除去した。さらに、上記金属回路層(銅回路層)4の配線パターン以外の基板表面に残留していた金属ろう材層5を溶解除去することにより、図3(g)に示すような幅が0.2mmであり高さが0.5mmである金属回路層4を有する各実施例に係るセラミックス回路基板1aをそれぞれ調製した。
【0038】
また上記実施例以外に金属回路層の幅Wを0.3〜0.5mmの範囲および高さを1〜1.5mmの範囲に変更した以外は上記実施例と同様な条件で処理することにより、それぞれの各実施例に係る多数のセラミックス回路基板1aを調製した。
【0039】
上記のように調製した各実施例に係るセラミックス回路基板1aは、図1に示すように、各セラミックス基板2の上面側に多数の精細な金属回路層4が一体に接合され、各金属回路層4の断面形状は、幅Wが0.3〜0.5mmの範囲であり高さHが1〜1.5mmの範囲であるため、アスペクト比は2〜5の範囲となった。
【0040】
一方、比較例として図2に示すような従来のセラミックス回路基板1を調製した。すなわち、各実施例で用いたセラミックス基板2と同一寸法のアルミナ基板表面に厚さ0.3mmの銅回路板を金属回路板3としてDBC法により直接接合し、さらに最小となる配線パターンの断面の幅Wが0.5mmで高さが0.3mm(アスペクト比は0.6以下)となるようにパターン形成した
こうして同一サイズのセラミックス基板を使用して調製した各実施例および比較例に係るセラミックス回路基板について、配線密度および通電容量を比較したところ、各実施例に係るセラミックス回路基板の配線密度は比較例と比べて2.1倍から3.5倍に増加した。また、通電容量は比較例と比べて2.5倍から4.7倍に増加した。
【0041】
但し、各実施例に係るセラミックス回路基板においても、金属回路層4の幅Wに対する高さHの比であるアスペクト比が2.5から5近くに達すると、金属回路層4の構造強度が低下し、変形が生じ易くなるため、上記金属回路層4のアスペクト比は1.0〜2.2の範囲が好適であった。
【0042】
なお、各実施例では隣接する金属回路層の配設ピッチは50〜250μmと微細にできるが、比較例での配設ピッチは0.3mmと粗大であった。
【0043】
このように各実施例においては、セラミックス基板上に回路パターン状の金属ろう材層を形成後、フォトレジスト塗布を実施して精細な回路パターンを形成し、回路パターンに沿って金属めっきを施すことで金属回路層の厚さ(高さ)より小さいピッチの金属回路層を有するセラミックス回路基板を実現することが可能になった。この結果、従来比で配線密度が2倍以上になり、高出力トランジスタ、パワーモジュール、半導体装置の高機能化が達成でき、さらに信頼性を向上させることができた。
【0044】
また各実施例のセラミックス回路基板の金属回路層4に無電解めっき法によって、Ni,Ag,Auの少なくとも1種のめっき層(図示せず)を厚さ2〜6μmの範囲で形成することにより、耐食性を向上させることができた。
【0045】
【発明の効果】
以上説明の通り、本発明に係るセラミックス回路基板によれば、幅に対する高さの比(アスペクト比)が高い金属回路層が高い形状精度で安定した状態で形成されているため、セラミックス基板上における金属回路層の配線密度を高めることができ、高精細な金属回路層にもかかわらず通電容量を大幅に増大させることが可能であり、高出力トランジスタやパワーモジュール、半導体装置の機能および信頼性を向上させることが可能になる。
【図面の簡単な説明】
【図1】本発明に係るセラミックス回路基板の一実施例の構成例を示す断面図。
【図2】従来のセラミックス回路基板の構成例を示す断面図。
【図3】本発明に係るセラミックス回路基板の製造工程を示す断面図であり、(a)はセラミックス基板を示し、(b)は金属ろう材層を形成した状態を示し、(c)はフォトレジスト膜を形成した状態を示し、(d)は回路パターンに沿ったフォトレジスト膜を除去した状態を示し、(e)はフォトレジスト膜を除去した部位に金属めっき層を堆積充填した状態を示し、(f)は回路パターン以外の部位のフォトレジスト膜を除去した状態を示し、(g)は残留した金属ろう材層を除去した状態を示す断面図。
【符号の説明】
1,1a,1b セラミックス回路基板
2 セラミックス基板(Al基板,Si基板,AlN基板,アルミナ−ジルコニア化合物基板)
3 金属回路板(銅回路板)
4 金属回路層(銅回路層)
5 金属ろう材層
6 フォトレジスト膜
7 空隙部
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ceramic circuit board mainly used for mounting a high-output transistor or a power module or mounted on a semiconductor device. In particular, it is possible to increase a wiring density by a metal circuit layer and greatly increase a current carrying capacity. And a ceramic circuit board capable of improving the function and reliability of a high-output transistor, a power module, and a semiconductor device.
[0002]
[Prior art]
Conventionally, a metal circuit board made of conductive copper or the like is integrally formed on a surface of a ceramic substrate having excellent insulation properties, such as an alumina (Al 2 O 3 ) sintered body, with a brazing material, an adhesive, or a metallized metal layer. A bonded ceramic circuit board is widely used as a substrate for a power transistor module or a substrate for a switching power supply module.
[0003]
However, in the above-mentioned ceramic circuit board, since a brazing material containing an active metal such as Ti, Zr, and Hf, an intervening agent such as an adhesive or a metallized layer exists between the metal circuit board and the ceramic substrate, both of them are present. However, there is a disadvantage that it is difficult to quickly radiate the heat generated by the semiconductor element provided on the metal circuit board to the outside of the system due to a large thermal resistance between them.
[0004]
In order to solve such problems, in recent years, without using the above-mentioned brazing material, adhesive or metallized layer, a metal circuit board punched into a predetermined shape is directly placed on a ceramic substrate, and is directly heated only by heating. The way to do it is also widespread. Specifically, a DBC method (Direct Bonding Copper method) for directly joining a ceramic substrate and a Cu plate, and a DBA method (Direct Bonding Aluminum method) for directly joining a ceramic substrate and an Al plate are employed.
[0005]
That is, the direct joining method is a method of directly joining ceramics and a metal plate without interposing a joining layer such as a brazing material layer, an adhesive layer, or a metallized layer. In this direct joining method, a eutectic liquid phase of a binder (oxygen in the case of copper) existing in the metal or on the surface of the metal and the metal is generated, and the two members are directly joined.
[0006]
Further, as described above, a brazing material layer containing an active metal such as Ti, Zr, or Hf is formed between the metal circuit board and the ceramic substrate, and the metal circuit board and the ceramic substrate are interposed via the brazing material layer. The active metal method of joining together is often used, and achieves excellent joining strength.
[0007]
FIG. 2 is a cross-sectional view showing a configuration example of a conventional ceramic circuit board 1. As a material of the ceramic substrate 2, an oxide ceramic sintered body such as alumina (Al 2 O 3 ), zirconia (ZrO 2 ), mullite, or a nitride sintered body such as aluminum nitride (AlN) is used. . FIG. 2 shows a ceramic circuit board 1 in which a metal circuit board 3 made of copper containing no oxygen as a binder is directly bonded to the surface of an Al 2 O 3 substrate 2.
[0008]
When this ceramic circuit board 1 is used as a power module, a copper circuit board as a metal circuit board 3 is directly bonded to the surface side of the Al 2 O 3 substrate 2, while a copper plate as a back copper plate is also provided on the back side. Similarly, a structure is formed in which the semiconductor elements are directly joined, and the semiconductor elements are integrally joined at predetermined positions of the copper circuit board 3 on the front side via a solder layer (not shown).
[0009]
Note that the direct bonding method (DBC method) can be directly applied only to oxide-based ceramics such as Al 2 O 3 , and is not applicable to aluminum nitride (AlN) substrates and silicon nitride (Si 3 N 4 ) substrates. Even when applied directly to an oxide-based ceramic substrate, sufficient bonding strength of the metal circuit board cannot be obtained due to low wettability to the substrate.
[0010]
Therefore, when a non-oxide ceramic substrate is used, it is necessary to form an oxide layer on the surface of the ceramic substrate in advance to enhance wettability to the substrate. In this case, an oxide layer (Al 2 O 3 film) is formed on the entire surface of the AlN substrate by subjecting the AlN substrate to heat treatment in an oxidizing atmosphere in advance before the bonding operation of the metal circuit board.
[0011]
According to the ceramic circuit board in which the metal circuit board is joined to the ceramic substrate by the above direct joining method, since the brazing material or the adhesive layer is not interposed at the joint interface, the heat resistance between both members is small, and the circuit has excellent heat dissipation. A substrate is obtained. In addition, since it has a simple structure in which a Mo plate or the like is not interposed between ceramics and metal, it has advantages that a small size and high mounting can be achieved, and that a work process can be shortened.
[0012]
In addition, as a method of forming a metal plate into a circuit shape to form a metal circuit board, as described above, a method of forming a circuit by punching a metal plate into a predetermined shape by a punching press or the like before joining or a method of forming a metal plate on a ceramic substrate A method of forming a circuit by performing an etching process after joining is generally adopted.
[0013]
[Problems to be solved by the invention]
In recent years, technical demands for higher output, higher function, higher reliability, and smaller size of high output transistors, power modules and semiconductor devices have been further increased, and the current carrying capacity is higher than before. The demand for ceramic circuit boards having fine circuit patterns has increased significantly.
[0014]
However, in the above-mentioned conventional ceramic circuit board, when a circuit is formed on the metal plate before the metal plate and the ceramic substrate are joined, and the prepared fine metal circuit board is joined to the ceramic substrate, a predetermined circuit pattern is formed. It has been extremely difficult to stably join a large number of fine metal circuit boards to predetermined positions on a ceramic substrate while maintaining the shape. In particular, it is necessary to stably and accurately join a metal circuit layer having a height higher than a width such that an aspect ratio defined by a ratio of a height to a width of the metal circuit board is 1 or more, with high positional accuracy. It was virtually impossible.
[0015]
On the other hand, when a circuit is formed by an etching method after joining a metal plate to a ceramic substrate, the etching liquid is simultaneously eroded not only in the thickness direction of the metal plate but also in the horizontal direction. Will be limited. That is, if the thickness of the metal plate is 0.5 mm, the gap (pitch) between adjacent metal circuit layers becomes as rough as 0.5 mm, and a fine metal circuit layer cannot be formed. In particular, it has been impossible at all to prepare a metal circuit layer having a high height with a high shape precision as compared with a width having an aspect ratio defined by a ratio of the height to the width of the metal circuit layer of 1 or more. .
[0016]
Therefore, in the conventional ceramic circuit board, as shown in FIG. 2, the cross-sectional shape of each of the metal circuit boards 3 is limited to a shape having a width extending in the plane direction of the ceramic substrate 2, so that the metal circuit It is impossible to form a metal circuit layer having a height H larger than the width W such that the aspect ratio defined by the ratio of the height H to the width W of the plate 3 is 1 or more. Was in the range of approximately 0.01 to 0.8. Specifically, the width W of the metal circuit board having the minimum width is about 0.5 mm, the height H is about 0.3 mm, the aspect ratio is about 0.6, and most of those have the maximum value. is there. As a result, the number of metal circuit layers that can be formed per unit surface area of the ceramic substrate is small, making it difficult to improve the wiring density. In addition, by increasing the current carrying capacity, it is possible to achieve higher output, higher function, and smaller size of the semiconductor device. There was a problem that it was difficult.
[0017]
The present invention has been made in order to solve the above problems, and in particular, it is possible to increase the wiring density by a metal circuit layer and greatly increase a current carrying capacity, and to provide a high output transistor, a power module, and a semiconductor device. It is an object of the present invention to provide a ceramic circuit board capable of improving function and reliability.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, the present inventors diligently studied a method of forming a metal circuit layer having a fine circuit width and a sufficient height in a stable state with high accuracy. As a result, after forming a brazing metal layer along a predetermined circuit pattern on the ceramic substrate, a thick resist is further applied on the entire surface of the ceramic substrate, and the resist corresponding to the circuit pattern is removed. It has been found that, when metal plating is applied by electroforming, a fine pitch metal circuit layer having a high height to width ratio (aspect ratio) can be formed in a stable state with high shape accuracy for the first time.
[0019]
The present invention has been completed based on the above findings. That is, in the ceramic circuit board according to the present invention, in a ceramic circuit board in which a metal circuit layer is integrally joined on at least one surface of the ceramic substrate, an aspect ratio which is a ratio of a height to a width of the metal circuit layer is 1 It is characterized by the above.
[0020]
When the aspect ratio, which is the ratio of the height to the width of the metal circuit layer, is less than 1, the number of metal circuit layers arranged per unit area of the ceramic substrate is reduced, and it is difficult to sufficiently increase the wiring density. Become. As the aspect ratio is increased, the cross-sectional area of the metal circuit layer can be increased and the conduction capacity can be increased.
[0021]
However, if the aspect ratio is excessively increased, the structural strength of the metal circuit layer is apt to decrease. Therefore, the aspect ratio is set to 5 or less, though it depends on the width of the metal circuit layer. A more preferred aspect ratio is in the range of 1.2 to 2.5. Specifically, the width W of the metal circuit layer is preferably in the range of 0.3 to 0.5 mm, while the height H of the metal circuit layer is preferably in the range of 1 to 1.5 mm.
[0022]
In the ceramic circuit board, it is preferable that the metal circuit layer is made of copper or aluminum. That is, the metal constituting the metal circuit layer has a good wettability with a brazing metal layer such as a simple substance of copper, aluminum, iron, nickel, chromium, silver, molybdenum, and cobalt, or an alloy thereof. The metal is not particularly limited as long as it can be applied, but copper, aluminum or an alloy thereof is particularly preferable from the viewpoints of conductivity and cost.
[0023]
Further, in the ceramic circuit board, a metal brazing layer containing at least one of Ag, Cu, Ti and Zr is provided between the metal circuit layer and the ceramic substrate, and the metal brazing layer is interposed through the metal brazing layer. It is preferable that the circuit layer and the ceramic substrate are integrally joined. The bonding strength between the metal circuit layer and the ceramic substrate can be increased by the metal brazing material layer, and a ceramic circuit substrate having excellent durability and reliability can be obtained.
[0024]
The joining method using the active metal method as described above joins a ceramic substrate and a metal circuit layer via a metal brazing material layer containing at least one active metal selected from, for example, Ti, Zr, Hf, and Nb. How to As the composition of the active metal-containing brazing material to be used, for example, an Ag-Cu eutectic composition (72 wt% Ag-28 wt% Cu) or a composition in the vicinity thereof is mainly composed of an Ag-Cu brazing material or a Cu brazing material. A composition in which at least one active metal selected from Ti, Zr, Hf, Nb and the like is added in an amount of 1 to 10% by weight can be exemplified. In addition, a low melting point metal such as In may be added to the active metal-containing brazing material.
[0025]
Further, in the above-mentioned ceramic circuit board, it is preferable that the ceramic board is made of any one of aluminum nitride, silicon nitride, alumina, and a compound of alumina and zirconia (commonly called argyl).
[0026]
That is, the ceramic substrate used for the ceramic circuit board according to the present invention is not particularly limited, and electrical strength such as strength, heat dissipation (thermal conductivity), dielectric constant, and breakdown voltage required for the circuit board is required. It is selected according to the characteristics. Specifically, in addition to an oxide-based ceramic substrate such as aluminum oxide (alumina: Al 2 O 3 ), a nitride such as aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), titanium nitride (TiN), etc. Or a non-oxide ceramic substrate such as a carbide such as silicon carbide (SiC) or titanium carbide (TiC), or a boride such as lanthanum boride. These ceramic substrates may contain a sintering aid such as yttrium oxide.
[0027]
In the ceramic circuit board, it is preferable that a plating layer made of at least one of Ni, Ag and Au is formed on the surface of the metal circuit layer. It is sufficient that the thickness of the plating layer is about 1 to 5 μm. By forming the plating layer, the corrosion resistance of the metal circuit layer can be greatly increased, and the durability and reliability of the ceramic circuit board can be greatly improved.
[0028]
The ceramic circuit board according to the present invention can be manufactured, for example, by the following procedure. That is, first, a metal brazing material paste is printed on the surface of the ceramic substrate by a screen printing method or the like, and a metal brazing material layer having a predetermined circuit pattern is formed on the ceramic substrate.
[0029]
Here, in order to increase the bonding strength of the metal brazing material layer to the ceramic substrate, it is preferable to perform a heat treatment at a temperature suitable for the bonding condition of the printed brazing material, that is, at a temperature of 700 to 900 ° C. for about 10 minutes to 1 hour. This brazing material layer may be formed on the entire surface of the ceramic substrate at first, and after forming the metal circuit layer, the brazing material layer other than the circuit pattern may be removed.
[0030]
Next, a photoresist is applied to the surface of the ceramic substrate so as to have a thickness equal to or greater than the thickness of the finally formed metal circuit layer, thereby forming a resist film. Thereafter, the resist film at the portion where the metal circuit layer is to be formed is removed by photolithography or the like to form a void along the wiring pattern. At this time, a wiring pattern-like void having a depth larger than the width of the void is formed so that the metal brazing material layer formed at the bottom of the void can be directly observed from the resist film surface direction.
[0031]
Next, a metal having good wettability with respect to the metal constituting the brazing metal layer is deposited and filled to a predetermined thickness in the above-mentioned gap by plating to form a metal circuit layer. After that, the resist film remaining on the parts other than the metal circuit layer is removed with a stripping solution, so that the metal circuit layer having a high height to width ratio (aspect ratio) and excellent shape accuracy is integrally joined. The manufactured ceramic circuit board can be manufactured in a stable state.
[0032]
According to the ceramic circuit board according to the above configuration, since the metal circuit layer having a high height to width (aspect ratio) is formed in a stable state with high shape accuracy, wiring of the metal circuit layer on the ceramic substrate is performed. Density can be increased and current carrying capacity can be significantly increased despite high-definition metal circuit layers, and the function and reliability of high-output transistors, power modules, and semiconductor devices can be improved. become.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of a ceramic circuit board according to the present invention will be specifically described with reference to the accompanying drawings.
[0034]
As shown in FIG. 3A, an alumina (Al 2 O 3 ) substrate, a silicon nitride (Si 3 N 4 ) substrate having a thickness of 0.635 mm, an aluminum nitride (AlN) substrate having a thickness of 0.9 mm, An alumina-zirconia compound substrate having a thickness of 0.9 mm is prepared as the ceramic substrate 2, and a brazing material paste is printed on the surface of each ceramic substrate 2 using a screen printing method, and as shown in FIG. Is 0.2 mm, a metal brazing material layer 5 having a predetermined circuit pattern was formed. In addition, BAg-18 (Ag / Cu / Sn-based brazing material) composition was applied as the brazing material paste.
[0035]
Further, each ceramic substrate 2 on which the brazing material paste is printed is subjected to a heat treatment at a temperature of 800 ° C. for 15 minutes in a heating furnace having a degree of vacuum of 1 × 10 −4 Torr or less, so that the ceramic substrate 2 of each metal brazing material layer 5 is formed. The bonding strength for
[0036]
Thereafter, as shown in FIG. 3C, a 0.5 mm-thick photoresist film 6 is applied to the surface of the ceramic substrate 2 on which the metal brazing material layer 5 is formed by applying an ultraviolet curing photoresist. Formed. Next, the portions other than the circuit pattern are selectively irradiated with ultraviolet rays according to the desired wiring pattern shape to cure the resist film in the irradiated portion, while the resist film in the wiring pattern portion has a predetermined shape. By cleaning with a cleaning liquid, a void 7 was formed along the wiring pattern as shown in FIG.
[0037]
Next, by performing an electroplating process on the ceramic substrate on which the voids 7 are formed, as shown in FIG. 3E, a height corresponding to the thickness (0.5 mm) of the photoresist film 6 is obtained. A metal circuit layer (copper circuit layer) 4 having a height H was formed. Thereafter, as shown in FIG. 3F, the cured resist film 6 was removed by washing with a predetermined stripper. Further, by dissolving and removing the metal brazing material layer 5 remaining on the substrate surface other than the wiring pattern of the metal circuit layer (copper circuit layer) 4, the width as shown in FIG. Each of the ceramic circuit boards 1a according to the examples having the metal circuit layer 4 having a height of 0.5 mm was prepared.
[0038]
In addition to the above embodiment, the metal circuit layer was processed under the same conditions as in the above embodiment except that the width W of the metal circuit layer was changed to a range of 0.3 to 0.5 mm and the height was changed to a range of 1 to 1.5 mm. A large number of ceramic circuit boards 1a according to the respective examples were prepared.
[0039]
As shown in FIG. 1, the ceramic circuit board 1a according to each embodiment prepared as described above has a large number of fine metal circuit layers 4 integrally joined on the upper surface side of each ceramic substrate 2, and each metal circuit layer In the cross-sectional shape of No. 4, the width W was in the range of 0.3 to 0.5 mm and the height H was in the range of 1 to 1.5 mm, so that the aspect ratio was in the range of 2 to 5.
[0040]
On the other hand, a conventional ceramic circuit board 1 as shown in FIG. 2 was prepared as a comparative example. That is, a copper circuit board having a thickness of 0.3 mm is directly bonded as a metal circuit board 3 to the surface of an alumina substrate having the same dimensions as the ceramic substrate 2 used in each embodiment by the DBC method, and the cross-section of the wiring pattern which is further minimized. Ceramics according to Examples and Comparative Examples prepared using ceramic substrates of the same size, which were patterned so that width W was 0.5 mm and height was 0.3 mm (aspect ratio was 0.6 or less) When the wiring density and the current carrying capacity of the circuit board were compared, the wiring density of the ceramic circuit board according to each example increased from 2.1 times to 3.5 times as compared with the comparative example. The current carrying capacity increased from 2.5 times to 4.7 times as compared with the comparative example.
[0041]
However, also in the ceramic circuit board according to each embodiment, when the aspect ratio, which is the ratio of the height H to the width W of the metal circuit layer 4, approaches 2.5 to 5, the structural strength of the metal circuit layer 4 decreases. However, since the deformation is likely to occur, the aspect ratio of the metal circuit layer 4 is preferably in the range of 1.0 to 2.2.
[0042]
In each of the examples, the arrangement pitch of the adjacent metal circuit layers can be made as fine as 50 to 250 μm, but the arrangement pitch in the comparative example was as coarse as 0.3 mm.
[0043]
As described above, in each embodiment, after forming a metal brazing material layer having a circuit pattern on a ceramic substrate, a fine circuit pattern is formed by applying a photoresist, and metal plating is performed along the circuit pattern. Thus, a ceramic circuit board having a metal circuit layer having a pitch smaller than the thickness (height) of the metal circuit layer can be realized. As a result, the wiring density is more than doubled as compared with the related art, and high-performance transistors, power modules, and semiconductor devices can be achieved, and the reliability can be further improved.
[0044]
Further, at least one type of plating layer (not shown) of Ni, Ag, or Au is formed on the metal circuit layer 4 of the ceramic circuit board of each embodiment by an electroless plating method in a thickness of 2 to 6 μm. And the corrosion resistance could be improved.
[0045]
【The invention's effect】
As described above, according to the ceramic circuit board of the present invention, since the metal circuit layer having a high height to width (aspect ratio) is formed in a stable state with high shape accuracy, The wiring density of the metal circuit layer can be increased, and the current carrying capacity can be greatly increased despite the high-definition metal circuit layer, and the function and reliability of high-output transistors, power modules, and semiconductor devices can be improved. It can be improved.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a configuration example of one embodiment of a ceramic circuit board according to the present invention.
FIG. 2 is a cross-sectional view showing a configuration example of a conventional ceramic circuit board.
3A and 3B are cross-sectional views illustrating a process of manufacturing a ceramic circuit board according to the present invention, wherein FIG. 3A illustrates a ceramic substrate, FIG. 3B illustrates a state in which a brazing metal layer is formed, and FIG. (D) shows a state in which the photoresist film along the circuit pattern is removed, and (e) shows a state in which a metal plating layer is deposited and filled in a portion where the photoresist film has been removed. (F) is a cross-sectional view showing a state in which the photoresist film other than the circuit pattern is removed, and (g) is a state showing the state in which the remaining metal brazing material layer is removed.
[Explanation of symbols]
1, 1a, 1b Ceramic circuit substrate 2 Ceramic substrate (Al 2 O 3 substrate, Si 3 N 4 substrate, AlN substrate, alumina-zirconia compound substrate)
3 metal circuit board (copper circuit board)
4 Metal circuit layer (copper circuit layer)
5 Brazing metal layer 6 Photoresist film 7 Void

Claims (5)

セラミックス基板の少なくとも一方の表面上に金属回路層を一体に接合したセラミックス回路基板において、上記金属回路層の幅に対する高さの比であるアスペクト比が1以上であることを特徴とするセラミックス回路基板。A ceramic circuit board in which a metal circuit layer is integrally bonded on at least one surface of a ceramic substrate, wherein an aspect ratio which is a ratio of a height to a width of the metal circuit layer is 1 or more. . 請求項1記載のセラミックス回路基板において、前記金属回路層が銅またはアルミニウムから成ることを特徴とするセラミックス回路基板。2. The ceramic circuit board according to claim 1, wherein said metal circuit layer is made of copper or aluminum. 請求項1記載のセラミックス回路基板において、前記金属回路層とセラミックス基板との間に、Ag,Cu,TiおよびZrの少なくとも1種を含有する金属ろう材層を設け、この金属ろう材層を介して上記金属回路層とセラミックス基板とを一体に接合したことを特徴とするセラミックス回路基板。2. The ceramic circuit board according to claim 1, wherein a metal brazing material layer containing at least one of Ag, Cu, Ti and Zr is provided between the metal circuit layer and the ceramic substrate, and the metal brazing material layer is interposed therebetween. A ceramic circuit board, wherein the metal circuit layer and the ceramic substrate are integrally joined. 請求項1記載のセラミックス回路基板において、前記セラミックス基板が窒化アルミニウム,窒化けい素,アルミナおよびアルミナとジルコニアとの化合物のいずれかから構成されていることを特徴とするセラミックス回路基板。2. The ceramic circuit board according to claim 1, wherein said ceramic substrate is made of any one of aluminum nitride, silicon nitride, alumina, and a compound of alumina and zirconia. 請求項1記載のセラミックス回路基板において、前記金属回路層の表面上に、Ni,AgおよびAuの少なくとも1種からなるめっき層を形成したことを特徴とするセラミックス回路基板。2. The ceramic circuit board according to claim 1, wherein a plating layer made of at least one of Ni, Ag and Au is formed on the surface of the metal circuit layer.
JP2002295937A 2002-10-09 2002-10-09 Ceramic circuit board Pending JP2004134493A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013247158A (en) * 2012-05-23 2013-12-09 Denki Kagaku Kogyo Kk Ceramic circuit board
JP2016015493A (en) * 2007-08-03 2016-01-28 アルファ・メタルズ・インコーポレイテッドAlpha Metals,Inc. Methods of producing conductive patterns
CN114478022A (en) * 2021-12-31 2022-05-13 南通威斯派尔半导体技术有限公司 High-reliability aluminum nitride copper-clad ceramic substrate and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016015493A (en) * 2007-08-03 2016-01-28 アルファ・メタルズ・インコーポレイテッドAlpha Metals,Inc. Methods of producing conductive patterns
KR101913184B1 (en) 2007-08-03 2018-10-30 알파 어셈블리 솔루션스 인크. Conductive patterns and methods of using them
JP2013247158A (en) * 2012-05-23 2013-12-09 Denki Kagaku Kogyo Kk Ceramic circuit board
CN114478022A (en) * 2021-12-31 2022-05-13 南通威斯派尔半导体技术有限公司 High-reliability aluminum nitride copper-clad ceramic substrate and preparation method thereof

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