JP2004120193A - Digital receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital receiver reducing phase distortion of an analog signal produced by converting a digital audio data sequence transmitted on a radio transmission line. <P>SOLUTION: Time series digital audio signals demodulated from transmission signals are written sequentially in a first-in first-out register 36 in synchronism with their generation timing. The time series digital audio signals are read out sequentially from the register 36 in synchronism with the timing of a read signal from a numeric control oscillator 40. The numeric control oscillator 40 is controlled by a control section 42 to read out the time series digital audio signals at a quick timing if the number of writing stages of the time series digital audio signals in the shift register 36 is larger than a specified value otherwise read out the time series digital audio signals at a slow timing. The read out timing is selected such that the variation thereof becomes smaller than the variation in generation timing. The time series digital audio signals read out from the register 36 are interpolated at an interpolating section 44 to correspond with the conversion timing at a digital/analog converter 30. <P>COPYRIGHT: (C)2004,JPO

Description

によって表され、この演算をラグランジェサンプリングレートコンバータ４６が行う。
【００３０】
ここで、デジタル・アナログ変換器３０の変換タイミングにおけるデータｙを求めるためには、この変換タイミングと、各データｙ（０）乃至ｙ（ｎ）の入力タイミングｘ（０）乃至ｘ（ｎ）との位置関係を明確にする必要がある。そのため、デジタル・アナログ変換器３０に変換タイミングを与えている基準信号Ｆｓｄａｃを、基準タイミング信号発生手段、例えば逓倍手段４８によってｋ（例えば５１２のような２^ｎとなる値）倍して、ｋ＊Ｆｓｄａｃとして、位置決定部５０に供給する。なお、基準信号Ｆｓｄａｃは、基準信号源２６ａのクロック信号に基づいてタイミング供給手段２７によって生成されている。位置決定部５０には、数値制御発振器４０から読み出し信号Ｆｓｆｉｆｏが供給されており、入力される読み出し信号Ｆｓｆｉｆｏが、ｋ＊Ｆｓｄａｃを基準とした場合、どの位置に位置するかを決定し、その位置をラグランジェサンプリングレートコンバータ４６に供給する。これが上記公式のｘ［ｉ］となる。なお、基準信号Ｆｓｄａｃは、上記公式のｘとして、ラグランジェサンプリングレートコンバータ４６に供給されている。
【００３１】
図５に、Ｆｓｄａｃ、ｋ＊Ｆｓｄａｃ、Ｆｓｆｉｆｏの関係を示す。同図において、破線で示すのがｋ＊Ｆｓｄａｃで、実線で示すのがＦｓｆｉｆｏで、各Ｆｓｆｉｆｏにおいて白丸で示すのがｙ（０）乃至ｙ（ｎ）である（同図ではｎは６）。一点鎖線で示すのがＦｓｄａｃである。このようにして、ｙ（０）乃至ｙ（ｎ）のタイミングｘ（０）乃至ｘ（ｎ）とデジタル・アナログ変換器３０の変換タイミングｘとの関係が、ｋ＊Ｆｓｄａｃを基準として求められ、デジタル・アナログ変換器３０の変換タイミングが到達するごとに、補間されたデジタルオーディオデータｙが出力される。
【００３２】
この補間されたデジタルオーディオデータｙがデジタル・アナログ変換器３０によってアナログ変換され、増幅器３２によって増幅され、スピーカ３４から拡声される。
【００３３】
このように構成すると、デジタル・アナログ変換器３０における変換タイミングに一致するように補間部４４によってデジタルオーディオデータ列の各デジタルオーディオデータの補間が行われているので、位相歪みを増大させることがない。
【００３４】
サンプリングレートコンバータ４６としては、デジタルオーディオデータを、例えばＦｓｆｉｆｏの周波数とＦｓｄａｃの周波数との公倍数の周波数にオーバーサンプリングした後に、Ｆｓｄａｃの周波数にダウンサンプリングするものを使用することも考えられる。しかし、これにはオーバーサンプリング用のＦＩＲフィルタを構成するために、畳み込み演算を行う必要がある。畳み込み演算には、加算器と乗算器とシフトレジスタとが必要である。乗算器とシフトレジスタとは、フィルタの次数分だけ準備しなければならず、畳み込み演算の回路構成が複雑になる。しかも、デジタルオーディオデータを処理するためには、このＦＩＲフィルタは鋭い遮断特性が必要であり、ＦＩＲフィルタは、かなりの高次のものとしなければならず、ますます回路構成が複雑になる。
【００３５】
これに対し、ラグランジェ補間を行う場合、上記の式から明らかなように、ラグランジェ補間サンプリングレートコンバータ４６は、加算器と乗算器と除算器等から構成でき、畳み込み演算と比較して、回路構成を簡略化することができる。しかも、補間のための（ｎ−１）次の多項式の次数を比較的小さい次数としても補間データを得ることができ、ますます回路構成を簡略化することができる。
【００３６】
第２の実施の形態のデジタル無線受信機の一部を図６及び図７に示す。第２の実施の形態では、レジスタ３６の制御が異なる以外、第１の実施の形態と同様に構成されている。同等部分には同一符号を付して、その説明を省略する。第１の実施の形態では、レジスタ３６へのデータの書き込み段数が所定段数よりも多いか少ないかによって読み出しタイミング信号の周波数を調整している。そのため、再生サンプリングタイミング信号Ｆｓｒがタイミング供給手段２７からの基準信号と位相も含めて完全に一致していない限り、データが書き込まれる段が所定段Ｒｅｇ３を前後することになる。従って、読み出し信号Ｆｓｆｉｆｏも常に変動する。レジスタ３６から読み出されたオーディオデータ列は、補間部４４において補間されるので、補間部４４に供給されるオーディオデータ列のタイミングの変動が少ない程、補間演算の精度が高くなる。
【００３７】
そこで、第２の実施の形態では、読み出し信号Ｆｓｆｉｆｏの変動を小さくするために、書き込まれる段数の変化量、即ち、微分量に応じて周波数上昇／低下指令を制御部４２が生成する。即ち、図６に示すように、レジスタ３６の所定段、例えば３段を基準段であるＦＩＦＯ「０」段に設定し、これよりも１つ上段の段をＦＩＦＯ「＋１」段に、これよりも更に１つ上段の段をＦＩＦＯ「＋２」段に設定する。また、ＦＩＦＯ「０」段よりも１つ下段の段をＦＩＦＯ「−１」段に、さらに１つ下段の段をＦＩＦＯ「−２」段と設定する。
【００３８】
そして、制御部４２は、書き込まれた段数がＦＩＦＯ「０」段よりも例えば１段増加した結果、ＦＩＦＯ「＋１」段まで達すると、所定値だけ読み出し信号Ｆｓｆｉｆｏの周波数を高くする。これでも、さらに書き込まれた段数がＦＩＦＯ「２」段まで増加すると、所定値だけ読み出し信号Ｆｓｆｉｆｏの周波数を更に高くする。書き込まれる段がＦＩＦＯ「＋１」段またはＦＩＦＯ「＋２」段に維持されているときには、そのときの周波数を維持する。或いは書き込まれた段数が基準段ＦＩＦＯ「０」よりも１段減少した結果、ＦＩＦＯ「−１」段にしか書き込まれていない場合、読み出し信号Ｆｓｆｉｆｏの周波数を所定値だけ低下させる。これでも、さらに書き込まれた段数がＦＩＦＯ「−２」段まで減少すると、さらに所定値だけ読み出し信号Ｆｓｆｉｆｏの周波数を低下させる。ＦＩＦＯ「−１」段またはＦＩＦＯ「−２」段において、書き込まれる段数に変化がない場合には、そのときの周波数を維持する。
【００３９】
例えば図７に示す時刻Ｔ１乃至Ｔ１３は、読み出し信号Ｆｓｆｉｆｏによって与えられる書き込みタイミングを示している。時刻Ｔ１では、読み出し信号Ｆｓｆｉｆｏの周波数が、再生サンプリングタイミング信号Ｆｓｒの周波数よりも低く、読み出し速度が書き込み速度よりも遅れている。このとき、現在値よりも所定値だけ読み出し信号Ｆｓｆｉｆｏの周波数が高くされ、読み出し信号Ｆｓｆｉｆｏの速度が速められる。時刻Ｔ２、Ｔ３では、レジスタ３６において書き込みが行われる段は、ＦＩＦＯ「＋１」段のままであるので、読み出し信号Ｆｓｆｉｆｏの周波数は高い周波数に維持される。
【００４０】
時刻Ｔ４において、読み出し信号Ｆｓｆｉｆｏの周波数を高めたが、まだ書き込み速度よりも読み出し速度が遅く、書き込まれる段数がＦＩＦＯ「＋２」段に増加している。そこで、更に所定値だけ読み出し信号Ｆｓｆｉｆｏの周波数が高められる。この状態が時刻Ｔ５、Ｔ６においても維持される。
【００４１】
時刻Ｔ７において、書き込まれる段数がＦＩＦＯ「＋１」段まで減少している。それは、再生サンプリングタイミング信号Ｆｓｒの周波数が低くなって、書き込み速度が遅くなったからである。従ってレジスタ３６の書き込み及び読み出し速度が追従してきたものであるので、読み出し信号Ｆｓｆｉｆｏの周波数は現在の値を維持する。従って、通常には読み出し信号Ｆｓｆｉｆｏの周波数が下がるように、周波数変更指令を出力するのであるが、読み出し信号Ｆｓｆｉｆｏの周波数は変化せずに、書き込まれる段が変更されていない。時刻Ｔ８、Ｔ９でも、この状態を維持する。
【００４２】
時刻Ｔ１０では、読み出し信号Ｆｓｆｉｆｏの周波数は変化していないが、再生サンプリングタイミング信号Ｆｓｒの周波数が低くなり、書き込み速度が遅くなり、書き込まれる段がＦＩＦＯ「０」まで減少する。このとき、読み出し速度が書き込み速度よりも速いが、レジスタ３６での書き込みが基準であるＦＩＦＯ「０」段に行われたので、見かけ上、書き込みと読み出しとは均衡している。従って、読み出し信号Ｆｓｆｉｆｏの周波数は現在の値を維持する。書き込まれる段がＦＩＦＯ「０」段を維持しているので、時刻Ｔ１１、Ｔ１２においても読み出し信号Ｆｓｆｉｆｏの周波数は、時刻Ｔ１０での値が維持される。
【００４３】
時刻Ｔ１３では、読み出し信号Ｆｓｆｉｆｏの周波数が、再生サンプリングタイミング信号の周波数よりも高く、書き込み速度が読み出し速度よりも遅いので、書き込まれる段がＦＩＦＯ「−１」段まで減少している。そこで、読み出し信号Ｆｓｆｉｆｏの周波数を所定値だけ低くする。以下同様にして、動作する。
【００４４】
このように、レジスタ３６における書き込まれる段数の変化量に応じて読み出し信号Ｆｓｆｉｆｏの周波数を制御しているので、読み出し信号Ｆｓｆｉｆｏの変動が小さくなり、読み出されるデジタルオーディオデータのタイミングの変動も小さくなる。従って、補間部４４において補間が行われたときに高精度に補間を行うことができる。
【００４５】
上記の実施の形態では、レジスタ３６による読み出しタイミングの変動の低減と、補間部４４による読み出しタイミングの変動の低減とを行ったが、いずれか一方のみを行うように構成しても、位相歪みを低減させ、アナログオーディオ信号を再生することができる。この場合、両方を設けた場合よりも位相歪みの低減効果が低くなるが、使用する回路の構成を簡略化することができるし、コストも低減することができる。
【００４６】
上記の実施の形態では、補間部４４ではラグランジェ補間法を用いたが、これに限ったものではなく、例えばニュートン補間法、ネヴィル補間法等の多項式補間法はもちろん、直線補間法等の公知の補間法を使用することができる。
【００４７】
上記の第１の実施の形態では、レジスタ３６における上限閾値及び下限閾値の段を３段としたが、これに限ったものではなく、他の段とすることもできる。また、上限閾値の段と下限閾値の段とを別々の段とすることもでき、例えば上限閾値の段を４段とし、下限閾値の段を２段とすることもできる。
【００４８】
上記の第１及び第２の実施の形態では、本発明をデジタル無線受信機に実施したが、これに限ったものではなく、例えば有線伝送路を伝送される送信信号を受信するデジタル有線受信機に実施することもできる。
【００４９】
また、上記の第１及び第２の実施の形態では、デジタル・アナログ変換器を使用して、アナログ信号に変換したが、これに限ったものではなく、他のデジタル処理手段、例えばデジタルオーディオインターフェースやデジタルオーディオトランスミッタを使用することもできる。
【００５０】
また、上記の第１及び第２の実施の形態では、デジタル波形信号列としてデジタルオーディオデータ列を使用したが、これに限ったものではなく、例えば心電図測定装置のような測定手段が発生したアナログ波形信号をデジタル波形信号列に変換したものを使用することもできる。
【００５１】
上記の第１及び第２の実施の形態では、デジタル・アナログ変換器３０に変換タイミングを与えているタイミング供給手段２７からの基準信号Ｆｓｄａｃを、ｋ（例えば５１２のような２^ｎとなる値）倍して、ｋ＊Ｆｓｄａｃを発生したが、逆にｋ＊Ｆｓｄａｃの周波数を持つ基準信号をタイミング供給手段２７に発生させ、ｋ＊Ｆｓｄａｃを位置決定部５０に供給し、かつｋ＊Ｆｓｄａｃを１／ｋに分周した分周信号をタイミング供給手段２７によって発生させ、この分周信号をデジタル・アナログ変換器３０に変換タイミングを与える基準信号として供給することもできる。
【００５２】
【発明の効果】
以上のように、本発明によるデジタル受信機では、送信信号が伝送路を伝送されている間に受けたジッタの影響を低減して、最終的にアナログ信号に変換されたときに位相歪みの発生を抑えることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態のデジタル無線受信機のブロック図である。
【図２】図１のデジタル無線受信機において使用されるレジスタの構成を示す図である。
【図３】図１のデジタル無線受信機におけるレジスタ３６におけるデータの書き込み及び読み出しの説明図である。
【図４】図１のデジタル無線受信機における補間部４４のブロック図である。
【図５】図４の補間部４４において実行される補間の説明図である。
【図６】本発明の第２の実施の形態のデジタル無線受信機におけるレジスタの構成を示す図である。
【図７】図６のデジタル無線受信におけるレジスタ３６におけるデータの書き込み及び読み出しの説明図である。
【図８】従来のデジタル無線送信機及びデジタル無線受信機のブロック図である。
【符号の説明】
２２　高周波部（復調手段）
２４　信号処理部（復調手段）
３６　レジスタ（記憶手段）
４２　制御部（制御手段）
４４　補間部（補間手段）[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital receiver for receiving a transmission signal modulated with a digitized waveform signal sequence such as a digital audio signal.
[0002]
[Prior art]
2. Description of the Related Art Generally, a digital receiver includes, for example, a digital audio wireless receiver that transmits a wireless transmission path and receives a transmission signal. This digital audio radio receiver is used together with a digital audio radio transmitter. FIG. 8 shows an example of the digital audio radio receiver and the digital audio radio transmitter. 8, in a digital audio transmitter 2, an audio signal from an audio signal source such as a microphone 4 is amplified to a predetermined level by an amplifier 6, and then supplied to an analog / digital converter 8. The analog-to-digital converter 8 sequentially samples the amplified audio signal based on a sampling timing signal generated by the reference signal source 10 at a predetermined sampling period, and converts the amplified audio signal into a digitized waveform signal having a predetermined number of bits. A sequence, for example, a digital audio data sequence. Each digital audio data of the digital audio data string is supplied to the signal processing unit 12 at each sampling timing. The signal processing unit 12 generates a digital modulation data sequence by adding a frame synchronization signal, an error detection or error correction code, etc. to the digital audio data sequence at a timing based on the sampling timing signal from the reference signal source 10. It is supplied to the high frequency unit 14. The high frequency section 14 modulates the carrier with the digital modulation data sequence to generate a transmission signal, amplifies the signal, and transmits the signal from the antenna 16. Since the same sampling timing signal is supplied from the reference signal source 10 to the analog-to-digital converter 8 and the signal processing unit 12, the digital conversion and the signal processing are synchronized.
[0003]
In the digital audio radio receiver 18, the transmission signal received by the antenna 20 is demodulated by the high frequency unit 22 into a data sequence corresponding to the digital modulation data sequence. This demodulated digital modulation data sequence is supplied to the signal processing unit 24, where it is demodulated into a digital audio data sequence. This demodulation is performed by detecting a frame synchronization signal from a demodulated digital modulation data string in which each bit is synchronized with a transmission clock Fclk to be described later, and performing error detection and error correction processing. The high frequency section 22 and the signal processing section 24 function as demodulation means. The digital modulation data sequence demodulated by the high-frequency unit 22 and the reference signal generated at predetermined intervals from the reference signal source 26 are supplied to the PLL 28, and phase-synchronized to synchronize with each bit of the demodulation digital modulation data sequence. The transmission clock Fclk is reproduced. The reproduction sampling timing signal Fsr is reproduced in the signal processing unit 24 based on the transmission clock Fclk, and is supplied to the digital / analog converter 30 to give a sampling timing. In the digital / analog converter 30, the demodulated digital audio signal sequence is converted into an analog signal, amplified by an amplifier 32, and loudspeaked from a speaker 34.
[0004]
[Problems to be solved by the invention]
In this digital radio receiver, since the transmission clock Fclk synchronized with each bit of the demodulated digital modulation data string is reproduced by the PLL 28, the transmission side and the reception side are synchronized, and data duplication or loss during reception is performed. Does not occur. However, the digitally modulated signal that is wirelessly transmitted is affected by fading that occurs in the wireless transmission path, and has jitter. There is also a jitter due to the response speed of the PLL 28, and the phase of the transmission clock Fclk is shifted. The reproduced sampling timing signal Fsr reproduced based on the transmission clock Fclk is completely different from the sampling timing signal of the reference signal source 10. Not a match. Therefore, the sampling timing in the digital-to-analog converter is not constant, and the analog signal to be converted has a phase distortion due to a variation in the sampling timing.
[0005]
An object of the present invention is to provide a digital receiver that reduces the phase distortion of an analog signal that is finally converted from a digitized waveform signal sequence.
[0006]
[Means for Solving the Problems]
One aspect of the digital wireless receiver according to the present invention includes a demodulation unit that demodulates a transmission signal transmitted from a transmission source. This transmission signal is obtained by modulating a carrier with a digitized waveform signal sequence composed of continuous digitized waveform signals. The digitized waveform signal sequence may be a digital audio data sequence, or a digitized version of an analog waveform signal obtained from the measuring means, for example. The demodulation means also demodulates the generation timing of the digitized waveform signal. This digital receiver further has storage means. This storage means is of a first-in first-out type, in which demodulated digitized waveform signals are sequentially written in synchronization with their generation timing. In synchronization with each read timing, the read control means sequentially reads the digitized waveform signals from the storage means. The read control unit reads the digitized waveform signal at a timing earlier than the reference read timing when the number of the digitized waveform signals written in the storage unit is larger than a predetermined number, and reads the digitized waveform signal more than the predetermined number. When the number is small, the digitized waveform signal is read at a timing later than the reference read timing. The predetermined number for reading at a faster timing and the predetermined number for reading at a later timing can be the same or different. The read timing is set so that the change in the read timing is smaller than the change in the write timing.
[0007]
In this aspect, when the number of digitized waveform signals written in the first-in first-out type storage means is larger than a predetermined number, it indicates that reading is slower than writing. In this case, the read timing is advanced so as to speed up the read. On the other hand, if the number of digitized waveform signals written in the first-in first-out type storage means decreases below a predetermined number, it indicates that writing is slower than reading. In this case, the read timing is delayed so that the read is delayed. However, the change in the timing is set smaller than the change in the generation timing of the digitized waveform signal. Therefore, even if the generation timing of the digitized waveform signal changes, the influence of the change can be reduced. For example, even if this digitized waveform signal is directly converted to an analog signal, the influence of the phase distortion is reduced. Can be reduced.
[0008]
The read control means can include a variable frequency oscillator that generates a read timing signal that specifies a read timing. As this variable frequency oscillator, an analog oscillator can be used, or a digital oscillator can be used. When using a variable frequency oscillator, oscillation frequency control means is used. The oscillation frequency control means supplies a frequency increase command to increase the oscillation frequency by a predetermined frequency to the frequency variable oscillator when the number of the digitized waveform signals written in the storage means is larger than a predetermined number. When the number is smaller than the predetermined number, a frequency reduction command for lowering the oscillation frequency by a predetermined frequency is supplied to the variable frequency oscillator. The predetermined frequency is set to be smaller than a frequency change of the generation timing.
[0009]
Alternatively, the frequency control means can be configured as follows. That is, the frequency control means supplies a frequency increase command for increasing the oscillation frequency by a predetermined frequency every time the number of writing of the digitized waveform signal to the storage means increases, and Each time the number of writes decreases, a frequency reduction command is supplied to the variable frequency oscillator to lower the oscillation frequency by a predetermined frequency. The predetermined frequency is set to be smaller than a frequency change of the generation timing. For example, in a state where the number of writes in the storage means is larger than a predetermined number, if the number of writes increases, a frequency increase command is issued, and in a state where the number of writes in the storage means is smaller than the predetermined number of steps, When the frequency decreases, a frequency lowering command may be generated.
[0010]
In such a configuration, the change in the read timing changes only when the number of digitized waveform signals written increases or decreases. For example, when the number of digitized waveform signals written does not change, the read timing changes. Does not change. Therefore, the fluctuation of the read timing is reduced.
[0011]
For each input timing of the processing means for processing the digitized waveform signal sequentially read from the storage means, an interpolation digital waveform signal corresponding to each of these timings is generated based on each digitized waveform signal sequentially read from the storage means. Interpolating means can be provided. As the processing means, for example, a digital-analog converter, a digital audio interface, or the like can be used.
[0012]
By performing the interpolation after reducing the timing deviation of the digitized waveform signal in this way, a digitized waveform signal sequence interpolated to match the input timing of the processing means can be obtained. Is directly converted into an analog signal, there is no increase in phase distortion due to timing fluctuation.
[0013]
In another aspect of the digital receiver according to the present invention, demodulation means is provided. This demodulation means demodulates the transmission signal. This transmission signal is obtained by modulating a carrier with a digitized waveform signal sequence including a plurality of continuous digitized waveform signals transmitted from a transmission source. Any one of a plurality of reference timings represented by a reference timing signal having a frequency that is a multiple of the frequency of the input timing signal that defines the input timing signal to the processing means for one digitized waveform signal in the digitized waveform signal sequence The position determining means determines whether the position of another digitized waveform signal in each digitized waveform signal sequence corresponds to the above. Based on the values of these other digitized waveform signals and the positions of the other digitized waveform signals determined by the position determining means, the interpolating means interpolates at the input timing of the one digitizing waveform signal processing means. A digitized waveform signal is calculated and supplied to the processing means. As the interpolation method used by the interpolation means, various known methods can be used. For example, a polynomial interpolation method, more specifically, a Lagrange interpolation method can be used.
[0014]
In the digital receiver configured as described above, the timings of the interpolated digitized waveform signals obtained by the interpolation all correspond to the input timings of the processing means, and therefore, for example, the digital / analog conversion means was used as the processing means. In this case, phase distortion can be reduced.
[0015]
Furthermore, means for reducing the timing deviation of the digitized waveform signal sequence can be provided between the demodulation means and the interpolation means. As the mitigation means, for example, a means using a first-in first-out storage means as described above can be used. When such a mitigation means is provided, interpolation is performed after the timing deviation of the digitized waveform signal input to the interpolation means is mitigated. For example, when the processing means is a digital-to-analog conversion means, the timing variation Does not increase phase distortion.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a digital audio wireless receiver according to a first embodiment of the present invention. This digital audio radio receiver includes an antenna 20, a high-frequency unit 22, a signal processing unit 24, a PLL 28, a digital-to-analog converter 30, an amplifier 32, and a speaker 34, similarly to the above-described conventional one.
[0017]
However, storage means, for example, a FIFO (first-in first-out) register 36 is provided between the signal processing unit 24 and the digital / analog converter 30. The register 36 has a plurality of stages, for example, six stages Reg1 to Reg6, as shown in FIG. Each of the stages Reg1 to Reg6 has a bit capable of storing each digital audio data constituting the digital audio data string output from the signal processing unit 24.
[0018]
Digital audio data from the signal processing unit 24 is sequentially written into the register 36. This writing is performed in the next stage after the last stage of the stage in which writing is already performed among the writable stages. For example, if no data has been written to any of the stages, the data is first written to the stage Reg1, then written to the stage Reg2, and then written to the stage Reg3 in that order. The write timing is synchronized with the reproduction sampling timing signal Fsr output from the signal processing unit 24.
[0019]
The reading from the register 36 is performed every time a pulsed read signal Fsfifo is generated from a frequency variable oscillator, for example, a numerically controlled oscillator (NCO) 40, and is read from the first stage Reg1. Each time this reading is performed, the data in each stage is shifted one by one to the previous stage. That is, the register 36 is configured as a shift register.
[0020]
The numerical control oscillator 40 is supplied from the timing supply unit 27 with a reference signal generated every predetermined period. The timing supply unit 27 generates a reference signal based on a clock signal from the reference signal source 26a. This reference signal is also supplied to the PLL 28. The frequency of the read signal Fsfifo is changed by changing the frequency of the reference signal based on a frequency increase / decrease command from the control unit 42. The control unit 42 determines whether the final writing stage in the register 36 is a predetermined stage, for example, a stage higher or lower than the stage Reg3, and changes the frequency control command according to the result.
[0021]
For example, when digital audio data is written to the stage Reg4 beyond the stage Reg3, that is, when the digital audio data exceeds the upper threshold value, it indicates a state where the reading speed is lower than the data writing speed. Conversely, when there is no data in the stage Reg3 and data has been written only up to the stage Reg2, that is, when the data is below the lower threshold, this indicates a state where the reading speed is faster than the data writing speed. In any case, the sampling timing on the transmission side cannot be accurately reproduced on the receiver side.
[0022]
Therefore, when digital audio data is written to a stage exceeding the upper threshold, the control unit 42 supplies a frequency increase command to the NCO 40 so as to increase the frequency of the read signal Fsfifo by a predetermined value in order to increase the read speed. I do. Further, when the digital audio data is written only to the stage exceeding the lower threshold value, the control unit 42 issues a frequency reduction command to reduce the frequency of the read signal Fsfifo by a predetermined frequency in order to reduce the reading speed. Supply to NCO40.
[0023]
However, the amount by which the frequency of the read signal increases / decreases is set to be smaller than the amount of frequency change that is actually expected to occur in the reproduction sampling timing signal Fsr. Therefore, even if the reproduction sampling timing signal Fsr fluctuates due to the influence of the jitter, the digital audio data can be output from the register 36 while following the fluctuation of the timing while reducing the influence of the fluctuation.
[0024]
FIG. 3 shows the relationship among the reproduction sampling timing signal Fsr, the read signal Fsfifo, the write data WD, the read data RD, the residual data amount of the register 36, and the frequency increase / decrease command. At time t1, the reproduction sampling timing signal Fsr matches the read signal Fsfifo, and accordingly, the data x1 is written and the data y1 is read. At this time, the number of stages of the residual data in the register 36 is 3, and the frequency increase / decrease command also commands the reference frequency.
[0025]
When the write timing based on the reproduction sampling timing signal Fsr is reached at time t2, the data x2 is written. At this time, the number of stages of the residual data is four. At the read timing at time t3, the data y2 is read, and the number of remaining data stages becomes three. However, since the number of remaining data stages immediately before is four as described above, that is, the write timing is longer than the read timing. Therefore, the frequency of the read signal Fsfifo increases by a predetermined value.
[0026]
When the write timing comes at time t4, data x3 is written, and at this time, the number of stages of the residual data becomes four again. Because the frequency of the read signal Fsfifo has been increased earlier, the read timing is reached at time t5, the data y3 is read, and the number of stages of the residual data is three. Since the read timing is faster than the read timing, the frequency of the read signal Fsfifo is made higher by a predetermined value than the current frequency. As a result, at the time t6, the read timing is reached, the data y4 (= x1) is read, and the number of stages of the residual data is two. However, the number of stages immediately before is three, which is a predetermined number of stages. Maintain the frequency of
[0027]
At time t7, the writing timing comes, data x4 is written, and the number of stages of the residual data becomes three. At time t8, the read timing is reached, the data y5 (= x2) is read, and the number of stages of the residual data becomes 2. Since the number of stages immediately before that is 3, the read signal Fsfifo maintains the current frequency. At time t9, the read timing comes, and the data y6 (= x3) is read, and the number of stages of the residual data immediately before that is two, which is smaller than the predetermined three. Therefore, the frequency of the read signal Fsfifo becomes lower than the current frequency by a predetermined value. Hereinafter, the read timing is similarly adjusted. In addition, since the amount by which the frequency of the read signal Fsfifo is changed is set to be smaller than the amount expected when the reproduction sampling timing signal changes, the effect of jitter on the digital audio data string read from the register 36 is small. It has been reduced.
[0028]
The digital audio data sequence in which the influence of the jitter has been reduced in this way is supplied to the interpolation unit 44. As shown in FIG. 4, the interpolation unit 44 includes an interpolation unit, for example, a Lagrange sampling rate converter 46 for performing Lagrange interpolation. The Lagrangian sampling rate converter 46 converts the digital audio data string read from the register 36, in which the influence of the jitter is reduced, into digital data composed of digital audio data that matches the conversion timing of processing means, for example, the digital / analog converter 30. Interpolation into an audio data string.
[0029]
In the Lagrange interpolation, for example, when there is data y (0) to y (n) corresponding to input timings x (0) to x (n), an n-1 order interpolation polynomial is obtained from y (0) to y (n). To obtain data y at an arbitrary timing, in this case, the conversion timing of the digital / analog converter 30. The interpolation formula is

The Lagrange sampling rate converter 46 performs this calculation.
[0030]
Here, in order to obtain the data y at the conversion timing of the digital / analog converter 30, the conversion timing and the input timings x (0) to x (n) of the data y (0) to y (n) are calculated. It is necessary to clarify the positional relationship. Therefore, the reference signal Fsdac giving the conversion timing to the digital / analog converter 30 is converted to k (for example, 2 such as 512) ⁿ The value is multiplied by k) and supplied to the position determination unit 50 as k * Fsdac. Note that the reference signal Fsdac is generated by the timing supply unit 27 based on the clock signal of the reference signal source 26a. The position determination unit 50 is supplied with the read signal Fsfifo from the numerically controlled oscillator 40, and determines which position the input read signal Fsfifo is located on the basis of k * Fsdac, and determines the position. To the Lagrange sampling rate converter 46. This is x [i] in the above formula. The reference signal Fsdac is supplied to the Lagrange sampling rate converter 46 as x in the above formula.
[0031]
FIG. 5 shows the relationship between Fsdac, k * Fsdac, and Fsfifo. In the figure, the broken line indicates k * Fsdac, the solid line indicates Fsfifo, and the white circles in each Fsfifo indicate y (0) to y (n) (in the figure, n is 6). Fsdac is indicated by a dashed line. In this way, the relationship between the timings x (0) to x (n) of y (0) to y (n) and the conversion timing x of the digital / analog converter 30 is obtained based on k * Fsdac, Every time the conversion timing of the digital-to-analog converter 30 arrives, the interpolated digital audio data y is output.
[0032]
The interpolated digital audio data y is analog-converted by the digital-analog converter 30, amplified by the amplifier 32, and loudspeaked from the speaker 34.
[0033]
With this configuration, the interpolation of the digital audio data in the digital audio data sequence is performed by the interpolation unit 44 so as to match the conversion timing in the digital-to-analog converter 30, so that the phase distortion does not increase. .
[0034]
As the sampling rate converter 46, it is conceivable to use a digital audio data that is oversampled to a frequency that is a common multiple of the frequency of Fsfifo and the frequency of Fsdac, and then downsampled to the frequency of Fsdac. However, this requires a convolution operation to construct an FIR filter for oversampling. The convolution operation requires an adder, a multiplier and a shift register. The multiplier and the shift register must be prepared for the order of the filter, which complicates the circuit configuration of the convolution operation. Moreover, in order to process digital audio data, the FIR filter needs to have a sharp cutoff characteristic, and the FIR filter must be of a considerably higher order, and the circuit configuration becomes more and more complicated.
[0035]
On the other hand, when performing Lagrange interpolation, as is apparent from the above equation, the Lagrange interpolation sampling rate converter 46 can be constituted by an adder, a multiplier, a divider, and the like. The configuration can be simplified. Moreover, even if the order of the (n-1) -th order polynomial for interpolation is set to a relatively small order, interpolation data can be obtained, and the circuit configuration can be further simplified.
[0036]
FIGS. 6 and 7 show a part of the digital wireless receiver according to the second embodiment. The second embodiment has the same configuration as the first embodiment except that the control of the register 36 is different. The same reference numerals are given to the same parts, and the description thereof will be omitted. In the first embodiment, the frequency of the read timing signal is adjusted depending on whether the number of stages of writing data to the register 36 is larger or smaller than a predetermined number. Therefore, unless the reproduction sampling timing signal Fsr completely matches the reference signal from the timing supply unit 27 including the phase, the stage to which data is written is before or after the predetermined stage Reg3. Therefore, the read signal Fsfifo also constantly changes. Since the audio data sequence read from the register 36 is interpolated in the interpolation unit 44, the smaller the timing variation of the audio data sequence supplied to the interpolation unit 44, the higher the accuracy of the interpolation calculation.
[0037]
Therefore, in the second embodiment, in order to reduce the fluctuation of the read signal Fsfifo, the control unit 42 generates a frequency increase / decrease command according to the amount of change in the number of stages to be written, that is, the amount of differentiation. That is, as shown in FIG. 6, a predetermined stage, for example, three stages of the register 36 is set to a FIFO “0” stage which is a reference stage, and the next higher stage is set to a FIFO “+1” stage. In addition, the next upper stage is set to the FIFO “+2” stage. Further, a stage one stage below the FIFO “0” stage is set as a FIFO “−1” stage, and a stage one stage further below the FIFO “0” stage is set as a FIFO “−2” stage.
[0038]
Then, the control unit 42 increases the frequency of the read signal Fsfifo by a predetermined value when the number of written stages increases by, for example, one stage from the FIFO “0” stage and reaches the FIFO “+1” stage. Even in this case, when the number of written stages further increases to the FIFO “2” stages, the frequency of the read signal Fsfifo is further increased by a predetermined value. When the stage to be written is maintained at the FIFO “+1” stage or the FIFO “+2” stage, the frequency at that time is maintained. Alternatively, if the number of stages written is reduced by one stage from the reference stage FIFO “0”, and only the FIFO stage “−1” is written, the frequency of the read signal Fsfifo is reduced by a predetermined value. Even in this case, when the number of written stages further decreases to FIFO “−2” stages, the frequency of the read signal Fsfifo is further reduced by a predetermined value. If there is no change in the number of stages to be written in the FIFO “−1” stage or the FIFO “−2” stage, the frequency at that time is maintained.
[0039]
For example, times T1 to T13 shown in FIG. 7 indicate write timing given by the read signal Fsfifo. At time T1, the frequency of the read signal Fsfifo is lower than the frequency of the reproduction sampling timing signal Fsr, and the read speed is slower than the write speed. At this time, the frequency of the read signal Fsfifo is made higher by a predetermined value than the current value, and the speed of the read signal Fsfifo is increased. At times T2 and T3, the stage where writing is performed in the register 36 remains at the FIFO “+1” stage, so that the frequency of the read signal Fsfifo is maintained at a high frequency.
[0040]
At time T4, the frequency of the read signal Fsfifo was increased, but the read speed is still slower than the write speed, and the number of stages to be written has increased to FIFO “+2” stages. Therefore, the frequency of the read signal Fsfifo is further increased by a predetermined value. This state is maintained at times T5 and T6.
[0041]
At time T7, the number of stages to be written has decreased to FIFO “+1” stages. This is because the frequency of the reproduction sampling timing signal Fsr has decreased and the writing speed has decreased. Therefore, since the writing and reading speeds of the register 36 follow, the frequency of the reading signal Fsfifo maintains the current value. Therefore, normally, the frequency change command is output so that the frequency of the read signal Fsfifo decreases. However, the frequency of the read signal Fsfifo does not change, and the stage to be written is not changed. This state is maintained at times T8 and T9.
[0042]
At time T10, the frequency of the read signal Fsfifo does not change, but the frequency of the reproduction sampling timing signal Fsr decreases, the write speed decreases, and the number of stages to be written decreases to FIFO “0”. At this time, although the reading speed is higher than the writing speed, the writing in the register 36 is performed in the FIFO “0” stage which is the reference, so that the writing and the reading are apparently balanced. Therefore, the frequency of the read signal Fsfifo maintains the current value. Since the stage to be written maintains the FIFO “0” stage, the frequency of the read signal Fsfifo is maintained at the value at the time T10 even at the times T11 and T12.
[0043]
At time T13, since the frequency of the read signal Fsfifo is higher than the frequency of the reproduction sampling timing signal and the write speed is lower than the read speed, the number of stages to be written is reduced to FIFO “−1”. Therefore, the frequency of the read signal Fsfifo is lowered by a predetermined value. Hereinafter, the same operation is performed.
[0044]
As described above, since the frequency of the read signal Fsfifo is controlled in accordance with the amount of change in the number of stages to be written in the register 36, the fluctuation of the read signal Fsfifo becomes small, and the fluctuation of the timing of the read digital audio data also becomes small. Therefore, when the interpolation is performed in the interpolation unit 44, the interpolation can be performed with high accuracy.
[0045]
In the above embodiment, the variation of the read timing by the register 36 is reduced and the variation of the read timing by the interpolation unit 44 is reduced. However, even if only one of them is performed, the phase distortion is reduced. It is possible to reproduce the analog audio signal by reducing it. In this case, the effect of reducing the phase distortion is lower than when both are provided, but the configuration of the circuit to be used can be simplified and the cost can be reduced.
[0046]
In the above-described embodiment, the Lagrange interpolation method is used in the interpolation unit 44. However, the present invention is not limited to this. Can be used.
[0047]
In the above-described first embodiment, the upper threshold value and the lower threshold value in the register 36 are three stages. However, the present invention is not limited to this, and other stages may be used. In addition, the upper threshold level and the lower threshold level may be different levels. For example, the upper threshold level may be four levels and the lower threshold level may be two levels.
[0048]
In the first and second embodiments, the present invention is applied to a digital wireless receiver. However, the present invention is not limited to this. For example, a digital wired receiver for receiving a transmission signal transmitted through a wired transmission path It can also be implemented.
[0049]
In the first and second embodiments, the digital signal is converted into an analog signal by using a digital / analog converter. However, the present invention is not limited to this. Other digital processing means such as a digital audio interface Or a digital audio transmitter can be used.
[0050]
In the first and second embodiments, the digital audio data sequence is used as the digital waveform signal sequence. However, the present invention is not limited to this. For example, an analog signal generated by a measuring unit such as an electrocardiogram measuring device may be used. A signal obtained by converting a waveform signal into a digital waveform signal sequence can also be used.
[0051]
In the above-described first and second embodiments, the reference signal Fsdac from the timing supply unit 27 that gives the conversion timing to the digital-to-analog converter 30 is set to k (for example, 2 such as 512). ⁿ K * Fsdac is generated, but a reference signal having a frequency of k * Fsdac is generated in the timing supply unit 27, and k * Fsdac is supplied to the position determining unit 50. * Fsdac may be divided by 1 / k to generate a frequency-divided signal by the timing supply unit 27, and the frequency-divided signal may be supplied to the digital / analog converter 30 as a reference signal for giving a conversion timing.
[0052]
【The invention's effect】
As described above, in the digital receiver according to the present invention, the influence of the jitter received while the transmission signal is transmitted through the transmission path is reduced, and phase distortion occurs when the transmission signal is finally converted into an analog signal. Can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram of a digital wireless receiver according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a register used in the digital wireless receiver in FIG. 1;
FIG. 3 is an explanatory diagram of writing and reading of data in a register 36 in the digital wireless receiver in FIG. 1;
FIG. 4 is a block diagram of an interpolation unit 44 in the digital wireless receiver in FIG. 1;
FIG. 5 is an explanatory diagram of interpolation performed by an interpolation unit 44 in FIG. 4;
FIG. 6 is a diagram illustrating a configuration of a register in a digital wireless receiver according to a second embodiment of the present invention.
7 is an explanatory diagram of writing and reading of data in a register 36 in the digital wireless reception in FIG.
FIG. 8 is a block diagram of a conventional digital radio transmitter and digital radio receiver.
[Explanation of symbols]
22 High frequency section (demodulation means)
24 signal processing unit (demodulation means)
36 registers (storage means)
42 control unit (control means)
44 Interpolation unit (interpolation means)

Claims (6)

Demodulation means for demodulating a transmission signal obtained by modulating a carrier with a digitized waveform signal sequence consisting of a continuous digitized waveform signal transmitted from a transmission source,
A first-in first-out storage means in which digitized waveform signals of the demodulated digitized waveform signal sequence are sequentially written in synchronization with their generation timing;
Read control means for sequentially reading digitized waveform signals of the digitized waveform signal sequence from the storage means in synchronization with the read timing;
Said read control means,
When the number of the digitized waveform signals written in the storage means is larger than a predetermined number, the digitized waveform signal is read at a timing earlier than the reference read timing, and when the number is smaller than the predetermined number, the reference read is performed. A digital receiver which reads the digitized waveform signal at a timing later than a timing, and wherein the read timing is set so that a change thereof is smaller than a change of the generation timing. 2. The digital receiver according to claim 1, wherein the read control unit includes:
A variable frequency oscillator that generates a read timing signal that specifies the read timing;
When the number of digital waveform signals written in the storage means is larger than the predetermined number, a frequency increase command to increase the frequency by a predetermined frequency is supplied to the variable frequency oscillator, and the frequency increase command is less than the predetermined number. When supplying a frequency reduction command to reduce the frequency by a predetermined frequency to the variable frequency oscillator, the predetermined frequency, oscillation frequency control means that is set less than the frequency change of the generation timing,
Digital receiver equipped. 2. The digital receiver according to claim 1, wherein the read control unit includes:
A variable frequency oscillator that generates a read timing signal that specifies the read timing;
Every time the number of writing of the digitized waveform signal to the storage means increases, a frequency increase command for increasing the oscillation frequency by a predetermined frequency is supplied to the variable frequency oscillator, and the digitized waveform to the storage means is supplied. Every time the number of signal writes decreases, a frequency reduction command is supplied to the variable frequency oscillator to reduce the oscillation frequency by a predetermined frequency, and the predetermined frequency is set to be smaller than the frequency change of the generation timing. Frequency control means,
Digital receiver equipped. 2. The digital receiver according to claim 1, wherein for each input timing of the processing means for processing the digitized waveform signal sequentially read from the storage means, an interpolation digital waveform signal corresponding to each of these input timings is sequentially output from the storage means. A digital receiver provided with interpolation means for generating based on a digitized waveform signal to be read. Demodulation means for demodulating a transmission signal obtained by modulating a carrier with a digitized waveform signal sequence consisting of a continuous digitized waveform signal transmitted from a transmission source,
The reference timing represented by a reference timing signal having a frequency that is a multiple of the input timing signal that defines the input timing of one digitized waveform signal of the demodulated digitized waveform signal sequence demodulated by the demodulation means to the processing means. Position determining means for determining at which position another digitized waveform signal of the demodulated digitized waveform signal is located,
Interpolation at the input timing of the one digitized waveform signal to the processing means based on the value of the other digitized waveform signal and the position of the other digitized waveform signal determined by the position determining means Interpolating means for calculating a digitized waveform signal and supplying it to the processing means,
Digital receiver equipped. 6. The digital receiver according to claim 5, further comprising means for reducing a timing deviation of the digitized waveform signal between the demodulation means and the interpolation means.

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