JP2004118644A - Disk array control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a disk array control system capable of shortening a time to be required to backup and capable of reducing a capacity of a battery. <P>SOLUTION: This disk array control system 10 is provided with a channel control unit 103 for controlling a channel 11 connected to a host computer for communication, a disk control unit 104 for controlling a disk device, and a cash memory unit 101 for temporarily storing data transmitted between the channel control unit 103 and the disk control unit 104. The cash memory unit 101 is provided with a connecting means 1012 for connecting a backup disk 1013 storing the data stored in the cash memory unit. When power supplied from outside is cut, the cash memory unit 101 outputs the data stored in the cash memory unit 101 to the connecting means, and the data stored in the cash memory unit 101 is stored in the backup disk independently of the disk control unit 104. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to protection of a volatile memory such as a cache memory in an emergency, and particularly to a disk control device and a control method for backing up data using a disk.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a disk array device that backs up the contents of a cache memory to a disk device in an emergency has been known.
[0003]
FIG. 15 is a block diagram showing a configuration of a conventional disk array device. This conventional disk array device includes a disk device 20 for storing data and a disk array control device 10 for controlling the disk device 20.
[0004]
The disk array controller 10 is connected to the host computer 1 through a channel 11. The disk array control device 10 includes a plurality of channel control units 103 for transferring data between the host computer 1 and the disk array control device 10, and a communication between the disk device 20 and the disk array control device 10 via the disk-side channel 12. The system includes a plurality of disk control units 104 for transferring data among them, a cache memory unit 101 for temporarily storing data, and a shared memory unit 102 for storing control information on the disk array control device 10.
[0005]
The cache memory unit 101 includes a memory module 1011 composed of, for example, an SDRAM. Generally, the access speed of the memory module 1011 is higher than that of the disk device 20, but since the storage capacity and the cost per capacity are inferior to those of the disk device 20, the data required by the host computer is read from the disk device 20 in advance and the cache memory unit is read. The data is stored in the disk drive 101, and after the processing of the host computer 1 is completed, the processed data is written back to the disk device 20 and is used for temporarily storing the data.
[0006]
During the operation of the disk array device, as a measure against momentary power failure and surge current, even when the external power supply is cut off or the power supply voltage fluctuates, the power is supplied from the battery 1061 to the disk array control device 10 and the disk device 20. A power supply device 106 that can be supplied is provided. At the time of a continuous power failure, all the contents stored in the cache memory unit are read by referring to the control information stored in the shared memory unit 102 until the holding time of the battery 1061 of the power supply unit 106 ends. By writing back to, data consistency can be maintained even when power is suddenly shut down.
[0007]
In such a disk device, for example, in the invention described in Japanese Patent Application Laid-Open No. 2000-357059, the operation of the device is maintained by a battery when power is turned off, and data in a cache memory is stored in the disk device within the battery duration. It is configured as follows.
[0008]
[Patent Document 1]
JP 2000-357059 A
[0009]
[Problems to be solved by the invention]
However, as the capacity of the memory module increases, the time until the entire contents of the cache memory unit is written back to the disk device 20 increases. However, during this write-back time, the operation of the disk array device is maintained by the battery 1061. Therefore, there is a problem that a large capacity battery is required for the power supply device 106, the volume of the battery is increased, the cost is increased, and the size of the device is also increased.
[0010]
[Means for Solving the Problems]
The present invention provides a channel controller for controlling a channel connected to a host computer for performing communication, a disk controller for controlling a disk device, and data transferred between the channel controller and the disk controller. A cache memory unit that temporarily stores data, wherein the channel control unit transfers data between the channel and the cache memory unit, and the disk control unit is configured to transfer the disk device and the Transferring data to and from a cache memory unit, the cache memory unit includes connection means for connecting a backup disk that stores data stored in the cache memory unit, and when the power supplied from the outside is cut off, The data stored in the cache memory is output to the connection means, Regardless of the part, and to store the data stored in the cache memory unit to said backup disk.
[0011]
Function and effect of the present invention
According to the present invention, a channel control unit that controls a channel connected to a host computer and performs communication, a disk control unit that controls a disk device, and data transferred between the channel control unit and the disk control unit. A cache memory unit that temporarily stores data, wherein the channel control unit transfers data between the channel and the cache memory unit, and the disk control unit is configured to transfer the disk device and the Transferring data to and from a cache memory unit, the cache memory unit includes connection means for connecting a backup disk that stores data stored in the cache memory unit, and when the power supplied from the outside is cut off, Outputting the data stored in the cache memory unit to the connection means; Since the data stored in the cache memory unit is stored in the backup disk regardless of the control unit, the time required for backup can be reduced, and the capacity of the battery is reduced to limit the power supply range of the battery. Since the power supply device can be downsized, the disk control device can be downsized and the installation area can be reduced.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0013]
FIG. 1 is a block diagram illustrating an outline of the disk array device according to the first embodiment.
[0014]
The disk array device according to the embodiment of the present invention includes a disk device 20 that stores data and a disk array control device 10 that controls the disk device 20.
[0015]
The disk array control device 10 is connected to the host computer 1 via the channel 11, and transmits and receives data between the disk device 20 and the host computer 1. As the channel 11, for example, a fiber channel or the like is used.
[0016]
The cache memory unit 101 temporarily stores data stored in the disk device 20, and the stored data is transmitted to and received from the host computer via the channel 11. The cache memory unit 101 includes a memory control unit 1010 that is connected to the interconnection network 105 and exchanges data with the memory module 1011. Data input to the cache memory unit 101 is stored in the memory module 1011. . The memory module 1011 is formed of, for example, an SDRAM. The cache memory unit 101 is provided with a built-in backup disk 1013. The built-in backup disk 1013 stores data stored in the memory module 1011 in an emergency such as when power is turned off, and backs up the storage contents of the memory module 1011. The disk protocol control unit 1012 is connected to the built-in backup disk 1013 and controls data input / output to / from the built-in backup disk 1013.
[0017]
The shared memory unit 102 stores control information on the disk array control device 10. The shared memory unit 102 includes a memory control unit 1020 connected to the interconnection network 106 and exchanging data with the memory module 1021. Data input to the shared memory unit 102 is stored in the memory module 1021. . The memory module 1021 is configured by, for example, an SDRAM. The shared memory unit 102 includes a built-in backup disk 1023. The built-in backup disk 1023 stores data stored in the memory module 1021 and backs up the memory module 1021 in an emergency such as when power is turned off. The disk protocol control unit 1022 is connected to the internal backup disk 1023 and controls input / output of data to / from the internal backup disk 1023.
[0018]
The channel control unit 103 controls an interface with the host computer 1 and is connected to the host computer 1 via the channel 11. The channel control unit 103 and the disk control unit 104 are connected to the cache memory unit 101 and the shared memory unit 102 via interconnection networks 105 and 106.
[0019]
The disk control unit 104 is connected to the disk device 20 via the disk-side channel 12. As the disk-side channel 12, a fiber channel or the like is used. A plurality of disk devices 20 are provided, and a disk array is constructed with a RAID level configuration according to a user's request.
[0020]
The interconnection network 105 connects the cache memory unit 101 and the interconnection network 106 connects the shared memory unit 102 to the channel control unit 103 and the disk control unit 104, respectively, and is configured by a crossbar switch or the like.
[0021]
Power is supplied to the disk array control device 10 by a power supply device 106. The power supply device 106 is provided with a battery 1061, and when the power supplied from the outside is shut off, the power stored in the battery 1061 is temporarily supplied to the disk array control device 10. The power supply 106 also supplies power to the disk device 20. Power is supplied to the cache memory unit 101 and the shared memory unit 102 of the disk array control device 10 by the memory unit power supply unit 107. The power supply device 107 is provided with a battery 1071. When the power is turned off, the power stored in the battery 1071 is used to temporarily supply power to the cache memory unit 101 and the shared memory unit 102, and the operation is continued.
[0022]
The status of these power supplies 106 and 107 is monitored by a service processor (SVP) 105.
[0023]
When the host computer 1 accesses data in the disk array device, direct access to the disk device 20 causes a large overhead when reading / writing data. Therefore, the data requested from the host computer 1 is cached in units of blocks. The information is stored in the unit 101. The disk array control device 10 performs processing by reading data stored in the cache memory unit 101 or writing data to the cache memory unit 101.
[0024]
The data stored in the cache memory unit 101 is rewritten in response to a write request from the host computer. However, since these are data (dirty data) not yet stored in the disk device 20, they are written back to the disk device 20. It is necessary to perform processing (destaging). This destaging may be performed at any time in response to a request from the host computer 1 (write-through), or when the cache usage rate exceeds a prescribed amount, the target data may be processed according to an algorithm such as LRU (Least Recently Used). May be performed after deciding (write back).
[0025]
The shared memory unit 102 uses directory information of data stored in the cache memory unit 101, job information for processing an input / output request of the host computer 1 in cooperation with the channel control unit 103 and the disk control unit 104, and uses the same. Control information such as configuration information indicating the assignment of a logical volume to the disk device 20 according to the RAID level is stored.
[0026]
FIG. 2 is a block diagram showing a detailed configuration of the cache memory unit 101.
[0027]
The memory control unit 1010 includes an access path control unit 10101 and a memory module control unit 10102.
[0028]
The access path control unit 10101 selectively connects the access path 1016 connected to the interconnection network 105 and the disk protocol control unit 1012 to the data line 10110, and connects the access path 1016, the disk protocol control unit 1012 to the memory module 1011. Is connected to the selector 10112. For example, during normal times, the access path 1016 and the memory module 1011 are connected, and data is transmitted and received between the memory module 1011 and the channel control unit 103 and the disk control unit 104. When an abnormality such as power interruption occurs, the disk protocol control unit 1012 and the memory module 1011 are connected to perform control to dump and save data of the memory module 1011 to the built-in backup disk 1013. The details of this control will be described later with reference to FIG.
[0029]
The memory module control unit 10102 controls the memory module 1011 via the command line 10111.
[0030]
The disk protocol control unit 1012 controls access to the internal backup disk 1013 via the backup disk connection unit 1015 based on SCSI, Fiber Channel, or the like, and stores data stored in the memory module 1011 in the internal backup disk 1013. To control the backup of the data in the memory module 1011. Also, restoration control for returning the backed up data to the memory module 1011 is performed.
[0031]
The emergency backup control unit 1014 receives the signal from the SVP 105, and controls the memory control unit 1010 and the disk protocol control unit 1012 to perform the backup process or the restore process.
[0032]
Unlike the cache memory unit 101, the shared memory unit 102 stores control information on the disk array control device 10, but its hardware configuration is the same as that of the cache memory unit 101 described above. I do.
[0033]
FIG. 3 is a block diagram illustrating a detailed configuration of the power supply device 106, the memory unit power supply device 107, and the SVP 105.
[0034]
The power supply device 106 receives power supply from the power supply 2 (for example, commercial power supply) and supplies power to the disk array control device 10 and the disk device 20. The power supply device 106 includes a battery 1061. When a short-time power supply stop or power cut-off occurs in the power supply 2, the power supply device 106 supplies power to the disk array control device 10 and the disk device 20 within the power supply time from the battery. Supply power.
[0035]
The memory unit power supply device 107 receives power supply from the power supply 2 and supplies power to the cache memory unit 101 and the shared memory unit 102. The power supply device 107 for the memory unit includes a battery 1071. When the power supply 2 is stopped or shut down for a short time, the power is supplied to the cache memory unit 101 and the shared memory unit 102 within the battery supply time. Supply. Since the power supply unit 107 for the memory unit that supplies power only to a limited range such as the cache memory unit 101 and the shared memory unit 102 is used, the current required for the power supply unit 107 for the memory unit at the time of the occurrence of a power failure can be small. . Note that even when only the power supply device 106 is provided, the same can be achieved by switching means (not shown) for switching the power supply range.
[0036]
The SVP 105 is a control device that manages the disk array control device 10, is connected to the power supply 106 via the power supply communication unit 1062, and is connected to the memory unit power supply 107 via the power supply communication unit 1072. It monitors the state of each power supply device (for example, the voltage state or the occurrence of a short-time power-off or power-off).
[0037]
The SVP 105 is connected to each module of the cache memory unit 101, the shared memory unit 102, the channel control unit 103, and the disk control unit 104 via the SVP connection unit 1052, and in the case of power interruption or manual emergency shutdown instruction. When this is done, an emergency shutdown is notified to the entire disk array controller 10 to cause each unit to perform termination processing and backup processing.
[0038]
FIG. 4 is a block diagram illustrating a detailed configuration of the channel control unit 103.
[0039]
The channel interface (channel IF) 1032 is connected to the channel 11 connected to the external host computer 1. The cache memory access path interface unit (cache memory access path IF unit) 1033 is connected to the interconnection network 105 inside the disk array control device 10. The shared memory access path interface unit (shared memory access path IF unit) 1036 is connected to the interconnection network 106 inside the disk array controller 10. The channel IF section 1032, the cache memory access path IF section 1033, the shared memory access path IF section 1036, and the processor peripheral control section 1035 are mutually connected.
[0040]
The processor 1031 is connected to the channel IF unit 1032, the cache memory access path IF unit 1033, and the shared memory access path IF unit 1036 via the processor peripheral control unit 1035, and the channel IF unit 1032, the cache memory access path IF unit 1033 The shared memory access path IF unit 1036 is controlled by the processor 1031. A local memory 1034 is connected to the processor 1031. The local memory 1034 stores a control program and control information for the processor 1031 and also functions as a buffer for temporarily storing data communicated between the channel 11 and the interconnection networks 105 and 106 (access paths). I do.
[0041]
FIG. 5 is a block diagram showing a detailed configuration of the disk control unit 104.
[0042]
The disk-side channel interface unit (disk-side channel IF unit) 1042 is connected to the disk device 20 via the disk-side channel 12.
[0043]
The cache memory access path interface unit (cache memory access path IF unit) 1043 is connected to the interconnection network 105 via the cache memory access path 1047. The interconnection network 105 is connected to the cache memory unit 101, and the disk control unit 104 controls the input and output of data between the cache memory unit 101 and the disk device 20. The cache memory access path IF unit 1043 and the disk-side channel IF unit 1042 are directly connected by a data line 1049, and can transfer large-sized data at high speed.
[0044]
The shared memory access path IF unit 1046 is connected to the interconnection network 106 via the shared memory access path 1048. The interconnection network 106 is connected to the shared memory unit 102, and the disk control unit 104 includes cache directory information, channel control unit 103, which is control information on the disk array control device 10 stored in the shared memory unit 102. The disk device 20 is controlled using job information for cooperation, volume configuration information, and the like.
[0045]
The processor 1041 is connected to the disk-side channel IF unit 1042, the cache memory access path IF unit 1043, and the shared memory access path IF unit 1046 via the processor peripheral control unit 1045, and the disk-side channel IF unit 1042, the cache memory access The path IF unit 1043 and the shared memory access path IF unit 1046 are controlled by the processor 1041.
[0046]
Further, a local memory 1044 is connected to the processor 1041 via a processor peripheral control unit 1045. The local memory 1044 stores a control program and control information of the processor 1041, and also functions as a buffer for temporarily storing data communicated between the disk-side channel 12 and the access paths 1047 and 1048.
[0047]
Next, the operation of the disk array control device according to the first embodiment will be described with reference to the drawings.
[0048]
FIG. 6 is a flowchart illustrating a process performed when a power shutdown or the like occurs.
[0049]
According to the present invention, when an abnormality such as power interruption occurs, the data of the cache memory unit 101 and the shared memory unit 102 of the disk array control device 10 within the storage time of the battery 1071 provided in the memory unit power supply device 107 are maintained. The data is backed up to the built-in disks 1013 and 1023.
[0050]
The SVP 105 constantly monitors the power supply 106. That is, the continuous power outage time of the power supply device 106 is compared with a preset time, and when the continuous power outage time is equal to or longer than the preset time, or by an instruction from the host computer 1 or an operation of a switch, etc. When the generated emergency backup command is received by the SVP 105, the emergency backup process is started (process 601).
[0051]
When the emergency backup process is started, an operation stop request is transmitted to the channel control unit 103 and the disk control unit 104, and the channel control unit 103 and the disk control unit 104 start the emergency operation stop process (process 602). The channel control unit 103 and the disk control unit 104 that have received the backup request signal perform an emergency operation stop process. In this emergency operation stop processing, the transmission and reception of the data being processed between the host computer and the disk device are normally completed, and even if the operation is resumed, the data in the cache and the disk are kept in a consistent state. The operation of the control unit 103 and the disk control unit 104 is stopped (process 603). Details of the emergency operation stop processing will be described later with reference to FIG.
[0052]
Upon receiving the notification of the completion of the emergency operation stop processing from the channel control unit 103 and the disk control unit 104, the SVP 105 confirms that the operation of the channel control unit 103 and the disk control unit 104 has stopped (step 604).
[0053]
Upon confirming the notification of the completion of the operation stop processing in step 604, the SVP 105 stops power supply from the battery provided in the power supply unit 106 to the channel control unit 103 and the disk control unit 104 (step 605).
[0054]
Next, a backup request is transmitted to the cache memory unit 101 and the shared memory unit 102, and the cache memory unit 101 and the shared memory unit 102 start a backup process (process 606). The cache memory unit 101 and the shared memory unit 102 that have received the backup request signal perform a backup process and stop the operations of the cache memory unit 101 and the shared memory unit 102 (process 607). The details of this backup processing will be described later with reference to FIG.
[0055]
As described above, since the contents stored in the cache memory unit 101 and the shared memory unit 102 are backed up without using the normal destaging operation, both a quick backup process and a device configuration using a small-capacity power supply device are realized. can do.
[0056]
Upon receiving the notification of the end of the backup process from the cache memory unit 101 and the shared memory unit 102 (process 608), the SVP 105 supplies power to the cache memory unit 101 and the shared memory unit 102 from the battery of the memory unit power supply unit 107. It stops (process 609).
[0057]
With the above processing, the emergency backup processing of the disk array control device 10 ends.
[0058]
FIG. 7 is a flowchart showing the emergency operation stop process of the channel control unit 103 and the disk control unit 104 in the process 603 of FIG.
[0059]
When receiving the operation stop request from the SVP 105 (process 701), the channel control unit 103 and the disk control unit 104 complete the transfer of the data currently stored in the queue, and end the process currently being executed (process 702).
[0060]
Next, in the present embodiment, in order to smoothly resume the operation, the temporary state of the processor in the channel control unit 103 and the disk control unit 104 is stored. The contents of the local memory 1034 in the channel control unit 103 and the contents of the local memory 1044 in the disk control unit 104 are transmitted to the cache memory unit 101 or the shared memory unit 102, and the memory modules of the cache memory unit 101 or the shared memory unit 102 are transmitted. It is stored in a predetermined area of 1011, 1021 (process 703).
[0061]
When the emergency operation stop process ends, the channel control unit 103 and the disk control unit 104 notify the SVP 105 of the end of the emergency operation stop process (process 704).
[0062]
FIG. 8 is a flowchart showing details of the backup process of the cache memory unit 101 and the shared memory unit 102 in the process 607 of FIG.
[0063]
Upon receiving the backup request from the SVP 105 (process 801), the cache memory unit 101 and the shared memory unit 102 immediately store the data stored in the memory module 1011 in the internal backup disk 1012 and store the data in the memory module 1021. The stored data is stored in the built-in backup disk 1022. The data is stored in the internal backup disks 1013 and 1023 by sequentially writing (dumping) the storage contents of the memory modules 1011 and 1021 from a predetermined address (process 802). As described above, by sequentially writing the storage contents of the memory modules 1011 and 1021 to the internal backup disks 1012 and 1022 from a predetermined address, the burst function of the memory module can be used and the seek operation of the backup disk does not occur. The data can be copied at high speed from the memory modules 1011 and 1021 to the built-in backup disks 1012 and 1022 without requiring complicated processing for data copying.
[0064]
When the writing of the data in the memory by the dump is completed, the cache memory unit 101 and the shared memory unit 102 notify the SVP 105 of the end of the backup process (process 803).
[0065]
FIG. 9 is a flowchart showing a process when the power is restored and the disk array controller 10 resumes the operation.
[0066]
First, when the supply of power from the power supply device is restarted and a manual restart instruction is issued from the host computer 1 (process 901), the SVP 105 checks each module (the cache memory unit 101, the shared memory unit 102, the channel control unit). 103 and the disk control unit 104) and whether or not the state of the power supply unit 106 is normal (processing 902).
[0067]
When it is confirmed that each module and each power supply can operate normally, first, a memory content recovery command is issued to the cache memory unit 101 and the shared memory unit 102 (process 903).
[0068]
The cache memory unit 101 and the shared memory unit 102 that have received the memory content recovery instruction write the data backed up in the built-in backup disks 1012 and 1022 back to the memory modules 1011 and 1021 again, and the cache memory unit 101 and the shared memory unit 102 To the state before the execution of the above-described backup processing (FIG. 8). When the data is normally written back and the memory modules 1011 and 1021 return to the state before the backup processing, the memory control units 1010 and 1020 notify the SVP 105 of the recovery of the memory contents.
[0069]
When the SVP 105 confirms the restoration of the contents of the memory modules 1011 and 1021 of the cache memory unit 101 and the shared memory unit 102 by the memory contents restoration notification (process 904), the SVP 105 normally operates the channel control unit 103 and the disk control unit 104. A restart instruction is issued (process 905).
[0070]
In the present embodiment, the channel control unit 103 and the disk control unit 104, which have received the normal operation restart instruction, transfer the data (the data stored in the processing 703 in FIG. 7) stored in the cache memory unit 101 or the shared memory unit 102. The restoration processing is performed by writing back to the local memories 1034 and 1044 to return the channel control unit 103 and the disk control unit 104 to the state before the execution of the above-described emergency operation stop processing (FIG. 7). When the data is normally written back and the local memories 1034 and 1044 of the channel control unit 103 and the disk control unit 104 return to the state before the emergency operation stop processing, the channel control unit 103 and the disk control unit 104 Notify the restoration of the contents.
[0071]
When the SVP 105 confirms that the memory contents of all the channel control units 103 and the disk control units 104 have been restored (writing back the memory contents) (step 906), the SVP 105 restarts the operation of the channel control units 103 and the disk control units 104. An instruction is issued (process 907).
[0072]
With the above processing, the operation of the disk array control device 10 is restarted.
[0073]
As described above, the disk array control device according to the first embodiment includes the built-in backup disks 1013 and 1023 in the cache memory unit 101 and the shared memory unit 102. The contents of the units 101 and 102 are dumped and backed up to the internal backup disks 1013 and 1023 without passing through the disk control unit 104. That is, when the power is shut down, the contents of the cache memory are directly backed up to the backup disk, so there is no need to destage the cache contents when a power failure occurs, and the time required for the backup can be reduced. Since the range of power supply can be limited, the capacity of the battery can be reduced. In addition, since the capacity of the battery that supplies power to the device when a power failure occurs can be small, the installation area of the disk array control device 10 can be reduced, and the accompanying increase in cost can be suppressed. Further, a significant change of the system is not required from the conventional disk array device, and the design cost can be reduced. In addition, a shared memory for storing control information commonly used in the disk control device is provided, and configuration information of the disk device, job information, and directory information of cache data can be backed up. You can recover.
[0074]
FIGS. 10 and 11 are explanatory diagrams of the cache memory unit 101 of the disk array control device according to the second embodiment. FIG. 10 is a block diagram showing a detailed configuration of the cache memory unit 101. 11 is an explanatory diagram of a storage area of the memory module 1011 of the cache memory unit 101 and the backup disk 1024.
[0075]
In the disk array control device 10 according to the second embodiment, the internal backup disk 1013 is not provided in the cache memory unit 101 but the backup disk 1024 is provided outside the cache memory unit 101, as compared with the first embodiment. And that the backup disk 1024 can be used not only as a backup of data in the cache memory but also as a virtual memory. Note that the same reference numerals are given to components having the same functions as in the first embodiment, and description thereof will be omitted.
[0076]
The cache memory unit 101 provided in the disk array control device 10 temporarily stores data necessary for processing an input / output request from the host computer 1 among the data stored in the disk device 20, The purpose is to improve the processing speed of the entire system by reading and writing to the memory module 1011 that can be accessed at a higher speed than the device 20.
[0077]
In the disk array control device 10 according to the second embodiment, a backup disk is not provided in the cache memory unit 101, but a backup disk 1024 is provided outside the cache memory unit 101. Correspondingly, the backup disk connection means 1015 is connected to the backup disk 1024, and is provided so that the data to be backed up by the backup disk connection means 1015 is output to the outside of the cache memory unit 101.
[0078]
The backup disk 1024 has a capacity (address area) sufficiently larger than that of the memory module 1011. When the available address area of the memory module 1011 is 0 to x (FIG. 11A), the area of 0 to x in the available address area (0 to y) of the backup disk device 1024 is backed up by the memory module 1011. The area is allocated as an area 10241, and the remaining areas x to y are used as a virtual memory area 10242 (FIG. 11B). Among the data stored in the cache memory unit 101 and the shared memory unit 102, there is a type of data whose speed is relatively low (for example, configuration information). If such data is allocated to the virtual memory area, the backup disk 1024 is less expensive than the memory module 1011 and the size of the device does not increase even if the capacity of the backup disk is increased. The capacity can be easily increased.
[0079]
The memory control unit 1010 is connected to the disk protocol control unit 1012. The memory control unit 1010 is provided with an address determination unit 10103 in addition to the access path control unit 10101 and the memory module control unit 10102. The address determination unit 10103 determines the correspondence between the address area of the backup disk 1024 and the address area of the memory module 1011.
[0080]
Since the data stored in the virtual memory of the backup disk 1024 does not need to be backed up in an emergency, the time required for the backup process when the power is turned off does not increase, and the capacity of the battery 1061 of the power supply device 106 is reduced. No need to increase.
[0081]
FIG. 12 is a block diagram illustrating an outline of the disk array control device according to the third embodiment.
[0082]
In the first embodiment, data is communicated within the disk array controller 10 via the interconnection networks 105 and 106. The interconnection networks 105 and 106 are configured by crossbar switches. However, the difference is that the disk array control device of the third embodiment communicates data using the shared bus 109. The cache memory unit 101 is connected to the shared bus 109.
[0083]
In the first embodiment, the control information is configured to be stored in the shared memory unit 102. However, in the third embodiment, the control information is stored in the memory module 1011 in the cache memory unit 101. The difference is in the configuration. The memory module 1011 includes an area for storing cache data 10111 and an area for storing control information 10112.
[0084]
The operation of the other components is the same as that of the disk array control device 10 according to the first embodiment, and a detailed description of each component will be omitted.
[0085]
As described above, in the third embodiment, the shared bus is used, the shared memory unit 102 is not provided, and the control information is stored in the cache memory unit 101. Therefore, the effects of the first embodiment are reduced. In addition, the disk array controller 10 can be simplified.
[0086]
FIG. 13 is a block diagram illustrating an outline of the disk array control device according to the fourth embodiment.
[0087]
The disk array control device 10 according to the fourth embodiment is different from the first embodiment in that backup disks for the cache memory unit 101 and the shared memory unit 102 are provided outside the disk array control device 10. I do. The backup disks 1014 and 1024 are installed in the same housing as the disk device 20, for example. Note that the same reference numerals are given to components having the same functions as in the first embodiment, and description thereof will be omitted.
[0088]
The backup disk 1014 is connected to the disk protocol control unit 1012 of the cache memory unit 101, and backs up and stores data stored in the memory module 1011 of the cache memory unit 101.
[0089]
The backup disk 1024 is connected to the disk protocol control unit 1022 of the shared memory unit 102, and backs up and stores data stored in the memory module 1021 of the shared memory unit 102.
[0090]
The backup disks 1014 and 1024 are supplied with power from the power supply unit 107 for the memory unit.
[0091]
As described above, in the fourth embodiment, the disk array control device 10 can be made smaller by providing a backup disk outside the cache memory unit 101 and the shared memory unit 102. In comparison, the installation area of the disk array control device 10 can be reduced, the accompanying increase in cost can be suppressed, and maintenance work such as replacement and inspection of a backup disk can be facilitated.
[0092]
FIG. 14 is a block diagram illustrating a modification of the disk array control device according to the fourth embodiment.
[0093]
The cache memory unit 101 is connected to the backup disk 1014 by duplicating the backup disk connection means.
[0094]
Also, two backup disks 1024 are connected to the shared memory unit 102, and the storage contents of the memory module 1021 are duplicated and backed up.
[0095]
A part of the disk device 20 is used as a backup disk, a backup area is provided in the backup disk, and the backup disk is connected to the disk protocol control unit 1012 of the cache memory unit 101. The storage contents of the memory module 1011 may be stored and backed up.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an outline of a disk array device according to a first embodiment.
FIG. 2 is a block diagram illustrating a detailed configuration of a cache memory unit 101.
FIG. 3 is a block diagram illustrating a detailed configuration of a power supply unit 106, a memory unit power supply unit 107, and an SVP 105.
FIG. 4 is a block diagram illustrating a detailed configuration of a channel control unit 103.
FIG. 5 is a block diagram showing a detailed configuration of a disk control unit 104.
FIG. 6 is a flowchart illustrating a process in a case where power interruption occurs.
FIG. 7 is a flowchart illustrating an emergency operation stop process of the channel control unit 103 and the disk control unit 104.
FIG. 8 is a flowchart illustrating a backup process of the cache memory unit 101 and the shared memory unit 102.
FIG. 9 is a flowchart showing processing when the disk array control device 10 resumes operation.
FIG. 10 is a block diagram illustrating a configuration of a cache memory unit 101 of a disk array control device according to a second embodiment.
FIG. 11 is an explanatory diagram of storage areas of a memory module 1011 and a backup disk 1024 according to the second embodiment.
FIG. 12 is a block diagram illustrating an outline of a disk array control device according to a third embodiment.
FIG. 13 is a block diagram illustrating an outline of a disk array control device according to a fourth embodiment.
FIG. 14 is a block diagram illustrating a modification of the disk array control device according to the fourth embodiment.
FIG. 15 is a block diagram showing a configuration of a conventional disk array device.
[Explanation of symbols]
1 Host computer
10 Disk array controller
11 channels
12 Disk side channel
13 Backup dual-purpose disk
20 disk unit
101 Cache memory unit
102 Shared memory section
103 Channel control unit
104 Disk control unit
105 Interconnection network
106 interconnection network
106 power supply
107 Power supply for memory unit
109 Shared Bus

Claims (16)

A channel control unit that controls a channel connected to the host computer and performing communication,
A disk control unit that controls the disk device;
A cache memory unit that temporarily stores data transferred between the channel control unit and the disk control unit, wherein the channel control unit includes the channel, the cache memory unit, Transfer data between
The disk control unit transfers data between the disk device and the cache memory unit,
The cache memory unit includes a connection unit that connects a backup disk that stores data stored in the cache memory unit,
When the external power supply is shut off,
Outputting the data stored in the cache memory unit to the connection unit,
A disk array control device, wherein data stored in the cache memory unit is stored in the backup disk without using the disk control unit. 2. The disk array control device according to claim 1, wherein the backup disk is installed in the cache memory unit. 2. The disk array control device according to claim 1, wherein the backup disk is installed outside the cache memory unit. A battery that supplies power to the cache memory unit when power supplied from the outside is shut off,
When the power supplied from the outside is cut off, the cache memory unit and the backup disk are operated by the power supply from the battery, and the data stored in the cache memory unit is stored in the backup disk. The disk array control device according to claim 1, wherein: The battery is
A first battery that supplies power to the cache memory unit and the backup disk when power supplied from the outside is shut off;
The disk array device according to claim 4, further comprising: a second battery that supplies power to the disk device when power supplied from the outside is cut off. When the power supplied from the outside is cut off, the operation of the cache memory unit supplied from the first battery is stopped after the processing of the disk device supplied from the second battery is completed. The disk array control device according to claim 5, wherein The data stored in the cache memory unit is stored in the backup disk by a signal input from the outside, regardless of whether or not power is supplied from the outside. 3. The disk array control device according to 1. 8. The disk array control device according to claim 1, wherein the data stored in the cache memory unit is sequentially read from a predetermined address of the data and stored in the backup disk. 9. The disk array control device according to claim 1, wherein a part of the backup disk is used as a virtual memory. A shared memory unit that stores control information of the disk array device,
The shared memory unit includes connection means for connecting the backup disk,
When the external power supply is shut off,
Outputting the data stored in the shared memory unit to the connection unit,
10. The disk array control device according to claim 1, wherein the data stored in the shared memory unit is stored in the backup disk without using the disk control unit. The backup disk is configured by a first backup disk that stores data stored in the cache memory unit and a second backup disk that stores data stored in the shared memory unit. The disk array device according to claim 10, wherein The first backup disk is installed in the cache memory unit,
12. The disk array device according to claim 11, wherein the second backup disk is installed in the shared memory unit. A channel control unit that controls a channel connected to the host computer and performing communication,
A disk control unit that controls the disk device;
A cache memory unit for temporarily storing data transferred between the channel control unit and the disk control unit,
The channel control unit transfers data between the channel and the cache memory unit;
The disk control unit transfers data between the disk device and the cache memory unit,
In the data backup method used in a disk array control device, the cache memory unit includes a connection unit that connects a backup disk that stores data stored in the cache memory unit.
When the external power supply is shut off,
A data backup method, wherein storage contents of the cache memory and the shared memory are stored in the backup disk. When the external power supply is shut off,
After storing the storage contents of the channel control unit and the disk control unit in the cache memory unit or the shared memory unit,
14. The data backup method according to claim 13, wherein storage contents of the cache memory and the shared memory are stored in the backup disk. A channel control unit that controls a channel connected to the host computer and performing communication,
A disk control unit that controls the disk device;
A cache memory unit for temporarily storing data transferred between the channel control unit and the disk control unit,
The channel control unit transfers data between the channel and the cache memory unit;
The disk control unit transfers data between the disk device and the cache memory unit,
In the data restoration method used in the disk array control device, the cache memory unit includes a connection unit that connects a backup disk that stores data stored in the cache memory unit.
When the external power supply is restored,
A data restoration method comprising: reading data from the cache memory unit or the shared memory unit; and restoring storage contents of the channel control unit and the disk control unit. When the external power supply is restored,
After reading data from the backup disk and restoring the storage contents of the cache memory and the shared memory,
16. The data restoration method according to claim 15, wherein data is read from the cache memory unit or the shared memory unit, and the storage contents of the channel control unit and the disk control unit are restored.

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