JP2004103899A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein increase of resistance value of a diffusion layer can be restrained by restraining the etching of a silicon substrate by substrate cleaning. <P>SOLUTION: An insulating film 105 for a side wall is deposited on a silicon substrate 101 on which a gate electrode 103 is formed. The film 105 is subjected to anisotropic dry etching, and a side wall insulating film 106 is formed on a side surface of the gate electrode 103. Further, a plasma treatment using fluorocarbon gas is performed, carbon is driven into a surface of a silicon substrate 101, and a surface protective layer 113 is formed. Ion implantation 108 of n-type impurities is performed, and an n-type extension region 109 is formed. After that, APM cleaning is performed, and contamination adhering to the surface of the substrate is eliminated. At this time, etching of the silicon substrate 101 is restrained by the surface protective layer 113. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device capable of suppressing etching of a silicon substrate surface due to surface cleaning.
[0002]
[Prior art]
In order to meet the demand for higher integration of MIS type semiconductor devices, the gate length of MIS transistors has been reduced. In such a miniaturized MIS transistor, the extension region which is a part of the source / drain region formed below the end of the gate electrode has a shallow junction with the surface region of the silicon substrate using low-energy ion implantation. (See, for example, Patent Document 1).
[0003]
3A to 3D and 4A to 4C are cross-sectional views showing the steps of manufacturing a conventional semiconductor device.
[0004]
First, in the step shown in FIG. 3 (a), on a silicon substrate 301, an element isolation insulating film 304 of trench partitioning the nMIS transistor forming region _{R TN} and pMIS transistor forming region _{R TP.} Thereafter, a gate insulating film 302 made of, for example, a silicon oxide film and a polysilicon film are sequentially formed on the entire surface of the silicon substrate 301, and then the polysilicon film is patterned by a dry etching method or the like, thereby forming the nMIS transistor and the pMIS transistor. Each gate electrode 303 is formed.
[0005]
Next, in a step shown in FIG. 3B, a sidewall insulating film 305 made of a silicon oxide film is deposited on the entire surface of the substrate by a CVD method. Thus, the overall nMIS transistor forming region _{R TN} and pMIS transistor forming region _{R TP} including the gate electrode 303 is covered with the sidewall insulating film 305.
[0006]
Next, in the step shown in FIG. 3C, anisotropic dry etching of the side wall insulating film 305 is performed using CF ₄ / O ₂ / Ar gas, and a side wall insulating film is selectively formed on the side surface of the gate electrode 303. A film 306 is formed. At this time, in the dry etching using CF ₄ / O ₂ / Ar gas, since the etching rate for the deposition film generated by the dry etching is high, the deposition film is hardly formed on the surface of the silicon substrate 301 in the source / drain formation region. It is not formed and the silicon surface is exposed.
[0007]
Next, in the step shown in FIG. 3 (d), has an opening on the nMIS transistor forming region _{R TN,} a resist mask 307 covering the pMIS transistor forming region _{R TP.} Thereafter, arsenic (As ⁺ ) ions 308 as an n-type impurity are implanted with an implantation energy of about 5 keV and a dose of 5 × 10 ^{14 to} 5 × 10 ^{15 using} the gate electrode 303, the sidewall insulating film 306, and the resist mask 307 as a mask. / by ion implantation under conditions of cm ^2, to form an n-type extension regions 309 in the nMIS transistor forming region _{R TN.}
[0008]
Next, in the step shown in FIG. 4A, after removing the resist mask 307, foreign substances adhering to the substrate surface are removed by performing APM (aqueous ammonia hydrogen peroxide solution) cleaning for about 10 minutes. .
[0009]
Next, in the step shown in FIG. 4 (b), has an opening on the pMIS transistor forming region _{R TP,} a resist mask 310 covering the nMIS transistor forming region _{R TN.} After that, using the gate electrode 303, the sidewall insulating film 306, and the resist mask 310 as masks, boron (B ⁺ ) ions 311 as p-type impurities are implanted at an implantation energy of about 1 keV and a dose of 8 × 10 ^{13 to} 6 × 10 ^14. / by ion implantation under conditions of cm ^2, to form a p-type extension regions 312 in the pMIS transistor forming region _{R TP.}
[0010]
Next, in the step shown in FIG. 4C, after removing the resist mask 310, APM (aqueous ammonia hydrogen peroxide solution) cleaning is performed for about 10 minutes to remove foreign substances adhering to the substrate surface. .
[0011]
[Patent Document 1]
JP-A-2000-91290 (page 6, FIG. 1)
[0012]
[Problems to be solved by the invention]
However, the conventional method for manufacturing a semiconductor device as described above has the following disadvantages.
[0013]
In the step of FIG. 4A, after removing the resist mask 307 used as an implantation mask for the n-type extension region 309, APM cleaning is performed to remove foreign substances adhering to the surface of the silicon substrate 301. The surface of the silicon substrate 301 exposed by the APM cleaning is etched. Similarly, also in the step of FIG. 4C, after removing the resist mask 310 used as the implantation mask in the p-type extension region 312, APM cleaning is performed to remove foreign substances adhering to the surface of the silicon substrate 301. Then, the surface of the silicon substrate 301 exposed by the APM cleaning is etched.
[0014]
When the surface of the silicon substrate 301 is etched by the APM cleaning, the surface regions of the n-type extension region 309 and the p-type extension region 312 are etched. There is a problem that the value increases.
[0015]
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing etching of a silicon substrate due to substrate cleaning and reducing an increase in resistance value of a diffusion layer.
[0016]
[Means for Solving the Problems]
The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a surface protection layer containing carbon on a silicon substrate, and a step (b) of forming a diffusion layer on the silicon substrate after the step (a). After the step (b), a step (c) of wet cleaning the silicon substrate with the surface protective layer formed is provided.
[0017]
With this configuration, when performing wet cleaning, the etching of the silicon substrate is suppressed by the surface protection layer, so that an increase in the resistance value of the diffusion layer can be reduced.
[0018]
The method for manufacturing a semiconductor device includes, before the step (a), a step of forming a gate electrode on a silicon substrate and a step of forming a sidewall insulating film on a side surface of the gate electrode. Using the gate electrode and the sidewall insulating film as a mask, a diffusion layer is formed by ion implantation.
[0019]
In the method of manufacturing a semiconductor device, the step of forming the sidewall insulating film may include forming the sidewall insulating film on the silicon substrate on which the gate electrode is formed, and then performing dry etching using a first fluorocarbon gas. The sidewall insulating film is formed by etching the insulating film for use.
[0020]
In the method for manufacturing a semiconductor device, in the step (a), a surface protective film is formed using the first fluorocarbon gas used for forming the sidewall insulating film.
[0021]
In the method of manufacturing a semiconductor device, in the step (a), the surface protective layer is formed by a plasma treatment using a gas containing a second fluorocarbon. The gas containing the second fluorocarbon is a gas represented by CxFy composed of carbon and fluorine (x and y are natural numbers), and the ratio of carbon to fluorine is 3 ≧ y / x ≧ 1.5.
[0022]
In the method of manufacturing a semiconductor device, in the step (a), the surface protection layer may be formed by a plasma treatment using a CO gas.
[0023]
In the method of manufacturing a semiconductor device, in the step (a), the surface protection layer may be formed by performing a plasma treatment using a gas composed of carbon and hydrogen represented by CxHy (x and y are natural numbers). good.
[0024]
The thickness of the surface protective layer is preferably 1 nm or more and 4 nm or less.
[0025]
The wet cleaning is performed using an aqueous solution of ammonia and hydrogen peroxide.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0027]
FIGS. 1A to 1D and 2A to 2C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.
[0028]
First, in the step shown in FIG. 1 (a), on a silicon substrate 101, an element isolation insulating film 104 of trench partitioning the nMIS transistor forming region _{R TN} and pMIS transistor forming region _{R TP.} Thereafter, a gate insulating film 102 made of, for example, a silicon oxide film and a polysilicon film are sequentially formed on the entire surface of the silicon substrate 101, and then the polysilicon film is patterned by a dry etching method or the like, so that the nMIS transistor and the pMIS transistor are formed. Each gate electrode 103 is formed.
[0029]
Next, in a step shown in FIG. 1B, a sidewall insulating film 105 made of a silicon oxide film is deposited on the entire surface of the substrate by a CVD method. Thus, the overall nMIS transistor forming region _{R TN} and pMIS transistor forming region _{R TP} including the gate electrode 103 is covered with the sidewall insulating film 105.
[0030]
Next, in the step shown in FIG. 1C, anisotropic dry etching of the side wall insulating film 105 is performed using a fluorocarbon gas of CF ₄ / Ar gas, and a side wall insulating film is selectively formed on the side surface of the gate electrode 103. A film 106 is formed. At this time, when dry etching is performed using CF ₄ / Ar gas, the etching controllability can be improved because the etching rate for the side wall insulating film 105 is low. Further, after the silicon surface is exposed, overetching is performed using CF ₄ / Ar gas, whereby carbon in the plasma is implanted into the exposed surface of the silicon substrate 101 to form the surface protective layer 113. The surface protective layer 113 is a layer containing silicon and carbon, and preferably has a thickness of 1 nm or more and 4 nm or less.
[0031]
Next, in the step shown in FIG. 1 (d), has an opening on the nMIS transistor forming region _{R TN,} a resist mask 107 covering the pMIS transistor forming region _{R TP.} Thereafter, arsenic (As ⁺ ) ions 108, which are n-type impurities, are implanted with an implantation energy of about 5 keV and a dose of 5 × 10 ^{14 to} 5 × 10 ^{15 using} the gate electrode 103, the sidewall insulating film 106, and the resist mask 107 as a mask. / by ion implantation under conditions of cm ^2, to form an n-type extension regions 109 in the nMIS transistor forming region _{R TN.}
[0032]
Next, in the step shown in FIG. 2A, after removing the resist mask 107, foreign matter adhering to the substrate surface is removed by performing APM (aqueous ammonia hydrogen peroxide solution) cleaning for about 10 minutes. .
[0033]
Next, in the step shown in FIG. 2 (b), has an opening on the pMIS transistor forming region _{R TP,} a resist mask 110 covering the nMIS transistor forming region _{R TN.} Thereafter, using the gate electrode 103, the sidewall insulating film 106, and the resist mask 110 as masks, boron (B ⁺ ) ions 111, which are p-type impurities, are implanted at an energy of about 1 keV and a dose of 8 × 10 ^{13 to} 6 × 10 ^14. / by ion implantation under conditions of cm ^2, to form a p-type extension regions 112 in the pMIS transistor forming region _{R TP.}
[0034]
Next, in the step shown in FIG. 2C, after removing the resist mask 110, foreign matter adhering to the substrate surface is removed by performing APM (aqueous ammonia hydrogen peroxide solution) cleaning for about 10 minutes. .
[0035]
FIG. 5 is a correlation diagram showing the relationship between the APM cleaning time and the sheet resistance increase rate of the diffusion layer. The sheet resistance is obtained by measuring an n-type diffusion layer formed by implanting As ions under the conditions that the implantation energy is about 3 keV and the dose is 1 × 10 ¹⁵ / cm ² . In addition, the case where the plasma treatment is performed means that the treatment is performed for 5 seconds using CF ₄ gas as the plasma gas after the ion implantation.
[0036]
As shown in FIG. 5, in the conventional manufacturing method without performing the plasma treatment including carbon, the sheet resistance is increased by 7% by performing the APM cleaning for 10 minutes. On the other hand, it can be seen that the increase in the sheet resistance is reduced to about 5% by performing the plasma treatment containing carbon as in the present invention. This is because by performing the plasma treatment including carbon, a surface protection layer in which carbon is implanted is formed on the surface of the silicon substrate, and etching of the silicon substrate by APM cleaning is suppressed by the surface protection layer.
[0037]
Therefore, according to the present embodiment, since the surface protection layer containing carbon is formed on the surface of the silicon substrate after the extension is implanted, the etching of the silicon substrate by the APM cleaning can be suppressed. The increase in the value can be reduced.
[0038]
(Other embodiments)
In the above embodiment, in the step of forming the side wall insulating film 106, the anisotropic dry etching of the side wall insulating film 105 is performed using fluorocarbon gas of CF ₄ gas to expose the surface of the silicon substrate 101, and then the plasma is formed. The surface protection layer 113 is formed using CF ₄ gas as the gas.
[0039]
However, the present invention is not limited to the above embodiment. That is, when the surface protective layer 113 is formed, etching properties are not required, and any plasma gas containing carbon that can introduce carbon into the silicon substrate may be used.
[0040]
As a plasma gas for forming the surface protective layer, a fluorocarbon gas CxFy (x, y is a natural number) having a higher C / F ratio than that of CF ₄ gas, such as C ₄ F ₈ gas or C ₅ F ₈ gas, is used as the plasma gas. By using (3 ≧ y / x ≧ 1.5), a surface protective layer containing more carbon can be formed than by using CF ₄ gas. This surface protective layer is a layer containing more carbon, and can suppress etching of the silicon substrate in APM cleaning in a later step.
[0041]
Further, a CxHy gas (x and y are natural numbers) such as a CH ₄ gas may be used as a plasma gas for forming the surface protective layer. In this case, compared to the fluorocarbon gas as described above, since it does not contain fluorine, the silicon substrate is not etched by fluorine radicals generated in the plasma, and a surface protection layer into which carbon is implanted can be formed. This surface protection layer can also suppress the etching of the silicon substrate in the subsequent APM cleaning.
[0042]
Further, a CO gas may be used as a plasma gas for forming the surface protective layer. In this case, since a large amount of CO ⁺ ions are generated in the plasma, a surface protection layer mainly composed of SiOC into which carbon and oxygen are implanted can be formed on the silicon substrate. The surface protective layer is a layer containing silicon, carbon, and oxygen, and can suppress etching of the silicon substrate in APM cleaning in a later step.
[0043]
【The invention's effect】
According to the method of manufacturing a semiconductor device of the present invention, the surface protection layer containing carbon is formed in the surface region of the silicon substrate before the cleaning step, whereby the etching of the silicon substrate in the cleaning step can be suppressed. This suppresses a rise in the resistance value of the diffusion layer having a shallow junction formed in the silicon substrate, so that deterioration in transistor characteristics can be prevented.
[Brief description of the drawings]
FIGS. 1A to 1D are cross-sectional views showing a first half of a manufacturing process of a semiconductor device according to an embodiment of the present invention; FIGS. FIGS. 3A to 3D are cross-sectional views illustrating a first half of a manufacturing process of a conventional semiconductor device. FIGS. 3A to 3D are cross-sectional views illustrating a first half of a manufacturing process of a conventional semiconductor device. FIGS. FIGS. 5A to 5C are cross-sectional views showing a latter half of a conventional semiconductor device manufacturing process. FIG. 5 is a correlation diagram showing a relationship between an APM cleaning time and a sheet resistance increase rate.
Reference Signs List 101 silicon substrate 102 gate insulating film 103 gate electrode 104 element isolation insulating film 105 sidewall insulating film 106 sidewall insulating film 107 resist mask 108 n-type impurity ions 109 n-type extension region 110 resist mask 111 p-type impurity ions 112 p-type Extension area 113 Surface protective layer

Claims (10)

(A) forming a surface protection layer containing carbon on a silicon substrate;
A step (b) of forming a diffusion layer on the silicon substrate after the step (a);
And (c) wet-cleaning the silicon substrate with the surface protective layer formed after the step (b). The method for manufacturing a semiconductor device according to claim 1,
Prior to the step (a), a step of forming a gate electrode on the silicon substrate; and a step of forming a sidewall insulating film on a side surface of the gate electrode,
In the step (b), the diffusion layer is formed by ion implantation using the gate electrode and the sidewall insulating film as a mask. The method for manufacturing a semiconductor device according to claim 2,
The step of forming the sidewall insulating film includes forming a sidewall insulating film on the silicon substrate on which the gate electrode is formed, and then etching the sidewall insulating film by dry etching using a first fluorocarbon gas. Forming the side wall insulating film. The method for manufacturing a semiconductor device according to claim 3,
In the step (a), a method for manufacturing a semiconductor device, wherein the surface protective film is formed using the first fluorocarbon gas used for forming the sidewall insulating film. The method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein in the step (a), the surface protective layer is formed by a plasma treatment using a gas containing a second fluorocarbon. The method for manufacturing a semiconductor device according to claim 5,
The gas containing the second fluorocarbon is a gas represented by CxFy composed of carbon and fluorine (x and y are natural numbers), and the ratio of carbon to fluorine is 3 ≧ y / x ≧ 1.5. Manufacturing method of a semiconductor device. The method of manufacturing a semiconductor device according to claim 1,
In the method (a), the surface protection layer is formed by a plasma treatment using a CO gas. The method of manufacturing a semiconductor device according to claim 1,
In the step (a), the surface protective layer is formed by performing a plasma treatment using a gas composed of carbon and hydrogen represented by CxHy (x and y are natural numbers). . The method for manufacturing a semiconductor device according to claim 1, wherein
The method of manufacturing a semiconductor device, wherein the thickness of the surface protective layer is 1 nm or more and 4 nm or less. The method for manufacturing a semiconductor device according to claim 1, wherein
The method for manufacturing a semiconductor device, wherein the wet cleaning is performed using an aqueous solution of ammonia and hydrogen peroxide.

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