JP2004102867A - Hardware controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce software overhead by simplifying command processing between a hardware driver and control execution hardware. <P>SOLUTION: In this hardware controller which has a hardware driver having a memory and the control execution hardware for executing a command, and controls target hardware by the control execution hardware, the hardware driver analyzes a request from a host application, converts the request into a plurality of commands for controlling the target hardware, a control command table in which the commands are arranged is formed in the memory, the contents of the control command table are set in block by a group of registers provided in the control execution hardware and after that, the control execution hardware performs execution processing of the commands between it and the target hardware by referring to the contents of the group of registers. Thus, continuous execution of the commands by the control execution hardware becomes possible by making pieces of information set by every command execution into the control command table by the hardware driver and transferring the group of commands made into the table to the control execution hardware in block. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a hardware control device, and more particularly to a hardware control device that simplifies a command execution procedure in control execution hardware and reduces software overhead.
[0002]
[Prior art]
Generally, a large computer includes a service processor, a package for an arithmetic processing unit, a platter for an IO processor, and the like in its housing. The service processor includes a hardware driver and control execution hardware to control an arithmetic processing device which is hardware to be controlled.
[0003]
Conventionally, a hardware driver controls target hardware, for example, as shown in FIG. That is, the hardware driver analyzes a request from the host application and converts the request into a plurality of commands for the hardware to be controlled. The hardware driver sequentially executes these commands one by one. For one command execution, the hardware driver sets a command in a register of the control execution hardware and data such as a data storage area head address of transfer data and a data transfer length during data transfer processing, and activates the command. . When the command has been completed, the hardware driver performs a command completion check of the processing, and then executes the next command. Commands are sequentially executed by repeating such a procedure.
[0004]
In the data transfer process, if a FIFO (First In First Out) buffer exists on the target hardware side, the hardware driver divides the transfer data according to the size of the FIFO buffer and divides the data in units of the divided data. Controls the transfer process and activates the execution hardware. When one transfer process is completed, the hardware driver checks the status of the data transfer process. If the status check is completed normally, the hardware driver requests the next divided transfer data to the control execution hardware. Such a procedure must be repeated.
[0005]
[Problems to be solved by the invention]
An object of the present invention is to provide a hardware control device that simplifies a command processing procedure between a hardware driver and control execution hardware and reduces software overhead.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention relates to a hardware control device having a hardware driver having a memory and control execution hardware for executing a command, and controlling target hardware by the control execution hardware. The hardware driver analyzes a request from a higher-level application, converts the request into a plurality of commands for controlling the target hardware, forms a control command table in which these commands are arranged in a memory, and stores the contents of the control command table in a memory. The control execution hardware is set in a register group provided in the control execution hardware, and the control execution hardware is configured to execute a command execution process with the target hardware by referring to the contents of the register group thereafter. .
[0007]
According to the present invention, in addition to the command, the control command table is formed to include information indicating a data storage area start address and a data transfer length necessary for data transfer. Is set in the register group similarly to the command.
[0008]
Further, according to the present invention, when the control execution hardware continuously executes the commands set in the register group, the next command is executed if each command processing is normally completed, and the processing is executed if the command processing is abnormally ended. The information is interrupted and error information is notified to the hardware driver, and the hardware driver performs an error recovery process.
[0009]
Further, according to the present invention, when the target hardware has a data transfer FIFO buffer, the control execution hardware checks whether or not the data transfer process is normally completed every time the data transfer of the size of the FIFO buffer is completed. And a status check logic unit for checking the data transfer rate, and configured to continuously process data transfer processing exceeding the size of the FIFO buffer. Preferably, when the data transfer processing to the target hardware is executed, the control command table includes a control bit for switching the validity / invalidity of the check in the status check logic unit.
[0010]
As described above, according to the present invention, the information set by the hardware driver every time a command is executed is converted into a control command table (SCW), and the grouped commands are collectively transferred to the control execution hardware. Conventionally, commands that have been processed sporadically can be continuously executed by the control execution hardware.
[0011]
When a data transfer FIFO buffer exists on the target hardware side, the data transfer process can be performed smoothly. That is, conventionally, when the hardware driver determines that the data transfer amount exceeds the FIFO size, the hardware driver has to process the transfer data by dividing it according to the FIFO size. According to the present invention, by providing a status check permission bit in the control command table and incorporating status check logic in the control execution hardware, data transfer between the target hardware / hardware control device can be performed more smoothly. I can do it.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an information processing system to which a hardware control device according to one embodiment of the present invention is applied.
1, a computer 1 includes a service processor (SVP) 2, a processing unit (BPU) package 11, and a platter 16 for an IO processor in its housing. A console 10 is connected to the computer 1, and a command input, a display input, and control are performed on the computer 1 from the console 10.
[0013]
The service processor 2 includes an upper application 3, a hardware driver 4, and control execution hardware 6. The hardware driver 4 analyzes a request from the host application 3 and converts the request into a plurality of commands for the hardware to be controlled. The control execution hardware 6 controls the arithmetic processing unit 11 which is hardware to be controlled. The configurations of the hardware driver 4 and the control execution hardware 6 will be described later in detail with reference to FIG. The hardware driver 4 has a memory 5 and basically performs a function of executing a command. A feature of the embodiment of the present invention is that a control command table is formed in the memory 5, and information set by the hardware driver every time a command is executed is collected in the control command table (SCW). The configuration and operation of this table will be described later in detail.
[0014]
The control execution hardware 6 includes a bus control unit 7, a control register group 8, a command FIFO buffer 91, and a data FIFO buffer 92. The configuration of the register group 8 and related hardware will be described later.
The arithmetic processing unit 11 is hardware to be controlled, and includes a memory 12, a memory controller 13, and a processor module 14 including a plurality of processors 15. The memory 12 stores user application software, commands, an OS, and the like. The memory controller 13 has a plurality of paths in consideration of redundancy and load distribution. Note that the configuration of the arithmetic processing unit 11 as described above does not directly relate to the gist of the present invention.
The IO processor 16 includes a channel processor 17 and a plurality of channels 18 connected thereto. Input / output devices are connected to these channels 18.
[0015]
Next, a hardware control device according to an embodiment of the present invention will be described with reference to FIG.
When the hardware driver 4 receives an instruction from the host application 3, it analyzes the instruction and creates a control command table (SCW) 51 in the memory 5. The commands are arranged in the table 51 in the order in which the commands are executed. The write data 52 stores write data, and the read data 53 stores read data. Regarding the table 51, SCWAP indicates the head address of this table, and SCWWC indicates the table length. The ICMD is an immediate execution command, such as a reset command or a stop command when there is no data transfer. The command is, for example, 4 bytes / word, CMD-WR indicates a write command, and CMD-RD indicates a read command. If the command is a data transfer command, the data storage area start address and the data transfer length are also stored in the control command table 51. Addresses 1 to 3 indicate the head address of the data, and words 1 to 3 indicate the data length. Further, when the FIFO buffer on the target hardware side is used, the status check permission bit is set according to the transfer data amount.
[0016]
These commands created in the form of a table are collectively transferred to the control execution hardware 6. The control execution hardware 6 receives commands and write data via the bus control unit 7. The command is temporarily stored in a command buffer (FIFO) 91, then decoded by the decode logic unit 63, and set in an associated register of the register group 8. As a result of decoding, some of the commands are not set in the register group 8 but are set in the command register 64 and transferred to the arithmetic processing unit 11. The embodiment of the present invention is characterized by the processing of commands in a table. The start address register (SCWAP) 81 stores the start address of the table 51. The word number register (SCWWC) 82 stores the number of words, that is, the table length of the table 51. In this example, since one word is 4 bytes, the table length can be determined from the number of words. The start request register 83 indicates a start instruction. If the value of the start request register 83 is "1", the start is indicated. When the contents of the table are completely executed, "0" is written as the value. The data address register (DATAAP) 84 sets an address pointer of data, and sets addresses 1 to 3 in the table. The data word number register (DATAWC) 85 similarly sets words 1 to 3. The status check bit enable register (STRFLG) 86 is a bit for controlling whether to use the status check logic 62 or not. If this bit is "1", check logic 62 is used, while if "0", it is not used. The status information read command register (STRCMD) 87 is a command for reading status information.
The write data is set in a write data buffer (FIFO) 92 and then sent to the one-word write register 65 for transfer to the arithmetic processing unit 11.
[0017]
On the other hand, the read data from the arithmetic processing unit 11 is set in the one-word read register 66, then stored in a read buffer (FIFO) 93 and sent to the read data buffer 53 of the memory 5 via the bus control unit 7. . The result of the data transfer (such as error information) is set in the status register 67 via the register 66. The value is checked by the status check logic unit 62. Interrupt control is performed on the memory 5 via the interrupt control unit 61 according to the check result. The status check logic unit 62 will be described later in detail with reference to FIG.
[0018]
Next, the status check logic in the hardware control device will be described with reference to FIG.
The error state check logic has three types of check functions.
All check functions are based on the value of the status register 67 which reflects the result of data transfer (error information and the like). The three types of check functions are as follows.
(1) Match / mismatch determination between the value of the status register 67 and the compare value.
(2) Determine whether the value of the status register 67 is larger than the compare value.
(3) Processing interruption determination based on the determination result of the value of the status register 67 and the compare value.
As for the above (1) and (2), the results of both check functions are associated and output.
Since one register value is used in all the check functions, which bit in the register is used for each check function is determined by the values of the masks 620, 621, and 622. The value of the status register 67 is ANDed with the values of the masks 620, 621, and 622, and compared with the values of the comparisons 623, 624, and 629 to check.
The above (1) and (2) are logics for checking what value the value of the status register 67 takes to perform processing mainly continuously, and (3) detects an error and performs processing. Is used as logic for interrupting
[0019]
Each check function has Sel registers 625, 626, and 628, and the contents of determination are determined by the Sel registers 625, 626, and 628. The value of the Sel registers 625, 626, and 628 of each check function is 2 bits, and the meaning of each bit is as follows.
(A) Bit 0: Match determination valid. Bit 1: validity of mismatch determination.
(B) Bit 0: greater-than judgment valid. Bit 1: Less than judgment valid.
(C) Bit 0: match determination valid. Bit 1: validity of mismatch determination.
It has become.
If both bits of each Sel register 625, 626, 628 are "0", the corresponding check function is invalidated.
[0020]
As the value of the status register 67, the value read by the control execution hardware 6 is used, but the mask value, the compare value, and the Sel value are set by the hardware driver 4 according to the purpose.
The determination logic of the match / mismatch determination ANDs the value of the status register 67 with the mask 621, and if bit 0 of the Sel register 625 is "1", determines whether or not the value matches the value of the compare 623. If bit 1 of the Sel register 625 is “1”, it is determined whether the value does not match the value of the compare 623.
[0021]
The determination logic of the magnitude determination performs an AND operation between the value of the status register 67 and the mask 622, and if the bit 0 of the Sel register 626 is “1”, determines whether or not the value is greater than the value of the compare 624. If bit 1 of the Sel register 626 is “1”, it is determined whether the value is smaller than the value of the compare 624.
The association between the two determination results is performed by the Sel register 627. This register 627 has one bit, and if the bit is “0”, outputs the OR of the result of the match / mismatch determination and the result of the size determination. On the other hand, if the bit of the register 627 is “1”, AND of the result of the match / mismatch determination and the result of the size determination is output.
[0022]
The determination logic of the processing interruption determination ANDs the value of the status register 67 and the mask 620, and if bit 0 of the 2-bit Sel register 628 is "1", determines whether or not the value matches the value of the compare 629. If they match, the processing is stopped. If bit 1 of the Sel register 628 is “1”, it is determined whether or not the value matches the value of the compare 629. If not, the process is stopped.
[0023]
Next, the operation of the hardware control of FIG. 2 will be described with reference to the flowchart shown in FIG.
When the hardware driver 4 receives an instruction from the host application 3, it analyzes the instruction and creates a control command table 51 in the memory 5. Commands are arranged in the table 51 in the order of execution.
[0024]
In the case of a data transfer command, the data storage area start address and the data transfer length are also stored in the table 51. Further, when the target hardware FIFO is used, a status check permission bit is set according to the amount of transfer data. In the data transfer process, if a FIFO exists on the target hardware side, the hardware driver 4 determines whether the data transfer amount exceeds the FIFO size. If it is determined that the size exceeds the FIFO size, the status check permission bit in the table 51 is set.
[0025]
When the creation of the control command table 51 is completed, the hardware driver 4 sets the head address of the table 51 in the SCW start address register 81 and the number of words in the table 51 in the SCW word number register 82 of the control execution hardware 6. Also, a command for reading status information at the time of status check is set in the status information read command register 87, a mask value, a comparison value, and the like are set in the status check logic unit 62, a start bit is set in the SCW start request register 83, and then control is performed. Requests the execution hardware 6 to start processing the table. The control execution hardware 6 reads the contents of the table 51 into the command buffer (SCWFIFO) 91 via the BUS control unit 7 with reference to the contents of the start address register 81 and the word number register 82. Thereafter, the control execution hardware 6 reads the commands one by one from the command buffer 91 and decodes them by the decode logic unit 63. The decoding logic unit 63 determines whether the command is a single command or a data transfer command. As a result of the decoding, if the command is a one-time command, the command is set in the command register 64 and the command is executed on the target hardware. On the other hand, if the command is a data transfer command, the data storage area start address and the data transfer length are read from the command buffer 91, and the data address register 84, the data word number register 85, and the status check permission bit register 86 are set. Thereafter, in the case of the write processing, the write data is read from the memory 5 of the hardware driver 4 to the data buffer 92 with reference to the contents of the data address register 84 and the data word number register 85, and Start data transfer. In the case of the read processing, the data read into the read data buffer 93 is written into the memory 5 of the hardware driver 4 based on the data address register 84 and the data word number register 85.
[0026]
The control execution hardware 6 continuously performs the processing until the value of the word number register 82 becomes “0” (or until a command error is detected).
When the status check permission bit register 86 is set, the control execution hardware 6 uses the status information read command register 87 to read the status information. The read data is stored in the status register 67, and the status check logic unit 62 checks the status information. If there is no data to be checked, the next data transfer process is continued. For example, when the command processing data of the transfer data 1 divided into the FIFO size shown in FIG. 4 is exhausted, the command processing of the transfer data 2 and then the command processing of the transfer data 3 are performed in the order of the control execution hardware 6 and the target. Command execution processing is sequentially performed with the hardware (that is, the arithmetic processing unit 11). If there is check data in the status check logic unit 62, an error is returned to the hardware driver 4 via the interrupt control unit 61.
[0027]
As described above, according to the present embodiment, a command to be executed is made into a control command table by the hardware driver, and the command group in this table is sent to the control execution hardware collectively and set in the register group. Thereafter, the command execution processing can be continuously executed between the control execution hardware and the target hardware. For this reason, it is not necessary to perform a process related to command transfer between a hardware driver and control execution hardware as in the related art, and command processing is simplified. Further, since the hardware driver is released from individual command processing, software overhead in the hardware driver is significantly reduced.
[0028]
【The invention's effect】
As described above, according to the present invention, the control command of the hardware to be controlled is tabulated in the hardware driver, and the table is sent to the control execution hardware. You can rely on the interaction with the target hardware. Therefore, the procedure for command processing between the hardware driver and the control execution hardware can be simplified, and the software overhead can be greatly reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an information processing system to which a hardware control device according to an embodiment of the present invention is applied.
FIG. 2 is a block diagram showing a hardware control device according to one embodiment of the present invention.
FIG. 3 is a logic diagram for checking an error state in the status check logic of the hardware control device according to one embodiment of the present invention.
FIG. 4 is a flowchart showing a sequence of hardware control in the hardware control device according to one embodiment of the present invention.
FIG. 5 is a flowchart showing a sequence of hardware control according to the related art.
[Explanation of symbols]
1. Computer 2. Service processor 3. Upper application 4. Hardware driver 5. Memory 6. 6. Control execution hardware Bus control unit 8. Control register group 91. Command register 92. Data register 10. Console 11. Arithmetic processing unit 12. Memory 13. Memory controller 14. Processor module 15. Processor 16. IO processor 17. Channel processor 18. Channel 51. Control command table (SCW) 52. Write data 53. Read data 81. SCW start address register 82. SCW word number register 83. SCW start request register 84. Data address register 85. Data word number register 86. Status check enable bit register 87. Status information read command register 61. Interrupt control unit 62. Status check logic unit 63. Decode logic 64. Command register 65.1 word Write register 66.1 word Read register 67. Status register

Claims (5)

In a hardware control device having a hardware driver having a memory and control execution hardware for executing a command, and controlling the target hardware by the control execution hardware, the hardware driver receives a request from a host application. Analyzed and converted into a plurality of commands for controlling the target hardware, a control command table in which these commands are arranged is formed in the memory, and the contents of the control command table are provided in the control execution hardware. A hardware control device which is set in a register group, wherein the control execution hardware thereafter executes a command execution process with target hardware by referring to the contents of the register group. The control command table is formed to include, in addition to the command, information indicating a data storage area start address and a data transfer length necessary for data transfer, and the information indicating the start address and the data transfer length is the same as the command. 2. The hardware control device according to claim 1, wherein the hardware control device is set in the register group. When the control execution hardware continuously executes the command set in the register group, the next command is executed if each command processing is normally completed, and if the command processing is abnormally terminated, the processing is interrupted and the hardware is interrupted. 2. The hardware control device according to claim 1, wherein error information is notified to the driver, and the hardware driver performs an error recovery process. When the target hardware has a data transfer FIFO buffer, the control execution hardware checks whether or not the data transfer process has been completed normally every time the data transfer of the size of the FIFO buffer is completed. 2. The hardware control device according to claim 1, further comprising a status check logic unit for continuously transferring data exceeding the size of the FIFO buffer. 5. The hardware according to claim 4, wherein, when executing a data transfer process to the target hardware, the control command table includes a control bit for switching valid / invalid of a check in the status check logic unit. Wear control device.

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