JP2004102739A - Parasitic element extraction method and delay computing method using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for extracting inductance by reflecting an operating frequency of each circuit precisely in a parasitic element extraction of inductance having a frequency-dependent characteristics, and a method for computing delays, capable of precise timing identification. <P>SOLUTION: Based on resistance/capacity network and transistor information, a frequency component of wiring is obtained (step S1 and S2), and then inductance and resistance are obtained (step S3 and S4), enabling a precise resistance/inductance/capacity network to be obtained. When, based on that, screening or delay computation is conducted in steps (S5) to step (S8), timing identification of the semiconductor integrated circuit is carried out accurately, thereby facilitating LSI designing. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to timing design of a semiconductor integrated circuit, particularly to extraction of parasitic elements and calculation of delay.
[0002]
[Prior art]
In an LSI configured by connecting basic logic cells or functional macro blocks (hereinafter referred to as cells) by inter-cell wiring, the resistance is reduced by adopting a copper wiring process, and the operating frequency of the chip reaches the gigahertz (GHz) level. As the clock transition time is shortened and the signal transition time is shortened, the influence of inductance is becoming remarkable even in the wiring in the LSI.
[0003]
For this reason, it has become necessary to handle the circuit analysis when verifying the operation of the circuit with an RLC circuit model including an inductance, instead of an RC circuit model in which a wiring load is modeled by resistance and capacitance.
[0004]
However, it is currently difficult to extract the parasitic inductance for all the wirings in the LSI and calculate the delay using the RLC circuit model. The reason is that it is difficult to accurately extract the inductance because the current path needs to be predicted from the wiring structure, and the inductance is different from the capacitance and the shielding effect of the nearby conductor cannot be expected. Is larger than the RC circuit model.
[0005]
Inductance depends on frequency. Therefore, when performing delay evaluation using an RLC circuit model including an inductance, a frequency under a certain condition is often assumed at the time of extracting a parasitic element. The frequency is represented by an effective frequency (significant frequency) Fs. When the waveform used as an input signal to the wiring is a trapezoidal pulse, this is a frequency including 85% of a plurality of frequency components constituting the pulse, and using the rise time of the trapezoidal pulse: tr ( It is expressed by equation 1) (see FIG. 2).
[0006]
Fs = 0.34 / tr (Equation 1)
Conventionally, the effective frequency has been determined based on the operating frequency of a specific signal net such as a circuit, a clock or a bus that operates at the highest speed. That is, this is a design method in which the worst case is taken into account, representing the fastest signal in the circuit. For example, see Non-Patent Document 1 for calculation of wiring delay.
[0007]
[Non-patent document 1]
LAWRENCE T. PILLAGE, and one other person, "Asymptotical Waveform Evaluation for Timing Analysis", IEEE Transactions on Computer Aided Design, vol. 9 No. 4, April 1990, pp. 139-143. 352-366
[0008]
[Problems to be solved by the invention]
The following problems arise in the above method.
1) The operation of an actual LSI naturally differs depending on various types of circuits. The worst case would encompass it all, but would be too pessimistic because it would take a lot of design margin.
[0009]
2) Since a parasitic element is extracted only at a specific frequency in the first place, an accurate RLC network cannot be formed.
3) When the parasitic element is extracted including the inductance, it takes more time than when the parasitic element is not included.
[0010]
4) Since the RCL network from which the parasitic elements are extracted is not accurate, the delay calculation result also includes a large error.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a parasitic element extracting method that requires an accurate resistance / inductance / capacitance network of a semiconductor integrated circuit in a shorter time than before.
[0011]
It is another object of the present invention to provide a delay calculation method capable of accurately performing timing verification from an accurate delay calculation result of a semiconductor integrated circuit.
[0012]
[Means for Solving the Problems]
In order to solve the above problems, a first invention is a parasitic element extracting method for extracting an accurate RCL network. The method is to generate an RCL network after accurately obtaining the frequency of each wiring net. That is, first, delay calculation is once performed based on the result of the conventional RC network, the slope and rise time of the input waveform of each wiring net are obtained, and the effective frequency is obtained based on (Equation 1). The RLC network is extracted based on the information.
[0013]
In other words, this is a parasitic element extraction method for timing verification in a semiconductor integrated circuit configured by connecting basic logic cells or functional macro blocks (hereinafter, referred to as cells) by inter-cell wiring. The slope of the electric signal waveform on the input side is calculated, the effective frequency of the wiring is obtained based on the value, and the inductance is calculated based on the effective frequency, and the electrical parameters of resistance, inductance, and capacitance are obtained.
[0014]
More specifically, a wiring RC parasitic element extraction step of obtaining resistance and capacitance as electrical information from wiring layout information, resistance / capacity information obtained from the wiring RC parasitic element extraction step, and transistor driving capability information connected thereto Calculating the slope of the input-side waveform of each wiring to obtain the slope of the electrical signal waveform immediately below the transistor, and calculating the effective frequency from the slope value of the waveform obtained from the calculating step of the slope of the input-side waveform of each wiring. Based on the effective frequency of each wiring and the effective frequency of an electric signal flowing through each wiring obtained in the effective frequency calculating step of each wiring, resistance, inductance, and capacitance are obtained as electrical information from wiring layout information. And a wiring RLC parasitic element extraction step for determining
[0015]
In order to solve the above problems, the second invention is to extract a parasitic element by using an RCL network only in a case where a circuit analysis including an inductance is necessary in addition to the first invention in order to realize a reduction in processing time. This is a delay calculation method for calculating delay.
[0016]
Usually, whether or not the inductance needs to be considered can be specified by performing a procedure called screening. According to the present invention, the delay calculation is performed only by the RLC circuit when the screening condition is satisfied, and the delay calculation is performed by the RC circuit otherwise. Specifically, based on the values of the resistance, the inductance, and the capacitance obtained by the parasitic element extraction method of the first invention, an RLC screening check step of determining, for each wiring, whether or not to calculate the delay including the inductance, When the RLC screening check step determines that inductance needs to be considered, the wiring network calculates the delay in the delay step by the RLC circuit, and when it is determined that the inductance is not considered, calculates the delay in the delay calculation step by the RC circuit. And a delay result combining step of combining one result of the delay step by the RC circuit and one result of the delay step by the RLC circuit.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a parasitic element extraction method and a delay calculation method using the same according to the present invention will be described based on specific examples.
[0018]
(Embodiment 1)
FIG. 1 is a diagram illustrating a parasitic element extraction flow of the present invention, FIG. 2 is a diagram illustrating an effective frequency, FIG. 3 is a wiring network diagram including a resistor and a capacitance component connected to both ends of a buffer, and FIG. FIG. 3 is a wiring network diagram formed of connected resistance, inductance, and capacitance components.
[0019]
In FIG. 1, S1 is a wiring RC parasitic element extracting step, S2 is a calculating step of a gradient of an input side waveform of each wiring, S3 is a calculating step of an effective frequency of each wiring, and S4 is a wiring RLC parasitic element extracting step.
[0020]
In step S1, a parasitic resistance and a capacitance are obtained as electrical information from the wiring layout of the semiconductor integrated circuit. The method used here may be a conventional method.
By combining with the resistance / capacitance network obtained in step S1 and the transistor circuit portion of the semiconductor integrated circuit, for example, a circuit as shown in FIG. 3 can be generated. FIG. 3 shows the resistance-capacitance network of the line 3 between the buffer BU1 and the buffer BU2.
[0021]
Next, in step S2, the “waveform slope: tr” on the input side of the wiring 3 is obtained from the network information in FIG. This can be obtained at the same time as the normal delay calculation is performed. "Asymptotic Waveform Evaluation for Timing Analysis", IEEE Transactions on Computer Aided Design, vol. 9 No. 4, April 1990, pp. 352-366). This step also uses that method.
[0022]
When the slope: tr of the waveform on the input side of each wiring 3 of the semiconductor integrated circuit is determined, in step S3, the effective frequency: Fs is determined according to (Equation 1). FIG. 2 is a diagram showing the concept of the effective frequency. Generally, a frequency at which about 85% of the spectrum of the trapezoidal wave is concentrated below the frequency is often used. Therefore, this is also used in this embodiment. The definition is arbitrary and any formula may be used, but the point is that the effective frequency is obtained by the waveform gradient: tr.
[0023]
Finally, since the frequencies of the electric signals flowing through the respective wirings are obtained in step S3, the inductance is obtained based on these values. Since the inductance depends on the frequency, the value obtained in step S3 is very effective, and is accurate because it is calculated based on the resistance / capacitance and the driving capability of the transistor.
[0024]
In step S4, resistance, inductance, and capacitance components are obtained based on the accurate frequency information obtained for each wiring. The conventional method may be used. Also, when the resistance component has a high frequency, the value changes depending on the frequency due to the skin effect. An accurate value of the resistance can be calculated at the same time depending on the frequency.
[0025]
FIG. 4 shows a result of extracting a parasitic element from FIG. 3 in consideration of an inductance component. Although the inductance component L written here is only the self-inductance, the mutual inductance can be obtained by the same method. Further, it is easy to consider the coupling capacitance for the capacitance.
[0026]
According to this configuration, since the frequency component of the wiring is obtained based on the resistance / capacitance network and the transistor information, and then the inductance and the resistance are obtained, an accurate resistance / inductance / capacitance network can be obtained. As a result, since the timing verification of the semiconductor integrated circuit becomes accurate, the LSI design becomes easy.
[0027]
(Embodiment 2)
FIG. 1 shows a flow of parasitic element extraction and delay calculation according to the second embodiment of the present invention. Steps S1 to S4 are the same as (Embodiment 1).
[0028]
5 is an RLC screening check step, 6 is a delay step by the RC circuit, 7 is a delay calculation step by the RLC circuit, and 8 is a synthesis step of the delay result.
[0029]
The delay calculation is performed using the result of (Embodiment 1) (Embodiment 2). The delay calculation is performed through Steps S1 to S4 in Step S5 based on the resistance, inductance, and capacitance networks. It is determined whether to calculate or to calculate based on the resistance / capacitance network.
[0030]
Without an inductance component, the delay difference is as small as several picoseconds (ps) to about several tens ps, depending on the circuit. When obtaining the inductance, it is necessary to specify not only the frequency but also the return path. For this reason, if delay calculation is performed with due consideration of inductance, an error may occur. Therefore, screening is performed to determine whether the inductance needs to be considered. The following (Equation 2) is a representative example of the equation for determination. However, it can be arbitrarily determined.
[0031]
2πFs · L> (Rwire + Rdriver) / 4 (formula 2)
Here, Rwire is a wiring resistance, Rdriver is a driving resistance of a transistor, L is an inductance, and Fs is an effective frequency.
[0032]
The delay calculation step 7 by the RLC circuit is executed in step S7 for the wiring that requires consideration of the inductance in the screening, and the delay calculation step 6 by the RC circuit is applied in step S6 to the unnecessary wiring.
[0033]
Finally, in step S8, the delay calculation results obtained as described above are combined into one.
According to this configuration, since the frequency component of the wiring is obtained based on the resistance / capacitance network and the transistor information, and then the result of obtaining the inductance and the resistance is used, accurate screening becomes possible. Further, since delay calculation can be performed based on an accurate resistance, inductance, and capacitance network, as a result, timing verification of a semiconductor integrated circuit becomes accurate, and thus LSI design becomes easy.
[0034]
【The invention's effect】
As described above, according to the present invention, since the frequency component of the wiring is obtained based on the resistance / capacitance network and the transistor information, and then the inductance and the resistance are obtained, it is possible to obtain an accurate resistance / inductance / capacity network. it can. Further, since the screening and the delay calculation are performed based thereon, as a result, the timing verification of the semiconductor integrated circuit can be accurately performed, and the LSI design becomes easy.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a parasitic element extraction flow according to a first embodiment of the present invention; FIG. 2 is a diagram illustrating an effective frequency; FIG. 3 is a wiring network diagram including a resistor and a capacitance component connected to both ends of a buffer; FIG. 4 is a wiring network diagram in which a buffer is composed of resistance, inductance, and capacitance components connected to both ends. FIG. 5 is a diagram showing a parasitic element extraction and delay calculation flow according to the second embodiment of the present invention.
S1 Wiring RC parasitic element extraction step S2 Calculation of input waveform slope of each wiring step S3 Calculation of effective frequency of each wiring step S4 Wiring RLC parasitic element extraction step S5 RLC screening check step S6 Delay by RC circuit S7 RLC circuit Delay calculation step S8 Delay result synthesis step

Claims (3)

A method for extracting parasitic elements for timing verification in a semiconductor integrated circuit configured by connecting basic logic cells or functional macro blocks (hereinafter, referred to as cells) by inter-cell wiring,
After extracting the resistance and the capacitance, the slope of the electric signal waveform on the wiring input side is calculated, the effective frequency of the wiring is calculated based on the calculated value, and then the inductance is calculated based on the effective frequency. Element extraction method for obtaining electrical parameters of capacitance and capacitance. The parasitic element extraction method according to claim 1, wherein
A wiring RC parasitic element extracting step of obtaining resistance and capacitance as electrical information from wiring layout information;
Calculating the slope of the input-side waveform of each wiring, calculating the slope of the electrical signal waveform immediately below the transistor from the resistance / capacitance information obtained from the wiring RC parasitic element extraction step and the driving capability information of the transistor connected thereto;
Calculating the effective frequency of each wiring to calculate the effective frequency from the slope value of the waveform obtained from the calculation step of the slope of the input side waveform of each wiring,
A wiring RLC parasitic element extraction step of obtaining resistance, inductance and capacitance as electrical information from wiring layout information based on the effective frequency of an electric signal flowing through each wiring obtained in the effective frequency calculation step of each wiring; A method for extracting a parasitic element, comprising: A delay calculation method for timing verification in a semiconductor integrated circuit configured by connecting basic logic cells or functional macro blocks (hereinafter, referred to as cells) by inter-cell wiring,
An RLC screening check step of determining, for each wiring, whether delay calculation including inductance is to be performed based on the values of resistance, inductance and capacitance obtained by the parasitic element extraction method according to claim 2;
In the RLC screening check step, the wiring network determined to require the consideration of the inductance is calculated at the delay step by the RLC circuit. A delay calculating step of synthesizing one result of the delay step by the RC circuit and one result of the delay step by the RLC circuit.

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