JP3558514B2 - Recording medium recording signal delay analysis program in LSI design - Google Patents

Description

【００１８】
【数２】

【００１９】
【数３】

【００２０】
【数４】

【００２１】
【数５】

【００２２】
【数６】

【００２３】
なお、数式１は、Ｖ_ｉ（０）＝Ｖ_ｊ（０）＝０を初期条件とし、時刻ｔ＝ｔ_ｉにおいてノードＮ_ｉの電圧が０から１へ変化し、かつ時刻ｔ＝ｔ_ｊにおいてノードＮ_ｊの電圧が１から０へ変化するというステップ入力条件のもとで得られたものである。数式２は、数式１の中の添字ｉと添字ｊとを交換して得られる。
【００２４】
図５に示された４個の対地容量関数Ｃ_ｙ２４（ｔ），Ｃ_ｙ４２（ｔ），Ｃ_ｙ４５（ｔ）及びＣ_ｙ５４（ｔ）は、上記の数式１〜６により定義される。具体的に説明すると、対地容量関数Ｃ_ｙ２４（ｔ）及びＣ_ｙ４２（ｔ）は各々数式１及び２においてｉ＝２かつｊ＝４として得られ、対地容量関数Ｃ_ｙ４５（ｔ）及びＣ_ｙ５４（ｔ）は各々数式１及び２においてｉ＝４かつｊ＝５として得られる。
【００２５】
さて、ステップＳ１０５では、上記従来の信号遅延解析方法のいずれかを適用して、図５中の各ノードの遅延時間を計算する。この際、ノードＮ_ｍ（Ｎ_ｍ＝Ｎ_１，Ｎ_２，Ｎ_３，Ｎ_４，Ｎ_５，Ｎ_ｄ１，Ｎ_ｄ２，Ｎ_ｄ３，Ｎ_ｄ４，Ｎ_ｄ５）の計算には、対地容量関数値Ｃ_ｙ２４（ｔ_ｍ），Ｃ_ｙ４２（ｔ_ｍ），Ｃ_ｙ４５（ｔ_ｍ）及びＣ_ｙ５４（ｔ_ｍ）が使用される。ここに、ｔ_ｍは、図４の回路に基づいてステップＳ１０３で計算されたノードＮ_ｍの初期遅延値である。すなわち、図４に基づいて計算された大まかな遅延値を用いて、対地容量関数を利用したより正確な遅延時間の値を求めるのである。ただし、各ノードの初期遅延値を計算で求めるのではなくて、これを外部から入力するようにしてもよい。
【００２６】
ステップＳ１０６では、各ノードの遅延時間の変化を調べる。ステップＳ１０５で計算された各ノードの遅延時間のうちのいずれかのノードの遅延時間が該ノードの元の遅延値（ステップＳ１０３で計算された遅延時間）に比べて基準値ΔＴｒより大きく変化した場合には、クロストークの影響が対地容量関数に十分には反映されていないため、ステップＳ１０４へ戻る。すなわち、ステップＳ１０５で計算された遅延時間を新たな初期遅延値として用いて、各対地可変容量の時間関数を更新する。そして、遅延時間の計算結果が所定の誤差範囲内に収束するまで、ステップＳ１０４からステップＳ１０６までの処理を繰り返す。
【００２７】
計算結果が収束すると、ステップＳ１０７で各ノードの遅延時間を出力する。上記のようにして反復計算で得られた正確な遅延時間を用いてタイミング検証が実行されるので、遅延仕様に予め大きいマージンを設定しておく必要がなく、論理ゲートのサイズ拡大防止、ひいてはＬＳＩチップ面積の拡大防止に役立つ。
【００２８】
図８は、図６中の配線間容量Ｃ_ｘｉｊを除去して得られた回路ＣＩＲ３を示している。図９に示された回路ＣＩＲ４は、図６中の配線間容量Ｃ_ｘｉｊを、各々これと等しい容量値を有する２個の対地固定容量に置換して得られたものである。また、図１０に示された回路ＣＩＲ５は、図６中の配線間容量Ｃ_ｘｉｊを、各々これの２倍の容量値を有する２個の対地固定容量に置換して得られたものである。図８、図９及び図１０のいずれの回路も配線間容量を含まない遅延モデルを表しているので、上記従来の信号遅延解析方法のいずれかを適用して遅延時間の計算を実行できるものである。
【００２９】
図１１は、図６〜図１０の各回路ＣＩＲ１〜ＣＩＲ５におけるステップ応答の具体例を示しており、Ｒ_ｉ＝Ｒ_ｊ＝３０００Ω、Ｃ_ｉ＝Ｃ_ｊ＝３６ｆＦ、かつＣ_ｘｉｊ＝６８ｆＦの条件下でノード電圧Ｖ_ｉ（ｔ）の時間変化を描いたものである。ただし、Ｖ_ｉ（０）＝Ｖ_ｊ（０）＝０を初期条件とし、時刻ｔ＝０．０ｎｓ（＝ｔ_ｉ）においてノードＮ_ｉの電圧が０から１へ変化し、かつ時刻ｔ＝０．１ｎｓ（＝ｔ_ｊ）においてノードＮ_ｊの電圧が１から０へ変化するものとした。回路ＣＩＲ１及びＣＩＲ２では、ノードＮ_ｊからノードＮ_ｉへのクロストークによって時刻ｔ＝０．１ｎｓ以後の電圧Ｖ_ｉ（ｔ）の上昇速度が低減される結果、ステップ応答を表す曲線に瘤ができる。上記瘤関数Ｋｎｏｂ_ｉｊ（ｔ）は、これを数学的に表現したものである。図１１によれば、図９の回路ＣＩＲ４を採用した場合の５０％遅延時間の計算誤差ΔＴは、１個の論理ゲートの素子伝搬遅延時間に匹敵する約０．２ｎｓにも達することが判る。
【００３０】
図１２は、図１１の場合と同じ条件で得られた、図７の回路ＣＩＲ２における対地容量関数Ｃ_ｙｉｊ（ｔ）の具体例を示している。
【００３１】
以上のとおり、図１の手順に従った信号遅延解析方法によれば、解析対象回路（図６参照）の中の配線間容量Ｃ_ｘｉｊを、各々時間関数で表現された容量値を有する２個の対地可変容量Ｃ_ｙｉｊ（ｔ）及びＣ_ｙｊｉ（ｔ）に置換（図７参照）することとしたので、配線間のクロストークを考慮した正確な信号伝搬遅延時間を短時間で求めることができる。なお、ステップＳ１０２及びＳ１０３では、初期遅延値を計算するための遅延モデルとして図８、図９及び図１０のいずれの回路を採用してもよい。また、上記ステップ入力以外の信号波形で対地容量関数を決定してもよい。初期条件についても同様である。
【００３２】
図１３は、本発明に係る信号遅延解析方法の他の例を示している。図１３中のステップＳ２０１〜Ｓ２０５は、図１中のステップＳ１０１〜Ｓ１０５と同様である。ここでは、図１３中のステップＳ２０６〜Ｓ２０９を１ステップごとに説明する。
【００３３】
ステップＳ２０６では、クロストークノードの遅延時間の変化を調べる。ステップＳ２０５で計算された各ノードの遅延時間のうちのいずれかのクロストークノードの遅延時間が該クロストークノードの元の遅延値（ステップＳ２０３で計算された遅延時間）に比べて基準値ΔＴｓより大きく変化した場合には、該ノードにおけるクロストークの影響が著しいものとみなし、ステップＳ２０７へ進んで処理を続ける。そうでなければ、遅延時間の計算を打ち切ってステップＳ２０９へ進む。
【００３４】
ステップＳ２０７では、遅延時間が大きく変化したクロストークノードの対地容量を、若干大きめに見積もるように、該ノードに接続されていた配線間容量の２倍の容量値に固定する。図１４は、図５中の３個の対地可変容量Ｃ_ｙ２４（ｔ），Ｃ_ｙ４２（ｔ）及びＣ_ｙ４５（ｔ）を、各々容量値２Ｃ_ｘ２４，２Ｃ_ｘ２４及び２Ｃ_ｘ４５を有する対地固定容量に置換して得られたものである。図１４の例ではノードＮ_ｄ５の遅延時間の変化が基準値ΔＴｓより小さかったものとしているので、該ノードＮ_ｄ５におけるクロストークの過大評価を防止するように、対地可変容量Ｃ_ｙ５４（ｔ）がそのまま残される。
【００３５】
ステップＳ２０８では、上記従来の信号遅延解析方法のいずれかを適用して、図１４中の各ノードの遅延時間を計算する。
【００３６】
ステップＳ２０９では、各ノードの遅延時間を出力する。
【００３７】
以上のとおり、図１３の手順に従った信号遅延解析方法によれば、高々３回の計算（ステップＳ２０３，Ｓ２０５及びＳ２０８）で遅延時間の計算結果が得られるので、図１の手順を採用した場合に比べて解析に要する時間が大幅に短縮される。なお、許容される処理時間内で、ステップＳ２０７でクロストークノードの対地容量を固定する前に対地容量関数の更新を何回か繰り返したり、ステップＳ２０８で求めた各ノードの遅延時間を初期値として対地容量関数を生成し、該対地容量関数を用いて各ノードの遅延時間を再計算したりできる。計算の反復回数を処理時間との兼ね合いで制御するようにしてもよい。ステップＳ２０７における固定容量値は、配線間容量の１．５倍から３倍までの範囲から選択できる。この倍率が１．５倍より小さいとクロストークの過小評価となり、３倍より大きいとクロストークの過大評価となる。
【００３８】
なお、上記いずれかの手順からなる解析プログラムをコンピュータ読み取り可能な媒体に記録しておけば、コンピュータによる信号遅延解析の繰り返し実施に好都合である。
【００３９】
【発明の効果】
以上説明してきたとおり、本発明によれば、解析対象回路の中の配線間容量を、時間関数で表現された容量値を有する対地可変容量に置換することとしたので、配線間のクロストークを考慮した正確な信号伝搬遅延時間を短時間で求めることができる。
【図面の簡単な説明】
【図１】本発明に係る信号遅延解析方法の一例を示すフローチャート図である。
【図２】解析対象回路の具体例を示すブロック図である。
【図３】配線間のクロストークを考慮した図２の等価回路を示すブロック図である。
【図４】図３中の配線間容量を対地固定容量に置換して得られたブロック図である。
【図５】図３中の配線間容量を対地可変容量に置換して得られたブロック図である。
【図６】図３中の一部を抜き出し、かつ一般化して得られた回路図である。
【図７】図６中の配線間容量を対地可変容量に置換して得られた回路図である。
【図８】図６中の配線間容量を除去して得られた回路図である。
【図９】図６中の配線間容量を対地固定容量に置換して得られた回路図である。
【図１０】図６中の配線間容量を他の容量値の対地固定容量に置換して得られた回路図である。
【図１１】図６〜図１０の各々の回路におけるステップ応答の具体例を示す図である。
【図１２】対地可変容量の容量値、すなわち対地容量関数の具体例を示す図である。
【図１３】本発明に係る信号遅延解析方法の他の例を示すフローチャート図である。
【図１４】図５中の一部の対地可変容量の容量値を固定して得られたブロック図である。
【符号の説明】
Ｃ_１〜Ｃ_５，Ｃ_ｉ，Ｃ_ｊ 配線容量
ＣＩＲ１〜ＣＩＲ５ 回路
Ｃ_ｘ２４，Ｃ_ｘ４５，Ｃ_ｘｉｊ 配線間容量
Ｃ_ｙ２４（ｔ），Ｃ_ｙ４２（ｔ） 対地可変容量（対地容量関数）
Ｃ_ｙ４５（ｔ），Ｃ_ｙ５４（ｔ） 対地可変容量（対地容量関数）
Ｃ_ｙｉｊ（ｔ），Ｃ_ｙｊｉ（ｔ） 対地可変容量（対地容量関数）
Ｎ_１〜Ｎ_５，Ｎ_ｄ１〜Ｎ_ｄ５ ノード
Ｎ_ｉ，Ｎ_ｊ，Ｎ_ｄｉ，Ｎ_ｄｊ ノード
Ｒ_１〜Ｒ_５，Ｒ_ｉ，Ｒ_ｊ 配線抵抗
ｔ_ｉ，ｔ_ｊ，ｔ_ｄｉ，ｔ_ｄｊ 各ノードの信号伝搬遅延時間
Ｖ_ｉ（ｔ），Ｖ_ｊ（ｔ） ノード電圧
Ｗ_１〜Ｗ_５ 配線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal delay analysis method in the design of a large-scale integrated circuit (LSI), and more particularly, to an accurate signal propagation delay time in consideration of crosstalk in wiring in an LSI after layout design. The present invention relates to a recording medium on which a program for executing a method for obtaining the above is recorded .
[0002]
[Prior art]
In the timing verification stage after the layout design of the LSI, it is checked whether or not the signal propagation delay time of each node satisfies a predetermined delay specification. In the current situation where the speed of LSIs has been increased and the process technology has become deeper sub-micron, it is necessary to grasp an accurate wiring delay in consideration of not only the wiring resistance and wiring capacitance parasitic on each wiring but also the capacitance between wirings. I have.
[0003]
J. Cong, "Modeling and Layout Optimization of VLSI Devices and Interconnects In Deep Submicron Design", Proceedings of ASP-DAC '97, p. 121-126, a method using an Elmore delay model and an AWE (Asymptotic Waveform Evaluation) method are introduced as signal delay analysis methods of an RC network including a wiring resistance and a wiring capacitance.
[0004]
[Problems to be solved by the invention]
When the distance between the wirings is small, crosstalk due to the capacitance between the wirings becomes remarkable. However, all of the conventional signal delay analysis methods described above are based on a delay model that does not include the capacitance between wirings, so that the reliability of the analysis result has been reduced. On the other hand, if a circuit simulation is performed in which the voltage and current at each node in the LSI are calculated one by one in minute specified time units, an analysis result cannot be obtained within a practical time.
[0005]
SUMMARY OF THE INVENTION An object of the present invention is to provide a signal delay analysis method capable of obtaining an accurate signal propagation delay time in a short time in consideration of crosstalk in wiring in an LSI.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention , using the initial delay value of each node of the analysis target circuit, replacing the inter-wiring capacitance in the analysis target circuit with a ground variable capacitance; Calculating a delay time of each node of the analysis target circuit including the analysis target circuit. Here, the ground variable capacity has a capacity value expressed by a time function.
[0007]
The initial delay value of each node can be obtained by various methods. First, the capacitance between wires in the circuit to be analyzed is replaced with a fixed ground capacitance, the delay time of each node of the analysis target circuit including the fixed ground capacitance is calculated, and the delay time of each node obtained by the calculation is calculated. The delay time is adopted as the initial delay value of each node. Here, as the capacitance value of the fixed-to-ground capacitance, a capacitance value equal to or larger than the capacitance between wirings can be adopted. Second, the inter-wiring capacitance in the analysis target circuit is removed, the delay time of each node of the analysis target circuit from which the inter-wiring capacitance is removed is calculated, and the delay time of each node obtained by the calculation is calculated. Is adopted as the initial delay value of each node. Third, there is a method of inputting the initial delay value of each node, instead of calculating the initial delay value by calculation.
[0008]
In order to improve the accuracy of the analysis result by iterative calculation, if the calculated delay time of any node greatly changes from the original delay value of the node, the calculated delay time is replaced with a new initial delay value. To update the time function of the ground variable capacity.
[0009]
In order to obtain the analysis result in a very short time, if the calculated delay time of the node (crosstalk node) to which the interwiring capacitance is connected greatly changes from the original delay value of the node, It is assumed that the capacitance value of the ground variable capacitance of the node is fixed to a capacitance value larger than the capacitance between wirings, and the delay time of each node of the analysis target circuit is recalculated.
[0010]
According to the present invention, there is provided a computer-readable recording medium on which a program for signal delay analysis in LSI design is recorded . The program includes means for replacing a computer with a ground variable capacitance by replacing an inter-wiring capacitance in the analysis target circuit with an initial delay value of each node of the analysis target circuit, and an analysis including the ground variable capacitance. This is to function as means for calculating the delay time of each node of the target circuit.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows an example of a signal delay analysis method according to the present invention. Hereinafter, steps S101 to S107 in FIG. 1 will be described step by step using a specific example of the analysis target circuit shown in FIG. In FIG. 2, FF1 to FF3 are each flip-flop, SC10～SC31 each configured logical gates in standard _cell, W 1 to _W-5 each wire. A logic gate SC10 is interposed between flip-flop FF1 and logic gate SC11, and a logic gate SC20 is interposed between flip-flop FF2 and logic gate SC21. Therefore, the logic gate SC10 output signal of the flip-flop FF1 through the line _{W 1,} the output signal of the logic gate SC10 is the logic gate SC11 via a wire _{W 2,} the output signal of the flip-flop FF2 wiring _{W 3} to the logic gate SC20 via the output signal of the logic gate SC20 is the logic gate SC21 via a wire _{W 4,} the output signal of the flip-flop FF3 are respectively supplied to the logic gate SC31 via a wire _{W 5.} Adjacent to each other in crosstalk portion _{X 24} is a wiring _{W 2} and the wiring _{W 4,} it is assumed that adjacent crosstalk portion _{X 45} is a wiring _{W 4} and the wiring _{W 5.}
[0012]
In step S101, the RC network of the wiring is input together with the net list. FIG. 3 shows the equivalent circuit of FIG. 2 in which crosstalk between wirings is considered. The wire _{W 1} is the wiring resistance _{R 1} and the line capacitance _{C 1,} the wiring _{W 2} is the wiring resistance _{R 2} and the wiring capacitance _{C 2,} wire _{W 3} being the wiring resistance _{R 3} and the wiring capacitance _{C 3,} wiring _{W 4} wiring the resistor _{R 4} and the wiring capacitance _{C 4,} the wire _{W 5} is the wiring resistance _{R 5} and the wiring capacitance _{C 5,} the crosstalk portion _{X 24} is inter-wire capacitance _{C x24,} crosstalk portion _{X 45} by the wiring capacitance _{C x45} Each is represented. 3, the output node of the _{N 1} is flip-flop FF1, the output node of the _{N 2} is the logic gates SC10, the output node of the _{N 3} is the flip-flop FF2, _{N 4} is an output node of the logic gate SC20, _{N 5} Is the output node of the flip-flop FF3, N _d1 is the input node of the logic gate SC10, N _d2 is the input node of the logic gate SC11, N _d3 is the input node of the logic gate SC20, and N _d4 is the input of the logic gate SC21. _{nodes, N d5} represents the input node of the logic gate SC31, respectively. Among these, three nodes N _d2 , N _d4 and N _d5 are crosstalk nodes having a connection of the capacitance between wirings.
[0013]
In step S102, the inter-wiring capacitance is removed or the inter-wiring capacitance is replaced with a fixed ground capacitance. FIG. 4 shows a case in which the inter-wiring capacitance C _x24 in FIG. 3 is replaced by two fixed-to-ground capacitors each having the same capacitance value, and the inter-wiring capacitance C _x45 is replaced by two having the same capacitance value. It is obtained by replacing with a fixed ground capacity.
[0014]
In step S103, the delay time of each of the ten nodes in FIG. 4 is calculated. FIG. 4 shows a delay model that does not include the capacitance between wires, so that calculations can be performed by applying any of the above-described conventional signal delay analysis methods. The delay time of each node is expressed based on the transition time of the common clock signal to the three flip-flops FF1 to FF3.
[0015]
In step S104, a ground capacity function is generated. FIG. 5 shows a case in which the inter-wiring capacitance C _x24 in FIG. 3 is replaced with two ground variable capacitances C _y24 (t) and C _y42 (t) each having a capacitance value expressed by a time function, and The capacitance C _x45 is obtained by replacing the capacitance C _x45 with two fixed ground capacitances C _y45 (t) and C _y54 (t) each having a capacitance value represented by a time function. Here, t is a variable representing time, and the time function is called a ground capacity function.
[0016]
Here, a method of obtaining the ground capacity function will be described. FIG. 6 shows a circuit CIR1 obtained by extracting and generalizing a part of the circuit in FIG. 6, the _{R i} and _{R j} are wire resistance, the _{C i} and _{C j} is the wiring _capacitance, the _{C xij} wiring _{capacitance, N i, N j, N} di and _{N dj} represent nodes respectively . Here, the voltage at the node N _di is represented by a time function V _i (t), and the voltage at the node N _dj is represented by a time function V _j (t). The signal propagation delay time of each of the four nodes N _i , N _j , N _di and N _dj is assumed to be t _i , t _j , t _di and t _dj . FIG. 7 shows a circuit _CIR2 obtained by replacing the inter-wiring capacitance C _xij in FIG. 6 with two ground variable capacitances C _yij (t) and C _yji (t). When the time functions C _yij (t) and C _yji (t) are determined so that the circuit CIR2 of FIG. 7 has the same step response as the circuit CIR1 of FIG. 6, the following equations 1 and 2 are obtained. Here, Knob _ij (t) is a knob function defined by the following formulas 3 to 6, and if T ≦ 0, Knob _ij (T) = 0.
[0017]
(Equation 1)

[0018]
(Equation 2)

[0019]
(Equation 3)

[0020]
(Equation 4)

[0021]
(Equation 5)

[0022]
(Equation 6)

[0023]
Note that Equation _1, the _{V i (0) = V j} (0) = 0 as the initial condition, the voltage at the node _{N i} at time t = _{t i} is changed from 0 to 1, and at time t = _{t j} This is obtained under the step input condition that the voltage of the node _Nj changes from 1 to 0. Equation 2 is obtained by exchanging the subscripts i and j in Equation 1.
[0024]
The four ground capacity functions C _y24 (t), C _y42 (t), C _y45 (t), and C _y54 (t) shown in FIG. 5 are defined by the above-described equations 1 to 6. More specifically, the ground capacity functions C _y24 (t) and C _y42 (t) are obtained as i = 2 and j = 4 in Equations 1 and 2, respectively, and the ground capacity functions C _y45 (t) and C _y54 ( t) is obtained as i = 4 and j = 5 in Equations 1 and 2, respectively.
[0025]
In step S105, the delay time of each node in FIG. 5 is calculated by applying any of the above-described conventional signal delay analysis methods. In this case, node _{N m (N m = N 1} , N 2, N 3, N 4, N 5, N d1, N d2, N d3, N d4, N d5) The calculation of, earth capacitance function value C _{y24 (t m), C y42} (t m), C y45 (t m) and _C y54 _{(t m)} is used. Here, t _m is the initial delay value of the node N _m calculated in step S103 based on the circuit of Figure 4. That is, using the approximate delay value calculated based on FIG. 4, a more accurate value of the delay time using the ground capacity function is obtained. However, instead of calculating the initial delay value of each node by calculation, it may be input from outside.
[0026]
In step S106, a change in the delay time of each node is checked. When the delay time of any one of the delay times of the nodes calculated in step S105 is larger than the reference value ΔTr compared to the original delay value of the node (the delay time calculated in step S103). Does not sufficiently reflect the influence of the crosstalk on the ground capacity function, the process returns to step S104. That is, the time function of each ground variable capacity is updated using the delay time calculated in step S105 as a new initial delay value. Then, the processing from step S104 to step S106 is repeated until the calculation result of the delay time converges within the predetermined error range.
[0027]
When the calculation results converge, the delay time of each node is output in step S107. Since the timing verification is performed using the accurate delay time obtained by the iterative calculation as described above, it is not necessary to set a large margin in the delay specification in advance, and it is possible to prevent an increase in the size of the logic gate and, consequently, the LSI. Helps prevent chip area expansion.
[0028]
FIG. 8 shows a circuit CIR3 obtained by removing the inter-wiring capacitance C _xij in FIG. The circuit CIR4 shown in FIG. 9 is obtained by replacing the inter-wiring capacitance C _xij in FIG. 6 with two fixed-to-ground capacitors each having the same capacitance value. The circuit CIR5 shown in FIG. 10 is obtained by replacing the inter-wiring capacitance C _xij in FIG. 6 with two fixed-to-ground capacitances each having a capacitance twice as large as this. Since each of the circuits in FIG. 8, FIG. 9 and FIG. 10 shows a delay model that does not include the capacitance between wirings, the calculation of the delay time can be executed by applying any of the conventional signal delay analysis methods. is there.
[0029]
FIG. 11 shows a specific example of the step response in each of the circuits CIR1 to CIR5 shown in FIGS. 6 to 10, where R _i = R _j = 3000Ω, C _i = C _j = 36 fF, and C _xij = 68 fF. 5 illustrates a time change of the node voltage V _i (t). _{However, V i (0) = V} j (0) = 0 and the initial conditions, the time _t = 0.0ns (= t _i) in the voltage at the node _{N i} is changed from 0 to 1, and time t = 0 the voltage of the node _{N j} is assumed to vary from 1 to 0 in .1ns (= _{t j).} The circuit CIR1 and CIR2, results rising speed of the time by crosstalk t = 0.1 ns after the voltage _V i (t) from the node _{N j} to node _{N i} is reduced, it is aneurysm curve representing the step response . The knob function Knob _ij (t) is a mathematical expression of this. According to FIG. 11, it is understood that the calculation error ΔT of the 50% delay time when the circuit CIR4 of FIG. 9 is adopted reaches about 0.2 ns which is equivalent to the element propagation delay time of one logic gate.
[0030]
FIG. 12 shows a specific example of the ground capacitance function C _yij (t) in the circuit CIR2 of FIG. 7 obtained under the same conditions as in FIG.
[0031]
As described above, according to the signal delay analysis method in accordance with the procedure of FIG. 1, the inter-wiring capacitance C _xij in the circuit to be analyzed (see FIG. 6) is changed to two capacitors each having a capacitance value expressed by a time function. (See FIG. 7) with the ground variable capacitors C _yij (t) and C _yji (t), so that an accurate signal propagation delay time in consideration of crosstalk between wirings can be obtained in a short time. . In steps S102 and S103, any of the circuits shown in FIGS. 8, 9, and 10 may be employed as a delay model for calculating the initial delay value. Further, the ground capacitance function may be determined by a signal waveform other than the step input. The same applies to the initial conditions.
[0032]
FIG. 13 shows another example of the signal delay analysis method according to the present invention. Steps S201 to S205 in FIG. 13 are the same as steps S101 to S105 in FIG. Here, steps S206 to S209 in FIG. 13 will be described for each step.
[0033]
In step S206, a change in the delay time of the crosstalk node is checked. The delay time of any of the crosstalk nodes among the delay times of the nodes calculated in step S205 is compared with the original delay value of the crosstalk node (the delay time calculated in step S203) by the reference value ΔTs. If there is a large change, it is considered that the influence of crosstalk at the node is significant, and the process proceeds to step S207 to continue. Otherwise, the calculation of the delay time is terminated, and the process proceeds to step S209.
[0034]
In step S207, the ground capacitance of the crosstalk node whose delay time has significantly changed is fixed to twice the capacitance of the wiring connected to the node so as to be slightly larger. FIG. 14 shows three ground variable capacitances C _y24 (t), C _y42 (t) and C _y45 (t) in FIG. 5 _converted into ground fixed capacitances having capacitance values of 2C _x24 , 2C _x24 and 2C _x45 , respectively. It was obtained by substitution. In the example of FIG. 14, it is assumed that the change in the delay time of the node N _d5 is smaller than the reference value ΔTs, so that the ground variable capacitance C _y54 (t) is set so as to prevent the crosstalk at the node N _{d5 from being} overestimated. It is left as it is.
[0035]
In step S208, the delay time of each node in FIG. 14 is calculated by applying any of the above-described conventional signal delay analysis methods.
[0036]
In step S209, the delay time of each node is output.
[0037]
As described above, according to the signal delay analysis method in accordance with the procedure of FIG. 13, since the calculation result of the delay time can be obtained at most three times (steps S203, S205, and S208), the procedure of FIG. 1 is employed. The time required for analysis is greatly reduced as compared with the case. It should be noted that, within the allowable processing time, the update of the ground capacity function is repeated several times before fixing the ground capacity of the crosstalk node in step S207, or the delay time of each node obtained in step S208 is used as an initial value. A ground capacity function can be generated, and the delay time of each node can be recalculated using the ground capacity function. The number of repetitions of the calculation may be controlled in consideration of the processing time. The fixed capacitance value in step S207 can be selected from a range of 1.5 to 3 times the inter-wiring capacitance. If the magnification is smaller than 1.5, the crosstalk is underestimated, and if it is larger than 3, the crosstalk is overestimated.
[0038]
It should be noted that if the analysis program including any of the above procedures is recorded on a computer-readable medium, it is convenient to repeatedly execute the signal delay analysis by the computer.
[0039]
【The invention's effect】
As described above, according to the present invention, the capacitance between wirings in the circuit to be analyzed is replaced with the ground variable capacitance having a capacitance value expressed by a time function, so that crosstalk between wirings is reduced. An accurate signal propagation delay time that is considered can be obtained in a short time.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating an example of a signal delay analysis method according to the present invention.
FIG. 2 is a block diagram showing a specific example of a circuit to be analyzed.
FIG. 3 is a block diagram showing an equivalent circuit of FIG. 2 in which crosstalk between wirings is considered.
4 is a block diagram obtained by replacing a capacitance between wires in FIG. 3 with a fixed capacitance to ground.
FIG. 5 is a block diagram obtained by replacing the inter-wiring capacitance in FIG. 3 with a ground variable capacitance.
6 is a circuit diagram obtained by extracting a part of FIG. 3 and generalizing it.
FIG. 7 is a circuit diagram obtained by replacing the inter-wiring capacitance in FIG. 6 with a ground variable capacitance.
FIG. 8 is a circuit diagram obtained by removing a capacitance between wirings in FIG. 6;
9 is a circuit diagram obtained by replacing the capacitance between wires in FIG. 6 with a fixed capacitance to ground.
10 is a circuit diagram obtained by replacing the inter-wiring capacitance in FIG. 6 with a fixed capacitance to ground having another capacitance value.
FIG. 11 is a diagram showing a specific example of a step response in each of the circuits of FIGS. 6 to 10;
FIG. 12 is a diagram showing a specific example of a capacitance value of a ground variable capacitance, that is, a ground capacitance function.
FIG. 13 is a flowchart illustrating another example of the signal delay analysis method according to the present invention.
FIG. 14 is a block diagram obtained by fixing the capacitance values of some ground variable capacitors in FIG. 5;
[Explanation of symbols]
C ₁ -C ₅ , C _i , C _j wiring capacitances CIR 1 -CIR 5 Circuits C _x24 , C _x45 , C _xij capacitances between wirings C _y24 (t), _{Cy 42} (t) Variable capacitance to ground (ground capacitance function)
_Cy45 (t), _Cy54 (t) Variable capacity to ground (capacity function to ground)
_{C yij (t), C yji} (t) ground variable capacitance (ground capacitance function)
_{N 1 ~N 5, N d1 ~N} d5 nodes _{N i, N j, N di} , N dj node _{R 1 ~R 5, R i,} R j wiring resistance _{t i, t j, t di} , t dj nodes Signal propagation delay time V _i (t), V _j (t) of the node voltages W _{1 to} W ₅

Claims (8)

A computer-readable recording medium recording a program for signal delay analysis in LSI design, comprising:
Means for replacing the inter-wiring capacitance in the analysis target circuit with a ground variable capacitance having a capacitance value represented by a time function, using an initial delay value of each node of the analysis target circuit; and
A recording medium storing a program for functioning as a means for calculating a delay time of each node of the analysis target circuit including the ground variable capacitance. 2. The recording medium according to claim 1, wherein the program is:
Replacing the inter-wiring capacitance in the analysis target circuit with a ground fixed capacitance having a fixed capacitance value;
Calculating the delay time of each node of the analysis target circuit including the fixed-to-ground capacitance, and employing the delay time of each node obtained by the calculation as an initial delay value of each node. A recording medium further comprising: 3. The recording medium according to claim 2, wherein the program is:
A recording medium having a function of causing the computer to execute a step of adopting a capacitance value equal to the inter-wiring capacitance as the capacitance value of the ground fixed capacitance. 3. The recording medium according to claim 2, wherein the program is:
A recording medium having a function of causing the computer to execute a step of adopting a capacitance value larger than the inter-wire capacitance as the capacitance value of the fixed-to-ground capacitance. 2. The recording medium according to claim 1, wherein the program is:
Removing the inter-wire capacitance in the analysis target circuit;
Calculating the delay time of each node of the analysis target circuit from which the inter-wire capacitance has been removed, and adopting the delay time of each node obtained by the calculation as the initial delay value of each node. A recording medium, further comprising a function of causing the recording medium to have a function of causing the recording medium to perform a recording operation. 2. The recording medium according to claim 1, wherein the program is:
A recording medium further comprising a function of causing the computer to execute a step of inputting an initial delay value of each of the nodes. 2. The recording medium according to claim 1, wherein the program is:
If the calculated delay time of any node greatly changes from the original delay value of the node, the time function of the ground variable capacity is updated using the calculated delay time as a new initial delay value. A recording medium further comprising a function of causing the computer to execute the step of performing the following. 2. The recording medium according to claim 1, wherein the program is:
If the calculated delay time of the node to which the inter-wire capacitance is connected greatly changes from the original delay value of the node, the capacitance value of the ground variable capacitance of the node is set to a value larger than the inter-wire capacitance. Fixing to a value,
Re-calculating the delay time of each node of the analysis target circuit by the computer.

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