JP2004096436A - DeltaSigma MODULATOR AND PLL CIRCUIT IN DeltaSigma MODULATION METHOD - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ΔΣ modulator which is excellent in spurious characteristics and in which power consumption can be reduced and the scale of a circuit can be reduced, and to provide a PLL circuit in a ΔΣ modulation method. <P>SOLUTION: The ΔΣ modulator 6a has a multiplier 11 to multiply a first setting value and a feedback signal, a first adder 12 to add a second setting value to an output signal of the multiplier 11, a first integrator 13 to integrate an output signal of the first adder 12, a second integrator 14 to integrate an output signal of the first integrator 13, a second adder 15 to add both output signals of the first/second integrators 13, 14, and a comparator 16 to compare an output signal of the second adder 15 with a value correlative to the first setting value and to output three values showing comparison results as the feedback signal. A division ratio of a divider 2 in the PLL circuit in the ΔΣ modulation method can be set to three types since the output of the comparator 16 in the ΔΣ modulator 6a is made to be the three values. It is possible to prevent spuriousness from occurring since a changing cycle of a division ratio can be set longer than that of the conventional one. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ΔΣ modulator used for a PLL circuit, an A / D converter, and the like, and a PLL circuit using the ΔΣ modulator.
[0002]
[Prior art]
To increase the conversion accuracy of an A / D converter or the like, the sampling frequency must be extremely high, which makes it difficult to realize a circuit. Further, as the number of bits of the A / D converter increases, quantization noise and aliasing noise increase.
[0003]
A Δ 手法 modulation method is known as a technique that can reduce quantization noise and aliasing noise without increasing the sampling frequency. The ΔΣ modulator is used not only for an A / D converter and a D / A converter but also for a PLL circuit.
[0004]
FIG. 6 is a block diagram showing a schematic configuration of a conventional PLL circuit using a conventional ΔΣ modulator. As shown, the conventional PLL circuit includes a voltage controlled oscillator (VCO) 1, a frequency divider 2, a phase comparator 3, a charge pump 4, a loop filter 5, and a ΔΣ modulator 6. .
[0005]
The ΔΣ modulator 6 determines the next frequency division ratio of the frequency divider 2 based on the frequency division ratio of the frequency divider 2. The output of the ΔΣ modulator 6 is binary, and the frequency divider 2 determines a new frequency division ratio based on the binary output of the ΔΣ modulator 6. More specifically, the frequency divider 2 sets the frequency division ratio to ± 1 based on the binary output of the Δ ± modulator 6.
[0006]
[Problems to be solved by the invention]
As described above, since the conventional ΔΣ modulator 6 outputs only two values, the frequency division ratio of the ΔΣ modulation type PLL circuit is only one of +1 and −1. Since the output cycle of No. 6 could not be set long, spurious characteristics were not good.
[0007]
The division ratio of the ΔΣ modulation type PLL circuit is represented by (N + F / D), where N is the division ratio of the divider 2. F and D are values input to the ΔΣ modulator 6. Conventionally, since F has a positive value, the number of bits of the adder in the ΔΣ modulator 6 increases, and as a result, the circuit scale of the ΔΣ modulator 6 increases and the current consumption increases. Was.
[0008]
The present invention has been made in view of such a point, and an object of the present invention is to provide a ΔΣ modulator and a ΔΣ modulation type PLL circuit that have good spurious characteristics, can reduce current consumption, and can reduce the circuit scale. Is to do.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides a multiplier that multiplies a first set value and a feedback signal, and a first adder that adds a second set value to an output signal of the multiplier. A first integrator for integrating an output signal of the first adder, a second integrator for integrating an output signal of the first integrator, and outputs of the first and second integrators A second adder for adding the signals to each other, comparing an output signal of the second adder with a value correlated with the first set value, and outputting a ternary value indicating a comparison result as the feedback signal; And a comparator.
[0010]
In the present invention, by outputting three values indicating the comparison result from the comparator, the output cycle of the ΔΣ modulator is set long, and spurious is prevented.
[0011]
A voltage-controlled oscillator that outputs an oscillation signal having a frequency corresponding to the voltage signal; a frequency divider that outputs a frequency-divided signal obtained by dividing the frequency of the oscillation signal by a predetermined frequency division ratio; A phase comparator that outputs a signal corresponding to a phase difference between the signal and a reference frequency signal, a charge pump that outputs a current signal corresponding to an output signal of the phase comparator, and a charge pump that outputs a current signal according to the current signal output from the charge pump. A loop filter that outputs a divided voltage signal, and a ΔΣ modulator that determines a frequency division ratio of the frequency divider. The ΔΣ modulator includes a multiplier that multiplies a first set value by a feedback signal. A first adder for adding a second set value to an output signal of the multiplier, a first integrator for integrating an output signal of the first adder, and an output of the first integrator A second integrator for integrating a signal; and a first integrator for the first and second integrators. A second adder for adding the force signals to each other, comparing an output signal of the second adder with a value correlated with the first set value, and outputting a ternary value indicating the comparison result as the feedback signal And the divider sets a frequency division ratio based on an output of the comparator.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a ΔΣ modulator and a ΔΣ modulation type PLL circuit according to the present invention will be specifically described with reference to the drawings.
[0013]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a ΔΣ modulation type PLL circuit using a ΔΣ modulator according to the present invention. 1 is a voltage controlled oscillator (VCO) 1 that outputs an oscillation signal having a frequency corresponding to a voltage signal, and a frequency divider that divides the frequency of the oscillation signal of the VCO 1 by a predetermined frequency division ratio. A frequency divider 2 for outputting a signal, a phase comparator 3 for outputting a signal corresponding to a phase difference between the divided signal and the reference frequency signal, and a charge for outputting a current signal according to the output signal of the phase comparator 3 It includes a pump 4, a loop filter 5 that outputs a voltage signal corresponding to a current signal output from the charge pump 4, and a ΔΣ modulator 6 a that determines a frequency division ratio of the frequency divider 2.
[0014]
The ΔΣ modulation type PLL circuit of FIG. 1 is different from the conventional ΔΣ modulation type PLL circuit shown in FIG. 6 in that the ΔΣ modulator 6a outputs three values. Therefore, the frequency divider 2 of FIG. 1 is set to ± 1 of the immediately preceding frequency dividing ratio N or the same frequency dividing ratio N as the immediately preceding frequency dividing ratio N.
[0015]
FIG. 2 is a block diagram showing the internal configuration of the ΔΣ modulator 6a of FIG. The ΔΣ modulator 6a of FIG. 2 includes a multiplier 11 for multiplying a first set value and a feedback signal, a first adder 12 for adding a second set value to an output signal of the multiplier 11, A first integrator 13 for integrating the output signal of the first adder 12, a second integrator 14 for integrating the output signal of the first integrator 13, and first and second integrators 13, 14. A second adder 15 that adds the output signals of the second adder 15 to each other, compares the output signal of the second adder 15 with a value correlated with the first set value, and outputs a ternary value indicating the comparison result as a feedback signal. And a comparator 16.
[0016]
The first integrator 13 is composed of a third adder 17 and a first delay circuit 18, and the second integrator 14 is composed of a fourth adder 19 and a second delay circuit 20. .
[0017]
If the number of bits of the first adder 12 is A, the number of bits of the third adder 17 is b, the number of bits of the fourth adder 19 is c, and the number of bits of the second adder 15 is d, The relationship of A <b <c ≦ d holds.
[0018]
The frequency division value of the ΔΣ modulation type PLL circuit of FIG. 1 is expressed by (N + F / D), similarly to the ΔΣ modulation type PLL circuit of FIG. The denominator D of the fractional part (F / D) is input to the multiplier 11 as a first set value, and the numerator F is input to the first adder 12 as a second set value.
[0019]
The comparator 16 compares the output Y of the second adder 15 with a value D / 4 correlated with the first set value, and outputs the following three values.
[0020]
When Y <−D / 4, +1 is output.
[0021]
When D / 4 ≦ Y ≦ D / 4, 0 is output.
[0022]
If D / 4 <Y, -1 is output.
[0023]
Note that the value correlated with the first set value does not necessarily need to be D / 4, but may be any value that correlates with D.
[0024]
The output of the comparator 16 is input to the multiplier 11 and also to the frequency divider 2. If the output of the comparator 16 is +1, the frequency divider 2 sets the frequency division ratio N to (N + 1). If the output of the comparator 16 is 0, the frequency divider 2 keeps the frequency division ratio N unchanged. If the output is -1, the dividing ratio N is set to (N-1).
[0025]
As described above, in the conventional Δａ modulator 6a, the frequency division ratio N is changed to (N + 1) or (N−1). However, in the present embodiment, it is possible to set the frequency division ratio to N. This makes it possible to set the period in which the frequency division ratio N changes longer than in the past, and to prevent spurious.
[0026]
The value of the first set value D is not particularly limited, but is, for example, 200 to 300. As the value of D increases, the number of bits of the multiplier 11 and the first to fourth adders 12, 15, 17, and 19 increases, and the circuit scale increases.
[0027]
The first and second set values D and F satisfy the relationship of -D / 2 ≦ F ≦ D / 2.
[0028]
Conventionally, since the second set value F is set to a positive value, the value of the second set value F must be increased, and compared with the first to fourth adders 12, 15, 17, and 19. There is a problem that the number of bits of the circuit 16 increases and the circuit scale increases. However, if the second set value F is allowed to take a negative value and the absolute value of the second set value F is set not to exceed D / 2 as in the present embodiment, the second set value F becomes smaller than the conventional one. The number of bits of the first to fourth adders 12, 15, 17, 19 and the comparator 16 can be reduced, and the circuit scale can be reduced.
[0029]
For example, (1) when the second set value F is a positive value and the output of the comparator 16 is binary, the relationship of (2) −D / 2 ≦ F ≦ D / 2 is established. Is binary, (3) When the second set value F is a positive value, and when the output of the comparator 16 is ternary, the relationship of (4) −D / 2 ≦ F ≦ D / 2 is satisfied. When the maximum value and the minimum value in the arithmetic processing in the ΔΣ modulator 6a are compared for each case where the output of the comparator 16 is ternary, the following results are obtained. The maximum value in the case (1) is Z1, the minimum value is Y1, the maximum value in the case (2) is Z2, the minimum value is Y2, the maximum value in the case (3) is Z3, the minimum value is Y3, In the case of (4), the maximum value is Z4, and the minimum value is Y4.
[0030]
In this case, the maximum value is Z1>Z3>Z2> Z4, and the minimum value is Y1 <Y3 <Y2 <Y4.
[0031]
From this, it can be seen that the number of bits can be reduced most in the case (4) similar to the present embodiment.
[0032]
For example, if the denominator D is 127, the number of bits required for the arithmetic processing in the conventional ΔΣ modulator 6 is 16 bits, whereas in the present embodiment, it is 10 bits. In particular, conventionally, each of the second adder 15, the fourth adder 19, and the comparator 16 requires 16 bits, whereas in the present embodiment, the second adder 15 has 9 bits, The fourth adder 19 and the comparator 16 each require 10 bits, and the number of bits can be greatly reduced as compared with the conventional case.
[0033]
Each of the first to fourth adders 12, 15, 17, and 19 is configured by cascade-connecting N adders 21, as shown in FIG. As shown in an enlarged manner in FIG. 4, each adder 21 performs an addition operation between inputs A and B, and supplies a carry output indicating overflow to a carry input terminal of the adder 21 at the next stage. A logical diagram showing the operation of the adder 21 is as shown in FIG.
[0034]
As described above, in the present embodiment, since the output of the comparator 16 in the ΔΣ modulator 6a is ternary, the frequency division ratio of the frequency divider 2 in the ΔΣ modulation type PLL circuit can be set to three ways, Since the period at which the ratio changes can be made longer than before, spurious can be prevented.
[0035]
Further, the numerator F of the fractional part F / D of the frequency division value (N + F / D) of the ΔΣ modulation type PLL circuit is set so as to satisfy the relationship of −D / 2 ≦ F ≦ D / 2. The number of bits of the first to fourth adders 12, 15, 17, 19 and the comparator 16 in the modulator 6a can be reduced as compared with the conventional case, the circuit scale can be reduced, and the current consumption can be suppressed.
[0036]
The ΔΣ modulation PLL circuit of the present embodiment is used for communication of, for example, a mobile phone, but the application is not particularly limited.
[0037]
【The invention's effect】
As described above in detail, according to the present invention, since the comparator in the ΔΣ modulator outputs three values, the output cycle of the ΔΣ modulator can be lengthened, and the occurrence of spurious can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a ΔΣ modulation type PLL circuit using a ΔΣ modulator according to the present invention.
FIG. 2 is a block diagram showing an internal configuration of the ΔΣ modulator of FIG. 1;
FIG. 3 is a block diagram showing an internal configuration of first to fourth adders.
FIG. 4 is an enlarged view of the adder of FIG. 3;
FIG. 5 is a logic diagram showing the operation of the adder of FIG. 3;
FIG. 6 is a block diagram showing a schematic configuration of a conventional PLL circuit using a conventional ΔΣ modulator.
[Explanation of symbols]
1 Voltage controlled oscillator (VCO)
2 frequency divider 3 phase comparator 4 charge pump 5 loop filter 6 ΔΣ modulator 11 multiplier 12 first adder 13 first integrator 14 second integrator 15 second adder 16 comparator 17 3 adders 18 1st delay circuit 19 4th adder 20 2nd delay circuit

Claims (7)

A multiplier for multiplying the first set value by the feedback signal;
A first adder for adding a second set value to an output signal of the multiplier;
A first integrator for integrating an output signal of the first adder;
A second integrator for integrating an output signal of the first integrator;
A second adder for adding output signals of the first and second integrators,
A comparator for comparing an output signal of the second adder with a value correlated with the first set value, and outputting a three-value indicating a comparison result as the feedback signal. Modulator. The Δ と き according to claim 1, wherein when the first set value is D and the second set value is F, the relationship of -D / 2? F? D / 2 is satisfied. Modulator. The comparator includes a first value indicating that an output signal of the second adder is larger than a value correlated with the first set value, and an output signal of the second adder being equal to the first signal. A second value indicating that the output value of the second adder is equal to a value correlated with the set value, and a third value indicating that the output signal of the second adder is smaller than the value correlated with the first set value. The ΔΣ modulation type PLL circuit according to claim 1, wherein the PLL circuit outputs the signal as a signal. A voltage-controlled oscillator that outputs an oscillation signal having a frequency corresponding to the voltage signal;
A frequency divider that outputs a frequency-divided signal obtained by dividing the frequency of the oscillation signal by a predetermined frequency division ratio,
A phase comparator that outputs a signal corresponding to the phase difference between the frequency-divided signal and the reference frequency signal,
A charge pump that outputs a current signal according to an output signal of the phase comparator,
A loop filter that outputs a voltage signal according to the current signal output from the charge pump,
A ΔΣ modulator for determining a frequency division ratio of the frequency divider,
The ΔΣ modulator includes:
A multiplier for multiplying the first set value by the feedback signal;
A first adder for adding a second set value to an output signal of the multiplier;
A first integrator for integrating an output signal of the first adder;
A second integrator for integrating an output signal of the first integrator;
A second adder for adding output signals of the first and second integrators,
A comparator that compares an output signal of the second adder with a value correlated with the first set value, and outputs a three-value indicating a comparison result as the feedback signal;
Has,
The frequency divider sets a frequency division ratio based on an output of the comparator. The comparator includes a first value indicating that an output signal of the second adder is larger than a signal correlated with the frequency division ratio signal, and an output signal of the second adder including the frequency division signal. And a third value indicating that the output signal of the second adder is smaller than the signal correlated with the frequency division ratio signal as the feedback signal. 5. The ΔΣ modulation type PLL circuit according to claim 4, wherein: The ΔΣ modulation type PLL circuit according to claim 4, wherein the value correlated with the first set value is a value obtained by quarter of the first set value. 7. 7. When the first set value is D and the second set value is F, the relationship of -D / 2 ≦ F ≦ D / 2 is satisfied. A ΔΣ modulation type PLL circuit according to any one of the above.

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