JP2004096015A - Semiconductor device and its fabricating process - Google Patents

Semiconductor device and its fabricating process Download PDF

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JP2004096015A
JP2004096015A JP2002258162A JP2002258162A JP2004096015A JP 2004096015 A JP2004096015 A JP 2004096015A JP 2002258162 A JP2002258162 A JP 2002258162A JP 2002258162 A JP2002258162 A JP 2002258162A JP 2004096015 A JP2004096015 A JP 2004096015A
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semiconductor chip
substrate
main surface
semiconductor
resin member
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JP4239528B2 (en
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Hirotaka Kobayashi
小林　寛隆
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Sony Corp
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Sony Corp
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device by which a warp is prevented, a lower profile, reduction in size, high reliability, and high yield are attained, and a fabricating process for this device. <P>SOLUTION: The semiconductor device includes a substrate 3 having a land 9 and connecting terminals 8 connected with the land 9, a semiconductor chip 2 mounted on the substrate 3, a resin member 4 filled in a gap between the semiconductor chip 2 and the substrate 3, and a straightening film 5 attached to one principal surface 2b opposite to the other principal surface 2a of the semiconductor chip 2 joined by the resin member 4. By means of stress caused by contraction of the resin member 4 filled in the gap between the semiconductor chip 2 and the substrate 3, the straightening film 5 straightens the warp generated by elastic deformation of the semiconductor chip 2, so that the resin member 4 contracts to prevent the warp from arising. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップと基板とを有する軽薄短小型の半導体装置、及びその製造方法に関する。
【０００２】
【従来の技術】
近年では、携帯電話に代表される情報通信技術の進展によって、様々な情報通信機器に例えば高周波通信モジュールや高速シリアルインターフェース等が実装されている。特に、携帯型の情報通信機器においては、これら高周波通信モジュールや高速シリアルインターフェースの軽薄短小化が要望されている。そして、この要望を満足させる半導体パッケージとして、図２１に示す軽薄短小型の半導体装置１００が注目されている。
【０００３】
この半導体装置１００は、特に薄型化を進めるために、シリコン基板上に半導体素子等が形成された厚みが１００μｍ以下の半導体チップ１０１を、例えばポリイミド等からなる厚みが１００μｍ程度の可撓性を有する基板１０２に実装させた構成になっている。具体的に、この半導体装置１００は、半導体チップ１０１の半導体素子等の一部に設けられた接続端子１０３と、基板１０２の表面に予めパターニングされた配線部等の一部に形成されたランド１０４とが電気的に接続され、これら半導体チップ１０１と基板１０２との間に例えばアンダーフィル法等により樹脂部材１０５が充填されることで、半導体チップ１０１を基板１０２に接合させた構成になっている。また、この半導体装置１００においては、樹脂部材１０５が接続端子１０３とランド１０４との接続部等を覆い保護することで、容易に半導体チップ１０１と基板１０２との接合が外れないようになっている。そして、この半導体装置１００は、全体の厚みが２００μｍ程度となり、軽薄短小化が実現された構成となる。
【０００４】
【発明が解決しようとする課題】
しかしながら、この上述した半導体装置１００では、線膨張率が比較的小さいシリコン基板上に半導体素子等が形成された半導体チップ１０１と、半導体チップ１０１以外の部材、特に樹脂部材１０５との線膨張率の違いにより反ってしまう。具体的には、半導体装置１００では、半導体チップ１０１と基板１０２との間に充填した樹脂部材１０５の線膨張率が大きく、例えば硬化した際に大きく収縮することから、この収縮による応力により基板１０２側に湾曲する反りが生じてしまう。
【０００５】
このように反った半導体装置１００では、実質の厚みは２００μｍ程度であるが、図２２に示すように、マザー基板２００に実装させた場合、反りの寸法も含まれてマザー基板２００の実装面２００ａを基準に図中矢印Ｘで示す最も厚い部分、いわゆる見かけの厚みが実質の厚みの数倍になることがある。このため、半導体装置１００では、軽薄短小化を図ることが困難となる。
【０００６】
また、半導体装置１００においては、基板１０２側に反ることで、基板１０２のランド１０４をマザー基板２００と平行に配設することが困難となり、マザー基板２００への実装自体も難しくなる。
【０００７】
さらに、この半導体装置１００では、−２５℃雰囲気と１２５℃雰囲気とを交互に繰り返す環境に放置するといった冷熱環境サイクル試験を行った場合、高温時に樹脂部材１０５が軟化して反りが無くなり、低温時に樹脂部材１０５が硬化し、収縮して反りが生じることが繰り返される。このため、半導体装置１００では、冷熱環境サイクル試験による反りの有無の繰り返しにより、半導体チップ１０１の接続端子１０３と基板１０２のランド１０４との接続部１０６に曲げ応力が繰り返し掛かり、この接続部１０６が断線して基板１０２と半導体チップ１０１との電気的接続が途切れてしまう問題もある。
【０００８】
そこで、本発明は、このような従来の事情に鑑みて提案されたものであり、反りを抑制して軽薄短小化を図ると共に製品信頼性及び歩留まりが高い半導体装置及びその製造方法を提供することを目的に提案されたものである。
【０００９】
【課題を解決するための手段】
上述した目的を達成する本発明に係る半導体装置は、ランドを有する基板と、ランドと電気的に接続される接続端子を有する半導体素子が一主面に形成され、基板上に実装された半導体チップと、半導体チップと基板との間に充填され、接続端子とランドとの接続部及び半導体素子を被覆すると共に半導体チップと基板とを接合させる樹脂部材と、樹脂部材により接合された半導体チップの一主面とは反対側の他主面に貼り付けられ、半導体チップとは異なる線膨張率を有する樹脂部材の膨張或いは収縮により半導体チップに生じる反りを矯正する矯正部材とを備えている。
【００１０】
また、本発明に係る半導体装置は、開口部とランドとを有する基板と、接続端子を有する半導体素子が一主面に形成され、接続端子と基板のランドとがワイヤーを介して電気的に接続された状態で基板の開口部内に収納された半導体チップと、少なくとも半導体チップが収納された基板の開口部内に充填され、接続端子とランドとのワイヤーを介した接続部と、ワイヤーと、半導体素子とを被覆すると共に半導体チップを基板の開口部内に固定する樹脂部材と、樹脂部材により固定された半導体チップの一主面とは反対側の他主面に貼り付けられ、半導体チップとは異なる線膨張率を有する樹脂部材の膨張或いは収縮により半導体チップに生じる反りを矯正する矯正部材とを備えている。
【００１１】
この半導体装置では、半導体チップの他主面に矯正部材が貼り付けられていることから、この矯正部材が、半導体チップとは異なる線膨張率を有し、半導体チップの一主面で半導体素子を覆うようにされた樹脂部材が膨張或いは収縮する際に生じる半導体チップを反らせる応力と釣り合いを取って半導体チップが弾性変形することで生じる反りを矯正させる。
【００１２】
上述した目的を達成する本発明に係る半導体装置の製造方法は、ランドを有する基板上に、接続端子を有する半導体素子が一主面に形成された半導体チップを、ランドと接続端子とが電気的に接続されるように配設する配設工程と、半導体チップと上記基板との間に、接続端子とランドとの接続部及び半導体素子を被覆するように樹脂部材を充填する充填工程と、半導体チップと基板との間に充填された樹脂部材が半導体チップと基板とを接合することで基板上に半導体チップを実装させる実装工程と、半導体チップの一主面とは反対側の他主面に、半導体チップとは異なる線膨張率を有する樹脂部材の膨張或いは収縮により半導体チップに生じる反りを矯正する矯正部材を貼り付ける貼付工程とを有している。
【００１３】
また、本発明に係る半導体装置の製造方法は、開口部とランドとを有する基板の開口部内に、接続端子を有する半導体素子が一主面に形成された半導体チップを収納し、ランドと接続端子とをワイヤーを介して接続する接続工程と、少なくとも半導体チップが収納された基板の開口部内に、接続端子とランドとのワイヤーを介した接続部と、ワイヤーと、半導体素子とを被覆するように樹脂部材を充填する充填工程と、基板の開口部内に充填された樹脂部材が半導体チップを基板の開口部内に固定させる固定工程と、半導体チップの一主面とは反対側の他主面に、半導体チップとは異なる線膨張率を有する樹脂部材の膨張或いは収縮により半導体チップに生じる反りを矯正する矯正部材を貼り付ける貼付工程とを有している。
【００１４】
この半導体装置の製造方法では、半導体チップとは異なる線膨張率を有する樹脂部材が半導体チップの一主面側に半導体素子を覆うように設けられ、半導体チップの反りを矯正する矯正部材が半導体チップの他主面側に貼り付けられた構成の半導体装置が製造される。このため、この半導体装置の製造方法では、半導体チップの他主面に貼り付けられた矯正部材が、半導体チップの一主面に設けられた樹脂部材の膨張或いは収縮により生じる半導体チップを反らせる応力と釣り合いを取って半導体チップが弾性変形することで生じる反りを矯正させることから、反りが抑制された半導体装置が得られる。
【００１５】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照して詳細に説明する。本発明の実施の形態として図１に示す半導体装置１は、厚みが１００μｍ以下の半導体チップ２と、この半導体チップ２を実装させる厚みが１００μｍ程度の基板３と、基板３に半導体チップ２を実装させる際にこれらを接合させる樹脂部材４と、半導体チップ２の基板３と相対する一主面２ａとは反対側の他主面２ｂに貼り付けられた矯正フィルム５とを有している。そして、この半導体装置１は、全体の厚みが２００μｍ程度にされて薄型化が図られている。
【００１６】
半導体チップ２は、例えばシリコン等からなるウエハー６上に半導体素子７が形成されている。また、半導体チップ２は、半導体素子７の一部として、半導体素子７が形成された面、いわゆる一主面２ａを囲むように複数の接続端子８が設けられた構成になっている。そして、半導体チップ２は、軽薄短小化を図るために、その厚みが１００μｍ以下、好ましくは５０μｍ〜３０μｍ程度にされている。
【００１７】
基板３は、ポリイミド等からなる可撓性フィルムの主面に配線回路等が予めパターニングされ、この配線回路の一部に、半導体チップ２が実装された際に接続端子８と電気的に接続されるランド９が設けられている。このランド９には、半導体チップ２が基板３に実装された際に、接続端子８との接続を適切に行うために、その表面に例えばニッケル−金等といった導電性金属からなるめっき層１０がめっき処理等により成膜されている。そして、基板３は、その厚みが５０μｍ〜１００μｍ程度にされることで、半導体装置１の軽薄短小化が図られる。
【００１８】
また、この基板３は、例えばランド９が露出する一主面３ａから反対側の他主面３ｂまで貫通するビア１１が形成され、このビア１１の他主面３ｂ側の端面にも導電性金属等によるめっき処理が施されて他主面３ｂ側で露出する端子部１２が形成されている。そして、基板３においては、半導体チップ２が実装された際に、一主面３ａ側で露出するランド９と、可撓性基板を貫通するビア１１と、他主面３ｂ側で露出する端子部１２とが電気的に接続されることで半導体チップ２に対する引出導体となる。なお、以上の例では、ポリイミド等からなる可撓性フィルムを用いた基板３について説明しているが、例えばリジットな基板を用いても良く、材質も無機、有機等に係わらず様々な材料を用いても良い。
【００１９】
樹脂部材４は、半導体チップ２と基板３との間に隙間無く充填されることで半導体チップ２と基板３とを接合させている。また、樹脂部材４は、半導体チップ２と基板３との間に、半導体チップ２の基板３と相対する面、すなわち半導体チップ２の一主面２ａに設けられた半導体素子７を覆うように充填されることで半導体素子７を保護するように機能する。また、樹脂部材４は、半導体チップ２と基板３との間に充填された際に、接続端子８とランド９との接続部も覆うことで、接続端子８とランド９との接続を保護すると共に、半導体チップ２と基板３との電気的な接続を強固にさせる。
【００２０】
この樹脂部材４には、例えばＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ　Ｃｏｎｄｕｃｔｉｖｅ　Ｐａｓｔｅ）、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ　Ｃｏｎｄｕｃｔｉｖｅ　Ｆｉｌｍ）等の異方性導電樹脂、ＮＣＰ（Ｎｏｎ−Ｃｏｎｄｕｃｔｉｖｅ　Ｐａｓｔｅ）、ＮＣＦ（Ｎｏｎ−Ｃｏｎｄｕｃｔｉｖｅ　Ｆｉｌｍ）等の導電粒子の無い樹脂等といった熱硬化性樹脂或いは光硬化性樹脂等を用いる。樹脂部材４として、例えばＡＣＰやＡＣＦ等を用いた場合、樹脂に含有される導電性粒子が接続端子８とランド９とを適切に接続させ、ＮＣＰやＮＣＦ等を用いた場合、樹脂が硬化した際の収縮力が接続端子８とランド９とを互いに押しつけることで適切に接続させるように作用する。
【００２１】
矯正フィルム５は、半導体チップ２の他主面２ｂに接着剤層１３で貼り付けられている。矯正フィルム５を半導体チップ２に貼り付ける接着剤層１３には、例えばエポキシ系接着材等といった有機樹脂系の接着材を用い、この有機樹脂系の接着材としては熱硬化性樹脂、熱可塑性樹脂のどちらでも使用可能である。矯正フィルム５には、例えばＣｕ、Ｎｉ、Ｆｅ、Ａｌ等のうちの一種以上からなる金属箔、セラミック等の無機材料からなるフィルム、ポリイミド等の有機材料からなるフィルム等を用いる。矯正フィルム５においては、例えば表面にＮｉめっき等が施されたＦｅ箔等を用いることで、低コスト化が図れる。
【００２２】
この矯正フィルム５は、半導体チップ２と基板３との間に半導体素子７を覆うように充填された樹脂部材４が硬化して収縮する際に生じる半導体チップ２を基板３側に反らせる応力と釣り合いを取ることから、半導体チップ２に生じた弾性変形による反りを矯正させるように作用する。このため、矯正フィルム５は、半導体チップ２よりも高い線膨張率を有している。
【００２３】
また、矯正フィルム５は、その厚みを調整することで、樹脂部材４が収縮して生じた半導体チップ２を反らせる応力と釣り合いを取っている。例えば基板３の厚みｔ１、弾性率ｐ１、線膨張率α１とし、樹脂部材４の厚みｔ２、弾性率ｐ２、線膨張率α２とし、矯正フィルム５の厚みｔ３、弾性率ｐ３、線膨張率α３とし、矯正フィルム５を半導体チップ２に貼り付ける際の接着材の厚みｔ４、弾性率ｐ４、線膨張率α４とし、半導体チップ２の線膨張率をα０とした場合、矯正フィルム５の厚みｔ３は｛（ｔ１×ｐ１×（α１−α０））＋（ｔ２×ｐ２×（α２−α０））−（ｔ４×ｐ４×（α４−α０））｝／（ｐ３×（α３−α０））で示される数式で求まる。
【００２４】
具体的には、基板３を厚みが５０μｍのポリイミドとし、樹脂部材４を厚みが５０μｍのＡＣＦとし、矯正フィルム５を銅箔とし、矯正フィルム５を半導体チップ２に貼り付ける接着材を１０μｍの厚みに塗布したエポキシ樹脂とし、ウエハー６をシリコン製のウエハー６を有する半導体チップ２の厚みを１００μｍとする場合、上述した数式より求めた銅箔からなる矯正フィルム５の厚みは１２μｍとなる。なお、上述した矯正フィルム５の厚みを求める数式は、矯正フィルム５の厚みを求める際の目安であり、半導体チップ２の反りの状態で矯正フィルム５の厚みを多少調整する必要がある。
【００２５】
次に、以上のような構成の半導体装置１の製造方法について説明する。この半導体装置１を製造する際は、先ず、図２に示すように、可撓性を有する厚みが５０μｍ程度の基板３を用意し、この基板３の一主面３ａ上に、例えばエポキシ樹脂、シリコン樹脂、アクリル樹脂等からなる接着層２０と、ポリエステル、ポリプロピレン、オレフィン、塩化ビニル等からなる保護層２１とを順次積層形成させる。
次に、基板３には、図３に示すように、例えばパンチング加工等により接着層２０と保護層２１とを一括して厚み方向に貫通する孔部２２が複数設けられる。
【００２６】
次に、基板３には、図４に示すように、保護層２１が除去されて接着層２０全面を覆うように例えば銅等の導電性金属箔等からなる金属箔２３が貼り付けられる。
【００２７】
次に、金属箔２３には、図５に示すように、例えばフォトリソグラフ処理等により所望の回路配線となるようにパターニング加工が施され、回路配線の一部にランド９が形成される。
【００２８】
次に、基板３の一主面３ａ上方には、図６に示すように、接着層２０、ランド９を覆うレジスト層２４が形成される。また、孔部２２には、その内周壁面に例えば銅等の導電性金属からなるめっきが施されてめっき部２５が形成され、孔内に導電ペースト２６が埋め込まれる。これにより、孔部２２は、基板３の一主面３ａから反対側の他主面３ｂまで貫通し、ランド９と導通するビア１１となる。
【００２９】
次に、レジスト層２４には、図７に示すように、ランド９が露出する開口部２４ａが設けられる。そして、基板３の一主面３ａ上方には、レジスト層２４及び開口部２４ａを覆うように例えばニッケル−金等からなる金属めっき層２６が成膜される。
【００３０】
次に、基板３の一主面３ａ側上方には、図８に示すように、レジスト層２４が除去されることで、ランド９を覆うようにめっき層１０が形成される。また、ビア１１における基板３の他主面３ｂで露出する端部には、導電ペースト２６を蓋するように例えばニッケル−金等のめっき処理が施されることで端子部１２が形成される。
【００３１】
次に、基板３の一主面３ａ上方には、図９に示すように、半導体チップ２が実装される領域に、上述した樹脂部材４が設けられる。図９においては、フィルム状の樹脂部材４を貼り付けた場合を示している。
【００３２】
次に、基板３の一主面３ａ側には、図１０に示すように、上述したウエハー６上に接続端子８を有する半導体素子７が形成された半導体チップ２を実装させる。具体的に、半導体チップ２を基板３に実装させる際は、半導体チップ２を所定の温度で加熱させながら樹脂部材４に押しつけることで樹脂部材４を軟化させ、半導体チップ２の接続端子８を軟化した樹脂部材４に突き刺す。このとき、半導体チップ２においては、接続端子８が基板３のランド９と相対するように基板３の一主面３ａ上に設置させるようにする。そして、半導体チップ２は、基板３の一主面３ａに押しつけながら、例えば冷却等によって樹脂部材４を硬化させることで接続端子８とランド９とが電気的に接続された状態で基板３の一主面３ａ上に実装される。
【００３３】
このとき、基板３に実装された半導体チップ２は、図１１に示すように、比較的に線膨張率が大きい樹脂部材４が硬化した際の収縮による応力が掛かり、基板３と共に基板３側に弾性変形して反ってしまう。このため、半導体チップ２及び基板３では、図中矢印Ａで示す実際の厚みＡに比べ、図中矢印Ｂで示す見かけの厚みが厚くなってしまう。
【００３４】
次に、基板３側に反りが生じた半導体チップ２には、他主面２ｂ側に例えば熱硬化性又は熱可塑性のエポキシ系接着剤等からなる接着剤層１３を介して矯正フィルム５を貼り付ける。半導体チップ２に矯正フィルム５を貼り付ける際は、半導体チップ２の他主面２ｂに、矯正フィルム５を間に接着剤層１３を介して押しつけながら所定の温度で加熱する。これにより、矯正フィルム５は、半導体チップ２に生じた反りを矯正するように半導体チップ２の他主面２ｂに貼り付けられることになる。
【００３５】
以上のようにして、図１２に示すような反りが矯正され、見かけの厚みも大幅に抑制され、薄型化が図られた半導体装置１が製造される。
【００３６】
この半導体装置１では、半導体チップ２の他主面２ｂに矯正フィルム５が貼り付けられていることから、この矯正フィルム５が半導体チップ２の一主面２ａで半導体素子７を覆うようにされた樹脂部材４が硬化する等して収縮する際に生じる半導体チップ２を弾性変形させて反らせる応力と釣り合いを取るように作用する。
【００３７】
したがって、この半導体装置１では、矯正フィルム５が半導体チップ２に生じた反りを矯正することから全体の反りが抑えられ、従来のように反りにより見かけの厚みが厚くなることが無く、薄型化を図ることができる。
【００３８】
また、この半導体装置１は、マザー基板３０に実装させる場合、図１３に示すように、例えばフリップチップボンディング法等により実装面３０ａにバンプ３１を介して実装面３０ａ上に設けられたランド３２に、端子部１２が電気的に接続されることでマザー基板３０に実装されることになる。
【００３９】
この半導体装置１では、上述したように、反りが抑制されていることから、マザー基板３０等に実装する際に、マザー基板３０の実装面３０ａと、基板３の他主面３ｂとが略平行となるように実装面３０ａに配設されることから、端子部１２をランド３２に適切に接続することが可能となり、マザー基板３０に歩留まり良く実装させることができる。
【００４０】
なお、上述した実施の形態においては、基板３に半導体チップ２を実装させた後に、矯正フィルム５を貼り付けたが、このような製造方法に限定されることはなく、例えば矯正フィルム５を貼り付けた半導体チップ２を基板３に実装させて製造された半導体装置１でも上述した作用効果が得られる。
【００４１】
以上の例では、可撓性を有する基板３の一主面３ａに半導体チップ２を実装させた半導体装置１について説明したが、本発明が適用可能な半導体装置は上述した構成に限定されることはなく、例えば図１４に示すような構成の半導体装置４０にも適用可能である。以下に、本発明の第２の実施の形態として半導体装置４０について説明する。
【００４２】
この半導体装置４０は、厚みが１００μｍ以下の半導体チップ４１と、この半導体チップ４１が実装される厚みが１００μｍ程度の基板４２と、基板４２に半導体チップ４１が実装される際に半導体チップ４１を固定する樹脂部材４３と、半導体チップ４１の一方主面に貼り付けられた矯正フィルム４４とを有している。
【００４３】
半導体チップ４１は、上述した半導体装置１における半導体チップ２と同様に、例えばシリコン等からなるウエハー４５上に半導体素子４６が形成された構成となっている。この半導体チップ４１は、半導体素子４６の一部として一主面４１ａを囲むように複数の接続端子４７が設けられた構成になっている。そして、この半導体チップ４１も、厚みが１００μｍ以下、好ましくは５０μｍ〜３０μｍ程度にされており、軽薄短小化が図られている。
【００４４】
基板４２は、例えばフェノール樹脂等からなるリジット基板の一主面４２ａから他主面４２ｂ貫通する開口部４８が設けられ、一主面４１ａに配線回路等が予めパターニングされた構成となっている。この基板４２に半導体チップ４１を実装させる際は、開口部４８内に半導体チップ４１が収納されることで行われる。
【００４５】
この基板４２には、一主面４２ａの配線回路の一部に、半導体チップ４１が実装された際に接続端子４７と例えば導電性金属のワイヤー等といった接続線４９を介して電気的に接続されるランド５０が開口部４８を囲むように設けられている。そして、基板４２では、その厚みが５０μｍ〜１００μｍ程度にされ、半導体チップ４１を開口部４８内に収納させることで、半導体装置４０を半導体装置１に比べて更に薄型化させることが可能となる。
【００４６】
また、この基板４２は、例えばランド５０が露出する一主面４２ａから反対側の他主面４２ｂまで貫通するビア５１が形成され、このビア５１の他主面４２ｂ側の端面にも導電性金属等によるめっき処理で他主面４２ｂ側に露出するた端子部５２が形成されている。そして、基板４２においては、半導体チップ４１が実装された際に、一主面４２ａ側で露出するランド５０と、リジット基板を貫通するビア５１と、他主面４２ｂ側で露出する端子部５２とが電気的に接続されることで半導体チップ４１に対する引出導体となる。ランド５０及び端子部５２には、半導体チップ４１が基板４２に実装された際に、接続線４９を介した接続端子４７との接続を適切に行うために、その表面に例えばニッケル−金等といった導電性金属からなるめっき層５３ａ、５３ｂがめっき処理等により成膜されている。
【００４７】
樹脂部材４３は、少なくとも半導体チップ４１が収納された基板４２の開口部４８内に充填されることで半導体チップ４１を開口部４８内で固定している。また、この樹脂部材４３は、接続端子４７と接続線４９との接続部５４ａと、ランド５０との接続線４９との接続部５４ｂと、接続線４９と、半導体チップ４１の一主面４１ａとを被覆し、これらを保護している。そして、この樹脂部材４３には、上述した半導体装置１でも使用可能な、例えばＡＣＰやＮＣＰ等の他に、エポキシ系の樹脂ペースト等、ペースト状の熱硬化性樹脂或いは光硬化性樹脂等を用いる。
【００４８】
矯正フィルム４４は、上述した半導体装置１と同様に、半導体チップ４１の他主面４１ｂに接着剤層５５で貼り付けられている。矯正フィルム４４には、上述した矯正フィルム５と同様に、例えばＣｕ、Ｎｉ、Ｆｅ、Ａｌ等のうちの一種以上からなる金属箔、セラミック等の無機材料からなるフィルム、ポリイミド等の有機材料からなるフィルム等を用いる。矯正フィルム４４を半導体チップ４１に貼り付ける接着剤層５５には、上述した半導体装置１における接着剤層１３と同様の材料を用いる。
【００４９】
この矯正フィルム４４は、半導体チップ４１を基板４２に固定するように開口部４８内に充填された樹脂部材４３が硬化して収縮する際に生じる半導体チップ４１を一主面４１ａ側に反らせる応力と釣り合いを取って半導体チップ４１に生じた弾性変形による反りを矯正させるように作用する。このため、矯正フィルム４４は、半導体チップ４１よりも高い線膨張率を有している。
【００５０】
次に、以上のような構成の半導体装置４０の製造方法について説明する。この半導体装置４０を製造する際は、先ず、図１５に示すように、厚みが１００μｍ程度のリジットな基板４２として用意し、この基板４２を例えばポリイミド、ポリエステル等からなるダミーフィルム６０を、間に粘着層６１を介して貼り付ける。この基板４２は、上述したように、開口部４８と、ランド５０と、ビア５１と、端子部５２と、めっき層５３ａ、５３ｂとを有している。
【００５１】
次に、ダミーフィルム６０上には、図１６に示すように、基板４２の開口部４８内に収納するように、矯正フィルム４４を粘着層６１に貼り付ける。なお、矯正フィルム４４は、接着層６１に貼り付けられることによって基板４２の開口部４８内に容易に固定されることになる。
【００５２】
次に、矯正フィルム４４には、図１７に示すように、半導体チップ４１を他主面４１ｂ側が対向するように接着剤層５５を介して貼り付ける。これにより、矯正フィルム４４及び半導体チップ４１は、粘着層６１上に順次積層された状態で基板４２の開口部４８内に収納されることになる。
【００５３】
次に、半導体チップ４１は、図１８に示すように、接続端子４７と、基板４２のランド５０とが接続線４９を介して接続されることで、基板４２に電気的に接続される。接続端子４７とランド５０とは、例えばワイヤーボンディング法等によって接続線４９で適切に接続される。
【００５４】
次に、基板４２の開口部４８内には、図１９に示すように、接続端子４７と接続線４９との接続部５４ａと、ランド５０との接続線４９との接続部５４ｂと、接続線４９と、半導体チップ４１の一主面４１ａとを被覆し、矯正フィルム４４及び半導体チップ４１を固定する樹脂部材４３が充填される。この樹脂部材４３には、上述したペースト状の熱硬化性樹脂或いは光硬化性樹脂等を用いる。そして、この樹脂部材４３は、開口部４８に充填された後に、熱硬化或いは光硬化されることで硬化して矯正フィルム４４及び半導体チップ４１を固定することになる。
【００５５】
このとき、半導体チップ４１には、比較的に線膨張率が大きい樹脂部材４３が硬化により収縮して半導体素子４６側、すなわち一主面４１ａ側に反らせる応力が掛かることになる。しかしながら、半導体チップ４１においては、一主面４１ａ側に反らせる応力と釣り合いを取って反りを矯正させるように作用する矯正フィルム４４が他主面４１ｂ側に配設されていることから、一主面４１ａ側に反ることが抑制される。
【００５６】
次に、ダミーフィルム６０は、図２０に示すように、基板４２及び矯正フィルム４４等より粘着層６１が剥がされることで、粘着層６１と共に除去される。以上のようにして、半導体装置４０が製造される。
【００５７】
この半導体装置４０は、上述した半導体装置１と同様に、半導体チップ４１の他主面４１ｂに矯正フィルム４４が貼り付けられていることから、この矯正フィルム４４が一主面４１ａで半導体素子４６を覆うようにされた樹脂部材４３が硬化して収縮する際に生じる半導体チップ４１を弾性変形させて反らせる応力と釣り合いを取るように作用することになる。
【００５８】
したがって、この半導体装置４０でも、矯正フィルム４４が半導体チップ４１に生じた反りを矯正することから全体の反りが抑えられ、従来のように反りにより見かけの厚みが厚くなることが無く、薄型化を図ることができる。特に、この半導体装置４０では、半導体チップ４１が基板４２の開口部４８内に収納された構成となっていることから、上述した半導体装置１のような基板３上に半導体チップ２を積層実装させた構成に比べ、更なる薄型化が図れる。
【００５９】
また、半導体装置４０では、上述した半導体装置１と同様に、反りが抑制されていることから、例えばマザー基板等に実装する際に歩留まり良く、適切に実装させることができる。
【００６０】
なお、上述した第２の実施の形態においては、配設した矯正フィルム４４に半導体チップ４１を貼り付けているが、このような製造方法に限定されることはなく、例えばダミーフィルム６０が除去された後に、基板４２の開口部４８に収納された半導体チップ４１の他主面４１ｂに矯正フィルム４４が貼り付けられて製造された半導体装置４０でも上述した作用効果が得られる。
【００６１】
【実施例】
以下、本発明を適用した半導体装置を実際に作製した実施例及び比較例について説明する。
【００６２】
〈実施例〉
実施例では、先ず、可撓性を有する厚みが５０μｍの可撓性を有する基板を用意し、この基板の一主面上にエポキシ樹脂からなる接着層と、ポリエステルからなる保護層とを順次積層形成させた。
次に、この基板には、パンチング加工により接着層と保護層とを一括して厚み方向に貫通する孔部を複数形成させた。
【００６３】
次に、基板には、保護層が除去されて接着層全面を覆うように銅からなる導電性の金属箔を貼り付けた。
【００６４】
次に、金属箔には、フォトリソグラフ処理等により所望の回路配線を形成させるパターニング加工を施した。そして、回路配線の一部には、ランドを形成させた。
【００６５】
次に、基板の接着層側の主面には、接着層、回路配線及びランドを覆うレジスト層を形成させた。また、この孔部には、その内周面に銅によるめっきが施されて、孔内に導電ペーストを埋め込んだ。このようにして、基板に、一主面から他主面に貫通し、ランドに接続するビアを形成した。
【００６６】
次に、レジスト層には、ランドが露出する開口部を設けた。そして、基板の一主面には、レジスト層及び開口部を覆うようにニッケル−金からなるめっきを成膜させた。
【００６７】
次に、基板の一主面上には、レジスト層を除去することで、ランドを覆うようにめっき層を形成させた。また、ビアにおける基板の他主面で露出する端部には、導電ペーストを蓋するようにニッケル−金からなるめっきを成膜させた端子部を形成させた。
【００６８】
次に、基板の一主面上には、半導体チップが実装される領域に、ＡＣＦからなる厚みが５０μｍの樹脂フィルムを配設させた。
【００６９】
次に、基板の一主面側には、ウエハー上に接続端子を有する半導体素子が形成された厚みが１００μｍの半導体チップを、半導体素子が基板に相対するように実装させた。具体的に、この半導体チップを基板に実装させた際は、半導体チップを所定の温度で加熱させながら樹脂フィルムに押しつけることで樹脂フィルムが軟化し、半導体チップの接続端子を軟化した樹脂フィルムに突き刺した。このとき、半導体チップにおいては、接続端子が基板のランドと相対するように基板の一主面上に設置させるようにした。そして、基板の一主面には、半導体チップを押しつけながら、樹脂フィルムを冷却し、硬化させることで接続端子とランドとを電気的に接続するように半導体チップを実装させた。
【００７０】
このとき、基板に実装された半導体チップは、基板に接合させる樹脂フィルムが硬化した際の収縮による応力が掛かり基板と共に反ってしまった。この反りは、半導体チップを基板に実装させた際の実際の全体の厚み、すなわち基板、樹脂フィルム、半導体チップの総厚みが２００μｍ程度になるところを、見かけの厚みを３８０μｍにさせてしまった。
【００７１】
次に、反りが生じた半導体チップには、他主面側に熱硬化性のエポキシ接着剤を１０μｍの厚みに塗布して厚みが１２μｍの銅箔からなる矯正部材を貼り付けた。具体的に、半導体チップに矯正部材を貼り付ける際は、半導体チップの基板と相対する一主面とは反対側の他主面に、矯正部材を間にエポキシ接着剤を介して押しつけながら所定の温度で加熱し、矯正部材を半導体チップの他主面に貼り付けた。
【００７２】
以上のようにして、半導体チップに生じた反りを矯正するように半導体チップの他主面に矯正部材が貼り付けられ、矯正部材により半導体チップに生じた反りが矯正されることで、全体の厚み、すなわち見かけの厚みが矯正部材を貼り付ける前の３８０μｍから２１０μｍに抑えられた半導体装置が製造された。
【００７３】
〈比較例〉
比較例では、半導体チップに矯正部材を貼り付けないこと以外は、上述した実施例と同様にして半導体装置を製造した。そして、この比較例では、半導体装置に反りが生じ、全体の厚み、すなわち見かけの厚みが３８０μｍになった。
【００７４】
そして、以上のように製造した実施例及び比較例の半導体装置について、−２５℃雰囲気と１２５℃雰囲気とを交互に繰り返す環境に放置するといった冷熱環境サイクル試験を施し、半導体チップの接続端子と、基板のランドとにおける断線の有無を確認した。
【００７５】
冷熱環境サイクル試験時の接続端子とランドとにおける断線の有無を確認した結果、半導体チップに矯正部材が貼り付けられた実施例では、冷熱環境を２０００サイクル以上変化させても接続端子とランドとに断線は見られなかった。これに対し、比較例では、冷熱環境を１０００サイクル変化させたところで接続端子とランドとが断線してしまった。
【００７６】
比較例では、１２５℃の環境下において樹脂フィルムが軟化して半導体チップに対する応力が無くなり見かけの厚みが２００μｍ程度になり、−２５℃の環境下において樹脂フィルムが硬化して半導体チップに反らせる応力が生じて見かけの厚みが４００μｍ程度となる。これにより、比較例では、冷熱環境サイクル試験による反りの有無の繰り返され、半導体チップの接続端子と基板のランドとの接続部に曲げ応力が繰り返し掛かることから、接続端子とランドとが途切れて断線してしまう。
【００７７】
実施例では、１２５℃の環境下における樹脂フィルムの軟化や、−２５℃の環境下における樹脂フィルムの硬化による応力が半導体チップに掛かっても、矯正部材が半導体チップに掛かる応力を矯正して冷熱環境サイクル試験により反りの有無が繰り返されることを抑制し、２００μｍ程度の厚みに保持させる。したがって、実施例では、冷熱環境サイクル試験により生じる反りを抑え、半導体チップの接続端子と基板のランドとの接続部に掛かる曲げ応力を抑制することから、接続端子とランドとが冷熱環境サイクル試験により断線してしまうことが防止される。
【００７８】
以上のことから、半導体チップに矯正部材を貼り付けることは、冷熱環境サイクル試験により半導体チップと基板との電気的接続が途切れて断線してしまうことを防止し、優れた製品信頼性を有する半導体装置を製造する上で大変有効であることがわかる。
【００７９】
【発明の効果】
以上、詳細に説明したように、本発明によれば、半導体チップの樹脂部材が覆われた一主面とは反対側の他主面に矯正部材を貼り付けることで、矯正部材が樹脂部材の膨張或いは収縮する際に生じる半導体チップを反らせる応力と釣り合いを取って半導体チップに生じた弾性変形を矯正させることから、反りが抑制された半導体装置が得られる。
【００８０】
したがって、本発明によれば、矯正部材が半導体チップに生じた弾性変形を矯正し、全体の反りを抑えることから、従来のように反りにより見かけの厚みが厚くなることが無く、薄型化が図られた半導体装置を提供できる。
【００８１】
本発明によれば、全体の反りが抑制されていることから、例えば他の基板等に実装する際に、半導体装置を他の基板に実装面同士を略平行にして配設することが可能となり、他の基板に対して半導体装置を容易に実装させることができ、他の基板に実装させる際の歩留まりを向上できる半導体装置が得られる。
【００８２】
本発明によれば、矯正部材により反りが矯正されており、周囲の雰囲気温度に伴う樹脂部材の膨張或いは収縮で生じる反りが抑制されていることから、冷たい雰囲気と厚い雰囲気とを交互に繰り返しても半導体チップと基板との電気的な接続が途切れることの無い優れた製品信頼性を有する半導体装置が得られる。
【図面の簡単な説明】
【図１】本発明に係る半導体装置を示す縦断面図である。
【図２】同半導体装置の製造工程を説明するための図であり、基板上に接着層と保護層とが順次積層形成された状態を示す縦断面図である。
【図３】同半導体装置の製造工程を説明するための図であり、基板に孔部が複数形成された状態を示す縦断面図である。
【図４】同半導体装置の製造工程を説明するための図であり、基板上に金属箔が貼り付けられた状態を示す縦断面図である。
【図５】同半導体装置の製造工程を説明するための図であり、基板上にランドが形成された状態を示す縦断面図である。
【図６】同半導体装置の製造工程を説明するための図であり、基板上にレジスト層が形成された状態を示す縦断面図である。
【図７】同半導体装置の製造工程を説明するための図であり、レジスト層に開口部が設けられた状態を示す縦断面図である。
【図８】同半導体装置の製造工程を説明するための図であり、レジスト層が除去されてランドを覆うめっき層が形成された状態を示す縦断面図である。
【図９】同半導体装置の製造工程を説明するための図であり、基板上に樹脂部材が設けられた状態を示す縦断面図である。
【図１０】同半導体装置の製造工程を説明するための図であり、基板上に樹脂部材を介して半導体チップが実装された状態を示す縦断面図である。
【図１１】同半導体装置の製造工程を説明するための図であり、基板上に半導体チップが実装された際に樹脂部材の収縮による応力で半導体チップ及び基板に反りが生じた状態を示す縦断面図である。
【図１２】同半導体装置の製造工程を説明するための図であり、製造された半導体装置を示す縦断面図である。
【図１３】同半導体装置がマザー基板に実装された状態を示す縦断面図である。
【図１４】本発明に係る半導体装置おける第２の実施の形態を示す縦断面図である。
【図１５】同第２の実施の形態の半導体装置における製造工程を説明するための図であり、ダミーフィルム上に基板を貼り付けた状態を示す縦断面図である。
【図１６】同第２の実施の形態の半導体装置における製造工程を説明するための図であり、基板の開口部内に矯正フィルムを配設させた状態を示す縦断面図である。
【図１７】同第２の実施の形態の半導体装置における製造工程を説明するための図であり、基板の開口部内に配設させた矯正フィルム上に半導体チップを積層させた状態を示す縦断面図である。
【図１８】同第２の実施の形態の半導体装置における製造工程を説明するための図であり、基板と半導体チップとを接続線で電気的に接続させた状態を示す縦断面図である。
【図１９】同第２の実施の形態の半導体装置における製造工程を説明するための図であり、樹脂部材で基板の開口部内に半導体チップを固定させた状態を示す縦断面図である。
【図２０】同第２の実施の形態の半導体装置における製造工程を説明するための図であり、製造された第２の実施の形態の半導体装置を示す縦断面図である。
【図２１】従来の半導体装置を示す縦断面図である。
【図２２】同半導体装置をマザー基板に実装させた状態を示す縦断面図である。
【符号の説明】
１，４０　半導体装置、２，４１　半導体チップ、３，４２　基板、４，４３樹脂部材、５，４４　矯正フィルム、７，４６　半導体素子、８，４７　接続端子、９，５０　ランド、１１，５１　ビア、１２，５２　端子部、３０　マザー基板、４８　開口部、４９　接続線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a light, thin, short, and small semiconductor device having a semiconductor chip and a substrate, and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, with the development of information communication technology represented by mobile phones, various information communication devices are equipped with, for example, high-frequency communication modules and high-speed serial interfaces. In particular, in portable information communication devices, there is a demand for reductions in the size of these high-frequency communication modules and high-speed serial interfaces. As a semiconductor package that satisfies this demand, a light, thin, short, and small semiconductor device 100 shown in FIG. 21 has attracted attention.
[0003]
The semiconductor device 100 has a flexibility of forming a semiconductor chip 101 having a thickness of 100 μm or less on which a semiconductor element or the like is formed on a silicon substrate, for example, a polyimide or the like having a thickness of about 100 μm in order to promote a reduction in thickness. It is configured to be mounted on a substrate 102. Specifically, the semiconductor device 100 includes a connection terminal 103 provided on a part of a semiconductor element or the like of a semiconductor chip 101 and a land 104 formed on a part of a wiring portion or the like which is patterned in advance on the surface of a substrate 102. Are electrically connected to each other, and the semiconductor chip 101 is bonded to the substrate 102 by filling the resin member 105 between the semiconductor chip 101 and the substrate 102 by, for example, an underfill method. . In the semiconductor device 100, the resin member 105 covers and protects a connection portion between the connection terminal 103 and the land 104, so that the bonding between the semiconductor chip 101 and the substrate 102 is not easily separated. . The semiconductor device 100 has a configuration in which the overall thickness is about 200 μm and the size and weight are reduced.
[0004]
[Problems to be solved by the invention]
However, in the above-described semiconductor device 100, the linear expansion coefficient of the semiconductor chip 101 in which a semiconductor element or the like is formed on a silicon substrate having a relatively small linear expansion coefficient and a member other than the semiconductor chip 101, particularly, the resin member 105 Warped by the difference. Specifically, in the semiconductor device 100, the resin member 105 filled between the semiconductor chip 101 and the substrate 102 has a large coefficient of linear expansion and, for example, largely contracts when cured. Warpage that curves to the side occurs.
[0005]
In the warped semiconductor device 100, the substantial thickness is about 200 μm. However, as shown in FIG. 22, when the semiconductor device 100 is mounted on the mother substrate 200, the mounting surface 200a of the mother substrate 200 includes the dimensions of the warp. , The thickest part indicated by an arrow X in the figure, the so-called apparent thickness, may be several times the substantial thickness. For this reason, in the semiconductor device 100, it is difficult to reduce the size and weight.
[0006]
Further, in the semiconductor device 100, warping toward the substrate 102 makes it difficult to arrange the lands 104 of the substrate 102 in parallel with the mother substrate 200, and it becomes difficult to mount the lands 104 on the mother substrate 200 itself.
[0007]
Further, in the semiconductor device 100, when a cold environmental cycle test is performed in which the semiconductor device 100 is left in an environment in which an atmosphere of -25 ° C. and an atmosphere of 125 ° C. are alternately repeated, the resin member 105 is softened at a high temperature and does not warp. The resin member 105 is hardened, shrunk and warped repeatedly. For this reason, in the semiconductor device 100, a bending stress is repeatedly applied to the connection portion 106 between the connection terminal 103 of the semiconductor chip 101 and the land 104 of the substrate 102 due to the repetition of the presence or absence of the warp in the thermal environment cycle test. There is also a problem that the electrical connection between the substrate 102 and the semiconductor chip 101 is interrupted due to disconnection.
[0008]
Therefore, the present invention has been proposed in view of such a conventional situation, and provides a semiconductor device having high product reliability and a high yield while suppressing warpage to reduce the weight and thickness, and a method of manufacturing the same. It has been proposed for the purpose.
[0009]
[Means for Solving the Problems]
A semiconductor device according to the present invention that achieves the above-described object includes a semiconductor chip having a substrate having lands and a semiconductor element having connection terminals electrically connected to the lands formed on one main surface, and mounted on the substrate. A resin member filled between the semiconductor chip and the substrate to cover the connection between the connection terminal and the land and the semiconductor element and to join the semiconductor chip to the substrate; and a resin chip joined by the resin member. A correction member that is attached to the other main surface opposite to the main surface and that corrects a warp generated in the semiconductor chip due to expansion or contraction of a resin member having a linear expansion coefficient different from that of the semiconductor chip.
[0010]
In the semiconductor device according to the present invention, a substrate having an opening and a land and a semiconductor element having a connection terminal are formed on one main surface, and the connection terminal and the land of the substrate are electrically connected to each other via a wire. A semiconductor chip housed in the opening of the substrate in a state where the semiconductor chip is filled, at least a connection portion of the connection terminal via a wire between the connection terminal and the land filled in the opening of the substrate housing the semiconductor chip, a wire, and the semiconductor element. A resin member for covering the semiconductor chip and fixing the semiconductor chip in the opening of the substrate, and a line different from the semiconductor chip attached to the other main surface opposite to the one main surface of the semiconductor chip fixed by the resin member A correction member for correcting a warp generated in the semiconductor chip due to expansion or contraction of the resin member having an expansion coefficient.
[0011]
In this semiconductor device, since the correction member is attached to the other main surface of the semiconductor chip, the correction member has a different coefficient of linear expansion from the semiconductor chip, and the semiconductor element is formed on one main surface of the semiconductor chip. A warp caused by elastic deformation of the semiconductor chip is corrected by balancing a stress generated when the covered resin member expands or contracts and warps the semiconductor chip.
[0012]
A method of manufacturing a semiconductor device according to the present invention that achieves the above-described object includes a method of manufacturing a semiconductor chip in which a semiconductor element having a connection terminal is formed on one main surface on a substrate having a land. A filling step of filling a resin member between the semiconductor chip and the substrate so as to cover a connection portion between the connection terminal and the land and the semiconductor element; and A resin member filled between the chip and the substrate joins the semiconductor chip and the substrate to mount the semiconductor chip on the substrate, and the other main surface opposite to the one main surface of the semiconductor chip. And a bonding step of bonding a correction member for correcting a warp generated in the semiconductor chip due to expansion or contraction of a resin member having a linear expansion coefficient different from that of the semiconductor chip.
[0013]
Further, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor chip having a semiconductor element having a connection terminal formed on one main surface is housed in an opening of a substrate having an opening and a land. And a connection step of connecting the connection terminal via a wire, and at least in an opening of the substrate in which the semiconductor chip is housed, so as to cover the connection portion via the wire between the connection terminal and the land, the wire, and the semiconductor element. A filling step of filling the resin member, a fixing step in which the resin member filled in the opening of the substrate fixes the semiconductor chip in the opening of the substrate, and the other main surface opposite to the one main surface of the semiconductor chip, And a bonding step of bonding a correction member for correcting a warp generated in the semiconductor chip due to expansion or contraction of a resin member having a linear expansion coefficient different from that of the semiconductor chip.
[0014]
In this method of manufacturing a semiconductor device, a resin member having a linear expansion coefficient different from that of the semiconductor chip is provided on one main surface side of the semiconductor chip so as to cover the semiconductor element, and the correction member for correcting the warpage of the semiconductor chip is provided on the semiconductor chip. A semiconductor device having a configuration in which the semiconductor device is attached to the other main surface side is manufactured. For this reason, in this method of manufacturing a semiconductor device, the correcting member attached to the other main surface of the semiconductor chip is not affected by the stress that warps the semiconductor chip caused by expansion or contraction of the resin member provided on one main surface of the semiconductor chip. Since the warpage caused by the elastic deformation of the semiconductor chip is balanced, the semiconductor device in which the warpage is suppressed can be obtained.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. A semiconductor device 1 shown in FIG. 1 as an embodiment of the present invention has a semiconductor chip 2 having a thickness of 100 μm or less, a substrate 3 having a thickness of about 100 μm on which the semiconductor chip 2 is mounted, and a semiconductor chip 2 mounted on the substrate 3. It has a resin member 4 to which these are joined at the time of bonding, and a correction film 5 attached to the other main surface 2b opposite to the one main surface 2a of the semiconductor chip 2 opposite to the substrate 3. The thickness of the semiconductor device 1 is reduced to about 200 μm as a whole.
[0016]
The semiconductor chip 2 has a semiconductor element 7 formed on a wafer 6 made of, for example, silicon or the like. Further, the semiconductor chip 2 has a configuration in which a plurality of connection terminals 8 are provided as a part of the semiconductor element 7 so as to surround a surface on which the semiconductor element 7 is formed, that is, a so-called one main surface 2a. The semiconductor chip 2 has a thickness of 100 μm or less, preferably about 50 μm to 30 μm in order to reduce the size and weight.
[0017]
In the substrate 3, a wiring circuit or the like is patterned in advance on a main surface of a flexible film made of polyimide or the like, and is electrically connected to the connection terminal 8 when the semiconductor chip 2 is mounted on a part of the wiring circuit. Land 9 is provided. In order to properly connect with the connection terminals 8 when the semiconductor chip 2 is mounted on the substrate 3, a plating layer 10 made of a conductive metal such as nickel-gold is provided on the land 9. The film is formed by plating or the like. The thickness of the substrate 3 is set to about 50 μm to 100 μm, so that the semiconductor device 1 can be reduced in weight and thickness.
[0018]
Further, the substrate 3 is provided with a via 11 penetrating from, for example, one main surface 3a from which the land 9 is exposed to the other main surface 3b on the opposite side. The terminal portion 12 exposed on the other main surface 3b side is formed by plating treatment. In the substrate 3, when the semiconductor chip 2 is mounted, the land 9 exposed on the one main surface 3a side, the via 11 penetrating the flexible substrate, and the terminal portion exposed on the other main surface 3b side 12 are electrically connected to each other to serve as a lead conductor for the semiconductor chip 2. In the above example, the substrate 3 using a flexible film made of polyimide or the like is described. For example, a rigid substrate may be used, and various materials may be used regardless of the material, such as inorganic or organic. May be used.
[0019]
The resin member 4 fills the space between the semiconductor chip 2 and the substrate 3 without any gap, thereby joining the semiconductor chip 2 and the substrate 3 together. The resin member 4 is filled between the semiconductor chip 2 and the substrate 3 so as to cover the surface of the semiconductor chip 2 facing the substrate 3, that is, the semiconductor element 7 provided on one main surface 2a of the semiconductor chip 2. This functions to protect the semiconductor element 7. When the resin member 4 is filled between the semiconductor chip 2 and the substrate 3, the resin member 4 also covers the connection between the connection terminal 8 and the land 9, thereby protecting the connection between the connection terminal 8 and the land 9. At the same time, the electrical connection between the semiconductor chip 2 and the substrate 3 is strengthened.
[0020]
The resin member 4 includes an anisotropic conductive resin such as ACP (Anisotropic Conductive Paste) and ACF (Anisotropic Conductive Film), an NCP (Non-Conductive Paste), and an NCF (Non-Conductive Paste without Non-Conductive Particle). A thermosetting resin such as a resin or a photocurable resin is used. For example, when ACP or ACF is used as the resin member 4, the conductive particles contained in the resin appropriately connect the connection terminal 8 and the land 9, and when NCP or NCF is used, the resin is cured. The contraction force at the time acts to press the connection terminal 8 and the land 9 together so as to properly connect them.
[0021]
The correction film 5 is attached to the other main surface 2b of the semiconductor chip 2 with an adhesive layer 13. As the adhesive layer 13 for attaching the correction film 5 to the semiconductor chip 2, an organic resin-based adhesive such as an epoxy-based adhesive is used. As the organic resin-based adhesive, a thermosetting resin, a thermoplastic resin, or the like is used. Both can be used. As the correction film 5, for example, a metal foil made of one or more of Cu, Ni, Fe, and Al, a film made of an inorganic material such as ceramic, a film made of an organic material such as polyimide, and the like are used. The cost of the correction film 5 can be reduced by using, for example, an Fe foil or the like having a surface plated with Ni or the like.
[0022]
The straightening film 5 balances the stress generated when the resin member 4 filled between the semiconductor chip 2 and the substrate 3 so as to cover the semiconductor element 7 cures and contracts, and the semiconductor chip 2 warps toward the substrate 3. Therefore, it acts to correct the warpage due to the elastic deformation generated in the semiconductor chip 2. Therefore, the correction film 5 has a higher linear expansion coefficient than the semiconductor chip 2.
[0023]
Adjusting the thickness of the correction film 5 balances the stress generated by the resin member 4 contracting and warping the semiconductor chip 2. For example, the thickness t1, the elastic modulus p1, and the linear expansion coefficient α1 of the substrate 3 are set as the thickness t2, the elastic modulus p2, and the linear expansion coefficient α2 of the resin member 4, and the thickness t3, the elastic modulus p3, and the linear expansion coefficient α3 of the correction film 5 are set. If the thickness t4, elastic modulus p4, and linear expansion coefficient α4 of the adhesive when the correction film 5 is attached to the semiconductor chip 2 are set to α4, and the linear expansion coefficient of the semiconductor chip 2 is set to α0, the thickness t3 of the correction film 5 becomes ｛. (T1 × p1 × (α1-α0)) + (t2 × p2 × (α2-α0)) − (t4 × p4 × (α4-α0))｝ / (p3 × (α3-α0)) Is determined by
[0024]
Specifically, the substrate 3 is made of polyimide having a thickness of 50 μm, the resin member 4 is made of ACF having a thickness of 50 μm, the correction film 5 is made of copper foil, and the adhesive for attaching the correction film 5 to the semiconductor chip 2 is made of 10 μm. When the thickness of the semiconductor chip 2 having the silicon wafer 6 is 100 μm, the thickness of the correction film 5 made of the copper foil obtained from the above equation is 12 μm. Note that the above formula for calculating the thickness of the correction film 5 is a guide when calculating the thickness of the correction film 5, and it is necessary to slightly adjust the thickness of the correction film 5 in a state where the semiconductor chip 2 is warped.
[0025]
Next, a method for manufacturing the semiconductor device 1 having the above configuration will be described. In manufacturing the semiconductor device 1, first, as shown in FIG. 2, a flexible substrate 3 having a thickness of about 50 μm is prepared, and an epoxy resin, for example, is formed on one main surface 3a of the substrate 3. An adhesive layer 20 made of silicon resin, acrylic resin, or the like, and a protective layer 21 made of polyester, polypropylene, olefin, vinyl chloride, or the like are sequentially laminated.
Next, as shown in FIG. 3, the substrate 3 is provided with a plurality of holes 22 that collectively penetrate the adhesive layer 20 and the protective layer 21 in the thickness direction by, for example, punching.
[0026]
Next, as shown in FIG. 4, a metal foil 23 made of a conductive metal foil such as copper is attached to the substrate 3 so that the protective layer 21 is removed and the entire surface of the adhesive layer 20 is covered.
[0027]
Next, as shown in FIG. 5, the metal foil 23 is patterned by, for example, a photolithographic process or the like so as to form a desired circuit wiring, and the land 9 is formed in a part of the circuit wiring.
[0028]
Next, a resist layer 24 covering the adhesive layer 20 and the lands 9 is formed above the one main surface 3a of the substrate 3, as shown in FIG. The inner peripheral wall surface of the hole 22 is plated with a conductive metal such as copper to form a plated portion 25, and a conductive paste 26 is embedded in the hole. As a result, the hole 22 penetrates from the one main surface 3a of the substrate 3 to the other main surface 3b on the opposite side, and becomes the via 11 that is electrically connected to the land 9.
[0029]
Next, as shown in FIG. 7, the resist layer 24 is provided with an opening 24a from which the land 9 is exposed. Then, a metal plating layer 26 made of, for example, nickel-gold or the like is formed above one main surface 3a of the substrate 3 so as to cover the resist layer 24 and the opening 24a.
[0030]
Next, as shown in FIG. 8, by removing the resist layer 24, a plating layer 10 is formed to cover the land 9 above the one main surface 3a side of the substrate 3. Further, a terminal portion 12 is formed on an end portion of the via 11 exposed on the other main surface 3 b of the substrate 3 by plating with, for example, nickel-gold or the like so as to cover the conductive paste 26.
[0031]
Next, as shown in FIG. 9, the resin member 4 described above is provided above the one main surface 3 a of the substrate 3 in a region where the semiconductor chip 2 is mounted. FIG. 9 shows a case where a film-shaped resin member 4 is attached.
[0032]
Next, as shown in FIG. 10, the semiconductor chip 2 on which the semiconductor element 7 having the connection terminal 8 is formed on the wafer 6 is mounted on the one main surface 3a side of the substrate 3. Specifically, when mounting the semiconductor chip 2 on the substrate 3, the resin member 4 is softened by pressing the semiconductor chip 2 against the resin member 4 while heating the semiconductor chip 2 at a predetermined temperature, and the connection terminals 8 of the semiconductor chip 2 are softened. The resin member 4 is pierced. At this time, in the semiconductor chip 2, the connection terminals 8 are disposed on one main surface 3 a of the substrate 3 so as to face the lands 9 of the substrate 3. The semiconductor chip 2 is pressed against the one main surface 3a of the substrate 3 while the resin member 4 is cured by, for example, cooling, so that the connection terminals 8 and the lands 9 are electrically connected to each other. It is mounted on the main surface 3a.
[0033]
At this time, as shown in FIG. 11, the semiconductor chip 2 mounted on the substrate 3 is subjected to a stress due to contraction when the resin member 4 having a relatively large linear expansion coefficient is cured, and is applied to the substrate 3 side together with the substrate 3. It is elastically deformed and warps. Therefore, in the semiconductor chip 2 and the substrate 3, the apparent thickness indicated by the arrow B in the figure becomes larger than the actual thickness A indicated by the arrow A in the figure.
[0034]
Next, on the semiconductor chip 2 having the warp on the substrate 3 side, the correction film 5 is attached to the other main surface 2b side via an adhesive layer 13 made of, for example, a thermosetting or thermoplastic epoxy adhesive. wear. When attaching the correction film 5 to the semiconductor chip 2, the semiconductor film 2 is heated at a predetermined temperature while pressing the correction film 5 against the other main surface 2 b of the semiconductor chip 2 with the adhesive layer 13 interposed therebetween. As a result, the correction film 5 is attached to the other main surface 2b of the semiconductor chip 2 so as to correct the warpage generated in the semiconductor chip 2.
[0035]
As described above, the semiconductor device 1 in which the warpage as shown in FIG. 12 is corrected, the apparent thickness is significantly suppressed, and the thickness is reduced is manufactured.
[0036]
In the semiconductor device 1, since the correction film 5 is attached to the other main surface 2 b of the semiconductor chip 2, the correction film 5 covers the semiconductor element 7 with one main surface 2 a of the semiconductor chip 2. It acts so as to balance with the stress generated by elastically deforming and warping the semiconductor chip 2 when the resin member 4 contracts due to hardening or the like.
[0037]
Therefore, in the semiconductor device 1, since the correction film 5 corrects the warp generated in the semiconductor chip 2, the entire warp is suppressed, and the apparent thickness is not increased due to the warp as in the related art, and the thickness can be reduced. Can be planned.
[0038]
When the semiconductor device 1 is mounted on the mother substrate 30, as shown in FIG. 13, the lands 32 provided on the mounting surface 30a via the bumps 31 on the mounting surface 30a by, for example, a flip chip bonding method or the like. The terminal section 12 is electrically connected to be mounted on the motherboard 30.
[0039]
In the semiconductor device 1, since the warpage is suppressed as described above, when the semiconductor device 1 is mounted on the mother substrate 30 or the like, the mounting surface 30 a of the mother substrate 30 and the other main surface 3 b of the substrate 3 are substantially parallel. Since the terminals 12 are disposed on the mounting surface 30a such that the terminal portions 12 can be appropriately connected to the lands 32, they can be mounted on the mother substrate 30 with a high yield.
[0040]
In the above-described embodiment, the correction film 5 is attached after the semiconductor chip 2 is mounted on the substrate 3. However, the present invention is not limited to such a manufacturing method. The above-described effects can be obtained also in the semiconductor device 1 manufactured by mounting the attached semiconductor chip 2 on the substrate 3.
[0041]
In the above example, the semiconductor device 1 in which the semiconductor chip 2 is mounted on one main surface 3a of the flexible substrate 3 has been described. However, the semiconductor device to which the present invention can be applied is limited to the above-described configuration. However, the present invention is also applicable to a semiconductor device 40 having a configuration as shown in FIG. Hereinafter, a semiconductor device 40 will be described as a second embodiment of the present invention.
[0042]
The semiconductor device 40 has a semiconductor chip 41 having a thickness of 100 μm or less, a substrate 42 having a thickness of about 100 μm on which the semiconductor chip 41 is mounted, and a semiconductor chip 41 fixed when the semiconductor chip 41 is mounted on the substrate 42. And a correction film 44 attached to one main surface of the semiconductor chip 41.
[0043]
The semiconductor chip 41 has a configuration in which a semiconductor element 46 is formed on a wafer 45 made of, for example, silicon or the like, similarly to the semiconductor chip 2 in the semiconductor device 1 described above. The semiconductor chip 41 has a configuration in which a plurality of connection terminals 47 are provided so as to surround one main surface 41 a as a part of the semiconductor element 46. The semiconductor chip 41 also has a thickness of 100 μm or less, preferably about 50 μm to 30 μm, and is light and thin.
[0044]
The substrate 42 is provided with an opening 48 extending from one main surface 42a to another main surface 42b of a rigid substrate made of, for example, a phenol resin, and a wiring circuit or the like is patterned on the one main surface 41a in advance. When the semiconductor chip 41 is mounted on the substrate 42, the semiconductor chip 41 is housed in the opening 48.
[0045]
The substrate 42 is electrically connected to a connection terminal 47 via a connection line 49 such as a conductive metal wire when the semiconductor chip 41 is mounted on a part of a wiring circuit on one main surface 42a. Land 50 is provided so as to surround the opening 48. The thickness of the substrate 42 is set to about 50 μm to 100 μm, and the semiconductor chip 40 is housed in the opening 48, so that the semiconductor device 40 can be made thinner than the semiconductor device 1.
[0046]
Further, the substrate 42 has a via 51 penetrating therethrough, for example, from one main surface 42a where the land 50 is exposed to the other main surface 42b on the opposite side. The terminal portion 52 exposed on the other main surface 42b side is formed by plating processing using the method described above. In the substrate 42, when the semiconductor chip 41 is mounted, the land 50 exposed on the one main surface 42a side, the via 51 penetrating the rigid substrate, and the terminal portion 52 exposed on the other main surface 42b side are formed. Are electrically connected to each other to serve as a lead conductor for the semiconductor chip 41. When the semiconductor chip 41 is mounted on the substrate 42, the lands 50 and the terminal portions 52 have, for example, nickel-gold or the like on their surfaces in order to properly connect to the connection terminals 47 via the connection wires 49. Plating layers 53a and 53b made of a conductive metal are formed by plating or the like.
[0047]
The resin member 43 fixes the semiconductor chip 41 in the opening 48 by filling at least into the opening 48 of the substrate 42 in which the semiconductor chip 41 is accommodated. The resin member 43 includes a connection portion 54a between the connection terminal 47 and the connection line 49, a connection portion 54b between the land 50 and the connection line 49, the connection line 49, and one main surface 41a of the semiconductor chip 41. To protect them. For the resin member 43, a paste-like thermosetting resin or a photo-setting resin, such as an epoxy-based resin paste, which can be used in the semiconductor device 1 described above, for example, other than ACP or NCP, is used. .
[0048]
The correction film 44 is attached to the other main surface 41b of the semiconductor chip 41 with an adhesive layer 55, similarly to the semiconductor device 1 described above. The correction film 44 is made of, for example, a metal foil made of one or more of Cu, Ni, Fe, and Al, a film made of an inorganic material such as ceramic, and an organic material such as polyimide, similarly to the correction film 5 described above. Use a film or the like. The same material as the adhesive layer 13 in the semiconductor device 1 described above is used for the adhesive layer 55 for attaching the correction film 44 to the semiconductor chip 41.
[0049]
The straightening film 44 has a stress generated when the resin member 43 filled in the opening 48 is hardened and contracted so as to fix the semiconductor chip 41 to the substrate 42 and warp the semiconductor chip 41 toward the one main surface 41a. It acts to balance and correct the warpage due to the elastic deformation generated in the semiconductor chip 41. For this reason, the correction film 44 has a higher linear expansion coefficient than the semiconductor chip 41.
[0050]
Next, a method of manufacturing the semiconductor device 40 having the above configuration will be described. When manufacturing the semiconductor device 40, first, as shown in FIG. 15, a rigid substrate 42 having a thickness of about 100 μm is prepared, and the substrate 42 is sandwiched with a dummy film 60 made of, for example, polyimide, polyester, or the like. It is attached via the adhesive layer 61. As described above, the substrate 42 has the openings 48, the lands 50, the vias 51, the terminal portions 52, and the plating layers 53a and 53b.
[0051]
Next, as shown in FIG. 16, the correction film 44 is attached to the adhesive layer 61 on the dummy film 60 so as to be stored in the opening 48 of the substrate 42. The correction film 44 is easily fixed in the opening 48 of the substrate 42 by being attached to the adhesive layer 61.
[0052]
Next, as shown in FIG. 17, the semiconductor chip 41 is attached to the correction film 44 via the adhesive layer 55 such that the other main surface 41b faces the same. Accordingly, the correction film 44 and the semiconductor chip 41 are stored in the opening 48 of the substrate 42 in a state of being sequentially laminated on the adhesive layer 61.
[0053]
Next, the semiconductor chip 41 is electrically connected to the substrate 42 by connecting the connection terminals 47 and the lands 50 of the substrate 42 via the connection lines 49, as shown in FIG. The connection terminal 47 and the land 50 are appropriately connected by a connection line 49 by, for example, a wire bonding method.
[0054]
Next, as shown in FIG. 19, a connection portion 54a between the connection terminal 47 and the connection line 49, a connection portion 54b between the land 50 and the connection line 49, The resin member 43 that covers the 49 and the one main surface 41 a of the semiconductor chip 41 and fixes the correction film 44 and the semiconductor chip 41 is filled. For the resin member 43, the above-mentioned paste-like thermosetting resin or photo-setting resin is used. After the resin member 43 is filled in the opening 48, the resin member 43 is cured by heat curing or light curing to fix the correction film 44 and the semiconductor chip 41.
[0055]
At this time, a stress is applied to the semiconductor chip 41 such that the resin member 43 having a relatively large coefficient of linear expansion contracts due to curing and warps toward the semiconductor element 46, that is, toward the one main surface 41a. However, in the semiconductor chip 41, the correction film 44 acting to balance the stress warping to the one main surface 41a and to correct the warp is disposed on the other main surface 41b side. Warping toward the 41a side is suppressed.
[0056]
Next, as shown in FIG. 20, the dummy film 60 is removed together with the adhesive layer 61 by peeling the adhesive layer 61 from the substrate 42, the correction film 44, and the like. As described above, the semiconductor device 40 is manufactured.
[0057]
In the semiconductor device 40, the correction film 44 is attached to the other main surface 41b of the semiconductor chip 41 in the same manner as the semiconductor device 1 described above, so that the correction film 44 attaches the semiconductor element 46 to the one main surface 41a. This acts to balance the stress generated when the semiconductor chip 41 is elastically deformed and warped when the covered resin member 43 cures and contracts.
[0058]
Therefore, in the semiconductor device 40 as well, since the correction film 44 corrects the warpage generated in the semiconductor chip 41, the entire warpage is suppressed, and the apparent thickness does not increase due to the warpage as in the related art, and the thickness can be reduced. Can be planned. In particular, since the semiconductor device 40 has a configuration in which the semiconductor chip 41 is housed in the opening 48 of the substrate 42, the semiconductor chip 2 is stacked and mounted on the substrate 3 like the semiconductor device 1 described above. It is possible to further reduce the thickness as compared with the configuration described above.
[0059]
Further, in the semiconductor device 40, similarly to the above-described semiconductor device 1, since warpage is suppressed, for example, when the semiconductor device 40 is mounted on a mother board or the like, the semiconductor device 40 can be mounted appropriately with a high yield.
[0060]
In the above-described second embodiment, the semiconductor chip 41 is attached to the correction film 44 provided. However, the present invention is not limited to such a manufacturing method. For example, the dummy film 60 is removed. After that, the semiconductor device 40 manufactured by attaching the correction film 44 to the other main surface 41b of the semiconductor chip 41 housed in the opening 48 of the substrate 42 also has the above-described effects.
[0061]
【Example】
Hereinafter, Examples and Comparative Examples in which a semiconductor device to which the present invention is applied are actually manufactured will be described.
[0062]
<Example>
In the embodiment, first, a flexible substrate having a thickness of 50 μm having flexibility is prepared, and an adhesive layer made of epoxy resin and a protective layer made of polyester are sequentially laminated on one main surface of the substrate. Formed.
Next, a plurality of holes were formed in the substrate through the adhesive layer and the protective layer in the thickness direction by punching.
[0063]
Next, a conductive metal foil made of copper was attached to the substrate so that the protective layer was removed and the entire surface of the adhesive layer was covered.
[0064]
Next, the metal foil was subjected to a patterning process for forming a desired circuit wiring by photolithographic processing or the like. A land was formed on a part of the circuit wiring.
[0065]
Next, a resist layer covering the adhesive layer, the circuit wiring, and the land was formed on the main surface of the substrate on the adhesive layer side. The inner peripheral surface of the hole was plated with copper, and a conductive paste was embedded in the hole. In this way, vias were formed in the substrate, penetrating from one main surface to the other main surface, and connected to the lands.
[0066]
Next, an opening for exposing the land was provided in the resist layer. Then, a plating made of nickel-gold was formed on one main surface of the substrate so as to cover the resist layer and the opening.
[0067]
Next, a plating layer was formed on one main surface of the substrate so as to cover the lands by removing the resist layer. Further, at the end of the via exposed on the other main surface of the substrate, a terminal portion formed by plating nickel-gold to cover the conductive paste was formed.
[0068]
Next, on one main surface of the substrate, a resin film having a thickness of 50 μm made of ACF was disposed in a region where the semiconductor chip was mounted.
[0069]
Next, on one main surface side of the substrate, a semiconductor chip having a thickness of 100 μm, on which a semiconductor element having connection terminals was formed on a wafer, was mounted so that the semiconductor element was opposed to the substrate. Specifically, when this semiconductor chip is mounted on a substrate, the resin film is softened by pressing the semiconductor chip against the resin film while heating the semiconductor chip at a predetermined temperature, and the connection terminals of the semiconductor chip are pierced into the softened resin film. Was. At this time, in the semiconductor chip, the connection terminals are arranged on one main surface of the substrate so as to face the lands of the substrate. Then, the semiconductor chip was mounted on one main surface of the substrate such that the resin film was cooled and cured while pressing the semiconductor chip, so that the connection terminals and the lands were electrically connected.
[0070]
At this time, the semiconductor chip mounted on the substrate was warped together with the substrate due to stress caused by shrinkage when the resin film bonded to the substrate was cured. This warp causes the apparent thickness to be 380 μm where the actual overall thickness of the semiconductor chip mounted on the substrate, that is, the total thickness of the substrate, the resin film, and the semiconductor chip is about 200 μm.
[0071]
Next, a thermosetting epoxy adhesive was applied to the other main surface side to a thickness of 10 μm on the warped semiconductor chip, and a straightening member made of copper foil having a thickness of 12 μm was attached. Specifically, when the correction member is attached to the semiconductor chip, the correction member is pressed on the other main surface opposite to the one main surface of the semiconductor chip opposite to the substrate with an epoxy adhesive therebetween. The heating member was heated at a temperature, and the correction member was attached to the other main surface of the semiconductor chip.
[0072]
As described above, the correction member is attached to the other main surface of the semiconductor chip so as to correct the warpage generated in the semiconductor chip, and the correction member corrects the warp generated in the semiconductor chip, thereby obtaining the entire thickness. That is, a semiconductor device was manufactured in which the apparent thickness was suppressed from 380 μm before attaching the correction member to 210 μm.
[0073]
<Comparative example>
In the comparative example, a semiconductor device was manufactured in the same manner as in the above-described example except that the straightening member was not attached to the semiconductor chip. In this comparative example, the semiconductor device was warped, and the overall thickness, that is, the apparent thickness was 380 μm.
[0074]
Then, the semiconductor devices of the example and the comparative example manufactured as described above are subjected to a cold environmental cycle test in which the semiconductor devices are left in an environment in which an atmosphere of -25 ° C. and an atmosphere of 125 ° C. are alternately repeated. The presence or absence of disconnection between the land and the substrate was confirmed.
[0075]
As a result of checking the presence or absence of disconnection between the connection terminal and the land at the time of the thermal environment cycle test, in the embodiment in which the straightening member was attached to the semiconductor chip, even if the thermal environment was changed over 2000 cycles or more, the connection terminal and the land remained No disconnection was seen. On the other hand, in the comparative example, the connection terminal and the land were disconnected when the cooling environment was changed by 1000 cycles.
[0076]
In the comparative example, the resin film is softened under the environment of 125 ° C., the stress on the semiconductor chip is eliminated, and the apparent thickness becomes about 200 μm. This results in an apparent thickness of about 400 μm. Thereby, in the comparative example, the presence / absence of the warpage in the thermal environment cycle test is repeated, and the bending portion is repeatedly applied to the connection portion between the connection terminal of the semiconductor chip and the land of the substrate. Resulting in.
[0077]
In the embodiment, even if stress due to softening of the resin film in an environment of 125 ° C. or curing of the resin film in an environment of −25 ° C. is applied to the semiconductor chip, the correcting member corrects the stress applied to the semiconductor chip to cool and heat the semiconductor chip. Repeating the presence or absence of warping by the environmental cycle test is suppressed, and the thickness is maintained at about 200 μm. Therefore, in the embodiment, since the warpage caused by the thermal environment cycle test is suppressed and the bending stress applied to the connection portion between the connection terminal of the semiconductor chip and the land of the substrate is suppressed, the connection terminal and the land are subjected to the thermal environment cycle test. Disconnection is prevented.
[0078]
From the above, attaching the straightening member to the semiconductor chip prevents the electrical connection between the semiconductor chip and the substrate from being interrupted and broken by a cold environment cycle test, and the semiconductor has excellent product reliability. It turns out that it is very effective in manufacturing the device.
[0079]
【The invention's effect】
As described above in detail, according to the present invention, the correction member is attached to the other main surface of the semiconductor chip opposite to the one main surface covered with the resin member, so that the correction member is formed of the resin member. Since the elastic deformation generated in the semiconductor chip is corrected by balancing the stress generated when the semiconductor chip warps when expanding or contracting, a semiconductor device in which warpage is suppressed can be obtained.
[0080]
Therefore, according to the present invention, since the correction member corrects the elastic deformation generated in the semiconductor chip and suppresses the entire warp, the apparent thickness does not increase due to the warp as in the related art, and the thickness can be reduced. Semiconductor device can be provided.
[0081]
According to the present invention, since the entire warp is suppressed, for example, when mounting the semiconductor device on another substrate or the like, it is possible to arrange the semiconductor device on the other substrate with the mounting surfaces substantially parallel to each other. In addition, a semiconductor device that can easily mount the semiconductor device on another substrate and can improve the yield when mounting the semiconductor device on another substrate can be obtained.
[0082]
According to the present invention, the warp is corrected by the correction member, and the warp caused by the expansion or contraction of the resin member due to the ambient atmosphere temperature is suppressed, so that a cold atmosphere and a thick atmosphere are alternately repeated. Also, a semiconductor device having excellent product reliability without interruption of electrical connection between the semiconductor chip and the substrate can be obtained.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view showing a semiconductor device according to the present invention.
FIG. 2 is a view for explaining a manufacturing process of the semiconductor device, and is a longitudinal sectional view showing a state in which an adhesive layer and a protective layer are sequentially laminated on a substrate.
FIG. 3 is a view for explaining a manufacturing process of the semiconductor device, and is a longitudinal sectional view showing a state where a plurality of holes are formed in the substrate.
FIG. 4 is a view for explaining a manufacturing process of the semiconductor device, and is a longitudinal sectional view showing a state where a metal foil is stuck on a substrate.
FIG. 5 is a view for explaining a manufacturing process of the semiconductor device, and is a longitudinal sectional view showing a state where lands are formed on the substrate.
FIG. 6 is a view for explaining the manufacturing process of the semiconductor device, and is a longitudinal sectional view showing a state where a resist layer is formed on the substrate.
FIG. 7 is a view for explaining the manufacturing process of the semiconductor device, and is a longitudinal sectional view showing a state in which an opening is provided in the resist layer.
FIG. 8 is a view for explaining the manufacturing process of the semiconductor device, and is a longitudinal sectional view showing a state in which the plating layer covering the lands is formed by removing the resist layer.
FIG. 9 is a view for explaining the manufacturing process of the semiconductor device, and is a longitudinal sectional view showing a state where a resin member is provided on the substrate.
FIG. 10 is a view for explaining the manufacturing process of the semiconductor device, and is a longitudinal sectional view showing a state where a semiconductor chip is mounted on a substrate via a resin member.
FIG. 11 is a view for explaining a manufacturing process of the semiconductor device, and is a longitudinal section showing a state in which the semiconductor chip and the substrate are warped due to stress caused by shrinkage of a resin member when the semiconductor chip is mounted on the substrate. FIG.
FIG. 12 is a view for explaining a manufacturing process of the semiconductor device, and is a longitudinal sectional view showing the manufactured semiconductor device.
FIG. 13 is a longitudinal sectional view showing a state where the semiconductor device is mounted on a mother board.
FIG. 14 is a longitudinal sectional view showing a second embodiment of the semiconductor device according to the present invention.
FIG. 15 is a view for explaining the manufacturing process in the semiconductor device of the second embodiment, and is a longitudinal sectional view showing a state where a substrate is attached on a dummy film.
FIG. 16 is a view for explaining the manufacturing process in the semiconductor device of the second embodiment, and is a longitudinal sectional view showing a state in which a correction film is provided in the opening of the substrate.
FIG. 17 is a view for explaining the manufacturing process in the semiconductor device of the second embodiment, and is a longitudinal section showing a state in which semiconductor chips are stacked on a correction film provided in the opening of the substrate. FIG.
FIG. 18 is a view for explaining the manufacturing process in the semiconductor device according to the second embodiment, and is a longitudinal sectional view showing a state where the substrate and the semiconductor chip are electrically connected by connection lines.
FIG. 19 is a view for explaining the manufacturing process in the semiconductor device of the second embodiment, and is a longitudinal sectional view showing a state where the semiconductor chip is fixed in the opening of the substrate with the resin member.
FIG. 20 is a view for explaining the manufacturing process in the semiconductor device of the second embodiment, and is a longitudinal sectional view showing the manufactured semiconductor device of the second embodiment.
FIG. 21 is a longitudinal sectional view showing a conventional semiconductor device.
FIG. 22 is a longitudinal sectional view showing a state where the semiconductor device is mounted on a mother board.
[Explanation of symbols]
1,40 semiconductor device, 2,41 semiconductor chip, 3,42 substrate, 4,43 resin member, 5,44 straightening film, 7,46 semiconductor element, 8,47 connection terminal, 9,50 land, 11,51 via , 12, 52 terminal part, 30 mother board, 48 opening, 49 connection line

Claims (4)

ランドを有する基板と、
上記ランドと電気的に接続される接続端子を有する半導体素子が一主面に形成され、上記基板上に実装された半導体チップと、
上記半導体チップと上記基板との間に充填され、上記接続端子と上記ランドとの接続部及び上記半導体素子を被覆すると共に上記半導体チップと上記基板とを接合させる樹脂部材と、
上記樹脂部材により接合された上記半導体チップの一主面とは反対側の他主面に貼り付けられ、上記半導体チップとは異なる線膨張率を有する上記樹脂部材の膨張或いは収縮により上記半導体チップに生じる反りを矯正する矯正部材と
を備える半導体装置。A substrate having lands;
A semiconductor element having a connection terminal electrically connected to the land is formed on one main surface, and a semiconductor chip mounted on the substrate,
A resin member that is filled between the semiconductor chip and the substrate, covers the connection portion between the connection terminal and the land and the semiconductor element, and joins the semiconductor chip and the substrate,
Affixed to the other main surface opposite to the one main surface of the semiconductor chip joined by the resin member, and the resin chip having a linear expansion coefficient different from that of the semiconductor chip due to expansion or contraction of the resin member. A semiconductor device comprising: a correction member configured to correct generated warpage. 開口部とランドとを有する基板と、
接続端子を有する半導体素子が一主面に形成され、上記接続端子と上記基板のランドとがワイヤーを介して電気的に接続された状態で上記基板の開口部内に収納された半導体チップと、
少なくとも上記半導体チップが収納された上記基板の開口部内に充填され、上記接続端子と上記ランドとの上記ワイヤーを介した接続部と、上記ワイヤーと、上記半導体素子とを被覆すると共に上記半導体チップを上記基板の開口部内に固定する樹脂部材と、
上記樹脂部材により固定された上記半導体チップの一主面とは反対側の他主面に貼り付けられ、上記半導体チップとは異なる線膨張率を有する上記樹脂部材の膨張或いは収縮により上記半導体チップに生じる反りを矯正する矯正部材と
を備える半導体装置。A substrate having an opening and a land;
A semiconductor element having connection terminals formed on one main surface, a semiconductor chip housed in an opening of the substrate in a state where the connection terminals and the lands of the substrate are electrically connected via wires,
Filling at least the opening of the substrate containing the semiconductor chip, connecting the connection terminal and the land via the wire, the wire, and the semiconductor element while covering the semiconductor chip. A resin member fixed in the opening of the substrate,
Affixed to the other main surface opposite to the one main surface of the semiconductor chip fixed by the resin member, the semiconductor chip is expanded or contracted by the resin member having a linear expansion coefficient different from that of the semiconductor chip. A semiconductor device comprising: a correction member configured to correct generated warpage. ランドを有する基板上に、接続端子を有する半導体素子が一主面に形成された半導体チップを、上記ランドと上記接続端子とが電気的に接続されるように配設する配設工程と、
上記半導体チップと上記基板との間に、上記接続端子と上記ランドとの接続部及び上記半導体素子を被覆するように樹脂部材を充填する充填工程と、
上記半導体チップと上記基板との間に充填された上記樹脂部材が上記半導体チップと上記基板とを接合することで上記基板上に上記半導体チップを実装させる実装工程と、
上記半導体チップの一主面とは反対側の他主面に、上記半導体チップとは異なる線膨張率を有する上記樹脂部材の膨張或いは収縮により上記半導体チップに生じる反りを矯正する矯正部材を貼り付ける貼付工程と
を有する半導体装置の製造方法。An arranging step of arranging a semiconductor chip having a semiconductor element having connection terminals formed on one main surface on a substrate having lands, such that the lands and the connection terminals are electrically connected;
A filling step of filling a resin member between the semiconductor chip and the substrate so as to cover the connection portion between the connection terminal and the land and the semiconductor element,
A mounting step of mounting the semiconductor chip on the substrate by joining the semiconductor chip and the substrate with the resin member filled between the semiconductor chip and the substrate,
A correction member for correcting a warp generated in the semiconductor chip due to expansion or contraction of the resin member having a linear expansion coefficient different from that of the semiconductor chip is attached to the other main surface opposite to the one main surface of the semiconductor chip. A method for manufacturing a semiconductor device having an attaching step. 開口部とランドとを有する基板の開口部内に、接続端子を有する半導体素子が一主面に形成された半導体チップを収納し、上記ランドと上記接続端子とをワイヤーを介して接続する接続工程と、
少なくとも上記半導体チップが収納された上記基板の開口部内に、上記接続端子と上記ランドとの上記ワイヤーを介した接続部と、上記ワイヤーと、上記半導体素子とを被覆するように樹脂部材を充填する充填工程と、
上記基板の開口部内に充填された上記樹脂部材が上記半導体チップを上記基板の開口部内に固定させる固定工程と、
上記半導体チップの一主面とは反対側の他主面に、上記半導体チップとは異なる線膨張率を有する上記樹脂部材の膨張或いは収縮により上記半導体チップに生じる反りを矯正する矯正部材を貼り付ける貼付工程と
を有する半導体装置の製造方法。A connection step of connecting a semiconductor element having a connection terminal to a semiconductor chip formed on one main surface, and connecting the land and the connection terminal via a wire, in the opening of the substrate having the opening and the land; ,
At least an opening of the substrate in which the semiconductor chip is housed is filled with a resin member so as to cover the connection portion between the connection terminal and the land via the wire, the wire, and the semiconductor element. Filling process,
A fixing step in which the resin member filled in the opening of the substrate fixes the semiconductor chip in the opening of the substrate,
A correction member for correcting a warp generated in the semiconductor chip due to expansion or contraction of the resin member having a linear expansion coefficient different from that of the semiconductor chip is attached to the other main surface opposite to the one main surface of the semiconductor chip. A method for manufacturing a semiconductor device having an attaching step.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008120705A1 (en) 2007-03-29 2008-10-09 Nec Corporation Semiconductor device
WO2010144848A3 (en) * 2009-06-12 2011-02-17 Qualcomm Incorporated Stress balance layer on semiconductor wafer backside
JP2011071267A (en) * 2009-09-25 2011-04-07 Nec Corp Electronic device package, method of manufacturing the same, and electronic equipment
JP2013519235A (en) * 2010-02-05 2013-05-23 クアルコム，インコーポレイテッド Die surface treatment to improve bond strength
US11349088B2 (en) * 2018-10-12 2022-05-31 Boe Technology Group Co., Ltd. Flexible display panel having distributed holes

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008120705A1 (en) 2007-03-29 2008-10-09 Nec Corporation Semiconductor device
CN101647109B (en) * 2007-03-29 2011-11-09 日本电气株式会社 Semiconductor device
JP5521547B2 (en) * 2007-03-29 2014-06-18 日本電気株式会社 Semiconductor device and manufacturing method thereof
WO2010144848A3 (en) * 2009-06-12 2011-02-17 Qualcomm Incorporated Stress balance layer on semiconductor wafer backside
JP2011071267A (en) * 2009-09-25 2011-04-07 Nec Corp Electronic device package, method of manufacturing the same, and electronic equipment
JP2013519235A (en) * 2010-02-05 2013-05-23 クアルコム，インコーポレイテッド Die surface treatment to improve bond strength
US11349088B2 (en) * 2018-10-12 2022-05-31 Boe Technology Group Co., Ltd. Flexible display panel having distributed holes

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