JP2004095668A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit capable of performing stable scanning tests by preventing the data from being slipping out due to the the flip-flop holding time fault caused by a clock skew. <P>SOLUTION: A scanning test of a combination circuit 200 is performed on the basis of a test pattern generated by a scan pattern generation circuit 300, a comparison control circuit 400 compares a test result with an expected value to check the shifting of the flip-flops 100-105. When the slip of the data is generated due to the hold time fault caused by a clock skew and non-coincidence between the test result and the expected value is generated, the circuit 400 specifies the generated position of the data slip and controls the clock delay by a control signal for a delay control selector. Then the test pattern is inputted from a scanning-in signal SI to perform the scanning test of the combination circuit 200. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a test of a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a scan path inside a semiconductor integrated circuit for easily testing the semiconductor integrated circuit.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the improvement of multilayer wiring technology and miniaturization technology in semiconductor manufacturing, the scale of a gate mounted on one chip of a semiconductor integrated circuit has been increased, and a semiconductor integrated circuit with high performance and high functionality can be realized. The increase in the size of the gate mounted on one chip has caused various problems in each of the design, manufacturing, and test processes. In particular, the problems related to testing are significant.
[0003]
2. Description of the Related Art In a semiconductor integrated circuit, a defect in a manufacturing process must be detected in addition to a test of whether a chip satisfies a desired function. That is, it is necessary to confirm the on / off operation for all the transistors in the semiconductor integrated circuit. One of the factors that makes such a test of a semiconductor integrated circuit difficult is that the controllability of the input and the observability of the output of the flip-flop inside the semiconductor integrated circuit are poor.
[0004]
As a conventional technique for solving such a problem, there is a scan path design method for providing a path (scan chain) for directly controlling and observing a flip-flop in a semiconductor integrated circuit from an external terminal.
[0005]
With reference to FIG. 3, a test based on a conventional scan path design will be described. 3, reference numerals 1000 to 105 denote flip-flops, 2000 denotes a combinational circuit of a semiconductor integrated circuit to be tested, 3000 to 3008 denote clock buffers, 4000, 4010, 4020, 4030 and 4040 denote delay circuits, and 4001 to 4003 denote buffers. is there. The flip-flops 1000 to 1005 are designed to latch data of the combination circuit 2000 and to be serially connected in the order of the flip-flops 1000, 1001,. I have.
[0006]
Next, the operation of the scan test will be described. First, test data is input from the scan-in signal SI, and the test data is shifted in the order of the flip-flops 1000, 1001, and 1002 using the shift function. Then, the combination circuit 2000 is operated using the outputs of the flip-flops 1000 to 1002 as pseudo inputs. The outputs of combination circuit 2000 at this time are latched by flip-flops 1003 to 1005. Further, the flip-flops 1000 to 1005 output test results latched by the scan-out signal SO from the last-stage flip-flop 1005 using the shift function. This scan-out signal SO is observed and compared with an expected value.
[0007]
As described above, in the test of the semiconductor integrated circuit by the scan path design, the combination circuit is operated by the test pattern pseudo-input from the scan-in signal SI by the shift operation of the flip-flops 1000 to 1005, the result is latched and the scan-out signal is output. Output to SO. Thus, the on / off operation of the transistor in the semiconductor integrated circuit can be confirmed.
[0008]
[Problems to be solved by the invention]
However, when the flip-flops 1000 to 105 constituting the shift register perform the shift operation, if the hold time, which is one of the timing conditions of the flip-flops 1000 to 1005, cannot be satisfied, and the data passes through, The signal observed in the scan-out signal SO does not match the expected value. That is, there is a problem that the semiconductor integrated circuit is determined to be defective due to the shift operation at the time of the scan test, although the combinational circuit 2000 operates correctly and the original function of the semiconductor integrated circuit is satisfied. Was.
[0009]
Such data slippage occurs due to the skew of the clock supplied to the clock terminals T of the flip-flops 1000 to 1005. The clock supplied to the clock terminal T of the flip-flops 1000 to 1005 is input to the clock buffer 3000 from the clock signal CK. Clock buffer 3000 outputs a signal input to clock buffers 3001 and 3002. The clock buffer 3001 outputs signals input to the clock buffers 3003 to 3005, and the clock buffer 3002 outputs signals input to the clock buffers 3006 to 3008. The clock buffer 3003 is connected to the clock terminal T of the flip-flop 1000, the clock buffer 3004 is connected to the clock terminal T of the flip-flop 1001, and the clock buffers 3003 to 3008 are input to the flip-flops 1000 to 1005. Are output. Clock tree synthesis (CTS: Clock Tree Synthesis) in which clocks are distributed in a tree structure using a plurality of clock buffers in this manner is a method suitable for applications that minimize clock skew with a large fan-out.
[0010]
However, as the number of flip-flops connected to the clock buffer increases, the skew until the clock reaches the clock terminal T of each flip-flop increases. In particular, with the miniaturization of semiconductor manufacturing, the ratio of the wiring delay to the entire path delay occupies the same specific gravity as the gate delay, and the problem of clock skew is increasing.
[0011]
In order to compensate for the violation of the hold time due to the clock skew (in this case, the shortage of the hold time), in the prior art shown in FIG. 3, a delay circuit is provided between flip-flops 1000 to 1005 constituting a shift register. 4000 to 4040 are inserted. The delay circuits 4000 to 4040 are constituted by buffers 4001 to 4003, for example, so that the signal at the output terminal O of the flip-flop 1000 is delayed by the gate delay of the buffers 4001 to 4003 and is input to the input terminal S of the flip-flop 1001. I have. However, there is a problem that the gate delay of the cell varies depending on the manufacturing, and the hold time cannot be reliably guaranteed.
[0012]
The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor integrated circuit that prevents data slippage due to a hold time violation of a flip-flop caused by clock skew and performs a stable scan test. I have.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor integrated circuit according to the present invention supplies a clock of a flip-flop designed for scan path in a tree structure by clock tree synthesis. A clock selection circuit for selecting a clock to be performed from a plurality of clocks loaded with different delays by a predetermined signal, a test pattern for a scan test, and an expected value when a test of a combinational circuit is performed using the test pattern. A scan pattern generation circuit to be generated, a first selector that selects a test pattern input from an external input terminal based on an external selection signal and a test pattern generated by the scan pattern generation circuit, Generated by the scan pattern generation circuit When a test pattern is selected, the test result of the combinational circuit in the test pattern is compared with the expected value.If the comparison results do not match, a portion of the flip-flop that malfunctions when shifting is specified. A comparison control for outputting, to the clock selection circuit, the control signal for a delay adjustment selector for increasing the delay load from the present time to the clock selection circuit supplying the clock to the specified flip-flop, as the predetermined signal. And a circuit.
[0014]
According to the present invention, the scan test of the combination circuit is executed based on the test pattern generated by the scan pattern generation circuit, the comparison control circuit compares the test result with the expected value, and confirms the shift operation of the flip-flop. Do. Then, when a mismatch between the test result and the expected value occurs, the comparison control circuit specifies a portion of the malfunction during the shift due to the hold time violation of the flip-flop, and adjusts the clock delay by the delay adjustment selector control signal. . Thereafter, a test pattern is input from an external input terminal, and a scan test of the combination circuit is executed.
[0015]
In the semiconductor integrated circuit according to the next invention, in the above invention, the clock selection circuit includes a delay adjustment circuit that generates a plurality of clocks loaded with different delays with respect to the input clock; and a delay adjustment selector control signal. A second selector for selecting any one of the input clock and the plurality of clocks loaded with the different delays based on the input clock.
[0016]
According to the present invention, the clock selection circuit generates a plurality of clocks loaded with different delays with respect to the input clock, and selects one of the generated plurality of clocks and the input clock based on the delay adjustment selector control signal. Output.
[0017]
A semiconductor integrated circuit according to the next invention is characterized in that, in the above invention, when a CPU is built in the semiconductor integrated circuit, the functions of the scan pattern generation circuit and the comparison control circuit are realized by the CPU. And
[0018]
According to the present invention, when the CPU is built in the semiconductor integrated circuit, the CPU compares the test result of the combination circuit performed with the test pattern for the scan test with the expected value, and when the result does not match. In addition, the location of a malfunction at the time of shift due to a hold time violation of the flip-flop is specified, and the delay of the clock is adjusted by the control signal for the delay adjustment selector.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of a semiconductor integrated circuit according to the present invention will be described below in detail with reference to the accompanying drawings.
[0020]
An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a scan-designed semiconductor integrated circuit according to the present embodiment. In FIG. 1, 100 to 105 are flip-flops, 200 is a combination circuit in a semiconductor integrated circuit to be tested, 300 is a scan pattern generation circuit, 400 is a comparison control circuit, 500 to 502 are selectors, and 610 to 631 are clock selections. Circuits, 701 to 703 are buffers, and 710 to 714 are delay circuits.
[0021]
The flip-flops 100 to 105 are designed to latch data of the combinational circuit 200 and serially connect the flip-flops 100, 101,. At the time of serial connection, delay circuits 710 to 714 are provided between the flip-flops 100 to 105 to serially connect the buffers 701 to 703 and provide a delay.
[0022]
The scan pattern generation circuit 300 generates a test pattern for a scan test. Then, the generated test pattern is output to the selector 500. Further, an expected value when the combination circuit 200 is operated with the test pattern is output to the comparison control circuit 400.
[0023]
The selector 500 selects one of the test pattern generated by the scan pattern generation circuit 300 and the test pattern input from the scan-in signal SI based on the external selection signal TEST for selecting the test pattern, Output.
[0024]
The comparison control circuit 400 receives the test result input from the flip-flop 105 and the input from the scan pattern generation circuit 300 when the scan test is performed with the test pattern generated by the scan pattern generation circuit 300 by the external selection signal TEST. To the expected value. If the result of the comparison is a mismatch, the flip-flop having the hold time violation is specified, and a control signal for a delay adjustment selector for adjusting the clock delay is output to the clock selection circuits 610 to 631.
[0025]
The selector 501 outputs any one of the external clocks CK0 to CK5 to the clock selection circuit 610 based on the selection signal SEL0. The selector 502 outputs any one of the external clocks CK6 to CK11 to the clock selection circuit 621 based on the selection signal SEL1.
[0026]
The clock selection circuits 610 to 631 load the input clock with a delay specified by the delay adjustment selector control signal and output the input clock. The clock selection circuit 610 loads the input clock input from the selector 501 with a delay specified by the delay adjustment selector control signal. Then, an output clock with a delay loaded is output to the clock selection circuits 611 and 612. The clock selection circuit 611 loads the input clock input from the clock selection circuit 610 with a delay specified by the delay adjustment selector control signal. Then, an output clock with a delay loaded is output to the clock selection circuits 613 to 616. The clock selection circuit 613 loads the input clock input from the clock selection circuit 611 with a delay specified by the delay adjustment selector control signal. Then, it outputs an output clock loaded with the delay of the clock terminal T of the flip-flop 100. The clock selection circuit 616 loads the input clock input from the clock selection circuit 611 with a delay specified by the delay adjustment selector control signal. Then, it outputs an output clock loaded with the delay of the clock terminal T of the flip-flop 101. Although not shown, the clock selection circuits 614 and 615 each output a delay-loaded output clock to a flip-flop FF in the semiconductor integrated circuit.
[0027]
The clock selection circuit 612 loads the clock input from the clock selection circuit 610 with a delay specified by the delay adjustment selector control signal. Then, an output clock with a delay loaded is output to the clock selection circuits 617 to 620. The clock selection circuit 619 loads the input clock input from the clock selection circuit 612 with a delay specified by the delay adjustment selector control signal. Then, an output clock with a delay loaded to the clock terminal T of the flip-flop 102 is output. The clock selection signals 617, 618, and 620 each output an output clock with a delay loaded to a flip-flop FF in the semiconductor integrated circuit (not shown).
[0028]
The clock selection circuits 621 to 631 are provided with the clock selection circuit 621 as a starting point, from the clock selection circuit 622 to the clock selection circuits 624 to 627, and from the clock selection circuit 623 to the clock selection circuits 628 to 631 similarly to the above-described clock selection circuits 610 to 620. Then, a tree structure is formed by CTS, and a clock is output with a delay specified by each delay adjustment selector control signal. Then, the clock selection circuits 625, 628, and 631 output clocks with delay loads to the clock terminals T of the flip-flops 103 to 105, respectively.
[0029]
The clock selection circuits 610 to 631 shown in FIG. 1 all have the same function. The function of the clock selection circuit will be described with reference to a block diagram showing the configuration of the clock selection circuit 610 shown in FIG. In FIG. 2, reference numeral 600 denotes a delay adjustment circuit, 602 denotes a clock buffer, and 603 denotes a selector. The input clock is output to the buffers 601 a, 601 b, 601 d, and 601 g and the selector 603 in the delay adjustment circuit 600 via the clock buffer 602. The delay adjustment circuit 600 loads a clock loaded with a gate delay of the buffer 601a, a clock loaded with a gate delay of the buffers 601b and 601c, a clock loaded with a gate delay of the buffers 601d to 601f, and a gate delay of the buffers 601g to 601j. A clock having four different delays of the clock is generated and output to the selector 603. The selector 603 selects a clock specified by the delay adjustment selector control signal, that is, one of five types of clocks having different delays, and sets the selected clock as an output clock. Note that the configuration of the delay adjustment circuit 600 is not limited to this as long as it generates clocks having different delays. Further, the number of generated clocks is not limited to this.
[0030]
Next, the operation of the semiconductor integrated circuit according to the present embodiment will be described. First, a signal for executing a scan test using the test pattern of the scan pattern generation circuit 300 is input to the external selection signal TEST. Thereby, the selector 500 outputs the test pattern of the scan pattern generation circuit 300 to the flip-flop 100.
[0031]
The selector 501 selects any one of the external clocks CK <b> 0 to CK <b> 5 having different periods and phases based on the selection signal SEL <b> 0 and outputs the same to the clock selection circuit 610. Further, the selector 502 selects any one of the external clocks CK6 to CK11 having different periods and phases based on the selection signal SEL1, and outputs the same to the clock selection circuit 621.
[0032]
The clock selection circuits 610 to 631 output clocks with delays applied to the clocks selected by the selectors 501 and 502 based on the respective delay adjustment selector control signals. Here, as an initial setting, the output of the clock buffer 602 having the smallest delay is selected. The flip-flops 100 to 105 perform a shift operation based on the clock supplied to each clock terminal T to shift the test data. Then, flip-flops 103 to 105 latch the outputs of the combinational circuit 200 that operates using the outputs of the flip-flops 100 to 102 as pseudo inputs. The flip-flops 100 to 105 output test results to the comparison control circuit 400 by a shift operation.
[0033]
The comparison control circuit 400 compares the expected value input from the scan pattern generation circuit 300 with the test result input from the flip-flop 105. If the comparison results match, it is determined that no data slippage has occurred due to clock skew, and the test is continued. If the comparison results do not match, it is determined that data slippage has occurred due to clock skew, and the location where the slippage occurred is identified. For example, the comparison control circuit 400 includes a counter for specifying the data passing position, and counts each time a shift operation is performed. As a result, it is possible to determine the order of the data where the mismatch between the expected value and the test result is, and it is possible to identify the place where the data slips through.
[0034]
When the location where data slippage occurs is specified, the comparison control circuit 400 changes the control signal for the delay adjustment selector of the clock selection circuit that supplies the clock to the flip-flop at the specified location. For example, when data passes between the flip-flop 102 and the flip-flop 103, that is, when a hold time violation occurs at the clock terminal T of the flip-flop 103, the comparison control circuit 400 supplies a clock to the flip-flop 102. The control signal for the delay adjustment selector output to the clock selection circuit 619 is changed so as to select a clock having a larger delay than the current one. Here, if the control signal for the delay adjustment selector has already been specified so that the clock selection circuit 619 selects the maximum delay, the control goes back to the starting point of the clock (in this case, the clock selection circuit 612) and the flip-flop 102 A delay is applied to the clock input to the clock terminal T.
[0035]
Next, a signal for executing a scan test using the test pattern input from the scan-in signal SI is input to the external selection signal TEST. Accordingly, the selector 500 outputs the test pattern input from the scan-in signal SI to the flip-flop 100. At this time, as the control signals for the delay adjustment selector input to the clock selection circuits 610 to 631, signals adjusted using the test pattern of the scan pattern generation circuit 300 are input. That is, a clock adjusted so that data does not pass through is input to the flip-flops 100 to 105. The flip-flops 100 to 105 perform a shift operation by this clock, execute a scan test of the combination circuit 200 according to the test pattern input from the scan-in signal SI, and output a test result as a scan-out signal SO. Then, the test result is compared with an expected value.
[0036]
As described above, in the present embodiment, the scan test of the combination circuit 200 is executed based on the test pattern generated by the scan pattern generation circuit 300, the comparison control circuit 400 compares the test result with the expected value, and The shift operation of 100 to 105 is confirmed. Then, when data slippage occurs due to a hold time violation due to clock skew, and a mismatch occurs between the test result and the expected value, the comparison control circuit 400 specifies the location where the data slippage occurred, and a delay adjustment selector The clock delay is adjusted by the control signal. Thereafter, a test pattern is input from the scan-in signal SI, and the scan test of the combinational circuit 200 is executed. Therefore, scan test failures due to clock variations at the time of manufacturing a semiconductor integrated circuit are reduced, and a stable scan test is performed. It can be performed.
[0037]
When a CPU (Central Processing Unit) is built in the semiconductor integrated circuit, the functions of the scan pattern generation circuit 300 and the comparison control circuit 400 may be executed by the CPU.
[0038]
【The invention's effect】
As described above, according to the present invention, a scan test of a combination circuit is executed based on a test pattern generated by a scan pattern generation circuit, a comparison control circuit compares a test result with an expected value, and Confirm the shift operation of. Then, when a mismatch between the test result and the expected value occurs, the comparison control circuit specifies a portion of the malfunction during the shift due to the hold time violation of the flip-flop, and adjusts the clock delay by the delay adjustment selector control signal. . Thereafter, a test pattern is input from an external input terminal, and a scan test of the combinational circuit is executed. Therefore, scan test failures due to clock variations during semiconductor integrated circuit manufacture are reduced, and a stable scan test is performed. be able to.
[0039]
According to the next invention, the clock selection circuit generates a clock loaded with a plurality of different delays with respect to the input clock, and selects one of the generated clock and the input clock based on the delay adjustment selector control signal. Since the output is performed, the delay of the clock supplied to the flip-flop can be set finely.
[0040]
According to the next invention, when the CPU is built in the semiconductor integrated circuit, the CPU compares the test result of the semiconductor integrated circuit performed with the test pattern for the scan test with the expected value, and the result does not match. In this case, the malfunction of the flip-flop during the shift due to the hold time violation is specified, and the delay of the clock is adjusted by the control signal for the delay adjustment selector. Scan test defects can be reduced, and a stable scan test can be performed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to an embodiment.
FIG. 2 is a block diagram showing a configuration of a clock selection circuit shown in FIG.
FIG. 3 is a diagram for explaining a conventional technique.
[Explanation of symbols]
100, 101, 102, 103, 104, 105, 1000, 1001, 1002, 1003, 1004, 1005 Flip-flop, 200, 2000 combination circuit, 300 scan pattern generation circuit, 400 comparison control circuit, 500, 501, 502, 603 Selector, 600 delay adjustment circuit, 601a, 601b, 601c, 601d, 601e, 601f, 601g, 601h, 601i, 601j, 701, 702, 703, 4001, 4002, 4003 buffers, 602, 3000, 3001, 3002, 3003 3004, 3005, 3006, 3007, 3008 clock buffers, 610, 611, 612, 613, 614, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624 25,626,627,628,629,630,631 clock selection circuit, 710,711,712,713,714,4000,4010,4020,4030,4040 delay circuit.

Claims (3)

In a semiconductor integrated circuit which supplies a flip-flop clock with a scan path design in a tree structure by clock tree synthesis,
A clock selection circuit for selecting a clock input to the clock terminal of the flip-flop from a plurality of clocks loaded with different delays by a predetermined signal;
A scan pattern generating circuit that generates a test pattern for a scan test and an expected value when a combination circuit is tested using the test pattern;
A first selector for selecting a test pattern input from an external input terminal based on an external selection signal and a test pattern generated by the scan pattern generation circuit;
When a test pattern generated by the scan pattern generation circuit is selected by the external selection signal, the test result of the combination circuit in the test pattern is compared with the expected value, and when the comparison result does not match, A malfunctioning portion during the shift of the flip-flop is specified, and a control signal for a delay adjustment selector for increasing a delay load from the present time is supplied to a clock selection circuit that supplies a clock to the specified flip-flop. A comparison control circuit that outputs the predetermined signal to the clock selection circuit;
A semiconductor integrated circuit comprising: The clock selection circuit,
A delay adjustment circuit that generates a plurality of clocks loaded with different delays with respect to the input clock;
A second selector for selecting any one of the input clock and a plurality of clocks loaded with the different delays based on the delay adjustment selector control signal;
The semiconductor integrated circuit according to claim 1, further comprising: The semiconductor integrated circuit according to claim 1, wherein when the semiconductor integrated circuit includes a CPU, the functions of the scan pattern generation circuit and the comparison control circuit are realized by the CPU.

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