JP2004095336A - Plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of addressing in the plasma display panel. <P>SOLUTION: A plasma display panel 1 of AC type comprises partition walls 29 of linear belt-shape that are arranged in a certain pitch for demarcating in a row a plurality of scan electrodes for row selection, a plurality of data electrodes for column selection, and the discharge space for matrix display. The partition walls 29 are formed so as to become narrower as they go from one end in the arrangement direction of the scan electrodes to the other end in the display screen 60, and thereby, the effective discharge start voltage between the scan electrode and the data electrode is made low for the cell the nearer to the other end. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a matrix display type plasma display panel (PDP) capable of displaying an arbitrary image.
[0002]
PDPs have come to be used in a variety of applications, such as televisions, computer monitors, station and airport guidance. As the market expands, so does the demand for operational reliability.
[0003]
[Prior art]
A surface discharge type AC PDP is known as a color display device for performing a matrix display. In the surface discharge type here, in a display discharge that determines the amount of light emitted from a cell, display electrodes serving as an anode and a cathode are arranged in parallel on one substrate of a pair of substrates, and an address electrode is arranged so as to intersect with the display electrode. This is a type having a three-electrode structure arranged on a substrate. The display electrodes are arranged so as to form an electrode pair for display discharge for each row of the matrix display, and are covered with a dielectric layer. One display electrode in the electrode pair is used as a scan electrode for row selection in addressing. One address electrode is arranged for each column, and faces the display electrode via a discharge space. In the surface discharge type, the phosphor layer for color display is formed on the substrate on which the address electrodes are arranged, so that the phosphor layer can be kept away from the display electrode pair in the panel thickness direction. Degradation can be reduced. However, since the display electrodes are parallel in the surface discharge type, it is necessary to partition the discharge space at least for each column in order to localize the display discharge for each cell.
[0004]
The contents to be displayed are set by addressing in units of lines. In the address period, each scan electrode is activated by being biased to a predetermined selection potential in the arrangement order. In synchronization with this row selection, one row of display data is output in parallel from all data electrodes. That is, the potentials of all data electrodes are controlled simultaneously according to the display data. In a cell in which both the scan electrode and the data electrode are biased to the selected potential, a so-called opposing discharge occurs between the scan electrode and the data electrode, which triggers a surface discharge between the display electrodes. This series of discharges is an address discharge.
[0005]
[Problems to be solved by the invention]
In the structure in which the discharge space is divided for each column by the partition walls as described above, the movement of the space charge that produces the priming effect occurs only in each column. Therefore, the charge that contributes to the priming effect of each cell in the address period in which a discharge is generated in a row unit is the space charge generated by the reset discharge prior to the addressing and the cell on the upstream side of the row selection (scanning). Is a space charge generated by the address discharge in the step S. When the upstream cell is a cell that does not need to generate an address discharge (for example, a non-lighting cell in a write address format), only the space charge generated by the reset discharge contributes to the priming effect. For this reason, particularly in the row selected at the end of the address period, the elapsed time from the reset discharge is long and the amount of the residual space charge is small, so that the discharge delay is remarkable, and the scanning time (address cycle) for one row is reduced. However, there is a serious problem that address discharge does not occur and a display defect occurs.
[0006]
An object of the present invention is to increase the reliability of addressing.
[0007]
[Means for Solving the Problems]
In the present invention, the effective discharge start voltage between the scan electrode and the data electrode is reduced from one end to the other end in the arrangement direction of the scan electrodes on the display surface, that is, the discharge is easily generated. To give a difference in structure between cells. In the AC PDP, the ease of occurrence of discharge can be varied by selecting the size of the discharge space of each cell, the distance between the electrodes, or the charging characteristics between the electrodes. As a configuration that can be easily realized, there is a configuration in which the width of the partition is changed with respect to the width of the discharge space, a configuration in which the height of the partition is changed with respect to the distance between the electrodes, and a configuration in which a dielectric or phosphor is used as the charging characteristic. There is a configuration that changes the thickness.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
[First Embodiment]
FIG. 1 is a schematic configuration diagram of a PDP according to the present invention. The PDP 1 includes a pair of substrate structures 10 and 20. The substrate structure means a structure including a glass substrate having a size equal to or larger than the screen size and at least one other panel component. The substrate structures 10 and 20 are arranged to face each other so as to overlap with each other, and are joined by a sealing material 35 at the periphery of the overlapping portion. A discharge gas is filled in the internal space sealed by the substrate structures 10 and 20 and the sealing material 35. The substrate structure 10 extends right and left in the figure with respect to the substrate structure 20, and the substrate structure 20 extends up and down in the figure with respect to the substrate structure 10. A flexible wiring board for conductive connection with the drive unit is joined to the overhanging end. The portion of the PDP 1 where the cells are arranged in plan view is the display surface 60, and the plane size is the screen size.
[0009]
FIG. 2 is a schematic diagram of an electrode matrix. On the display surface 60, display electrodes X and Y constituting an electrode pair for generating a display discharge are arranged in parallel, and address electrodes A are arranged so as to intersect the display electrodes X and Y. The display electrodes X and Y extend in the row direction (horizontal direction in the figure) of the matrix display, and the address electrodes A extend in the column direction (vertical direction in the figure). The total number of display electrodes X and Y is (n + 1) obtained by adding 1 to the number n of rows, and the total number of address electrodes A is the same as the number m of columns. In the figure, the suffixes of the reference numerals of the display electrodes X and Y and the address electrodes A indicate the arrangement order. In this embodiment, the number n of rows is an even number.
[0010]
FIG. 3 is a diagram showing a cell structure of the PDP. In FIG. 3, a portion corresponding to three columns of two rows in the PDP 1 is illustrated by separating the pair of substrate structures 10 and 20 so that the internal structure can be clearly understood.
[0011]
The substrate structure 10 on the front side includes a glass substrate 11, display electrodes X and Y, a dielectric layer 17, and a protective film 18. The display electrodes X and Y include a thick band-shaped transparent conductive film (transparent electrode) 41 for forming a surface discharge gap and a thin band-shaped metal film (metal electrode) 42 as a bus conductor for lowering electric resistance. The dielectric layer 17 covering the display electrodes X and Y is formed by firing a low-melting glass paste, and the protective film 18 is made of magnesia. The rear substrate structure 20 includes a glass substrate 21, address electrodes A, a dielectric layer 24, partition walls 29, and phosphor layers 28R, 28G, 28B. The partition wall 29 is a band-shaped structure having a straight planar shape, and is provided one for each electrode gap of the address electrode array. The partition wall 29 divides the discharge gas space for each column of the matrix display, and forms a column space 31 corresponding to each column. The column space 31 is continuous over all rows. The phosphor layers 28R, 28G, 28B are arranged so as to cover the region between the partitions in the insulating layer 24 and the side surfaces of the partitions, and emit light when excited by ultraviolet rays emitted by the discharge gas. Italic alphabets R, G, and B in the figure indicate the emission colors of the phosphor.
[0012]
FIG. 4 is a plan view showing an arrangement of cells. The display electrodes X and the display electrodes Y are arranged so as to be alternately arranged one by one in the order of XYXY... XYX, and the adjacent display electrodes X and Y constitute an electrode pair. The total number of electrode pairs is the same as the number n of rows. Of the (n + 1) display electrodes X and Y, the display electrode X at one end of the array is used for displaying the first row together with the adjacent display electrode Y, and the display electrode X at the other end of the array is the adjacent display electrode Y Used to display the last line. The remaining (n-1) display electrodes X and Y are used for two adjacent rows (odd row Lodd and even row Leven). The row (odd-numbered row or even-numbered row Leven) is a set of cells 50 of the number of columns (m) having the same arrangement order in the column direction, and the column R _j (j = 1, 2, 3,... A set of minute (n) cells 50.
[0013]
FIG. 5 is a schematic diagram of a partition pattern of the PDP according to the first embodiment. In FIG. 5, cells 50 ₁ , 50 ₂ , 50 ₃ ,.  , 50 _n Is shown. The suffix of the reference numeral of the cell 50 indicates the arrangement order of the row.
[0014]
In the PDP 1, the width of the partition wall 29 described above is not constant, and the partition wall 29 is gradually narrowed from one end of the display surface 60 in the arrangement direction (that is, the column direction) of the scan electrodes toward the other end. The width w2 on the last line side is smaller than the width w1 on the first line side (w1> w2). Since the partition walls 29 are arranged at a constant pitch p so that their center lines are parallel to each other, if the width is different, the partition wall gap is necessarily different. As the partition wall 29 becomes thinner, the partition wall gap becomes larger. The partition gap g2 on the last row side is larger than the partition gap g1 on the first row side (g1 <g2). The difference (w1-w2) between the widths of the partition walls may be appropriately selected according to the specifications of the screen size and the cell size. For example, a width difference of about 10 to 20 μm is practical for a 42-inch size.
[0015]
The cells 50 ₁ , 50 ₂ , 50 ₃ ,...  , 50 _n Discharge space is large. In the size range of the practical screen specification, the effective discharge starting voltage that determines the easiness of the discharge depends on the width of the discharge space. When the discharge space is narrow, the movement of ions is suppressed, so that discharge is unlikely to occur. Conversely, when the discharge space is large, discharge is likely to occur. In the PDP 1 of the first embodiment, the distance between the display electrode Y and the address electrode A is equal in all cells, but the discharge space in each column increases from the first row to the last row. That is, the discharge between the display electrode (scan electrode) Y and the address electrode (data electrode) A is caused by the cell 50 _{n in the} last row.  , And is more likely to occur in cells closer to the last row. Therefore, by performing row selection in order from the first row to the last row in the addressing, it is possible to surely generate an address discharge in all cells. Note that unevenness in luminance on the display surface, which may be caused by an uneven width of the partition, can be suppressed by changing the thickness of the phosphor layer.
[0016]
Next, a driving method of the PDP 1 will be briefly described. The frame to be displayed is composed of odd and even fields. In the display by the PDP 1, each of the odd field and the even field is divided into a predetermined number of subfields in order to perform color reproduction by selecting a lighting / non-lighting combination. That is, each field is replaced with a plurality of subfields weighted with luminance. Then, for each subfield, reset for equalizing wall charges, addressing for controlling wall charges according to display data, and sustain for generating a number of display discharges according to the weight of luminance are performed.
[0017]
FIG. 6 is a driving waveform diagram showing a row selection order in addressing. In the case of the odd-numbered field, in the first half TA1 of the address period TA, the odd-numbered display electrodes Xodd of the (n / 2 + 1) display electrodes X are collectively biased and activated, and n / 2 lines are activated. Of the odd-numbered display electrodes Yodd among the display electrodes Y, a scan pulse Py is applied by selecting one by one in the arrangement order. The polarity of the scan pulse Py is opposite to the bias potential of the display electrode Xodd. By the application of the scan pulse Py, scanning of each row having the order of 1, 5, 9,... (1 + 4k) is performed. k is an integer including 0. In the cell to which the bias and the pulse have been applied, the cell voltage becomes higher than that of the other cells, and the address discharge between the display electrode Y and the address electrode A is triggered to generate the address discharge between the display electrodes. In the latter half TA2, in a state where the even-numbered display electrodes Xeven are collectively biased, the scan pulses Py are applied to the even-numbered display electrodes Yeven of the display electrodes Y by selecting one by one in the arrangement order. As a result, scanning is performed on each row having the order of 3, 7, 11,... (3 + 4k). By scanning the first half TA1 and the second half TA2, predetermined wall charges are formed in the selected cells in the odd rows. Thus, in the addressing in which the scan pulse Py is applied while distinguishing the display electrode Yodd and the display electrode Yeven, the bias of the display electrode X does not need to be switched every time the scan pulse Py is applied, and is switched at the boundary between the first half TA1 and the second half TA2. As a result, it is possible to reduce wasteful power consumed for charging the capacitance between the display electrodes.
[Second embodiment]
FIG. 7 is a schematic diagram of the structure of the PDP according to the second embodiment. The basic configuration of PDP2 is the same as PDP1 of the first embodiment. In the PDP 2, the height of the partition wall 29B is not constant, and the partition wall 29B is gradually lowered from one end of the display surface 60 in the arrangement direction of the scan electrodes (that is, the column direction) toward the other end. The height h2 on the last row side is smaller than the height h1 on the first row side (h1> h2). The smaller the distance between the electrodes, the lower the effective firing voltage that determines the likelihood of discharge. That is, the discharge between the display electrode (scan electrode) Y and the address electrode (data electrode) A is most likely to occur in the cells in the last row, and is more likely to occur in the cells closer to the last row. Therefore, by performing row selection in order from the first row to the last row in the addressing, it is possible to surely generate an address discharge in all cells. The height of the partition wall 29B can be adjusted by increasing or decreasing the pressing force of the squeegee in printing the paste, or increasing or decreasing the number of screen printing depending on the region, when forming the partition wall by patterning the low melting glass paste by screen printing. Can be changed. The height difference (h1-h2) of the partition walls 29B may be appropriately selected according to the specifications of the screen size and the cell size. For example, a height difference of about 10 to 20 μm is practical for a 42-inch size.
[Third embodiment]
FIG. 8 is a schematic diagram of the structure of the PDP according to the third embodiment. The basic configuration of the PDP 3 is the same as the PDP 1 of the first embodiment. In the PDP 3, the thickness of the dielectric layer 24C serving as the base of the partition wall 29C is not constant, and the dielectric layer 24C gradually increases from one end in the arrangement direction (that is, the column direction) of the scan electrodes on the display surface 60 to the other end. It is thin. The thickness t2 on the last row side is smaller than the thickness t1 on the first row side (t1> t2). The thinner the dielectric layer interposed between the electrodes, the lower the effective firing voltage that determines the ease with which a discharge occurs. That is, the discharge between the display electrode (scan electrode) Y and the address electrode (data electrode) A is most likely to occur in the cells in the last row, and is more likely to occur in the cells closer to the last row. Therefore, by performing row selection in order from the first row to the last row in the addressing, it is possible to surely generate an address discharge in all cells. The thickness of the dielectric layer 24C may be increased or decreased by increasing or decreasing the pressing force of a squeegee in printing the paste, or increasing or decreasing the number of times of screen printing depending on the position when forming a layer in which the low-melting glass paste is screen-printed and fired. Can be changed. When a sheet-shaped dielectric material is used, the formation of the dielectric layer 24C can be realized by gradually changing the thickness of the sheet in advance. The difference (t1-t2) in the thickness of the dielectric layer 24C may be appropriately selected according to the specifications of the screen size and the cell size. For example, in the case of a 42-inch size, a thickness difference of about 1-2 μm is practical.
[Fourth embodiment]
FIG. 9 is a schematic diagram of a structure of a PDP according to the fourth embodiment. The basic configuration of PDP 4 is the same as PDP 1 of the first embodiment. In the PDP 4, the thickness of the phosphor layer 28 is not constant, and the thickness of the phosphor layer 28 is gradually reduced from one end of the display surface 60 in the arrangement direction (that is, the column direction) of the scan electrodes toward the other end. The thickness d2 on the last row side is smaller than the thickness d1 on the first row side (d1> d2). The thinner the insulator layer interposed between the electrodes, the lower the effective firing voltage that determines the ease with which a discharge occurs. That is, the discharge between the display electrode (scan electrode) Y and the address electrode (data electrode) A is most likely to occur in the cells in the last row, and is more likely to occur in the cells closer to the last row. Therefore, by performing row selection in order from the first row to the last row in the addressing, it is possible to surely generate an address discharge in all cells. The thickness of the phosphor layer 28 may be adjusted by increasing or decreasing the pressing force of a squeegee in printing the paste, or increasing or decreasing the number of times of screen printing in accordance with the part when forming a layer in which the phosphor paste is screen-printed and fired. Can be changed by The difference (d1-d2) in the thickness of the phosphor layer 28 may be appropriately selected according to the specifications of the screen size and the cell size. A thickness difference of about 30% of the maximum thickness d1 is practical. Note that unevenness in luminance on the display surface that may be caused by the uneven thickness of the phosphor layer 28 is combined with the configuration in which the width of the discharge space is changed along the column direction shown in the first embodiment. It is possible to suppress it. In the present embodiment, the brightness decreases as the thickness of the phosphor layer 28 decreases. In order to prevent the luminance from decreasing, the discharge space may be gradually widened from the first row toward the last row.
[0018]
In the above embodiment, the stripe type partition wall 29 in which the discharge spaces of the cells belonging to each column are continuous is exemplified, but the partition pattern may be a mesh type partitioning the discharge space for each cell. The present invention can also be applied to a configuration in which a pair of display electrodes are arranged for each row.
[0019]
【The invention's effect】
According to the first to fifth aspects of the present invention, the reliability of addressing can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a PDP according to the present invention.
FIG. 2 is a schematic diagram of an electrode matrix.
FIG. 3 is a diagram showing a cell structure of a PDP.
FIG. 4 is a plan view showing an arrangement of cells.
FIG. 5 is a schematic diagram of a partition pattern of the PDP according to the first embodiment.
FIG. 6 is a driving waveform diagram showing a row selection order in addressing.
FIG. 7 is a schematic view of a structure of a PDP according to a second embodiment.
FIG. 8 is a schematic diagram of a structure of a PDP according to a third embodiment.
FIG. 9 is a schematic view of a structure of a PDP according to a fourth embodiment.
[Explanation of symbols]
1,2,3,4 PDP (Plasma Display Panel)
Y display electrode (scan electrode)
A address electrode (data electrode)
60 display surface 29, 29B, 29C partition wall 24 dielectric layer 28, 28R, 28G, 28B phosphor layer

Claims (5)

An AC-type plasma display panel having a plurality of scan electrodes for row selection of a matrix display and a plurality of data electrodes for column selection,
A plasma display panel having a structure in which an effective discharge start voltage between a scan electrode and a data electrode decreases from one end to the other end in the arrangement direction of scan electrodes on a display surface. AC type plasma display having a plurality of scan electrodes for row selection of a matrix display, a plurality of data electrodes for column selection, and straight band-shaped partition walls arranged at a constant pitch to divide a discharge space into columns. A panel,
The partition wall is formed narrower from one end to the other end in the arrangement direction of the scan electrodes on the display surface, so that the cell closer to the other end has an effective discharge start voltage between the scan electrode and the data electrode. A plasma display panel characterized by being lowered. Scan electrodes for selecting rows for matrix display are arranged on one of a pair of substrates arranged opposite to each other, and data electrodes for selecting columns are arranged on the other. An AC-type plasma display panel having a partition for determining the size of the opposed gap,
The barrier ribs are formed to be lower from one end to the other end in the arrangement direction of the scan electrodes on the display surface, so that the closer the cell is to the other end, the lower the effective firing voltage between the scan electrode and the data electrode is. A plasma display panel characterized by being lowered. A scan electrode for row selection of matrix display is arranged on one of a pair of substrates arranged opposite to each other, and a data electrode for column selection is arranged on the other, and a dielectric covering the data electrode over the entire display surface. An AC-type plasma display panel having a layer,
The dielectric layer is formed to be thinner from one end to the other end in the arrangement direction of the scan electrodes on the display surface, so that a cell closer to the other end has an effective discharge between the scan electrode and the data electrode. A plasma display panel having a low starting voltage. A scan layer for selecting a row of a matrix display is arranged on one of a pair of substrates arranged oppositely, and a data electrode for selecting a column is arranged on the other, and a phosphor layer covering the data electrode over the entire length of the column An AC type plasma display panel having
The phosphor layer is formed to be thinner from one end to the other end in the arrangement direction of the scan electrodes on the display surface, so that a cell closer to the other end has an effective discharge between the scan electrode and the data electrode. A plasma display panel having a low starting voltage.

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