JP2004095168A - Nonvolatile semiconductor storage device, cache memory system, semiconductor storage device and semiconductor storage system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time needed for program verification and erasure verification and also to prevent the threshold voltage from changing too much even if rewriting and reerasing are performed. <P>SOLUTION: This nonvolatile semiconductor storage device is provided with a plurality of electrically rewritable nonvolatile semiconductor memory cells, a word line connected to the plurality of memory cells in common, a source line connected to the plurality of memory cells in common, a row decoder for supplying the word line with write verification voltage, a plurality of bit lines connected to the corresponding bit lines respectively, and a plurality of write verifying circuits provided in the corresponding bit lines respectively. Each of the write verifying circuit stores data of a first or second logical level. The write verifying circuits charge a corresponding bit line in advance and detect a write state of the corresponding memory cells after a prescribed time in the case of storing the data of the first logical level. The write verifying circuits connect a corresponding bit line to a prescribed power supply at least for the prescribed time in the case of storing the data of the second logical level. <P>COPYRIGHT: (C)2004,JPO

Description

<< The present invention relates to a nonvolatile semiconductor memory device, a cache memory system, a semiconductor memory device, and a semiconductor memory system.

Conventionally, magnetic disk devices have been widely used as storage devices in computer systems. However, the magnetic disk device has the following disadvantages: it has a highly precise mechanical drive mechanism, is vulnerable to impacts, is heavy in weight, has poor portability, consumes large power, and cannot easily be driven by batteries. And high speed access is not possible.

着 目 Focusing on such drawbacks, in recent years, semiconductor memory devices using EEPROM have been developed. Semiconductor memory devices generally have such advantages, that is, they have no mechanical driving parts, are resistant to shocks, are lightweight, are highly portable, have low power consumption, are easily driven by batteries, and have high-speed access. It has advantages such as being possible.

As one type of EEPROM, a NAND cell type EEPROM capable of high integration is known. It has the following structure. That is, the plurality of memory cells are arranged, for example, in the column direction. Sources and drains of adjacent cells among these cells are sequentially connected in series. With such a connection, a plurality of memory cells are connected in series to form a unit cell group (NADA cell). Such a unit cell group is connected to a bit line as one unit.

The memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cells are integrated and formed in an array in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to a bit line via a select gate. The source side of the NAND cell is connected to a source line (reference potential wiring) via a selection gate. The control gate of each memory cell is connected to a word line arranged in the row direction.

書 込 み The write operation of this NAND type EEPROM is as follows. The threshold value of all the memory cells in the NAND cell is made negative by the previous erase operation. Thereafter, data writing is performed in order from the memory cell located farthest from the bit line. A high voltage Vpp (approximately 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential VM (approximately 10 V) is applied to the control gate and the selection gate of the memory cell on the bit line side. 0 V or an intermediate potential is applied to the bit line according to write data. When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is set to “0”, for example. When an intermediate potential is applied to the bit line, electron injection does not occur. Therefore, at this time, the threshold value of the memory cell does not change. That is, the threshold value takes a negative value. This state is set to “1”.

Data erasure is performed on all memory cells in the NAND cell simultaneously. That is, all control gates and select gates are set to 0 V, the bit lines and source lines are set in a floating state, and a high voltage of 20 V is applied to the p-type well and the n-type substrate. As a result, electrons in the floating gate of all the memory cells are extracted to the p-type well, and the threshold value of the memory cells is shifted in the negative direction.

(4) The data read operation is performed as follows. That is, the control gate of the selected memory cell is set to 0 V, and the control gate and the selection gate of the unselected memory cell are set to the power supply potential Vcc (= 5 V). In this state, it is detected whether or not a current flows through the selected memory cell. It can be seen that data of "1" is stored if the data flows, and data of "0" is stored if the data does not flow.

As is clear from the above description of operation, in the NAND cell type EEPROM, at the time of write and read operations, unselected memory cells act as transfer gates. For this reason, there is a limit on the threshold voltage of the written memory cell. For example, a preferable range of the threshold value of the memory cell in which “0” is written must be about 0.5 to 3.5 V. In consideration of a change over time after data writing, a variation in manufacturing parameters of a memory cell, and a variation in power supply potential, the threshold distribution after data writing needs to be smaller than the above range.

However, in the conventional method in which the write potential and the write time are fixed and data is written to all memory cells under the same condition, it is difficult to keep the threshold range after “0” writing within an allowable range. For example, in memory cells, variations in cell characteristics occur due to variations in manufacturing processes. For this reason, a memory cell that is easy to write and a memory cell that is hard to write occur. Focusing on such a writing characteristic difference, in order to perform writing so that the threshold value of each memory cell falls within a desired range, the length of the writing time is adjusted, and writing is performed while verifying. It has also been proposed to put it in.

However, when such a method is adopted, the data of the memory cell must be output to the outside of the device in order to determine whether the writing has been sufficiently performed. For this reason, there was a problem that the total writing time was long.

As for the erase verify, as disclosed in Japanese Patent Application Laid-Open No. 3-259499, there is known a technique in which outputs of a plurality of sense amplifiers are inputted to an AND gate and their logic is taken to generate a batch erase verify signal. However, this circuit configuration can be used only for NOR type erase verify, and cannot be applied to write verify. The reason is that the write data takes both values of "1" and "0" and cannot perform the collective verification by taking the logic of the output of the sense amplifier. As described above, since write verification cannot be performed collectively, at the time of data writing, writing and verify reading are repeatedly performed, and data of each memory cell is output one by one to the outside of the chip each time. I had to. This has been a factor that hinders the speeding up of the write operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the difficulty in achieving the above-described high speed, and an object thereof is to speed up a write operation and a write verify and an erase operation and an erase verify without increasing the area of a control circuit. An object of the present invention is to provide an EEPROM and a system using the EEPROM.

The present invention provides a plurality of electrically rewritable nonvolatile semiconductor memory cells, a word line commonly connected to the plurality of memory cells, and a source line commonly connected to the plurality of memory cells. A nonvolatile semiconductor device comprising: a row decoder that supplies a write verify voltage to the word line; a plurality of bit lines connected to the corresponding memory cells; and a plurality of write verify circuits provided for the corresponding bit lines. A storage device, wherein each of the write verify circuits stores data of a first or second logic level, and charges the corresponding bit line in advance when storing the data of the first logic level. Then, after a predetermined period, the write state of the corresponding memory cell is detected, and if the data of the second logic level is stored, At least said predetermined period of time is configured as to connect the corresponding bit line to a predetermined power.

According to the present invention, it is possible to quickly detect whether or not writing and erasing are properly performed for each of a plurality of memory cells, and to quickly perform writing and erasing for all target memory cells. In addition, even if writing and erasing are repeated, it is possible to prevent the threshold value of the memory cell from fluctuating excessively.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a NAND type EEPROM according to a first embodiment of the present invention. A bit line control circuit 2 is provided for performing data write, read, rewrite, and verify read on the memory cell array 1. This bit line control circuit 2 is connected to a data input / output buffer 6. The address signal from the address buffer 4 is applied to the bit line control circuit 2 via the column decoder 3. A row decoder 5 is provided for controlling a control gate and a selection gate in the memory cell array 1. A substrate potential control circuit 7 is provided to control the potential of a p-type region (p substrate or p-type well) where the memory cell array 1 is formed.

(4) The program end detection circuit 8 detects data latched in the bit line control circuit 2 and outputs a write end signal. The write end signal is output from data input / output buffer 6 to the outside.

The bit line control circuit 2 mainly has a CMOS flip-flop (FF). These FFs perform latching of data to be written, a sensing operation for detecting a potential of a bit line, a sensing operation for verify reading after writing, and a latch of rewritten data.

FIGS. 2A and 2B are a plan view and an equivalent circuit diagram of one NAND portion of the memory cell array, respectively. 3A and 3B are a sectional view taken along the line AA 'and a sectional view taken along the line BB' of FIG. 2A, respectively. A plurality of memory cells, that is, a memory cell array having a plurality of NAND cells is formed in the p-type region 11 surrounded by the element isolation oxide film 12. The following description focuses on one NAND cell. In this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell. Each memory cell is above the substrate 11, floating gate 14 (14 _1, 14 _2, ..., 14 ₈₎ through a gate insulating film 13 is formed. Above these floating gates 14, control gates 16 (16 ₁ , 16 ₂ ,..., 16 ₈ ) are formed via an interlayer insulating film 15. Each n-type diffusion layer 19 is shared as a source in one of two adjacent memory cells and as a drain in the other. Thereby, each memory cell is connected in series.

The drain side and source side of NADA cells, respectively, selected formed by the same process as the floating gate and the control gate of the memory cell gate 14 _9, 19 ₉ and 14 _10, 16 ₁₀ are provided. The upper side of the substrate on which the elements are formed is covered with the CVD oxide film 17. Bit line 18 is provided on oxide film 17. The bit line 18 is in contact with the drain-side diffusion layer 19 at one end of the NAND cell. The control gates 14 of the same row of a plurality of NAND cells arranged in the row direction are connected in common and arranged as control gate lines CG1, CD2,... CG8 running in the row direction. These control gate lines are so-called word lines. Select gate 14 _9, 16 ₉ and 14 _10, 16 ₁₀ also, each of which is arranged as a selection gate line SG1, SG2 running in the row direction. The gate insulating film 13 between the select gates 14 ₁₀ and 16 ₁₀ and the substrate 11 can be made thicker than the gate insulating film of the memory cell. With such a thickness, reliability can be improved.

FIG. 4 shows an equivalent circuit of a memory cell array in which the plurality of NAND cells are arranged in a matrix.

FIG. 5 shows a specific configuration example of the bit line control circuit 2 in FIG. The CMOS flip-flop FF serving as a data latch and sense-up has first and second two signal synchronous CMOS inverters IV1 and IV2. The first signal synchronous CMOS inverter IV1 has E-type, p-channel MOS transistors Qp1, Qp2 and E-type, n-channel MOS transistors Qn3, Qn4. The second synchronous CMOS inverter IV2 has E-type, p-channel MOS transistors Qp3, Qp4 and E-type, n-channel MOS transistors Qn5, Qn6.

(4) The output node of the CMOS flip-flop FF and the bit line BLi are connected via an E-type, n-channel MOS transistor Qn7 controlled by a signal φF.

An E-type, n-channel MOS transistor Qn8 controlled by the output node of the flip-flop FF and an E-type, n-channel MOS transistor Qn9 controlled by the signal φV are connected in series between the bit lines BLi and Vcc. Have been. These transistors charge the bit line BLi to (Vcc-Vth) according to the data of the CMOS flip-flop FF at the time of verify reading.

A series circuit of the E type p-channel MOS transistor Qp5 and the D type n-channel MOS transistor QD1 is a circuit for precharging the bit line BLi to Vcc. The transistor QD1 is provided to prevent a high voltage from being applied to the transistor Qp5 during erasing or writing. The E-type, n-channel MOS transistor Qn10 is a reset transistor for resetting the bit line BLi to 0V.

The two nodes N11 and N12 of the CMOS flip-flop FF are connected to input / output lines / IO and IO via two transfer gates (E type, n-channel MOS transistors Qn1 and Qn2) controlled together by a column selection signal CSLi. It is connected.

{Circle around (4)} The node N11 of the CMOS flip-flop FF is connected to the gate of an E-type, n-channel MOS transistor Qn11. The output of the transistor Qn11 is used as a write end detection signal VDTC.

FIG. 6 shows a connection relationship between the bit line control circuit 2, the memory cell array 1, and the program end detection circuit 8.

(4) The E-type, p-channel MOS transistor Qp6 in the program end detecting circuit 8 outputs a write end detecting signal VDTC. As shown as a general example surrounded by a broken line in FIG. 6, FF is symbolized for convenience.

Next, the circuit operation at the time of writing and at the time of confirmation of this embodiment will be described. In the following description, it is assumed that one NAND cell is configured by a series circuit of eight memory cells as described above.

Prior to writing, data in the memory cell is erased by applying about 20 V (Vpp) to the p-type region (p substrate or p well) and setting the control gates CG1 to CG8 to 0V. By this erasing, the threshold value of the memory cell becomes 0 V or less.

FIG. 7 shows the operation at the time of writing / writing confirmation. In FIG. 5, write data is output line IO. / IO is latched by the CMOS flip-flop FF. Thereafter, the precharge signal φP becomes “H” and / φP becomes “L”, and the bit line BLi is precharged to Vcc. Further, the voltages VMB and φF change from Vcc to the intermediate potential VM (（10 V). According to the latched data, the bit line BLi becomes 0 V in the case of "0" writing, and becomes VM in the case of "1" writing. At this time, in FIG. 4, when the selection gate SG1 is VM and SG2 is 0V, and CG2 is selected as the control gate, CG1 is VM, CG2 is high voltage Vpp (up to 20V), and CG3 to CG8 are VM.

(4) When the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset to 0V, the signal φF becomes “L”, the reset signal φR becomes “H”, and the bit line BLi is reset to 0V. Subsequently, a write confirmation operation is performed.

(4) In the write confirmation operation, first, the precharge signal φp becomes “H” and / φp becomes “L”, and the bit line BLi is precharged to Vcc. Thereafter, the selection gate and the control gate are driven by the row decoder 5. After the data of the memory cell is read out to the bit line, the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset. Thereafter, the verify signal φV becomes "H", and (Vcc-Vth) is output only to the bit line BLi to which "1" has been written.

後 Thereafter, φSP and φRP become “H”, φSN and φRN become “L”, and φF becomes “H”. The signal φSP becomes “L” and φSN becomes “H”, and the bit line potential is sensed. Thereafter, the signal φRP becomes “L” and φRN becomes “H”, and the rewrite data is latched. At this time, the relationship between the write data, the memory cell data, and the rewrite data is shown in Table 1 below.

Table 1
Write data 0 0 1 1
Memory cell data 0 1 0 1
Rewrite data 1 0 1 1

Thereafter, the write end detection signal / φDV becomes “L”. If all the rewrite data is "1", the write end detection signal VDTC becomes "H". If at least one is "0", VDTC is "L". The write / write check operation is repeated until VDTC becomes "H". The detection result is output to the outside from the data input / output pin or the READY / BUSY pin.

In this embodiment, Table 2 shows the potentials of the bit line BLi, the select gates SG1 and SG2, and the control gates CG1 to CG8 at the time of erasing, writing, reading and writing confirmation. Here, a case where CG2 is selected is shown.

Table 2
Erase Write Read Write “0” “1” Confirm
Bit line BLi floating 0V 10V 5V 5V
Select gate SG1 0V 10V 10V 5V 5V
Control gate CG1 0V 10V 10V 5V 5V
〃 CG2 0V 20V 20V 0V 0. 5V
〃 CG3 0V 10V 10V 5V 5V
〃 CG4 0V 10V 10V 5V 5V
〃 CG5 0V 10V 10V 5V 5V
〃 CG6 0V 10V 10V 5V 5V
〃 CG7 0V 10V 10V 5V 5V
〃 CG8 0V 10V 10V 5V 5V
Select gate SG2 0V 0V 0V 5V 5V
Source line floating 0V 0V 0V 0V
Substrate 20V 0V 0V 0V 0V

FIG. 8 is a block diagram showing a NAND EEPROM according to a second embodiment of the present invention. The basic configuration is the same as in FIG. The second embodiment differs from the first embodiment in that the cell array 1 is divided into two blocks 1A and 1B, and a bit line control circuit 2 is provided in common for these cell blocks 1A and 1B.

FIGS. 9 and 10 show the bit line control circuit 2 and the program end detection circuit 8. FIG. In FIG. 9, an E-type, n-channel MOS transistor Qn16, Qn17 and an E-type, p-channel MOS transistor Qp7, Qp9 constitute an FF. The E type n-channel MOS transistors Qn14 and Qn15 are FF equalizing transistors. The E type, n-channel MOS transistors Qn27 and Qn28 are data detecting transistors.

The E-type, n-channel MOS transistor Qn18 and the E-type, p-channel MOS transistor Qp8 are FF activation transistors. The E-type, n-channel MOS transistors Qn19 and Qn20 include two nodes N1 and N2 of the FF and bit lines BLai (i = 0, 1,...) And BLbi (i = 0, 1,...) In the cell array blocks 1A and 1B. ). E-type, n-channel MOS transistors Qn21 to Qn24 are transistors for charging a bit line to Vcc-VTH in accordance with data. Qn25 and Qn26 are bit line precharge and reset transistors. In FIG. 10, E-type p-channel MOS transistors Qp10 and Qp11 are transistors for detecting the end of a program. / ΦDVA and / φDVB are program end detection signals, and φVEA and φVEB are program end detection signals.

Next, a description will be given of an operation of confirming writing to the EEPROM configured as described above with reference to FIG. Here, it is assumed that bit line BLai of memory cell array 1A is selected.

(4) For example, 0.5 V instead of 0 V is applied to the selected control gate as in the previous embodiment, and the verify signal φAV is output. First, the bit line BLai is precharged to 3V and BLbi is precharged to 2V. Thereafter, the precharge signals φPA and φPB become “L” level, and the bit lines BLai and BLbi float. The control gate and the selection gate are selected by the row decoder 5, and SG1, CG1, CG3 to CG8 are set to Vcc, and CG2 is set to, for example, 0.5V. In normal reading, if the threshold value of the memory cell is 0 V or more, reading is performed as "0", but in verify reading, "0" cannot be read unless it is 0.5 V or more.

(4) Thereafter, the bit line BLai is charged to (Vcc-Vth) by the verify signal φAV if “1” is written. Here, the voltage level of the precharge performed by the verify signal may be equal to or higher than the precharge voltage of the selected bit line. The equalizing signal φE is output, and the CMOS flip-flop is reset. Thereafter, .phi.A and .phi.B become "H", and the nodes N1 and N2 are connected to the bit lines BLai and BLbi, respectively. φP goes low and φN goes high, so that the data on bit line BLai is read. The read data is latched and becomes the next rewrite data. At this time, the rewrite data is converted from the data of the memory cell at the time of the verify read by the previous write data. This data conversion is the same as Table 1 in the previous embodiment.

(4) Thereafter, / φDVA becomes “L”, and as in the previous embodiment, if writing is completed, VDTCA becomes “H”, the program end detection signal φVEA becomes “L”, and the writing operation ends. At this time, the detection result is output from the data input / output pin or the READY / BUSY pin to the outside.

も Even in the verify read / rewrite operation of this embodiment, unnecessary rise of the threshold value of the memory cell to which “0” is written can be suppressed as in the previous embodiment.

In this embodiment, the potentials of the control gates CG1 to CG8 and the select gates SG1 and SG2 at the time of erasing, writing, verify reading, and reading are as shown in Table 3. Table 3 shows the potential relationship when the control gate CG2 is selected and the bit line BLai is selected.

Table 3
Erase Write Read Write “0” “1” Confirm
Bit line BLai floating 0V 10V 3V 3V
Bit line BLbi 〃 0V 0V 2V 2V
Select gate SG1 0V 10V 10V 5V 5V
Control gate CG1 0V 10V 10V 5V 5V
〃 CG2 0V 20V 20V 5V 0. 5V
〃 CG3 0V 10V 10V 5V 5V
〃 CG4 0V 10V 10V 5V 5V
〃 CG5 0V 10V 10V 5V 5V
〃 CG6 0V 10V 10V 5V 5V
〃 CG7 0V 10V 10V 5V 5V
〃 CG8 0V 10V 10V 5V 5V
Select gate SG2 0V 0V 0V 5V 5V
Source line floating 0V 0V 0V 0V
Substrate 20V 0V 0V 0V 0V
FIG. 12 schematically shows the data latch section in the bit line control circuit 2 and the program end detection circuit 8 in the present invention in relation to a selected bit line. FIG. 9A shows the first embodiment. The E type, n-channel MOS transistors QnD0 to QnDm correspond to the transistor Qn11 in FIG. The E type, p-channel MOS transistor Qp12 corresponds to the transistor Qp6 of the program end detecting circuit 8 in FIG.

（(B) shows an E-type, n-channel MOS transistor for data detection connected in series. If all the gates of the data detection transistors QnD0 to QnDm are at "H", the program ends, and Vx becomes "L".

(C) and (d), an E-type, p-channel MOS transistor QpD0 to QpDm is used as a data detecting transistor, and an E-type, n-channel MOS transistor Qn29 is used for a program end detecting circuit 8. Even in such a configuration, similarly to (a), it is possible to detect whether or not to end writing.

場合 As shown in FIG. 12A, when the detection transistors Qn DO to Qn Dm are connected in parallel, proper detection is possible even when the number of bit lines is several thousand bits. When these transistors are connected in series as shown in FIG. 1B, the source and drain of adjacent transistors can be shared, so that the pattern area can be reduced.

FIG. 13 shows an embodiment in which the circuit of FIG. 12 is applied to a one-transistor type (NOR type) flash EEPROM. In a NOR type flash EEPROM, data is inverted at the end of writing. Therefore, as shown in FIG. 13, the terminal of the FF opposite to that of FIG. 12 may be connected to the transistor for data detection.

Next, an embodiment of a NOR type flash EEPROM will be described.
FIG. 6 of Japanese Patent Application Laid-Open No. 3-250495 discloses a memory which employs a NOR type memory cell structure and achieves a high degree of integration similar to that of a NAND type. In this memory, both the writing and erasing operations can be performed by the FN tunnel current. By applying the batch verification circuit in the embodiment of the present invention to the memory as described above, the write verification time can be significantly reduced.

Such an embodiment will be described with reference to FIGS.
The circuit configuration of this embodiment is shown in FIG. This device is different from the NAND type E ² PROM in the following points. That is, data to be written to the memory cells MC in the memory cell block MCB is latched by the data latch DR. A signal is output from the node on the opposite side of the data latch DR to the detection transistor.

FIG. 15 shows the distribution of the threshold value _Vth of the cell in which data has been written and the cell in which data has been erased.

Table 4 shows the voltage applied to each part in multiple operations of erasing, writing, and reading.

Table 4
　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
BSL BL WL V _SS
　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
Erase 0v Floating 20v 0v
　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
Write “0” write (V _th > 5) 22v 0v 0v floating “1” write (V _th <5) 22v 20v 0v floating Unselected cell 22v 0v / 20v 10v floating 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
Lead 5v 0v / 5v 5v 0v
Next, the erasing operation will be described.
A block to be rewritten is selected by a row decoder of the block. In addition, the bit line corresponding to the selected memory cell is set to the floating state, and the word line is set to 20v. Thereby, electrons are injected into the floating gate of the selected memory cell. This injection is performed by the FN current. Therefore, the amount of current is extremely small. Therefore, it is possible to simultaneously erase memory cells of several thousand bits.

(4) The verify operation after erasing is performed by a batch verify operation. That is, for example, 5 V is added to the word line. At this time, the memory cell to be erased is turned on / off depending on whether or not its threshold value is sufficiently shifted in the positive direction by the erasing operation. That is, if it is off, it is understood that the erasure is OK.

More specifically, the verify operation is performed as follows. The signal PRE becomes "L" level, and the transistor T _PRE turns on. Thus, through the transistor T _PRE, the precharge line PRECL is precharged by V _cc. At this time, the select line SG is turned on by setting the select line BSL to 5v. Thereby, the bit line BL is also precharged. The word line WL to be selected is 5v. At this time, of the memory cells, those which have been erased / erased sufficiently are turned off / on. When the memory cell is turned off / on, the precharge potential of the bit line BL, that is, the precharge line PRECL is held / discharged. At this time, the potential of the precharge line PRECL is detected by the sense amplifier and latched in the data latch DR. Thereafter, the signal ERV is set to “H”, and the contents of the data latch DR are read out to the node NA. The potential of the node NA becomes “L” when all of the plurality of memory cells in the column corresponding to the node NA are erase OK, and becomes “H” when at least one of the memory cells has erase NG. The potential of the node NA is applied to the gate of the verify transistor T _VE . The transistor T _VE is turned off / on by “L / H” of the node NA. By turning off / on, the potential of the collective verify sense line L _VE does not reach the V _SS level. The above operation is performed for each column. Therefore, the level of the collective verify sense line L _VE becomes “H” when all cells in all columns are verified OK, and becomes “L” when at least one cell in any column is verified NG. ".

Next, a write operation (program operation) will be described.
The word line of the block to be programmed is set to 0v. The word lines of the other blocks are set to 10 V, and the electric field stress between the drain and the gate in each memory cell is reduced. In the block to be programmed, a bit line connected to a memory cell from which electrons are to be extracted from the floating gate is selectively set to 20 V and programmed.

(4) Program verify is determined based on the “H / L” level of the potential of the precharge line PRECL at the time of verify read and the program data “0/1”. However, the batch verification is performed by setting the signal PRV to “H”. Then, in the case of the program NG, rewriting is performed. In this rewriting, the precharge line PRECL connected to the cell of “0” write OK is discharged to “L” level. Therefore, at the time of rewriting, since the bit line is at the "L" level, no emission of electrons from the floating gate occurs. On the other hand, in the cell of “1” write OK, the threshold value is sufficiently lowered. For this reason, at the time of reprogramming, the precharge potential is discharged through the “1” write OK cell and becomes the “L” level. Therefore, even if reprogramming is performed, the threshold value of the “1” write OK cell does not change. On the other hand, in the case of program NG, that is, in the case of "1" write NG, there is no decrease due to the discharge of the precharge potential. Therefore, the “H” level is latched again and programmed again.

The embodiment as described above has the following effects.
Since the cell structure is the same as that of the NAND type cell, miniaturization is possible and the chip can be downsized. Further, since the cell itself is of the NOR type, the operating current I _cell is large and random access at high speed is possible. Further, page write / page read is possible.

In the embodiments of FIGS. 12 (b) and 12 (c), the same operation can be realized by directly connecting the gate of the data detecting transistor to the bit line BLi. Such examples are shown in FIGS. 16A and 16B, respectively. Similarly, in the embodiment shown in FIGS. 13A and 13D, the same operation can be realized by directly connecting the gate of the data detection transistor to the bit line BLi. This is shown in FIGS. 17A and 17B, respectively.

Further, in FIGS. 12, 13, 16, and 17, the single bit line system is employed, but an open or folded bit line system may be employed. The configurations of the data detection transistor, the COMS flip-flop FF, and the selected bit line may be the same as those in this embodiment.

FIGS. 12, 13, 16, and 17 schematically show the configuration of a data detection transistor, a CMOS flip-flop FF, and a selected bit line, and the present invention can be similarly implemented in various bit line systems.

Next, still another embodiment of the present invention will be described. In each of the embodiments described above, one end of the CMOS flip-flop (data latch / sense amplifier circuit) provided at one end of the bit line is connected to the gate electrode of the detection transistor. Then, regardless of the address signal, it is detected whether or not the contents in all the data latches are "1" write data, thereby detecting whether or not the write state is sufficient.

(4) For this reason, the data of the data latch circuit of the defective column address or the unused redundant column address provided for the relief is also detected. Normally, the write state is sufficient, but the detection is performed in an insufficient manner, which causes a problem that the write is not completed. That is, the write state confirmation operation after data writing may malfunction due to the influence of the defective column address or the unused column address.

Therefore, in this embodiment, means is provided to remedy a malfunction of the detection circuit for detecting rewrite data. This makes it possible to detect the write state of only the originally used column address without being affected by the write state of the defective column address or unused column address.

The basic configuration is the same as that of the first embodiment shown in FIGS. In this embodiment, in addition to the first embodiment, a fuse and a nonvolatile memory are connected to the write-end detecting MOS transistor, as described later, in order to remedy a malfunction of the write-end detecting circuit.

FIG. 18A shows an algorithm at the time of writing / writing confirmation. When a program command is input, "1" program data is automatically latched in data latch circuits at all column addresses including a redundant column. Here, when the cell array is divided and the data latch circuit is also divided, all the column addresses indicate all the column addresses of the selected divided part.

(4) The write operation is completely the same as that of the first embodiment, and the write confirmation operation is substantially the same as that of the first embodiment. However, in Table 1 above, the memory cells at the defective column address and the unused column address are reset to “1” before data input. Therefore, the rewrite data is always "1" regardless of the write data or the data of the memory cell.

If the write / write confirmation operation is performed in accordance with the algorithm shown in FIG. 18A, for example, even if there is a memory cell in which “0” cannot be written at the defective column address, the write end detection operation is affected by this memory cell. There is no malfunction. More specifically, although the write state is sufficient, the write cell is erroneously detected as insufficient write and is not terminated due to the influence of the memory cell at the defective column address or unused column address. Can be prevented beforehand.

FIG. 18 (b) shows another algorithm. For example, assume that a bit line at a certain defective column address is short-circuited to the ground potential. In this case, when "1" program data is set as shown in FIG. 18A, the intermediate potential VM is applied to this bit line. As a result, the intermediate potential VM is short-circuited to the ground potential. As a result, the VM generated by the booster circuit may not be boosted to a predetermined voltage.

Therefore, in the algorithm shown in FIG. 18B, "0" program data is automatically set only in unused column addresses (including defective addresses) after external data input. After the verify read, "1" program data is automatically set to an unused column address. By doing so, a highly reliable NAND cell type EEPROM can be realized without being affected by the defect of bit line leakage. In each of FIGS. 18A and 18B, the portion within the broken line indicates that the process is automatically performed inside the EEPROM.

FIG. 19A schematically shows a CMOS flip-flop data latch / sense amplifier and a write end detection transistor shown in FIG. FIGS. 17B and 17C show examples in which fuses Fu1 and Fu2 are connected to a write end detecting MOS transistor to remedy a malfunction of the write end detecting circuit. In FIG. 17B, a fuse Fu1 made of a poly-Si line or an Al line is provided between the source of the write completion detection MOS transistor and the ground line. After the EEPROM test, among the fuses Fu1, the fuse Fu1 at a defective column address or an unused column address is cut by a laser beam or the like. As a result, the write end detection operation is not performed for the column address where the fuse Fu1 has been cut.

FIG. 19C shows a case where a nonvolatile memory cell is used as the fuse Fu2. In order to use this nonvolatile memory cell as a fuse, ultraviolet light is first applied to erase (initialize) the fuse data. That is, for example, V _{th of the} memory cell Fu2 is set to be negative, or 0 <V _th <V _cc . In order to program the fuse data, VF1 is applied to, for example, a VM equal to or higher than _Vcc , VF2 is set to 0 V, and VDDTC is set to _Vcc . "0" program data is latched by a latch connected to a column address to be disconnected between the source of the write end detection MOS transistor and the ground potential. "1" program data is latched in a latch connected to a column address which is not to be disconnected. A current flows through the memory cell (fuse Fu2) at the column address that latches the “0” data, and its V _th increases due to hot electron injection. Since no current flows through the cell (fuse Fu2) at the column address latching the "1" data, its _Vth does not rise. In this case, VF2 may be set to _Vcc and VDDTC may be set to 0v.

During normal operation, the potential of each unit is set as follows. That is, when the V _th of the memory cell during erasure of fuse data becomes negative, cities V _th of the memory cell positive, as ground potential VF1, a disconnected state memory cell (fuse Fu2). If V _{th of the} memory cell is in the range of 0 <V _th <V _cc at the time of data erasure, V _th of the memory cell is set to V _th > V _cc , VF 1 = V _cc, and VF 2 is grounded. Thus, the disconnected state of the memory cell is obtained.

When erasing data in the fuse memory Fu2, VF1 is set to the ground potential, VF2 is set to a VM of _Vcc or more, and the tunnel current makes the _Vth of the fuse _Vth <0v or 0v < _Vth < _Vcc. Good.

FIG. 20 (a) focuses on a certain column in the circuit shown in FIG. 19 (c). FIG. 20B is a plan view of the write completion detecting MOS transistor and the nonvolatile memory for fuse of FIG. 20A. FIG. 20C is a sectional view taken along line XX ′ of FIG. The write completion detecting MOS transistor and the nonvolatile memory for the fuse are formed simultaneously with the formation of the NAND type memory cell. The gate electrode of the write completion detection MOS transistor has a two-layer structure, like the select gate of the NAND cell, and these two-layer gates are connected to each other on the isolation insulating film 12.

The first elements such as the write-end detection MOS transistor and the nonvolatile memory cell for the fuse are formed in the same manner as the second element such as the selection transistor and the memory cell in the NAND cell. For example, the concentration of the n-type diffusion layer of the first element may be slightly increased by injection of hot electrons to facilitate programming. For example, the concentration of the n-type diffusion layer of the first element is set to the concentration of the n-type diffusion layer of a peripheral transistor having a higher n-type diffusion layer than that of the second element. Then, the second element may be formed simultaneously with the n-type diffusion layer of the peripheral transistor.

FIG. 21 shows another example of the write completion detecting MOS transistor and the nonvolatile memory cell for fuse. 2A is a sectional view of the element structure, and FIGS. 2B and 2C are equivalent circuit diagrams of FIG. The programming of the nonvolatile memory cell for the fuse is performed in the same manner as in FIG. FIG. 21B shows the case where the VF2 is grounded for programming. FIG. 21C shows the case where the VDDC is grounded and programmed. This structure is formed similarly to the transistor shown in FIG.

When programming the nonvolatile memory cells shown in FIGS. 20 and 21, it is efficient to set the power supply potential _Vcc higher than during normal operation. Further, if the power supply VMB of the CMOS flip-flop is set to, for example, a VM of _Vcc or more, programming is efficient.

FIG. 22 shows a program algorithm for the NAND cell type EEPROM in the circuit having the fuses shown in FIGS. 19 (b) and 19 (c).

(4) After inputting the program command (S1), "0" program data is automatically set to all the column addresses including the unused column (including the defective column) (S2). Thereafter, program data is input in the page mode (S3), and writing / writing confirmation / writing end detection is automatically performed (S4 to S7). The reason why "0" program data is set in the unused column is to prevent the intermediate potential VM from being applied to the unused bit line during programming. Further, if VM is the output of the booster circuit and the unused bit line is short-circuited to, for example, the ground potential, the VM is not boosted to a predetermined potential.

FIG. 23 shows another example of FIG. 19 (b). A write end detection MOS transistor is connected to bit lines sharing the same column address selection signal CSLi. The fuses for these transistors may be shared. This results in a smaller layout area. Of course, this fuse may be replaced by a nonvolatile memory.

Next, an embodiment in which the above-described rescue means is applied to the second embodiment shown in FIGS.
The basic operation is the same as in the second embodiment. Also in this embodiment, if programmed by the algorithm shown in FIG. 18, it is possible to minimize the malfunction of the write end detecting circuit due to the influence of the unused column address.

Alternatively, as shown in FIG. 24, programming may be performed according to the algorithm of FIG. 22 using a fuse. In the case of FIG. 24A, two write detection MOS transistors are connected to one data latch and sense amplifier. One fuse is connected to each of these two transistors. Fuse cutting at the time of programming is performed simultaneously for two fuses. Therefore, one fuse may be used as shown in FIG. In FIGS. 24A and 24B, a nonvolatile memory can be used as a fuse.

し て も Even if the circuits in FIGS. 19 (b) and (c) are changed as shown in FIGS. 25 (a) and (b), the same function can be provided. As shown in FIGS. 26A and 26B, a p-channel E-type MOS transistor may be used as the detection MOS transistor. FIG. 27 shows an example in which a MOS transistor for detection is directly connected to a bit line. Also in this example, a nonvolatile memory can be used for the fuse.

FIG. 28 is a time chart for explaining the third embodiment. This is for explaining the operation of collectively latching "0" and "1" program data in the data latch and sense amplifier circuits at all column addresses, respectively.

に お い て In FIG. 6A, φF maintains “L”, I / O becomes “H”, / I / O becomes “L”, and φSP = “L”, φSN = “H”. Subsequently, φRP = “L”, φRN = “H”, and the “1” latch ends.

In the case of a “0” latch, I / O = “L” and / I / O = “H” as shown in FIG. After the FF becomes inactive, φRP = “L” and φRN = “H” first. Subsequently, φSP = “L” and φSN = “H”.

FIG. 29 is a time chart for explaining the fourth embodiment. This chart shows the operation when the data latch / sense amplifier at all column addresses latches "0" or "1" program data. φA and φB remain “L”, and the potential of I / O and / I / O is determined according to data “0” or “1”. φP = “H”, φN = “L”, and the FF is inactivated. Thereafter, φE becomes “H” and is equalized. After the equalization is completed, the all-column selection signal CSL becomes "H", .phi.P = "L", and .phi.N = "H", and are latched.

Note that all columns in FIGS. 28 and 29 are, for example, when the cell array is divided and the data latch and sense amplifier are also divided accordingly. Say. In FIG. 8, the open bit line system is used, but the same can be applied to the folded bit line system.

FIG. 30 shows a modification of the third embodiment, in which one CMOS flip-flop FF is shared by two adjacent bit lines. The gates of the p-channel E type write detection MOS transistors T1 and T2 are connected to the end of the bit line BL opposite to the flip-flop FF. The fuses F1, F2 of the write detection transistors T1, T1; T2, T2 whose gates are connected to the bit line selected by the same column selection signal CSLi can be shared as shown in FIG. Further, the fuses F1 and F2 can be inserted between the power supply potential _Vcc and the sources of the write detection transistors T1 and T2 (FIG. 31A). In this case, two fuses can be shared by one fuse F (FIG. 31B).

According to the third and fourth embodiments, in addition to the same effects as those of the first and second embodiments described above, the following effects can be obtained. That is, when detecting the result of the write verify read, the write state can be confirmed without being affected by the unused column address or the defective column address. This makes it possible to obtain an EEPROM having a write end detecting circuit with extremely few malfunctions.

Next, a fifth embodiment of the present invention will be described.
FIG. 32 is a block diagram of a NAND cell type EEPROM of the fifth embodiment. A bit line control circuit 2 for performing data write, read, rewrite, and verify read with respect to the memory cell array 1 is provided. This bit line control circuit 2 is connected to a data input / output buffer 6. The output of the column decoder 3 is applied to the memory cell array 1 via the bit line control circuit 2. The column decoder 3 receives an address signal from the address buffer 4 and a redundant address signal output from the column redundancy circuit 10. The address signal from the address buffer 4 is applied to the column redundancy circuit 10. Further, a row decoder 5 is provided to control a control gate and a selection gate in the memory cell array 1. A substrate potential control circuit 7 is provided to control the potential of the p substrate or the n substrate on which the memory cell array 1 is formed.

(4) The program end detection circuit 8 detects data latched in the bit line control circuit 2 and outputs a write end signal. The write end signal is output to the outside via the data input / output buffer 6. A bit line charging circuit 9 is provided to charge the bit line to a predetermined voltage regardless of the address signal. An equivalent circuit of the memory cell array 2 is shown in FIG.

FIG. 33 shows a specific configuration of the memory cell array 1, the bit line control circuit 2, and the bit line charging circuit 9. The NAND cells NC shown in FIG. 2 are arranged in a matrix. NCijr (i = 0 to k, j = 0 to n) is a redundant part. The data latch and sense amplifiers R / W0 to R / Wm and R / W0r to R / Wkr are respectively connected to bit lines BL0 to QFnkr via data transfer transistors QFn0 to QFnm and QFn0r to QFnkr of N-channel and E-type MOS transistors. BLm, BL0r to BLkr. The column selection signals CSL0 to CSLm and CSL0r to CSLkr which are the inputs of the data latch and sense amplifier R / W are the outputs CSL0 to CSLm of the column decoder 4 and the outputs (CSL0r to CSLkr) of the redundancy circuit 10. Of the bit lines BL0 to BLm, up to (k + 1) bits can be replaced by the bit lines BL0r to BLkr of the redundant part.

N-channel E-type MOS transistors QRn0 to QRnm, QRn0r to QRnkr are resetting transistors for resetting the bit lines to the ground potential. The n-channel E-type MOS transistors QPn0 to QPnm and QPn0r to QPnkr are charging transistors and transfer the bit line charging voltage VBL to the bit lines as necessary.

The fuses F0 to Fm and F0r to Fkr are used to cut off the connection between the charging transistor and VBL, and all the fuses connected to unused bit lines including the defective bit line are cut off. For example, when the bit line BL2 is replaced with the redundant bit line BL0r, the fuse F2 is cut. When the remaining redundant bit lines BL1r to BLkr are not used, all the fuses F1r to Fkr are cut.

FIG. 34 shows the operation at the time of writing. Prior to the write operation, all the data latch and sense amplifiers R / W are reset to "0" program data. Thereafter, the program data is transferred from the data lines I / O and / I / O to the R / W and latched. While data is latched in all R / Ws, bit lines, control gates, and select gates are precharged. After the bit line reset signal φR becomes “L”, the bit line precharge signal φP and the charging voltage VBL become the power supply voltage _Vcc . Bit lines other than unused bit lines, that is, used bit lines are charged to _Vcc . The control gates CG1 to CG8 of the NAND cell and the selection gate SG1 are charged to _Vcc . The select gate SG2 is set to the ground potential during the write operation. Thereafter, the bit line precharge signal φP and the charging voltage VBL are boosted to the intermediate potential VM (about 10 V), and the bit line BL, the control gates CG1 to CG8, and the selection gate SG1 are also boosted to VM.

After the completion of the data latch, the precharge signal φP becomes “L”, the data transfer signal φF becomes _Vcc , and then the voltage is raised to VM. According to the latched program data, only the bit line where the “0” data is latched is set to the ground potential. Further, the selected control gate (here, CG2) is boosted to a high voltage V _pp (about 20 V). Unused bit lines including defective bit lines remain at the ground potential because the corresponding R / W is reset to “0” program data before the data latch operation. In a memory cell connected to a bit line in which “0” program data is latched in R / W, the threshold value increases. In a memory cell connected to a bit line in which “1” is latched in R / W, the threshold value does not change and the threshold value at the time of erasing is maintained.

(4) After the control gates CG1 to CG8 and the selection gate SG1 are reset to the ground potential, the data transfer signal φF is grounded, the reset signal φR becomes “H”, and the bit line is reset to the ground potential.

During this write operation, the operation of resetting all R / Ws to “0” program data and the fuse cutting operation of the bit line charging circuit, which are performed prior to data loading, cause the intermediate potential VM to be applied to the unused bit lines. Is not applied.

FIG. 35 shows a read operation. The reset signal φR becomes “L”, and the precharge signal φP becomes “H”. As a result, all bit lines other than the unused bit lines are charged to VBL (typically V _cc ). The selected control gate (here, CG2) is grounded, and the remaining control gates CG1 and CG3 to CG8 are set to “H” (typically V _cc ). Since the threshold value of the memory cell into which the “0” data is written is high (V _th > 0 V), the bit line potential remains at “H”. Since the threshold value of the memory cell in which the “1” data is written is low (V _th <0 V), the bit line potential becomes “L”. After the data of the memory cell is output to the bit line as a bit line voltage, the data transfer signal φF becomes “H” and the bit line voltage is sensed by the data latch / sense amplifier R / W. Note that the potential of each part of the memory cell is the same as in Table 2.

As described above, according to the present embodiment, the defective bit can be relieved by cutting the fuse of the bit line charging circuit, and the same effects as those of the third and fourth embodiments described above can be obtained.

FIG. 36 shows the sixth embodiment, and shows a specific configuration of the memory cell array 1, the bit line control circuit 2, and the bit line charging circuit 9 as in FIG.

For two adjacent bit lines BLai and BLbi, BLajr and BLbjr (i = 0... M, j = 0... K), data latch and sense amplifiers R / Wi, R / Wjr (i = 0. j = 0... k) are arranged one by one. A data transfer signal φFa, a reset signal φRa, and a precharge signal φPa are prepared for bit line BLai. ΦFb, φRb, φPb are prepared for bit line BLbi. The bit line charging voltage power supply VBL is prepared in common for BLai and BLbi.

37 and 38 show the write and read operations, respectively. When BLai is selected, BLai operates in the same manner as the embodiment of FIG. The unselected bit line BLbi prevents erroneous writing to the memory cell connected to BLbi while being charged to the intermediate potential VM during the writing operation. BLbi keeps the ground state during the read operation, and functions to suppress the coupling noise between the bit lines. Table 5 shows the potential of each part of the memory cell.

Table 5
　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
Erase write read “0” “1”
　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
Bit line BLai floating 0v 10v 5v
Bit line BLbi 10v 10v 0v
Select gate SG1 0v 10v 10v 5v
Control gate CG1 0v 10v 10v 5v
Control gate CG2 0v 20v 20v 0v
Control gate CG3 0v 10v 10v 5v
Control gate CG4 0v 10v 10v 5v
Control gate CG5 0v 10v 10v 5v
Control gate CG60v 10v 10v 5v
Control gate CG7 0v 10v 10v 5v
Control gate CG80v 10v 10v 5v
Select gate SG2 0v 0v 0v 5
Source line floating 0v 0v 0
Base plate 20v 0v 0v 0
　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
FIG. 39 is a modification of the embodiment of FIG. Here, four types of data I / O lines I / O0 to I / O3 are used, and a common column selection signal CSLi is input to four data latch / sense amplifiers R / W. If any one of the four bit lines to which CSLi is commonly input has a leak failure, it must be repaired collectively. For this reason, in this embodiment, four fuses are combined into one. In the embodiment shown in FIG. 36, similarly, as shown in FIG. 40, fuses of a plurality of bit lines that commonly input CSLi can be combined into one.

FIG. 41 is a modification of the embodiment shown in FIG. The example of FIG. 41 differs from the embodiment shown in FIG. 40 in that the fuse is divided into a fuse Fa for BLai and a fuse Fb for BLbi. In this case, the provision of the two fuses Fa and Fb inevitably increases the circuit area. However, since the relief can be performed separately for BLai and BLbi, the relief efficiency increases. This rescue method will be described in detail with reference to FIGS.

FIG. 42 schematically shows the embodiment of FIG. When the repair is performed using only the column selection signal CSLi, BLai and BLbi are simultaneously replaced as shown in FIG. Similarly, in the case of FIG. 40, BLai0 to BLai3 and BLbi0 to BLbi3 are simultaneously replaced. On the other hand, in the embodiment of FIG. 36, as shown in FIG. 42B, only BLai or only BLbi can be replaced with the redundant portion BLajr or BLbjr without any problem in operation. For this purpose, relief is performed by the logical product of the column selection signal CSLi and the data transfer signal φFa (or φFb).

FIG. 43 schematically shows FIG. 41. Similar to FIG. 42B, only BLai0 to BLai3 can be replaced with BLajr0 to BLajr3, or only BLbi0 to BLbi3 can be replaced with BLbjr0 to BLbjr3. In this case, the fuses may be connected as shown in FIG. As is clear from FIGS. 42 and 43, it is only necessary to keep the arrangement relationship between BLa and BLb for relief.

FIG. 44 shows an embodiment in which one data latch and sense amplifier R / W is shared by four bit lines. BLa1i and BLbli are adjacent to each other. BLa2i and BLb2i are arranged symmetrically with respect to R / W. Even in such a case, various rescuing methods can be implemented as shown in FIGS. 45 and 46 by taking the logic of CSLi and φFa1, φFa2, φFb1, and φFb2 while keeping the arrangement relationship between BLa and BLb. .

{Specifically, in FIG. 45A, four bit lines BLa1i, BLa2i, BLb1i, BLb2i connected to the same R / W are simultaneously replaced. In FIG. 45B, two bit lines BLa1i and BLa2i or BLb1i and BLb2i are replaced as a unit. In FIG. 46A, two bit lines BLa1i and BLb1i or BLa2i and BLb2i are replaced as a unit. In FIG. 46B, each bit line is replaced with a bit line of a redundant portion.

In the embodiments of FIGS. 39, 40, and 41, as shown in FIGS. 47, 48, and 49, a precharge MOS transistor and a reset MOS transistor are shared by bit lines that force the column selection signal CSLi. You may make it. When the bit line is precharged or reset, that is, when φR or φP becomes “H”, φPR is set to “H”. In this example, the signal φPR is separately required, but the number of reset or precharge MOS transistors can be reduced.

In the fifth and subsequent embodiments, a fuse for repairing a defective bit is provided between the bit line charging circuit and the terminal voltage power supply line. However, these embodiments are used in combination with the third and fifth embodiments. It is also possible to use it.

In the above, various circuit configurations for shortening the write verification time have been described using the first to sixth embodiments. Next, an embodiment using the present invention for erase verification will be described.

FIG. 50 is a block diagram showing a nonvolatile semiconductor memory device using a NAND type EEPROM according to a seventh embodiment of the present invention. A sense amplifier / latch circuit 2 for performing data write, read, write, and erase verify is connected to the memory cell array 1. The memory cell array 1 is divided into blocks composed of a plurality of pages. This block is the minimum erasing unit. The sense amplifier / latch circuit 2 is connected to a data input / output buffer 6. An address signal from the address buffer 4 is input to the column decoder 3. An output from the column decoder 3 is input to the sense amplifier / latch circuit 2. A row decoder 5 is connected to the memory cell array 1 to control a control gate and a selection gate. A substrate potential control circuit 7 for controlling the potential of a p-type region (p-type substrate or p-type well) where the memory cell array 1 is formed is connected to the memory cell array 1.

The verify end detecting circuit 8 detects data latched in the sense amplifier / latch circuit 2 and outputs a verify end signal. The verify end signal is output to the outside through the data input / output buffer 6.

FIG. 51 shows a connection relationship between the sense amplifier / latch circuit 2, the memory cell array 1, and the verify end detection circuit 8. In the circuit of FIG. 51, detection means (detection transistor Qn12) controlled by the first output of the sense amplifier / latch circuit FF is provided. As the detection transistor Qn12, an E-type n-channel MOS transistor is used. The transistor Qn12 is provided in each sense amplifier / latch circuit FF connected to each bit line BLi. As shown in FIG. 51, the detection transistors Qn12 are provided in parallel by connecting their drains to the sense line VDTCE in common.

Next, the erase operation will be described first with reference to the flowchart of FIG. When an erase command is input, an erase verify cycle starts. If the erased state is detected, the erase is completed at that point (YES in step 101). If it is detected in step 101 that the memory cell has not been erased, the erase operation is started (step 102), and then a verify operation is performed (step 103). If verify is NG, erase and verify are repeated a predetermined number of times (step 104).

Next, an erasing confirmation operation will be described.
(1) In the erase operation, a high voltage (for example, 20 V) is applied to a p-type region (p-type substrate or p-well) where a memory cell is formed, and VSS is applied to a control gate. As a result, the threshold value of the memory cell shifts in the negative direction.
(2) Next, the data of the memory cell is read. In the state of ΦF being “H”, Φsp is set to “H”, Φsn is set to “L”, Φrp is set to “H”, and Φrn is set to “L” to deactivate the C ² MOS inverter. Thereafter, / ΦP is set to “L” to precharge the bit line to VCC. Next, the selected control gate is held at VSS, the unselected control gate is held at VCC, and the selected gate is held at VCC for a certain period of time. At this time, if the selected memory cell is erased and has a negative threshold value, a cell current flows and the bit line is discharged until it reaches VSS.
(3) Next, Φsp is set to “L” and Φsn is set to “H”, and the bit line potential is detected. The data is latched by setting Φrp to “L” and Φrn to “H”.
(4) After that, it is confirmed whether the verification is completed by using the detection transistor. As described above, the sense line VDTCE is commonly connected to the drains of the detection transistors of the plurality of sense amplifier / latch circuits. If all the memory cells have a negative threshold, the sense line VDTCE goes "H". In this case, check the next page. If at least one cell with a positive threshold value remains, VDTCE goes to the “L” state. In that case, erasure is repeated until VDTCE is detected to be "H". The detection result is output to the outside from the data input / output pin or the READY / BUSY pin.

デ ー タ In this example, data was confirmed page by page. However, the confirmation operation may be performed once for all pages in one NAND block. In this case, VSS is applied to all the control gates in the selected block, and the read operation is performed in this state. At this time, if one memory cell still has a positive threshold value, the bit line is not discharged, so that it can be detected in the same manner as in the above embodiment.

(4) The voltage applied to the control gate does not necessarily need to be at the VSS level. A negative voltage may be applied to include a margin. Further, even when VSS is applied to the control gate and a positive voltage is applied to the source or the source and the p-type substrate or the p-well, a state where a negative voltage is applied to the control gate is created. Good. Further, a fuse may be provided between the source of the detection transistor and VSS. If the fuse of the sense amplifier / latch circuit corresponding to the defective bit line or the unused one of the redundancy bit lines is cut off, there is no operational problem. As described above, the state of erasure can be detected.

These operations can also be controlled systematically. In this case, the system has a management table that stores, for each block of the NAND type EEPROM, whether or not the block is in an erased state. When performing erasing, the host system or the controller that controls the nonvolatile semiconductor memory device first refers to the management table to detect whether the block to be erased in the NAND type EEPROM is in the erased state. If the reference result is not erased, erase is performed. In the case of indicating that erasure has been completed, further erasure operation may not be performed.

消去 Erase confirmation is also valid before a write operation. Before the writing operation, it may be checked whether or not the area to be written is erased. In this case, it may be performed on a block basis or on a page basis.

に お い て In FIG. 51, the write verify operation is almost the same as the conventional one, so that the detailed description is omitted.

FIG. 53 shows an eighth embodiment of the present invention.
The basic configuration is the same as FIG. In the eighth embodiment, the cell array is divided into two blocks 1A and 1B, and a common sense amplifier / latch circuit 2 is provided for these cell array blocks 1A and 1B. FIG. 54 shows the configuration of the sense amplifier / latch circuit. E-type n-channel MOS transistors Qn16 and Qn17 and E-type p-channel MOS transistors Qp7 and Qp9 constitute a flip-flop FF. The E-type n-channel MOS transistors Qn14 and Qn15 are FF equalizing transistors. Qn27 and Qn28 are detection transistors.

E-type n-channel MOS transistor Qn18 and E-type p-channel MOS transistor Qp8 are FF activation transistors. The E-type n-channel MOS transistors Qn19 and Qn20 are transistors for connection between the two nodes N1 and N2 of the FF and the bit lines in the cell array blocks 1A and 1B. Qn25 and Qn26 are transistors for precharging and resetting bit lines. Qn21 to Qn24 are transistors for connection between the bit line and the VCC line.

The verify operation after erasure having such a configuration will be described.
Here, the case where bit line BLai of memory cell array 1A is selected will be described.

{First, the bit line BLai is precharged to 3v, and the BLbi is precharged to 2v (reference potential). Thereafter, the precharge signals ΦPA and ΦPB become “L”, and the bit lines BLai and BLbi enter a floating state. Next, the selected control gate is set to VSS, the non-selected control gate is set to VCC, and the selected select gate is set to VCC, and held for a certain period of time. After the CMOS flip-flop is reset by the equalize signal, ΦA and ΦB become “H”, and the nodes N1 and N2 are connected to the bit lines BLai and BLbi, respectively. ΦP becomes “L” and φN becomes “H”, and the bit line BLai is read. The read data is latched. Thereafter, the detection is collectively performed by the detection transistor Qn27.

Next, it is assumed that the bit line BLbi of the memory cell array 1B is selected.
First, the bit line BLbi is precharged to 3v, and BLai is precharged to 2v (reference potential). Thereafter, the precharge signals ΦPA and ΦPB become “L”, and the bit lines BLai and BLbi enter a floating state. Next, the selected control gate is set to VSS, the non-selected control gate is set to VCC, and the selected select gate is set to VCC, and held for a certain period of time. The CMOS flip-flop is reset by the equalizing signal. Thereafter, ΦA and ΦB become “H”, and the nodes N1 and N2 are connected to the bit lines BLai and BLbi, respectively. When ΦP becomes “L” and ΦN becomes “H”, the bit line BLbi is read. The read data is latched. Thereafter, the detection is collectively performed by the detection transistor Qn28.

(4) At the time of write verification of the memory cell array 1A, Qn28 is used as a detection transistor. At the time of write verification of the memory cell array 1B, Qn27 is used as a detection transistor. Thus, according to the memory address and the erase / write mode, which detection transistor is used at the time of the verify operation is controlled. Thus, the verify operation can be performed by one detection transistor.

FIG. 55 shows a ninth embodiment of the present invention. In the seventh embodiment of FIG. 51, the detection transistors are connected to both nodes of the sense amplifier / latch circuit. In contrast, in the ninth embodiment, a p-type detection transistor and an n-type detection transistor are connected to one node of the circuit. At the time of write verification, an n-type detection transistor is used as in the related art. At the time of erase verification, a p-type detection transistor is used. After erasing, a reading operation is performed. If there is an insufficiently erased memory cell, "H" is latched at the node on the bit line side of the sense amplifier / latch circuit, and "L" is latched at the node opposite to the bit line. As a result, the p-type detection transistor is turned on, and VDTCE becomes “H” level. This potential is detected, and the erase operation is performed again.

FIG. 56 shows a tenth embodiment of the present invention. In the eighth embodiment shown in FIG. 54, the detection transistors are connected to both nodes of the sense amplifier / latch circuit. In contrast, in the embodiment, a p-type detection transistor and an n-type detection transistor are connected to one node of the circuit. For the write verification of the memory cell array 1A, an n-type detection transistor Qn28 is used. For the erase verification of the memory cell array 1A, a p-type detection transistor of Qp29 is used. For write verification of the memory cell array 2A, a p-type detection transistor of Qp29 is used. For the erase verification of the memory cell array 2A, an n-type detection transistor Qn28 is used.

The embodiments using the present invention for erase verification have been described above. It is needless to say that this configuration can also be applied to a NOR type cell similarly to the above-described write verify.

(4) By using the present invention for erase verification, the following effects can be obtained. That is, the erase verify operation can be performed at a high speed without reading the data to the outside. Further, when the cell array is composed of two blocks, one detecting means can be used for erase verification of one memory cell array block and write verification of the other memory cell array block. Thus, the area of the batch verify circuit can be reduced. Further, prior to the erasing operation, a means for detecting whether or not the selected block is in an erasing state is provided. For this reason, it is not necessary to perform an unnecessary erasing operation at the time of a rewriting process or the like. As a result, it is possible to increase the speed and increase the reliability.

Next, a description will be given of an eleventh embodiment in which the erase verification and the write verification are used by one batch verification means.

特 徴 The features of this embodiment are as follows. That is, the program verify and erase verify are simultaneously and collectively read for 256 bytes, and the batch verify control circuit BBC is provided to determine whether the data is OK or NG. Further, the data register circuit DR is configured to be capable of performing batch verification, and is configured not to write again to the program completion bit when reprogramming is performed due to program verification NG after program verification. Further, a reprogram control circuit RPC for controlling the data register circuit DR as described above is provided.

Hereinafter, the EEPROM of FIG. 57 will be generally described.
The EEPROM of FIG. 57 has a byte configuration having an output of 8 bits and a configuration of 256 bytes per page. The memory cells are arranged in a matrix of m rows × 256 bytes in the memory cell array MCA. That is, m word lines are output from the row decoder RD. Further, in each byte, one NAND cell row unit RU is constituted by arranging eight NAND cells BC in which eight rows of memory cells are vertically connected in the row direction, and (m / 8) number of the row units RU. Are arranged in the column direction. In each unit RU, the drain of each 8NAND cell BC are connected to the corresponding bit line BL, and the source is connected to V _SS in common all.

In each unit, the control gates and eight select gates of eight memory cells arranged vertically are connected to a row decoder RD via eight word lines WL and SGD and SGS.

Each bit line BL'OO is connected to a data register circuit DR for latching data at the time of reading and writing. From the data register circuit DR, two types of signals, an output IO amplified according to whether the potential of the bit line BL'OO is high or low and an inverted signal NIO thereof, are output. The IO and NIO signals are input to a common IO bus line I / OBUS via a column gate transistor CGT which is turned on and off by output signals of the column decoders CDI and CDII. Signals IO and NIO are input from each common IO bus line I / OBUS to the sense amplifier circuit S / A. The output signal d ^* of the sense amplifier circuit is input to the output buffer circuit I / OBUF.

A write precharge circuit WPC for raising the bit line BL to a high potential at the time of writing and a read precharge circuit RPC for precharging the bit line BL at the time of reading are connected to each bit line BL. The write pre-charge circuit WPC, the drain and the signal BLCRL is, the signal BLCD to the gate is configured to the other end (source) bit lines are connected, a transistor TW ₁ of the n-channel type. The read precharge circuit RPC, the power supply V _DD to the one end, a transistor TR ₁ which signal PRE to the gate a bit line to the other end is connected, the bit line to one end, gate signal RST, the other end V _SS is connected to the transistor TR ₂ .

The data register circuit DR has a latch circuit composed of two inverters IV1 and IV2, and a transistor TT to which a signal BLCD is input to a gate and connected to a bit line of a memory cell. Furthermore, it has two transistors T _PV and T _EV connected to the output terminals of the two inverters IV 1 and IV 2, respectively. One end of the transistor T _PV is the signal IO is applied, the signal PROVERI is input to the gate. One end of the transistor T _EV is connected to NIO, signal ERAVERI is input to the gate. The other _ends of these transistors T _PV and T _EV are commonly connected to the gate of the transistor T ₁₄ . One end of the transistor T ₁₄ is connected to V _SS, and the other end is inputted to the collective verify control circuit BBC. In addition, it has transistors T ₁₁ and T ₁₂ . Transistor T ₁₁ is n-type, one end of which is connected to the power supply BLCRL, signal NIO is input to the gate, the other end is connected to one end of the transistor T _12. The gate of the transistor T _12, the output signal PV of reprogramming control circuit RPCC is input. Transistor T ₁₂ and the other end is connected to the bit line BL'00.

The batch verify control circuit BBC has a two-input NOR circuit NOR1 to which the signal PROVERI and the signal ERAVERI are input. The output signal of the NOR circuit NOR1 is input to the gates of the transistors TP _1, TN _1. One end of the transistor TP ₁ is to supply V _CC, the other end is connected to one terminal of the transistor TN _1. The other end of the transistor TN ₁ is connected to V _SS. The midpoint between the transistors TP ₁ and TN ₁ is connected to the transistor T ₁₄ in each data register circuit DR and to the input side of the inverter IV 3. The output signal PEOK of the inverter IV3 is output to the outside via an IO buffer circuit (not shown) as a determination signal as to whether or not it is OK at the time of verification.

The reprogram control circuit RPCC has an inverter IV _RP and a flip-flop circuit FF _RP . Signal PROVERI is input to inverter IV _RP . An output signal and an inverted signal of the inverter IV _RP are input to each of two NOR circuits in the flip-flop circuit FF _RP . The output signal PV of the flip-flop circuit FF _RP is input to the gate of n-channel transistor T ₁₂ of the data register circuit DR as the control signal.

Next, the operation of the EEPROM configured as described above will be described.
At the time of erasing, a high voltage (about 20 V) boosted by the erase boosting circuit SU6 is applied to the substrate (p-well) on which the memory cells are formed. At the same time, the word lines WL1 to WLm and the select gates SGD, SGS are controlled to “0” V under the control of the row decoder RD, and electrons are removed from the floating gate to the substrate to erase data.

Next, the read operation will be described.
The row decoder RD sets the select gates SGD, SGS of the row unit RU having the cell to be selected to “H” level for selection. Further, a target cell is selected by setting its word line WL to "0" V. After this state, applying a predetermined pulse signal as a signal PRE, by turning the transistor TR _1, precharged to "H" level of the bit line BL. At this time, when "0" data is written in the memory cell to be read, the memory cell is turned off and no current flows. Therefore, the level of the bit line BL maintains the “H” level, and the level H is latched by the data register circuit DR. On the other hand, when "1" data is written in the selected cell, the memory cell turns on. Therefore, the level of the bit line BL becomes “1” level, and the level is latched by the data register circuit DR. At this time, all data of 256 bytes connected to the selected (L level) word line is latched by the data register circuit DR connected to each bit line. Then, by changing the serial column address A _c added to the column address buffer CAB from "00" to "FF", the column gate transistors CGT in bytes 1 to 256 are sequentially turned on, the common bus line IO bus Are sequentially read through the memory.

At this time, due to the structure of the NAND cell, the ON current of the memory cell is very small, about several μA, and it takes about several μsec to charge and discharge. However, once the data is read out and taken into the data register circuit DR, the data is simply output via the common bus line I / OBUS, so that a high-speed access of about 100 nsec is possible.

Next, a write operation will be described.
FIG. 58 shows a timing chart for explaining the writing operation.

と When the program command PC is input, the mode is changed to the program mode. At this time, the signal BLCD for controlling the transmission transistor TT of the data register circuit DR becomes "L" level, and the transistor TT turns off. At the same time, the booster SU starts to operate, and the signals BLCRL and BLCU input to the write precharge circuit WPC gradually increase to about 10V. At this time, the potential of the bit line BL'OO in the memory cell array group also rises with the rise of BLCRL. At this time, the selected WL is set to a high potential of about 20 V, the gate of the select gate transistor on the source side of the NAND cell group is set to 0 V, and the other gates are set to an intermediate level of about 10 V.

In this state, the column address _Ac is sequentially changed, and write data is input to the data register circuit DR. At this time, the write data input to the data register circuit DR is latched there. When 256 bytes of write data are respectively latched by the data register circuit DR, the signal BLCU goes to "L" level and the write precharge circuit WPC is turned off. At the same time, the signal BLCD rises to about 10 V, the transistor TT turns on, and the bit line BL'OO is connected to the data register circuit DR. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" level is latched in this circuit DR, the high level of the bit line BL is maintained as it is. If the "0" level is latched in the circuit DR, the level of the precharged bit line BL is discharged to "L" level, and injection of electrons into the floating gate occurs. In this way, writing for 256 bytes is performed simultaneously.

The following describes each operation of program → program verify → reprogram with reference to a timing chart shown in FIG.

The first program operation is the same as in FIG. That is, when the program mode is entered and the program mode is entered, the control signal BLCD goes to the "L" level, the transmission transistor TT in the data register circuit DR is turned off, and the data register circuit DR is disconnected from the bit line. At the same time, the booster circuits SU1 to SU6 start operating, and the signals BLCRL and BLCU input to the write precharge circuit WPC gradually increase to about 10V. At this time, the potential of the bit line in the memory cell array MCA also rises to a high potential with the rise of the signal BLCRL. At this time, the high potential of about the WL selected 20V, the source side select gate transistor T ₂ of the gate of the NAND cell group (select line SL2) is the "0" V, the other transistor T ₁ of the gate ( The select line SL1) is set to an intermediate level of about 10V.

In this state, the column address _Ac is sequentially changed, and 8-bit write data for a certain byte n is input to the eight data register circuits DR and latched. This is repeated 256 times, and the write data of 256 bytes is latched in all the register circuits DR. Thereafter, the signal BLCU becomes “L” level, and the write precharge circuit WPC is turned off. At the same time, when the signal BLCD rises to about 10 V, the transistor TT turns on and the bit line and the data register circuit DR are connected. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" level data is latched in the data register circuit DR, the level of the bit line is maintained at a high level. If the data register circuit DR latches the “0” level, the high level of the precharged bit line is lowered by discharge to the “L” level, and electrons are transferred to the floating gate in the selected memory cell. Injection, that is, writing of “0” data occurs. Such writing is performed simultaneously for 256 bytes. The writing operation so far is the same as in the case of FIG.

Next, when the above-mentioned writing is completed, a verify command VC is input, and the program mode is released. The signal BLCD goes to “0” V, the BLCRL goes to “5” V, the signal VBIT goes to 5 V, and the bit line is discharged by the reset signal RST. At this time, in this embodiment, the latch data in the data register circuit DR is not reset. That is, the write data remains latched in the data register circuit DR. In this state, the H-level control signal PRE is applied to the read precharge circuit RPC, and the bit line is precharged. Now, consider a case where “0” data is written. Due to the latch circuit in the data register circuit DR, the signal IO is at "1" level, and the inverted signal NIO is at "0" level. In this case, at a program verify mode, the transistor T ₁₂ of the data register circuit DR is turned on, the transistor T ₁₁ is the level of that of the gate signal is turned off for "0" level, this path Is not charged to the bit line.

After such a “0” write operation, there are two cases, that is, a case where the writing becomes NG and a case where the writing becomes OK. That is, when it becomes OK, the threshold voltage of the memory cell is shifted in the positive direction, and the precharged potential is maintained as it is. Then, when the signal BLCD for controlling the transmission transistor TT goes to "1" level, the data register circuit DR and the bit line are connected, and the potential of the NIO which has been at "0" level is charged to a high potential. It is charged to the “1” level by the bit line. Therefore, the signal PROVERI through the transmission transistor TT which is inputted "0" level is input to the gate of the transistor T _14, the transistor T ₁₄ is turned off.

On the other hand, consider the case where the writing is NG. That is, despite writing "0", the threshold voltage of the memory cell exists in the negative direction, so that the potential is discharged to the "0" level while being precharged. Then, when the signal BLCD for controlling the transmission transistor TT becomes "1" level, the transistor TT is turned on, and the data register circuit DR and the bit line are connected. However, this time, the potential of NIO remains "0" level, the gate of the transistor _T 14 is "1" level signal is input, the transistor T ₁₄ is turned on.

Next, consider the case where "1" data is written.
When “1” is written, the signal IO is at “0” level and the signal NIO is at “1” level by the latch circuit in the data register circuit DR.

Doing verify operation in this state, transistor T ₁₁ of the data register circuit DR is turned on. For this reason, the bit line is kept charged through the transistors T ₁₁ and T ₁₂ during the verify operation. Read transistor TR ₂ for precharging is set as a smaller conductance gm is discharged to "0" level by the on current when the memory cell is turned on in the read. However, the conductance gm of the transistors T _11, T ₁₂ is "1" by the verify operation after the write, so as to always charge the "1" level bit line is set to a large value. That is, the gate is "0" level signal of the transistor T ₁₄ is inputted.

In addition, there may be a case where the threshold value of the memory cell is increased due to erroneous writing despite writing "1". In such a case, even if the verify operation, also gate the "0" level signal of the transistor T ₁₄ is inputted. For this reason, there is a problem that it cannot be distinguished from the above case. However, the presence or absence of such erroneous writing is determined by a test at the time of product shipment. For this reason, such erroneous writing hardly needs to be considered in practical use.

In this manner, the gate of the transistor T ₁₄ of the data register circuit DR connected to each bit line, in response to the read data by performing a verify operation "0" level or "1" level is input Is done. That is, when the bits of the program NG exists even one, the input signal to the gate of the transistor T ₁₄ is "1" level. Thus, transistor T ₁₄ is turned on, the signal PEOK becomes "1" level, indicating a verify NG.

時 に は At this time, a new program command PCII is input and reprogramming is performed. At the time of the reprogramming, unlike the first programming, the bit data of the program OK in the latch data in the data register circuit DR has been changed to "1" write data. Therefore, "0" write is performed only for the NG bit. In other words, no additional writing is performed on the bits that have been programmed as a result of the programming, and therefore no further increase in the threshold voltage occurs. In this way, reprogramming is performed several times, and when all bits become program OK, all the gate signals of the transistors become “0” level. At this time, the signal PEOK becomes the "0" level for the first time, and the program ends.

By using the method of the present invention, the verify operation can be performed collectively without sequentially changing the column address at the time of the verify. Therefore, the verification time can be shortened, which leads to a reduction in the program time. Further, when re-programming is performed at the time of verify NG, the program completion bit is not re-programmed. Thus, the distribution of the threshold voltage can be reduced, and the read margin can be improved. FIG. 60 shows a V _th distribution during a write operation when the present invention is used. When writing is performed from the erased state, even if the memory cell FMC where writing is fast is verified OK, the cell SMC where writing is slow is NG. When reprogramming is performed in this state, no additional writing is performed on the memory cells for which verification is OK. Therefore, the threshold does not rise. In other words, the distribution width of the threshold voltage at the time when the cell SMC with the slow writing becomes verify OK can be narrower than V _th DB. As a result, a sufficient read margin RM can be secured.

Although the above description has been made based on the program operation, the erase operation and the read operation as to whether or not the erase is OK can be performed collectively as in the case of the program verify. That is, erase verify is to be input a signal NIO to the transistor T _14. Therefore, the signal PEOK becomes "0" level at the time of erasure OK, and batch verification becomes possible.

FIG. 61 shows a flowchart in the erase mode. As can be seen from FIG. 61, in the erase mode, the erase operation itself is the same as the conventional one, but the verify operation can be performed collectively. Therefore, the verification time can be reduced.

57. In FIG. 57, I / O @ BUF is an output circuit, the details of which are shown, for example, in FIG.

FIG. 63 showing a conventional example shows a part of an array in which a plurality of memory cells are arranged in a matrix of m rows × 256 bytes as a memory cell array.

The bit lines are usually formed of an Al film having a thickness of several thousand angstroms, and are arranged at a pitch of several μm. Therefore, there is an interlayer capacitance between adjacent bit lines. In the figure shows the inter-layer capacitance of the bit lines BL1 and BL2 C _12, an interlayer capacitance of the bit line BL2 and bit line BL3 as C _23. Further, since the bit line is wired on the memory cell, there is also a capacitance with respect to the substrate. These are represented as C ₁ , C ₂ and C ₃ . The memory cell is connected to a bit line via a selection transistor. Therefore, capacitance also exists at the junction of the select transistor. These are represented as C _1j , C _2j and C _3j .

For example, taking a 16M NAND E ² PROM composed of 8192 × 256 bytes of memory cells as an example,
Capacitance between the bit line and the substrate C ₁ = C ₂ = C ₃ = 0.39 pF,
An interlayer capacitance C ₁₂ = C ₂₃ = 0.14 pF between bit lines,
Junction capacitance C _1j = C _2j = C _3j = 0.11 pF
It becomes.

As described above, when data is read from the memory cell, the bit line is precharged to the power supply voltage Vcc level and the precharged potential is discharged. That is, in the case of the "1" cell, the memory cell is turned on to discharge the precharged potential. In the case of the "0" cell, the precharged potential is kept as it is because the memory cell remains off. Now, consider three adjacent bit lines. It is assumed that the bit lines BL1 and BL3 are connected to "1" cells, and only the bit line BL2 is connected to "0" cells. When reading, the bit line BL2 is not discharged, and the bit lines BL1 and BL3 are discharged. At this time, since the above-described capacitance exists, the bit line BL2 is affected by the potential fluctuation. That is, if the voltage displaced by the influence is ΔV,
2C ₁₂
ΔV = 　　　　　　　　　 Vcc
C ₂ + 2C ₁₂ + C _2j

2.0.14
= 　　　　　　　　　　　　　　　　・ 5
0.39 + 2 · 0.14 + 0.11

= 1.79
It becomes.

Thus, a potential drop of about 1.8 V is caused. This applies not only to the read operation but also to the verify operation during programming. At the time of program verification, there may be memory cells to which data has not been sufficiently written, so that the operation margin is further strict.

The description is given below.
FIG. 64 shows a timing chart at the time of program verification.

と When a program command PC (not shown) is input, the mode is changed to the program mode. At this time, the signal BLCD for controlling the transmission transistor TT of the data register circuit DR becomes "L", and the transistor TT turns off. At the same time, the booster circuit SU starts operating, and the signals BLCRL and BLCU input to the write precharge circuit WPC (see FIG. 55) gradually increase to about 10V. At this time, the potential of the bit line BL in the memory cell array group also rises with the rise of BLCRL. At this time, the selected WL is set to a high potential of about 20 V, the gate of the select gate transistor on the source side of the NAND cell group is set to 0 V, and the other gates are set to an intermediate level of about 10 V.

(4) In this state, the column address AC is sequentially changed, and write data is input to the data register circuit DR. At this time, the write data input to the data register circuit DR is latched there. When 256 bytes of write data are respectively latched in the data register circuit DR, the signal BLCU becomes "L" and the write precharge circuit WPC is turned off. At the same time, the signal BLCD rises to about 10 V, the transistor TT turns on, and the bit line BL and the data register circuit DR are connected. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" is latched in this circuit DR, "H" of the bit line BL is maintained as it is. If "0" is latched in the data register circuit DR, the level of the precharged bit line becomes "L", and electrons are injected into the floating gate. In this way, writing for 256 bytes is performed simultaneously.

When the writing is completed, a verify command VC (not shown) is input, and the program mode is released. The signal BLCD becomes 5V, the BLCRL becomes 0V, the signal VBIT becomes 5V, and at the same time, the bit line BL is discharged by the reset signal RST. At this time, the write data is simultaneously reset in the data register DR.

(4) In this state, the transistor TR1 in the read precharge circuit RPC is turned on by the control signal PRE, and the bit line is precharged. Then, the data of the memory cell is read out as described above, and the write data is verified.

That is, when the bit lines are sufficiently discharged, the signals Pv and BLCD are set to the "H" level to transfer the "L" and "H" levels of the bit lines to the data latch circuit DR. Latch the reprogram data again. If the verification is NG, that is, if “1” is read out despite writing “0”, the bit line is at “L” level. Therefore, the “L” level is latched as it is. At the time of rewriting, "0" is written again. On the other hand, when the verification is OK, the bit line is at the “H” level. At this time, when the signals Pv and BLCD become "H" level, the "H" level of the bit line is transferred to the data latch circuit DR, and the latch data is inverted from "0" data to "1" data. That is, when reprogramming, the threshold voltage does not rise because "1" is written. The bit line to which "1" has been written is discharged to "L" level during verification. When the signal Pv becomes "H" level, the gate for "1" in the transistor T ₁₁ is the data register DR is latched to the "H" level. As a result, the bit line goes high again through the transistors T ₁₁ and T ₁₂ . Then, when the signal BLCD becomes “H”, the “H” level of the bit line is latched again by the data latch circuit DR. In this way, reprogramming is performed only on the NG bit of the bit line to which "0" has been written.

However, there are the following problems when performing such a program verify operation. Next, the problem will be described.

FIG. 65 is a diagram showing a combination of write data WD and verify data VD for three adjacent bit lines.

(1) shows a case where “1” is written to the bit lines BL1 and BL3 and “0” is written to the bit line BL2, and the bit written “0” is verify NG. That is, in the verify operation, the precharged potential is discharged to “L” level for all three bit lines. When the bit line is sufficiently discharged, the signal Pv goes to "H" level to set reprogram data. That is, since the bit lines BL1 BL3 are "1" write, as the description, the charge from the transistor T _11, T ₁₂ becomes "H" level. At this time, the transistors T _11, T _12, through the memory cell, the DC current paths exist toward the power supply Vcc to the Vss. Therefore, the gm of the transistors T ₁₁ and T ₁₂ is set to be sufficiently large with respect to the gm of the memory cell so that the “H” level is sufficiently ensured.

Since the bit line BL2 is "0" write NG, the bit line BL2 is also discharged to the "L" level, and the bit line BL2 remains at the "L" level even when the signal CON goes to the "H" level. At this time, the problem is that the potential of the bit line is recharged from "L" level to "H" level when reprogramming data is set in the bit line to which "1" is written. That is, as described above, the level of the bit line BL2 also rises due to the coupling effect between the adjacent bit lines (Tup). For example, considering the drop of the threshold due to the transistor T _11, when the power supply voltage Vcc is 5V, from 0V up to 4V, lifted. At this time, the level of the bit line BL2 is
ΔV = 0.358 × 4 = 1.4V
Only change.

(4) The distribution of the potential level after the predetermined verification also varies due to the variation in the threshold distribution of the memory cell to which "0" is written. This is shown in FIG. The level after the verification may be completely discharged to “0” V, or may be discharged only to about 1 V. At this time, under the influence of the above-mentioned coupling, the potential fluctuates to 2.4 V and exceeds the sense level. That is, a memory cell that is to be "0" write NG is erroneously detected as "0" write OK, and the operation margin of the memory cell is reduced. In the example of the combination of (2) to (8) shown in FIG. 65, there is no combination that malfunctions due to coupling.

A method for solving the above problem will be described below.
The operation of writing data to the memory cells after the program command is input is the same as the operation described with reference to FIG. The difference is the operation at the time of program verification. In the program verify mode, the bit line is precharged by the signal PRE. When the precharging of the bit line is completed, a verify read operation is performed. At this time, the signal Pv is also at the "H" level. Thus, for the "1" write to that bit line, the transistor T _11, T ₁₂ is for turning on, will be charged. Therefore, the "H" level is maintained without being discharged to the "L" level. After a predetermined time, the signal BLCD is set to the “H” level, whereby the potential level of the bit line is transferred to the data latch circuit DR, detected and latched. That is, the bit line to which "1" is written is always at "H" level, and the bit line to which "0" is written and verify OK is also at "H" level. Also, the verify NG bit line is discharged. By doing so, the bit line of "1" write is not discharged as described above. Therefore, when the rewrite data is set, the potential change from the “L” level to the “H” level as described above does not occur.

Therefore, data can be detected without being affected by coupling. For this reason, there is no erroneous data detection. This is shown in FIG. It can be seen that the combination of (1) in FIG. 68 is improved compared to the case of (1) described in FIG. This is shown in FIG. 69 in comparison with FIG. As described above, at the time of rewriting setting, lifting due to the influence of bit line coupling is eliminated, so that data can be read correctly.

FIG. 70 shows another example of the rewrite setting transistors T ₁₁ and T ₁₂ . (A) is an example used in the above description, and (b) is another example. As the transistor T _11, by using a transistor having a threshold voltage near 0V, the "H" level of the bit line at the time of verification can be set close to Vcc. The gate of the transistor T _12, by inputting the boosted potential, further effect increases.
That is, the amount of potential drop (threshold drop) with respect to the power supply voltage Vcc is reduced, thereby providing a larger margin for the read operation.

FIGS. 71 to 77 are general circuit diagrams used for implementing the above method, and thus description thereof is omitted.

(4) By performing the verify operation in this manner, the influence of bit line coupling can be ignored.

Although not particularly mentioned in the above description, at the time of program verification, the gate of the memory cell is raised by about 0.5 V in order to obtain a margin for the "0" cell.

As described above, with respect to the "1" write to that cell, when the verify operation, always transistors T _11, T ₁₂ is turned on, the current through the memory cell, so that is flowing .

(4) The sources of the memory cells are commonly connected outside the memory cell array. A high voltage of about 20 V is applied at the time of erasing, and connected to a Vwell circuit for setting to the GND level at the time of programming and reading. That is, the wiring resistance of the source line exists. It is assumed that a current of about 10 μA flows per cell during verification. When "1" is written for about one page, a current always flows for memory cells of 256 bytes. That is, 256 × 8 × 10 μ = 20 mA.

Assuming that a resistance of about 20Ω is present in the source line, the voltage of the source line rises by 0.4V. On the other hand, when "0" is written for most of one page, almost no current always flows. Therefore, the potential of the source hardly rises and becomes the GND level. That is, there is a problem that the source potential at the time of program verification changes due to the write pattern.

リ ー ド Also, at the time of reading, since there is no path for a current that always flows, the level of the source is almost the GND level. Therefore, the distribution of the memory cells differs depending on the write pattern, and the operation margin of the memory cells differs. Also, when writing a "1" pattern for most of the cells for one page, the source potential at the time of program verification is different from that at the time of reading. Therefore, even if the verification is OK, it will be NG if actually read.

FIG. 78 shows the configuration of a chip. At the time of program verification, the ground of the circuit that raises the gate of the memory cell by about 0.5 V is connected to the Vss line of the peripheral circuit. The source line of the memory cell is connected to the Vwell circuit. Therefore, even if the source line of the memory cell floats due to the write pattern, the source of the verify level setting circuit does not float, resulting in a difference in the potential of the source line. Therefore, it is assumed that the verify level is set to 1.0 V in anticipation of floating of the source. Assuming that the threshold distribution of the written memory cells is 2.5 V, when "0" is written in almost all cells of one page, the upper limit of the written memory cells is (1 V + 2.5 V =) 3.5 V. . On the other hand, when almost "1" is written, the potential of the source also increases by about 0.5 V, so that the gate of the memory cell is equivalent to 0.5 V, and the upper limit is 0.5 V + 2.5 V. The threshold value is 3.0V. This difference results in a difference in AC characteristics and a difference in reliability.

As shown in FIG. 79 to solve this problem, the source of the verify level setting circuit via a transistor T _A, is commonly connected to the source of the memory cell. _A signal "PROVERI" which becomes "H" level during program verify is applied to the gate of the transistor TA. With this configuration, at the time of program verification, the source of the verify level setting circuit is common to the source of the memory cell, and therefore, a change in the source potential of the memory cell can be directly reflected.

Therefore, if the source floats by 0.5 V, the output potential also becomes higher than the set value by 0.5 V, so that a constant voltage is always applied between the source and the gate of the memory cell. That is, no matter what pattern is written, the same distribution can be obtained, and higher reliability can be obtained.

FIG. 80 shows a verify level setting circuit, and FIG. 81 shows a Vwell circuit.
Next, a description will be given of a modification of the eleventh embodiment in which the same effect as that of the eleventh embodiment (FIG. 55) can be obtained with another circuit configuration. In FIG. 82 showing this modification, circuits equivalent to those in the eleventh embodiment (FIG. 55) are denoted by the same reference numerals. FIG. 82 shows a memory cell array for one column and its peripheral circuits.

In this modification, unlike the eleventh embodiment, the data latch circuit DR has two data latch circuits DR1 and DR2. The first data latch circuit DR1 has two inverters connected directly in anti-parallel between IO and NIO. Second data latch circuit DR2, via a transistor T _31, T _32, with two inverters connected between the IO and NIO. The transistors T ₃₁ and T ₃₂ are controlled by the signal SDIC. Further, output signals of the first and second data latch circuits DR1 and DR2 are applied to an exclusive NOR circuit XNOR. That is, only when the logic levels of the two input signals match, the signal becomes “H” level. The output of the exclusive NOR circuit XNOR is applied to IO via the transistor T ₂₁ which is controlled by a signal VREAD. Inverted signal of the output of this circuit XNOR through the transistor T ₂₂ which is controlled by a signal VREAD, applied to NIO. In FIG. 82, the transistors T ₁₁ and T ₁₂ in FIG. 55 are omitted because they are unnecessary.

読 み 出 し The read operation and the erase operation of the device of FIG. 82 are the same as those of the eleventh embodiment, and a description thereof will be omitted.

Hereinafter, the write operation will be described.
The program operation is the same as described above. A program command PC is input to enter the program mode. From the outside, a column address and a page address indicating a page are input. At this time, the signal BLCD becomes “L”, and the transistor TT turns off. At the same time, the booster circuit SU starts to operate, and the signals BLCRL and BLCU input to the write precharge circuit WPC gradually increase to about 10V. At this time, the potential of the bit line BL in the memory cell array group also rises with the rise of BLCRL. At this time, the selected WL is set to a high potential of about 20 V, the gate of the select gate transistor on the source side of the NAND cell group is set to 0 V, and the other gates are set to an intermediate level of about 10 V.

In this state, the column address AC is sequentially changed, and write data is input to the data register circuit DR. At this time, the write data input to the data register circuit DR is latched by the first data latch circuit DR1. After the 256 bytes of write data are respectively latched in the first data circuit DR1, the signal BLCU becomes "L" and the write precharge circuit WPC is turned off. Further, the signal SDIC changes to "H" transistors T _31, T ₃₂ are turned on, writing data to the second data latch circuit DR2 is latched. Subsequently, the transistors T _31, T ₃₂ becomes signal SDIC is "L" is turned off. The signal SDIC may be set to the “H” level simultaneously with the input of the write data, and the first and second data latch circuits may simultaneously perform the latch operation. At this time, VREAD transistors T _21, T ₂₂ because it is "L" is OFF. At the same time, the signal BLCD rises to about 10 V, the transistor TT turns on, and the bit line BL and the data register circuit DR are connected.

(4) At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" is latched in the first data latch circuit DR1, "H" of the bit line BL is maintained as it is. If "0" is latched in the first data latch circuit DR1, the level of the precharged bit line becomes "L", and electrons are injected into the floating gate. In this way, writing for 256 bytes is performed simultaneously.

Subsequently, as described above, the verify command CF is input after the program operation is completed. As a result, the signal BLCD becomes 0 V, the BLCRL becomes 5 V, the signal VBIT becomes 5 V, and the bit line is discharged by the reset signal RST. At this time, the write data remains latched in the second latch circuit DR2 in the data register circuit DR. In this state, the control signal RPC of “H” is applied to the read precharge circuit RPC, and the bit line is precharged.

Subsequently, the signal BLCD becomes 5V, and accordingly, the read data is latched by the first latch circuit. At this time, comparison is performed with the data latched by the second latch circuit DR2. Subsequently, the signal BLCD becomes 0 V, and the data latch circuit is disconnected from the memory cell. Then, next signal VREAD is 5V, the transistors T _21, T ₂₂ is turned on, comparator result is latched by the first latch circuit DR1. At this level, an error determination is made even under the condition that the write data is “1” and the verify data is “0”, which is surrounded by a broken line in FIG. That is, the verify NG signal is output even under the condition that the write data is “1” and the verify data is “0”, which is ignored in the eleventh embodiment.

The verify read operation is the same as in the eleventh embodiment. That is, when a verify read command CF is input after a lapse of a predetermined time from the program operation, a verify output mode is entered. Then, by sequentially changing / RE from “H” → “L” → “H” → “L”, the column address AC is incremented one after another, and the contents of the latch data are sequentially stored in 256 bytes (256 times). )Output. In the circuit configuration of FIG. 82, the result of comparison described in FIG. 83 is output. That is, "1" data is output in parallel with the verify NG bit, and "0" data is output in parallel with the other bits.

In the above, the method of performing program, verify, and reprogram by inputting a command has been described. However, by inputting a program command, a verify operation and a reprogram operation are performed by an internal auto operation, and PASS and FAIL determinations are performed. And this makes it even easier to use.

FIG. 85 shows a basic conceptual block diagram of FIGS. 84 and 85.
The program auto command is decoded by the command register circuit CR. Based on the output of the circuit CR, the logic circuit LOG1 outputs a pulse signal AUTOPules. The signal AUTOPules is input to the flip-flop FF1, and is latched when the program mode signal PRO is at the “H” level.

(4) Next, the program is started when the signal of PRO becomes "H" level. After a predetermined program time, the flip-flop FF1 and the command register circuit CR are reset by the program end signal PROE from the logic circuit 2. The program end signal PROE is input not only to the flip-flop FF1 but also to the flip-flop FF11, and the verify mode is set. The predetermined verify time is counted by the binary counter BC11.

At this time, the verify operation as described above is performed, and it is determined whether or not the verify is OK. If the result is NG, the count value of the counter PNC for counting the number of times of programming is incremented by one and reprogramming is performed. If OK, pass.

に す る By doing so, it becomes possible to judge PASS or FAIL only by inputting an auto program command, and it becomes easy to use.

Although the above description has been made based on the program operation, the erase operation can be considered in exactly the same way.

Next, a combination of the verify read and the auto program will be described.
If the verify remains NG after performing the reprogramming a predetermined number of times, the page (256 bytes) is treated as an error. Here, it is possible to externally identify how many bits of cells are verified NG. Here, this is called a verify read mode. Hereinafter, the operation of the program-> verify read will be described with reference to the time chart of FIG.

The program operation is the same as that described above. When the program command PC is input, the mode is changed to the program mode. A column address and a page address indicating a page are input from the outside. At this time, the signal BLCD for controlling the transmission transistor TT of the data register circuit DR becomes “L”, and the transistor TT turns off (see FIG. 55). At the same time, the booster circuit SU starts to operate, and the signals BLCRL and BLCU input to the write precharge circuit WPC gradually increase to about 10V. At this time, the potential of the bit line BL in the memory cell array group also rises with the rise of the potential of BLCRL. At this time, the selected WL is set to a high potential of about 20 V, the gate of the select gate transistor on the source side of the NAND cell group is set to 0 V, and the other gates are set to an intermediate level of about 10 V.

(4) In this state, the column address AC is sequentially changed, and write data is input to the data register circuit DR. In the figure, / WE functions as a latch signal for input data. At this time, the write data input to the data register circuit DR is latched there. When 256 bytes of write data are respectively latched in the data register circuit DR, the signal BLCU becomes "L" and the write precharge circuit WPC is turned off. At the same time, the signal BLCD rises to about 10 V, the transistor TT turns on, and the bit line BL and the data register circuit DR are connected. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" is latched in this circuit DR, "H" of the bit line BL is maintained as it is. If "0" is latched in the data register circuit DR, the level of the precharged bit line becomes "L", and electrons are injected into the floating gate. In this way, writing for 256 bytes is performed simultaneously.

(4) After a lapse of a predetermined time, when a verify read command CF is input instead of the batch verify command VC, a verify output mode is entered. The column address AC is incremented one after another, and the contents of the latch data are sequentially output for 256 bytes (256 times). “1” is output in parallel with the verify NG bit, and “0” is output in parallel with the other bits.

(4) With the configuration using the batch verification circuit, it is possible to output whether or not verification is NG to the outside of the chip. Here, the output data is not a data actually written in the cell as in the related art, but a verify NG signal indicating whether rewriting should be performed. Therefore, the number of cells having a write error can be counted without having to provide an external comparator circuit or the like. The total of cells to which "0" is output in the verify read is the total of verify NG in "1" page. Also, of course, it is possible to specify at which address the verify NG was found.

Next, an embodiment in which verification NG count and ECC (error correction circuit) are combined will be described.
In general, a method of compensating for an error cell by adding a redundant cell has been used to improve the reliability of stored data. For example, 64 bits of redundant bits are provided for a page of 256 bytes (2K bits). By performing Hamming coding using the Hamming distance as redundant bit data, data errors of up to 6 bits can be corrected. More generally, adding N redundant bits to an M-bit data string gives
_T
Σ _{N + M} C _i +1 ≤ 2 ^{N
i = 1}
T bit errors that satisfy

FIG. 87 shows a flowchart of an embodiment having an ECC circuit.
When a write operation is started and a program is started, data for one page (256 bytes) is written. Further, redundant data is written to a 64-bit redundant cell of the error correction circuit. Subsequently, the verify operation is started. If the verify operation is OK, the write operation is completed without any abnormality, and the write operation is completed. If the verification is NG, the counter is compared with a counter indicating the number of times of reprogramming, and if this is the third or less times, reprogramming is performed. When the number of times of reprogramming exceeds the set number of times (in this case, three times), the verify read is performed. Here, as described above, the number of NG bits for one page is counted. Subsequently, a comparison is made as to whether the count result can be corrected with a predetermined number of redundant bits (in this case, 64 bits), and if this can be done, the writing is OK and the writing operation ends. If the number of NG bits is too large to save even the redundant bits, a write error occurs.

(4) In this case, even if a write NG bit occurs, a write error does not occur within a range that can be remedied by ECC. Therefore, when the storage device is configured in this manner, the number of write errors as seen from the outside is significantly reduced as compared with the conventional case. In particular, the effect is remarkable in the EEPROM having the aging deterioration.

(4) When an ECC circuit is added in the above-described configuration, a write error may not occur even though there is an NG bit. However, while determining whether the NG bit is within the range that can be rescued by ECC, it is possible to know how close the ECC is to the rescue limit. For example, a warning may be issued when 80% of the ECC rescue limit becomes NG bits. In particular, in the case of an EEPROM that has deteriorated over time, it serves as a means for determining the life of a chip.

(4) As described in the embodiment shown in FIGS. 55 and 6, the verify operation can be performed collectively. Therefore, the writing time including the verification is not so long.

Although the embodiment in which the ECC is added has been described above, this may be configured as a single chip or as a storage system including a plurality of EEPROM chips. The effect remains the same. Although the Hamming method is used as a method for generating a redundant code, the present invention is not limited to this, and various coding methods such as a Reed-Solomon coding method, an HV coding method, a fire coding method, and a cyclic coding method are used. Method may be used.

The above description has been made on the method of performing the address control by the external input. Hereinafter, an example in which the address pin and the data input pin are used in common will be described.

FIG. 88 shows an example. Here, ALE, NWP, CE, NWE, and RE are external control signals. These signals are input from the corresponding input pins, respectively, and the operation mode of the chip is determined. Further, a signal indicating whether the chip is accessible or not is output from the control circuit to the outside via the Ready / Busy pin. The external signal CLE determines the command input mode. The external control signal ALE determines an address input mode. The external control signal CE is a chip select signal. The external control signal NWE functions as a clock signal for taking in respective input data in the command input mode, the address input mode, and the data input. The external control signal RE is a clock signal having an address increment and an output buffer enable function when reading a continuous address from an address input at the time of data reading.

FIG. 88 is a timing chart showing the external control mode when writing is performed. Here, first, in the command input mode, a serial data input command 80H is input. As a result, the chip enters the address input mode to input the program start address. In the address input mode, a column address and a page address are fetched into an address buffer by a three-step clock of the external control signal NWE, and each internal address signal is determined to have a predetermined logic level corresponding to input address data. At this time, the Ready / Busy output terminal is configured to hold the Ready signal. When the address input operation is completed, the signal SDIC changes from “L” to “H” level. Therefore, the write data and its inverted data are transferred to the common bus line IOi / IOiB from the I / O input terminal. Next, while the external control signal NWE is at the “L” level, the column decoder output signal CSLn corresponding to the input column address is at the “H” level. In this way, data is transferred into the data register.

As a result, the contents of the data registers from address 0 to address N-1 are data "1" at the time of initialization. Data input from the I / O input / output terminal is latched in data registers from address N to address N + j.

(4) After the data input mode, when the auto program command 10H is input in the command input mode, the chip performs writing to the memory cells.

Thereafter, the above-described operation (program → verify → reprogram) is automatically performed.

Bu During the write operation, the Busy signal is output from the Ready / Busy output terminal. It is set so that a READY signal is automatically output after a predetermined writing time has elapsed. It is possible to detect whether the write mode has been completed normally by inputting a flag read command of 70H in the command input mode and reading the result of the verification (signal PEOK) from the I / O input / output terminal.

FIG. 89 shows an input waveform of an external control signal and a data input timing when writing is performed in the above-described semiconductor memory without using an autocommand. In the command input mode, a serial data input command 80H is input. Thus, the chip enters the address input mode to input the program start address. In the address input mode, the column data output signal corresponding to the column address, which is input while the external control signal WE is at the "L" level, is at the "H" level, as in the read mode described above. As a result, the latch contents of the data register are written to the write data latch on the common bus line. Thus, the write data is sequentially latched. When the latch is completed, the program command “40H” is input, and the mode shifts to the program mode.

Next, when a verify command is input, a word line corresponding to an internal address signal in an address buffer circuit corresponding to a row address is selected. Further, after a predetermined delay time, one page of memory cell data in which the control gate is connected to the selected word line is read out via the bit line and latched in the data register. Next, the content PE of the data register is changed from “H” → “L” → “H”, the column address is incremented, and the data is sequentially called out of the chip. The read data is compared with external storage write data by a chip. As a result, it is possible to determine at which address and how many bits have an error.

FIG. 90 shows input waveforms of external control signals and data input timings when the write and verify operations are performed. First, in the command input mode, a serial data input command 80H is input. Thus, the chip enters the address input mode to input the program start address. In the address input mode, a column address and a page address are fetched into each address buffer circuit by a three-step clock of the external control signal WE, and each internal address signal corresponds to input address data, as in the above-described read mode. Is set to the predetermined logic level. Thereafter, the column data output data corresponding to the column address, which is input while the external control signal WE is at the "L" level, is at the "H" level. As a result, the contents of the latch of the data register are written to the write data on the common bus line. Thus, the write data is sequentially latched. When this latch is completed, the program command “40H” is input, and the mode shifts to the program mode. At the time of this data writing, writing is performed until the next verify read command is input.

Next, when a verify command (batch verification) is input, the batch verification is performed as described above. Next, in this state, the RE is changed from “H” to “L” to “H” in the same manner as described above, the column address is incremented, and the data is sequentially read out of the chip.

In this case, “0” data is output from a bit that has been written NG, and “1” data is output from a bit that has been written OK. For this reason, the number of defective bits can be determined, although it is pseudo. FIG. 91 shows another example of the system shown in FIG. Here, an example is shown in which the RE is moved after the verify read command is input, the flag read command “70H” is input without incrementing the column address, and whether or not the program is OK is output. Even if the system is configured in this way, the judgment of Fail / Pass is possible.

As is well known, data is written into a NOR type memory cell by injecting hot electrons into a floating gate. Therefore, at the time of writing, a writing current of about 1 to 2 mA is consumed per one memory cell. Therefore, although it is possible in NAND E ² type, can not be performed is the page write such 256 bytes in NOR type. However, the NOR type is used because it has advantages such as a high reading speed.

NOR type, thus E ^2, it is possible to rewrite the data on the on-board. First, an address is specified, write data is input, writing is performed on a memory cell, and then data at the written address is read, data is compared, and it is determined whether or not writing has been performed.

(4) When such an operation is performed on the board, the CPU generates signals necessary for data write and data verify operations. Therefore, there is a problem that the CPU is exclusively used during this time.

Therefore, it is common to open the CPU by automating the write and verify operations inside the chip.

At this time, there is an example in which a circuit for latching write data, a circuit for latching read data, and a circuit for comparing the data are also provided (Japanese Patent Application No. 3-125399). In this example, there is a problem that the pattern area becomes relatively large and the chip size becomes large.

In the embodiment described below, a relatively small pattern area can be used not only for writing but also for erasing.

{That is, the embodiments described so far are directed to a memory cell having a NAND structure as an example. Hereinafter, a batch verification method using a two-layer NOR type cell will be described. That is, FIGS. 92 to 94 show an example of a memory cell (EEPROM) having a two-layer structure.

92 is a pattern plan view, FIG. 93 is a sectional view taken along line BB 'of FIG. 92, and FIG. 94 is a sectional view taken along line CC' of FIG. In these figures, reference numeral 211 denotes a floating gate (FG) made of first-layer polycrystalline silicon. Reference numeral 212 denotes a control gate (CG) made of second-layer polycrystalline silicon. This control gate 212 is used as a word line of a memory cell.

213 is a P-type substrate. Reference numerals 214 and 215 denote a source (S) and a drain (D) composed of an N ⁺ type diffusion layer formed on the substrate 214. 216 is a contact hole. Reference numeral 217 denotes an aluminum layer (bit line BL) connected to the drain 216 via the contact hole 217. Further, reference numeral 218 denotes a gate insulating film for the floating gate transistor, and has a thickness of 100 angstroms. Reference numeral 219 denotes an insulating film provided between the floating gate 211 and the control gate 12, and is formed of, for example, a three-layer film having an O-N-O structure (Oxide-Nitride-Oxide), and has a thickness of It is about 200 Å in terms of an oxide film. 220 is a field insulating film, and 221 is an interlayer insulating film.

Next, the operation principle will be described.
At the time of erasing, an erasing voltage of 12 V is applied to the source 214, the drain 215 is set in a floating state, and the control gate 213 is set to 0V. Thus, a high voltage is applied between the floating gate 211 and the source 214 via the thin gate insulating film 18. As a result, electrons in the floating gate 211 are emitted to the source 214 due to the Fowler-Nordheim tunnel effect, and erasing is performed.

At the time of writing, approximately 6 V is applied to the drain 215, 0 V is applied to the source 214, and 12 V is applied to the control gate 213. Thereby, impact ionization occurs near the drain, electrons are injected into the floating gate 11, and writing is performed.

At the time of reading, 1 V is applied to the drain 215, 0 V is applied to the source 214, and 5 V is applied to the control gate 213. At this time, it is turned off / on depending on whether or not electrons are present in the floating gate 211, and indicates data "0" or "1", respectively.

半導体 A semiconductor integrated circuit using such a memory cell, for example, a flash EEPROM of a 4-bit configuration is configured as shown in FIG.

In FIG. 95, A _{0 to} A _i are row address input signals, which are amplified and shaped by the row address buffer circuit 1 and then input to the row decoder circuit 2. B _{i + 1 to} B _j are column address input signals, which are amplified and shaped by the column address buffer circuit 3 and then input to the column decoder circuit 4. The row decoder circuit 2 selects only one of the plurality of word lines WL. The column decoder circuit 4 selectively turns on one gate 6A in each column selection gate circuit 6, and selects only one bit line BL for each I / O, that is, four bit lines for convenience. As a result, four memory cells MC are selected from the memory cell array 5, one for each I / O. Information of each selected memory cell MC is detected and amplified by the sense amplifier circuit 7, respectively. The output of each sense amplifier circuit 7 is read out of the chip via each output buffer circuit 8. That is, four pieces of information are simultaneously output to the outside.

In FIG. 95, the memory cell array 5 includes four memory cell array units (MCAU) 5A. Each unit 5A has four word lines WL, four bit lines BL, sixteen memory cells MC, and four reference memory cells RMC for simplicity of description. Corresponding to the four bit lines BL, four gates 6A in the column selection gate circuit 6 are also provided. One of these gates 6A is turned on by the column decoder circuit 4. The reference memory cell RMC is connected to the sense amplifier circuit (SA) 7 by a reference bit line RBL having a reference gate RBT on the way.

(4) Writing of 4-bit data to the EEPROM having such a configuration is performed as follows. That is, four data are read from four input / output pads (not shown) for each I / O. The writing circuit 10 sets the potential of the bit line BL according to the read data. That is, the write circuit 10 supplies a high potential when the write data is “0” and a low potential when the write data is “1” to the bit line BL selected by the input address signal. At this time, a high potential is also output to the word line WL selected by the input address signal.

That is, when writing “0” data, the selected word line WL and the bit line BL to which data is to be written have a high potential. Thus, hot electrons generated near the drain D of the memory cell MC are injected into the floating gate FG of the memory cell MC. As a result, the threshold voltage of the memory cell MC is shifted in the positive direction, and “0” data is stored.

(4) On the other hand, when writing "1" data, the bit line BL becomes low potential. Thus, no electrons are injected into the floating gate FG, and the threshold voltage of the memory cell MC does not shift. As a result, "1" data is stored.

On the other hand, when erasing data, the source of the memory cell is set to a high voltage. Thus, the electrons injected into the floating gate FG are emitted by FN (Fowler-Nordheim) tunnel effect.

FIG. 96 specifically shows a part of FIG. 95. In these figures, the same reference numerals indicate the same circuits. FIG. 96 specifically shows the sense amplifier circuit (SA) 7 and the comparator circuit 9 in particular. Further, a circuit INCIR for inputting one signal to be compared to the comparator circuit 9 and a batch verify circuit VECIR for receiving an output of the comparator circuit 9 are shown.

As described above, MC is a memory cell formed of a floating gate MOS transistor, RMC is a reference memory cell (dummy cell) formed of a floating gate MOS transistor, BL is a bit line, RBL is a reference bit line, and RBT is a column. This is a dummy bit line selection transistor equivalent to one of the selection gate transistors 6A. The transistor RBT has a gate supplied with the V _CC potential and is inserted into the reference bit line RBL. BAS is a bus line to which a plurality of column select gate transistors 6A, 6A,... Are connected in parallel, LD1 is a first load circuit (bias circuit) connected to the bus line BAS, and LD2 is a reference bit. This is a second load circuit (bias circuit) connected to the line RBL. The potential Vin of the bit line BL 'on the output side of the first load circuit LD1 and the potential (reference potential) Vref of the reference bit line RBL' on the output side of the second load circuit LD2 are determined by the data detection circuit 28 (for example, CMOS current mirror).

In the sense amplifier circuit (SA) 7, a P-channel transistor P4 for activation control is connected between the V _CC power supply and the data detection circuit unit. The inverted signal / CE * 1 is applied to the gate of the transistor P4. When the transistor P4 is off, the data detection circuit unit 28 is in a non-operating state, and current consumption is reduced. An N-channel transistor N7 whose gate is supplied with an inverted signal / CE * 1 is connected between the output terminal DSO of the data detection circuit unit 28 and the ground terminal.

In the sense amplifier circuit 7, the reference potential Vref of the reference bit line RBL generated based on the data of the reference memory cell RMC and the potential Vin of the bit line BL generated based on the data read from the selected memory cell And are compared. Based on the comparison result, data stored in the memory cell is detected and output to the output buffer circuit 8 via three inverters.

The output of the sense amplifier circuit 7 is also input to one input terminal of the comparator circuit 9. A signal (write data) applied to I / O pad is applied to the other input terminal of the comparator circuit 9. In the comparator circuit 9, these two input signals are compared, and the result (VR0) is added to the batch verify circuit VECIR. The outputs VR1, VR2, and VR3 from the comparator circuit 9 for the other three bits are also added to the batch verify circuit VECIR. The batch verify circuit VECIR permits the output from the output circuit Dout only when all of these outputs VR0, VR1, VR2, VR3 indicate that writing is OK. In other cases, that is, when any one of the outputs VR0 to VR3 indicates a write NG, the output from the output circuit Dout is blocked.

FIGS. 97 and 98 show the output VR0 from the comparator circuit 9 at the time of program verification and at the time of erase verification, respectively. FIG. 97A shows the case of “1” write. In the case of the program OK, the sense amplifier output DS0 becomes “1”. As a result, the comparison output VR0 also indicates "1", that is, the program OK. FIG. 97B shows the case of “0” write. In the case of “0” write NG, the sense amplifier output DS0 indicates “1”. Therefore, the output VR0 of the comparator circuit is "0", that is, indicates the program NG. FIG. 97 (c) shows the case of "0" write. In the case of “0” write OK, the sense amplifier output DS0 indicates “0”. Therefore, the output VR0 of the comparator circuit is "H", that is, it indicates that the program is OK. When all of the comparator circuit outputs VR0 to VR3 indicate “H (program OK)”, the collective verify circuit output PVFY indicates “H”. As can be seen from FIG. 98, in the case of erase OK / NG, the sense amplifier output DS0 indicates “1 / O”. In response, the comparator circuit output VR0 indicates "1 / O". When all of the comparator circuit outputs VR0 to VR3 indicate erasure OK, the batch verify circuit output EVFY becomes "1". When at least one of the comparator circuit outputs VR0 to VR3 indicates the erase NG, the output EVFY becomes “0”.

Next, FIG. 99 shows still another embodiment. In this embodiment, a collective verify circuit is incorporated in the memory cell shown in FIG. 6 of Japanese Patent Application Laid-Open No. 3-250495. In FIG. 99, the same circuits as those in FIG. 96 are denoted by the same reference numerals.

Table 6 shows the voltages applied to the respective parts during erasing, writing, and reading in the apparatus shown in FIG.

Table 6
　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
I / O pad BSL BL WL Vss
Erase-0 V Flow 20 V 0 V
(Electron injection)
Light
"0" write (without removing electrons) 0 V 22 V 0 V 0 V Floating
"1" light (without electron) 5 V 22 V 20 V 0 V Floating
Unselected cell − 22 V 0 V / 20 V 10 V Floating lead − 5 V 1 V 5 V 0 V
　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　
The operations of the program verify and the erase verify in the device in FIG. 99 are the same as the operations in FIG. 90 described above, and thus the description will be omitted.

Next, an example of a storage system using a nonvolatile semiconductor storage device having the above-described batch verification function will be described.

Typically, storage systems are organized hierarchically to maximize capacity at minimum cost. A cache system as one of them utilizes the locality of memory access. A computer using an ordinary cache system includes a high-speed and small-capacity SRAM and a low-speed and large-capacity DRAM in addition to a CPU. In such a cache system, a part of the main memory constituted by a DRAM or the like having a long access time is replaced by an SRAM or the like having a short access time, thereby shortening the effective access time. That is, when accessing from the CPU or the like, if there is data in the SRAM (that is, when the cache hits), the data is read from the SRAM which can operate at a high speed. Reads data from storage. If the cache capacity and the replacement method are appropriate, the hit rate exceeds 95%, and the average access is greatly accelerated.

(4) In the NAND type EEPROM and the like as described above, writing and erasing can be performed in page units (for example, 2K bits). The processing on a page basis makes writing and erasing extremely fast. However, in such an apparatus, since a random access is sacrificed, a cache memory including a RAM such as an SRAM or a DRAM is essential. When the cache system is applied to a nonvolatile storage device such as a NAND type EEPROM, the number of times of writing is reduced, and as a result, the life of the chip is extended.

(1) A first embodiment of a memory system using a nonvolatile semiconductor memory device will be described. FIG. 100 shows the circuit configuration. This system has a ROM 121 and a control circuit 122. The ROM 121 has a batch verify function. The control circuit 122 controls writing to the ROM 121 and has at least an internal write data register. The write control circuit 122 outputs page data to be written next in response to the batch verify signal output from the ROM 121. This control circuit may be configured by using a CPU, or may be configured by a plurality of chips including a gate array and an SRAM.

(4) In the NAND type EEPROM as described above, the batch erase block usually covers several pages. Therefore, when a system such as a cache memory is configured, writing is performed for each batch erase block. For example, in the above-mentioned NAND type EEPROM having 8 NAND type memory cells, one batch erase block is composed of 2K bits (1 page) × 8 = 16K bits (8 pages), and writing is also performed in units of this block. . Therefore, the writing operation always involves writing of eight pages.

In the circuit shown in FIG. 100, the write operation of the next page is performed using the batch verify signal VFY output from the ROM 121. That is, after latching the data of the first page, writing and verifying are repeated inside the ROM. When writing of all data for one page is completed, a batch verify signal VFY for the first page is output. The control circuit 122 detects the batch verify signal VFY, and latches the data of the second page in the ROM 121. Subsequently, writing and verifying for the second page are repeated in the ROM, and when writing of all data for one page is completed, a batch verify signal VFY for the second page is output. The third and subsequent pages are written in the same manner as described above.

For example, in a NAND type EEPROM having 8 NAND type memory cells as described above, in one write operation, the control circuit 122 performs data transfer for 8 pages, and transmits a batch verify signal in the previous page for the second and subsequent pages. After the detection, the page data is transferred.

As described above, according to the present embodiment, the transfer of the write page data from the control circuit 122 to the ROM 121 can be performed based on the batch verify signal. Conventionally, a comparison circuit and a large-capacity register for verify reading are provided outside, but this is not necessary in the present embodiment. Thereby, the configuration of the control circuit 122 becomes very simple.

The above embodiment shows a configuration in which the control circuit 122 has one ROM 121. On the other hand, a memory system having a plurality of ROMs that output a batch verify signal can be configured. FIG. 101 shows this example. This system has a batch verify function as described above. This system has ROMs 101 to 103, a RAM 104, and a control circuit 105. The ROMs 101 to 103 output a collective verify signal when the writing is completed. The RAM 104 is used as a cache memory for access from a CPU (not shown). The control circuit 105 controls data transfer between the RAM 104 and the ROMs 101 to 103. Data transfer between the RAM 104 and the ROMs 101 to 103 is performed via the data bus 106. The ROMs 101 to 103 constitute a main memory, and have a much larger capacity than the RAM 104 used as a cache memory. Although a general 4-way mapping method is desirable, various existing mapping modes such as direct mapping and full associative are possible. The block in the cache memory has the same capacity as the block erase block.

Next, the case where the batch erase block is 16K and the mapping method is 4-way will be described. At this time, the SRAM is 64K bits and has four 16K blocks. These blocks temporarily hold the copy data of the batch erase block in the ROM. For example, suppose that data in the second, third, fourth, and fifth batch erase blocks in the ROM are being accessed. At this time, copy data of these data is temporarily held in four blocks in the SRAM.

(4) It is assumed that a CPU (not shown) performs a write and erase operation on, for example, a third batch erase block. At this time, since a copy of the data already exists (hits) in the SRAM, the data is exchanged only through the high-speed SRAM without accessing the ROM directly.

{Suppose that reading is performed from a CPU (not shown) to, for example, the sixth batch erase block. At this time, since the data of the batch erase block does not exist in the SRAM (miss-hit), the data read from the ROM needs to be transferred to the SRAM. However, prior to this, one of the blocks in the SRAM must be written back to the ROM. For example, when writing back the data of the second batch erase block from the SRAM to the ROM, the entire data of the batch erase block of the ROM is erased, and then the SRAM block data is sequentially transferred and written. In this write-back operation, an erase verify signal can be used. In response to the erase verify signal (indicating that the erase operation has been completed), the data of the first page is transferred from the SRAM. Subsequently, the transfer of the data of the second and subsequent pages can be performed by detecting the batch verify signal of the previous page as described above. In the above-described 8NAND EEPROM, data transfer for 8 pages is necessary. Subsequently, the entire data of the sixth batch erase block is copied to an empty block of the SRAM, and the data at the address is output to the CPU by the SRAM.

{Suppose that a CPU (not shown) writes data to, for example, the seventh batch erase block. At this time, a copy of the data of the batch erase block does not exist in the SRAM (miss hit). Therefore, the above-described write-back operation and read operation need to be performed prior to the write operation to the SRAM. For example, when the data of the third batch erase block is written back from the SRAM to the ROM, all the data of the batch erase block of the ROM are erased, and then the SRAM block data is sequentially transferred and written. In this write-back operation, an erase verify signal can be used. In response to the erase verify signal (indicating that the erase operation has been completed), the data of the first page is transferred from the SRAM. Subsequently, the transfer of the data of the second and subsequent pages can be performed by detecting the batch verify signal of the previous page as described above. In the above-described 8NAND EEPROM, data transfer for 8 pages is necessary. Subsequently, the entire data of the seventh batch erase block is copied to an empty block of the SRAM, and data requested to be written by the CPU is written to a corresponding area in the SRAM.

As described above, a ROM that outputs a batch verify signal can easily configure a cache system in combination with an SRAM or the like. This is because the collective verify signal is used for data write back at the time of a mishit.

Next, a description will be given of a third embodiment of the memory system having the batch verify function. FIG. 102 shows an example of the circuit. That is, it has ROMs 111 and 112 having a batch verify function and a control circuit 113 which controls writing and has at least an internal write data register. The control circuit 113 may be configured by using a CPU, or may be configured by a plurality of chips including a gate array and an SRAM. Further, the ROM 111 and the ROM 112 may be mixedly mounted on one chip, or may be constituted by a plurality of chips.

(4) The continuous page data is stored in the ROM 111 and the ROM 112 alternately. For example, the first, third, fifth,..., (2N−1) th pages are stored in the ROM 111, and the second, fourth, sixth,. As described above, the operation in the write mode includes the operation of transferring the page data to the write data latch in the chip, and the subsequent write and verify operations. In this system, while writing data is being transferred to the ROM 111, writing and verification of the ROM 112 are performed. Further, when writing data over a plurality of pages, data is alternately transferred to the ROM 111 and the ROM 112.

に お い て In the circuit configuration shown in FIG. 101 as well, control of write data transfer uses a batch verify signal output from the ROM. First, the data of the first page is transferred to the ROM 111, and then the write and verify operations are performed on the ROM 111. While the write and verify operations are being performed on the ROM 111, the control circuit 113 transfers the data of the second page to the ROM 112, and subsequently performs the write and verify operations. When the writing of the first page in the ROM 111 is completed, a batch verify signal is output. In response, the control circuit 113 transfers the data of the third page to the ROM 111, and subsequently performs a write and verify operation. The same applies to page writing for the fourth and subsequent pages.

As described above, according to the third embodiment, the transfer of the write page data from the control circuit 113 to the ROMs 111 and 112 can be performed based on the batch verify signal. In the present embodiment, unlike the related art, there is no need to provide a comparison circuit or a large-capacity register for verify reading outside, and the configuration of the control circuit 112 is extremely simplified. Further, since writing is performed alternately, the writing time becomes faster. However, the size of the batch erase block is doubled.

FIG. 2 is a block diagram showing a configuration of a NAND cell type EEPROM according to the first embodiment. FIG. 2 is a plan view and an equivalent circuit diagram showing a NAND cell configuration according to the first embodiment. FIG. 3 is a cross-sectional view taken along line AA ′ and line BB ′ in FIG. FIG. 3 is an equivalent circuit diagram of the memory cell array in the first embodiment. FIG. 3 is a diagram illustrating a configuration of a bit line control circuit unit according to the first embodiment. FIG. 4 is a diagram illustrating a connection relationship between a bit line control circuit unit and another circuit according to the first embodiment. FIG. 4 is a timing chart showing a data write / write check operation in the first embodiment. FIG. 4 is a block diagram showing a configuration of a NAND cell type EEPROM according to a second embodiment. FIG. 9 is a diagram illustrating a configuration of a bit line control circuit according to a second embodiment. FIG. 9 is a diagram illustrating a configuration of a program end detection circuit according to a second embodiment. FIG. 13 is a timing chart showing a write confirmation operation in the second embodiment. FIG. 14 is a diagram showing another embodiment of the data latch unit and the program end detection circuit. FIG. 14 is a diagram showing another embodiment of the data latch unit and the program end detection circuit. FIG. 1 is a circuit diagram of an embodiment of a NOR flash EEPROM. Threshold distribution diagram. FIG. 14 is a diagram showing another embodiment of the data latch unit and the program end detection circuit. FIG. 14 is a diagram showing another embodiment of the data latch unit and the program end detection circuit. FIG. 13 is a diagram illustrating an algorithm at the time of writing / writing confirmation in the third embodiment. FIG. 3 is a diagram schematically showing a data latch / sense amplifier and a write end detection transistor. FIG. 20 is a diagram showing a configuration of a write end detection transistor and a nonvolatile memory for fuse of FIG. 19. FIG. 21 is a diagram illustrating a configuration example different from the configuration in FIG. 20. FIG. 20 is a diagram illustrating a program algorithm when the circuit in FIG. 19 is used. FIG. 20 is a diagram illustrating a circuit configuration different from that in FIG. 19; FIG. 14 is a diagram illustrating a configuration of a bit line control circuit according to a fourth embodiment. FIG. 14 is a diagram illustrating another configuration example of the bit line control circuit in the third and fourth embodiments. FIG. 14 is a diagram illustrating another configuration example of the bit line control circuit in the third and fourth embodiments. FIG. 14 is a diagram illustrating another configuration example of the bit line control circuit in the third and fourth embodiments. FIG. 13 is a diagram showing the timing of the operation of latching the same data in the data latch section of the bit line control circuit in the third embodiment. FIG. 17 is a diagram showing the timing of the operation of collectively latching the same data in the data latch unit of the bit line control circuit according to the fourth embodiment. FIG. 19 is a diagram illustrating a circuit configuration in which one CMOSFF is shared by two adjacent bit lines in a modification of the third embodiment. FIG. 31 is a diagram showing another example of the configuration in FIG. 30. FIG. 13 is a diagram showing a configuration of a NAND cell type EEPROM according to a fifth embodiment. FIG. 2 is a diagram showing a specific configuration of a memory cell eye array and its peripheral circuits. FIG. 17 is a timing chart showing an operation at the time of writing in the fifth embodiment. FIG. 17 is a timing chart showing a read operation in the fifth embodiment. FIG. 14 is a diagram showing a specific configuration of a memory cell array and its peripheral circuits in a sixth embodiment. FIG. 17 is a timing chart showing a write operation in the sixth embodiment. FIG. 17 is a timing chart showing a read operation in the sixth embodiment. FIG. 34 is a view showing a modification of the thirty-third embodiment. FIG. 37 is a view showing a modification of the embodiment shown in FIG. 36. FIG. 37 is a view showing a modification of the embodiment shown in FIG. 36. FIG. 37 is a diagram schematically showing replacement of bit lines in the embodiment shown in FIG. 36. FIG. 37 is a diagram schematically showing replacement of bit lines in the embodiment shown in FIG. 36. FIG. 6 is a diagram showing an embodiment in which a data latch and sense amplifier is shared by four bit lines. FIG. 45 is a view schematically showing replacement of bit lines in the embodiment in FIG. 44. FIG. 45 is a view schematically showing replacement of bit lines in the embodiment in FIG. 44. FIG. 40 is a view showing a modification of the embodiment shown in FIG. 39. FIG. 41 is a view showing a modification of the embodiment shown in FIG. 40. FIG. 42 is a view showing a modification of the embodiment shown in FIG. 41. FIG. 14 is a block diagram showing a seventh embodiment of the nonvolatile semiconductor memory device according to the present invention. FIG. 14 is a circuit diagram of a sense amplifier / launch circuit according to a seventh embodiment. 15 is a flowchart illustrating an erase operation according to a seventh embodiment. FIG. 16 is a block diagram showing an eighth embodiment of the present invention. FIG. 14 is a circuit diagram of a sense amplifier / latch circuit according to an eighth embodiment. FIG. 15 is a circuit diagram of a sense amplifier / latch circuit according to a ninth embodiment of the present invention. FIG. 21 is a circuit diagram of a sense amplifier / latch circuit according to a tenth embodiment of the present invention. FIG. 19 is an overall configuration diagram of an eleventh embodiment of the present invention. 57 is a timing chart of FIG. 57. FIG. 58 is an explanatory diagram of a read margin in FIG. 57. 57 is an erasing flowchart of FIG. 57. Erase flowchart. FIG. 58 is a detailed example of the output circuit in FIG. 57. FIG. 6 is a partial view of a conventional memory. 4 is a timing chart at the time of program verification. FIG. 4 is a diagram showing a combination of write data WD and verify data VD. FIG. 6 is a diagram showing a potential level distribution after verification and a threshold dependency of a bit line. 4 is a timing chart of program verification. FIG. 4 is a diagram showing a combination of write data WD and verify data VD. FIG. 6 is a diagram showing a potential level distribution after verification and a threshold dependency of a bit line. Another example of a rewrite transistor. FIG. 1 is a general circuit diagram used to implement the present invention. FIG. 1 is a general circuit diagram used to implement the present invention. FIG. 1 is a general circuit diagram used to implement the present invention. FIG. 1 is a general circuit diagram used to implement the present invention. FIG. 1 is a general circuit diagram used to implement the present invention. FIG. 1 is a general circuit diagram used to implement the present invention. FIG. 1 is a general circuit diagram used to implement the present invention. FIG. 3 is a chip circuit diagram and a threshold distribution diagram as an embodiment. FIG. 4 is another circuit diagram of a chip as an example. Verify level setting circuit. Detailed example of Vwell circuit. A modification of the eleventh embodiment (FIG. 55). FIG. 83 is a chart for explaining the operation in FIG. 82; Schematic diagram of an auto program. 84 is the flowchart of FIG. 84. 9 is a timing chart of a verify operation after a program operation. 4 is a flowchart of an embodiment having an ECC circuit. 4 is a timing chart 1 of the external control mode. 4 is a timing chart 2 of the external control mode. 3 is a timing chart of the external control mode. Timing chart 4 of the external control mode. FIG. 4 is a plan pattern diagram of an EEFROM. FIG. 93 is a sectional view taken along line BB of FIG. 92. 92 is a sectional view taken along line CC of FIG. 92. FIG. 2 is a block diagram of a 4-bit flash EEPROM. FIG. 95 is a partial detailed view of FIG. 95; 4 is a timing chart at the time of program verification. 4 is a timing chart at the time of erase verify. FIG. 6 is a circuit diagram of still another embodiment. 1 illustrates a storage system as an embodiment. Storage system as a different embodiment. A storage system as still another embodiment.

Claims (30)

A plurality of electrically rewritable nonvolatile semiconductor memory cells;
A word line commonly connected to the plurality of memory cells;
A source line commonly connected to the plurality of memory cells;
A row decoder for supplying a write verify voltage to the word line;
A plurality of bit lines connected to the corresponding memory cells,
A plurality of write verify circuits provided on the corresponding bit lines,
A non-volatile semiconductor storage device comprising:
Each of the write verify circuits stores data of a first or second logic level, and when storing the data of the first logic level, charges a corresponding bit line in advance and after a predetermined period of time, A write state of the corresponding memory cell is detected, and when the data of the second logic level is stored, the corresponding bit line is connected to a predetermined power supply for at least the predetermined period. Non-volatile semiconductor storage device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage of the source line is different from the voltage level of the predetermined power supply. 4. The nonvolatile semiconductor memory device according to claim 1, wherein a logic level of data stored in the write verify circuit is determined by a state of the memory cell before detecting a write state. 2. The logic level of data stored in the write verify circuit controls a voltage of a bit line corresponding to a write operation to the memory cell performed after detecting a write state. Non-volatile semiconductor storage device. A main memory having a plurality of erase blocks, each erase block including a plurality of memory cells having a predetermined number of bits, and outputting an erase verify signal when all of the predetermined number of bits have been erased;
Cache memory,
Controlling a data transfer operation between the main memory and the cache memory, a control circuit,
With
When there is no data accessed in the cache memory due to a cache mishit, the control circuit erases one of the plurality of erase blocks, and the data is completely erased, whereby the erase verify signal is erased. Is output, the control circuit executes a data rewrite operation of rewriting data in the cache memory into one of the plurality of erase blocks.
A cache memory system, characterized in that: A first memory cell for storing first data;
A second memory cell for storing second data;
A data latch circuit for storing third data;
A first comparator circuit that compares the first data with the second data and generates first output data according to a comparison result;
A second comparator circuit that compares the third data with the first output data and generates second output data according to the comparison result;
A semiconductor memory device comprising: 7. The semiconductor memory device according to claim 6, wherein the first comparator circuit is a linear comparator using a current mirror type differential amplifier, and the second comparator circuit is a digital comparator. 7. The semiconductor memory device according to claim 6, wherein the first memory cell and the second memory cell are floating gate MOS transistors. 7. The semiconductor memory device according to claim 6, wherein the third data stored in the data latch circuit is supplied from outside. 7. The semiconductor memory device according to claim 6, wherein the third data is used to control a program operation performed on the first memory cell. 7. The semiconductor memory device according to claim 6, further comprising: an output circuit for outputting said second output data. 12. The semiconductor memory device according to claim 11, wherein the output circuit selectively outputs one of the first output data and the second output data. 7. The semiconductor memory device according to claim 6, further comprising a prohibition circuit that prohibits the comparison in the second comparator circuit and uses the first output data as the second output data. The first memory cell is a floating gate type MOS transistor,
A plurality of third memory cells which are floating gate type MOS transistors;
Drains of the first memory cell and the plurality of third memory cells are commonly connected to a bit line;
Sources of the first memory cell and the plurality of third memory cells are commonly connected,
A block selection MOS transistor connected between the bit line and the first comparator circuit;
The semiconductor memory device according to claim 6. 15. The semiconductor memory device according to claim 14, further comprising a column selection MOS transistor connected between said block selection MOS transistor and said first comparator circuit. A bit line voltage control terminal that is internally boosted and supplied with a boost voltage;
Bit lines,
A fuse connected between the bit line and the bit line voltage control terminal;
A memory cell connected to the bit line for storing data therein and being programmed by receiving the boost voltage;
A semiconductor memory device comprising: A bit line voltage control terminal,
Bit lines,
A fuse connected between the bit line and the bit line voltage control terminal;
A non-volatile semiconductor, having a floating gate connected to the bit line for storing data therein and storing electric charges, and a control gate connected to a word line, and programmed by injecting electric charges into the floating gate; A memory cell,
A nonvolatile semiconductor memory device comprising: 18. The nonvolatile semiconductor memory device according to claim 17, wherein the nonvolatile semiconductor memory cell is a NAND EEPROM cell. 18. The nonvolatile semiconductor memory device according to claim 17, further comprising a reset transistor for discharging said bit line in response to a reset signal. A bit line voltage control terminal that is internally boosted and supplied with a boost voltage;
Multiple bit lines,
A plurality of switches, one ends of which are connected to the corresponding bit lines, the other ends are connected in common, and a precharge signal is input and simultaneously turned on;
Fuses respectively connected between the bit line voltage control terminal and the other ends of the plurality of switches;
A plurality of memory cells connected to the plurality of bit lines, storing data therein, and programmed by receiving the boost voltage;
A semiconductor memory device comprising: 21. The semiconductor memory device according to claim 16, wherein the memory cell is a NAND type EEPROM cell. 21. The semiconductor memory device according to claim 16, further comprising a plurality of reset transistors for discharging said plurality of bit lines in response to a reset signal. A bit line voltage control terminal,
Multiple bit lines,
A plurality of switches, one end of which is connected to the corresponding bit line, the other end is connected in common, and a precharge signal is input and simultaneously turned on;
Fuses respectively connected between the bit line voltage control terminal and the other ends of the plurality of switches;
A floating gate that is connected to the plurality of bit lines, stores data therein, stores a charge, and has a control gate connected to a word line, and is programmed by injecting a charge into the floating gate. A non-volatile semiconductor memory cell;
A nonvolatile semiconductor memory device comprising: 24. The nonvolatile semiconductor memory device according to claim 23, wherein said nonvolatile semiconductor memory cell is a NAND type EEPROM cell. 24. The nonvolatile semiconductor memory device according to claim 23, further comprising a plurality of reset transistors for discharging said plurality of bit lines in response to a reset signal. Multiple bit lines,
Multiple word lines,
A nonvolatile semiconductor memory cell array having a plurality of nonvolatile semiconductor memory cells each being a floating gate type MOS transistor;
A plurality of data latch circuits each connected to a corresponding one of the plurality of bit lines and storing data read from the plurality of memory cells;
An error correction circuit (ECC) for performing error correction on the data stored in the data latch circuit, and generating and outputting corrected data;
A semiconductor storage system comprising: The error correct circuit (ECC) counts the number of failed bits in the data stored in the data latch circuit, and generates and outputs the collect data when the number of failed bits is smaller than a predetermined number. 27. The semiconductor storage system according to claim 26, wherein the semiconductor storage system is characterized in that: The error correction circuit (ECC) counts the number of failed bits in the data stored in the data latch circuit, and outputs an alarm signal when the number of failed bits is larger than a predetermined number. 27. The semiconductor storage system according to claim 26. 27. The semiconductor memory system according to claim 26, wherein the error correction circuit (ECC) counts the number of failed bits in the data stored in the data latch circuit. A chip is constituted by the plurality of bit lines, the plurality of word lines, the nonvolatile semiconductor memory cell array, the plurality of data latch circuits, and the error correct circuit (ECC). The semiconductor storage system according to claim 26.

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