JPH02146185A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a current from flowing into a defective digit line by interrupting the digit line connected to a defective memory cell array by means of interrupting substances provided between the power source of a memory, and a digit line and a redundant digit line. CONSTITUTION:Transfer gate transistors (TR) TR3 and TR4, driver TRs TR5 and TR6, and resistances R1 and R2 constitute a static memory cell. A voltage VCC is applied to digit lines D and the inverse of D by the TRs TR1 and TR2. Further, fuses are provided between the power source VCC and the sources of the TRs TR1 and TR2. When the defective digit is detected by probing in a wafer condition, the fuse is disconnected by laser beams, and the digit is replaced with the redundant digit. Thus, the digit line connected to the defective memory cell is disconnected from the power source, and the current can be prevented from flowing in.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor memory devices, particularly digital devices [Prior Art] Conventionally, semiconductor memory devices have been manufactured with redundancy as a measure against low yields, especially in the early stages of development. A circuit is provided. One method of redundancy circuitry is to replace a defective digit line with a redundant digit line by cutting a fuse. At this time,
Like other normal digit lines, the defective digit line is supplied with a power supply potential when the semiconductor memory device is not in operation, and is supplied with a predetermined potential in accordance with the operation when the semiconductor memory device is in operation.

[Problems to be Solved by the Invention] The conventional redundant circuit for repairing digit lines described above does not prevent defective digit lines even after they are replaced with redundant digit lines by detecting a defective digit line and cutting the fuse with a laser beam. Like other normal digit lines, the defective digit line is always supplied with a power supply potential when the semiconductor memory device is not in operation, and is also supplied with a predetermined potential in accordance with data read and write operations during operation. For this reason, the defective digit line is shorted to the GND potential, for example, the memory cell is connected to the GND potential.
If there is a short circuit with the aluminum wiring that supplies the level, current will flow from the digit line, so even if the replacement with redundant digits is successful, the current standard cannot be met and the memory device will be defective. be.

[Differences between the invention and the prior art] In contrast to the conventional redundant circuit for digit line relief described above,
The present invention has a difference in that after a defective digit line is replaced with a redundant digit line, a power supply potential is not applied to the defective digit line regardless of whether the semiconductor memory device is operating or not.

[Means for Solving the Problems] The gist of the present invention is to provide a plurality of memory cell columns, a plurality of digit lines respectively connected to the memory cell columns, a redundant memory cell column, and a plurality of digit lines connected to the redundant memory cell columns. In a semiconductor memory device having a redundant digit line and a power supply connected to the plurality of digit lines and the redundant digit line, a circuit breaker is provided between the power supply and the digit line and the redundant digit line, respectively. It is possible to disconnect between the digit line connected to the memory cell column and the power supply.

[Example code] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

Tri and Tr2 are transfer gate transistors Tr
3. Tr4, driver transistors Tr5, Tr6, and high-resistance loads R1, R2 are connected to the static memory cell.
is a gate input signal that controls transistors Trl and Tr2.

The fuse is the power supply potential vCC and the transistor Tri.

It is arranged between the source of Tr2. When a defective digit is detected in the wafer test by blowing and it is determined that replacing it with a redundant digit will result in a non-defective product, the fuse is cut by a laser beam to replace the digit and remove the defective digit line. The fuses connecting the transistors Tri and Tr2 and the vCC power line are also cut with a laser beam. Similarly to other digits, the control signal P for supplying the VCC power supply potential to the digit line is supplied to the transistor Trl.
Even if the power supply potential is applied to the gate of Tr2, the power supply potential is not supplied because the fuse is cut, thereby preventing a current failure due to a defective digit.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

In this embodiment, an N-channel transistor Tri,
The gate input signal of Tr2 is controlled by cutting the fuse with a laser beam. For digits that are not defective, node 1 is connected to the CC power supply through the fuse, so node 1 becomes high level, and node 2 becomes low level due to the inverter. This allows transistors Tri and Tr to pass through (NOR)
The gate manual signal to 2 is controlled by control signal F, and ■
Only when a low level is input to the transistor Tri
, Tr2 are applied with a high level, transistors Tri and Tr2 are turned on, and a high level is supplied to the digit line.

In the case of a defective digit line, after replacing it with a redundant digit, the fuse of the defective digit line is cut with a laser beam, so that the level of node 1 decreases, and the level of node 20 increases accordingly, causing the N-channel transistor Tr7 to By turning on, node 1 becomes low level and node 2 becomes high level. Since node 2 is at a high level, no matter what signal is input to F, the output of the NOR gate, that is, the gate input signal of transistors Tri and Tr2, is always at a low level, and Tri and Tr2 are always turned off.
This prevents the digit line from being supplied with a high level.

[Effects of the Invention] As explained above, the present invention prohibits the supply of power supply potential to a defective digit line by electrically disconnecting a predetermined circuit. It has the effect of preventing this from happening.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment, and FIG. 3 is a circuit diagram of a conventional system. Driver transistor of cell, R1, R2...φ High resistance load of static type memory cell, Trl, Tr2. Trl...transistor, P, P''
・・・・・・・・・Digital line level control signal.

Claims (1)

[Scope of Claims] A plurality of memory cell columns, a plurality of digit lines respectively connected to the memory cell columns, a redundant memory cell column, a redundant digit line connected to the redundant memory cell columns, and the plurality of digit line and a power supply connected to the redundant digit line, a circuit breaker is provided between the power supply and the digit line and the redundant digit line, respectively, and the digit line connected to the defective memory cell column is What is claimed is: 1. A semiconductor memory device characterized in that it is possible to cut off a connection between a power source and a power source.