JP2004093894A - Display device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device having superior display quality and image scanning performance and to provide its manufacturing method. <P>SOLUTION: When hydrogenating the channel part of a TFT11 and the I layer of photodiodes D1 and D2 together during a manufacturing process of the display device, the progress of the hydrogeneration is made different for the TFT11 and the photodiodes D1 and D2 so that defect density of the channel part of the TFT11 is made low and defect density of the I layer of the photodiodes D1 and D2 is made high. Thus, leak current of the TFT11 is suppressed and light sensitivity of the photodiodes D1 and D2 is improved. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device having an image capturing function and a method for manufacturing the same.
[0002]
[Prior art]
The liquid crystal display device includes an array substrate on which signal lines, scanning lines, and pixel TFTs are arranged in rows, and a driving circuit that drives the signal lines and scanning lines. With the recent advancement and development of integrated circuit technology, a process technology for forming a part of a drive circuit on an array substrate has been put to practical use. As a result, the entire liquid crystal display device can be made lighter, thinner and smaller, and is widely used as a display device for various portable devices such as a mobile phone and a notebook computer.
[0003]
By the way, there has been proposed a display device in which a contact area sensor for capturing an image is arranged on an array substrate (for example, see Patent Documents 1 and 2).
[0004]
[Patent Document 1]
JP-A-2001-292276
[Patent Document 2]
JP 2001-339640 A
[Problems to be solved by the invention]
Since polysilicon has higher mobility than amorphous silicon, it is preferable to use polysilicon to form a part of a driver circuit on an array substrate.
[0007]
However, even if the active layers of the various TFTs formed on the array substrate are formed of polysilicon, there is a problem that a leak current flows through the TFT if there are many dangling bonds in the active layer.
[0008]
As a method for solving such a problem, hydrogenation of the active layer to terminate dangling bonds can be considered. However, in the case of the above-mentioned contact type area sensor, it is desirable to have a dangling bond in the active layer of the sensor in order to increase the trap level in order to increase the sensitivity to light.
[0009]
The present invention has been made in view of such a point, and an object of the present invention is to provide a display device excellent in display quality and image capturing performance, and a method of manufacturing the same.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a display element formed near each intersection of signal lines and scanning lines arranged in rows and columns, and at least one display element corresponding to each of the display elements. A photoelectric conversion unit that receives incident light in a specified range and converts the light into an electric signal, wherein the photoelectric conversion unit has an I layer formed between a p layer and an n layer. The defect density of the I layer is higher than the defect density of the channel of the display element.
[0011]
In the present invention, since the defect density of the photoelectric conversion portion in the pixel is higher than the defect density of the channel portion of the display element, the leakage current of the display element can be suppressed while improving the sensitivity of the photoelectric conversion portion to light.
[0012]
Also, at least one display element is provided corresponding to each of the display elements formed near each intersection of the signal lines and the scanning lines arranged in rows and columns, and each of the display elements is configured to receive incident light in a designated range. A photoelectric conversion unit that receives light and converts it into an electric signal, wherein the photoelectric conversion unit has an I layer including a p ⁻ layer and an n ⁻ layer formed between the p ⁺ layer and the n ⁺ layer. A defect density of the p ⁻ layer is set higher than a defect density of a channel portion of the display element; a first gate having a first gate length is disposed above the p ⁻ layer; Above, a second gate having a second gate length shorter than the first gate length is arranged.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a display device and a method for manufacturing the same according to the present invention will be specifically described with reference to the drawings.
[0014]
FIG. 1 is a schematic configuration diagram of a first embodiment of a display device according to the present invention, showing a configuration on an array substrate. The display device shown in FIG. 1 includes a pixel array section 1 in which signal lines and scanning lines are arranged in a row, a signal line driving circuit 2 for driving signal lines, a scanning line driving circuit 3 for driving scanning lines, and an image capturing device. And a sensor control circuit 5 for controlling an image capturing sensor.
[0015]
FIG. 2 is a block diagram showing a part of the pixel array unit 1 in detail. The pixel array unit 1 in FIG. 2 includes a pixel TFT 11 formed near each intersection of a signal line and a scanning line arranged vertically and horizontally, a liquid crystal capacitor C1 connected between one end of the pixel TFT 11 and a Cs line, and It has an auxiliary capacitor C2 and two image capture sensors 12a and 12b provided for each pixel TFT 11. The sensors 12a and 12b are connected to a power line and a control line (not shown).
[0016]
FIG. 3 is a circuit diagram showing a part of FIG. 2 in detail. As shown in FIG. 3, the sensors 12a and 12b have photodiodes D1 and D2 and sensor switching transistors Q1 and Q2, respectively. The photodiodes D1 and D2 output an electric signal according to the amount of received light. The sensor switching transistors Q1 and Q2 alternately select one of the plurality of photodiodes D1 and D2 in one pixel.
[0017]
Each pixel includes two sensors 12a and 12b, a capacitor C3 shared by the two sensors 12a and 12b in the same pixel, a buffer 13 for storing binary data corresponding to the charge stored in the capacitor C3, and a buffer 13 And a reset transistor Q4 for initializing the buffer 13 and the capacitor C3.
[0018]
The buffer 13 is composed of a static RAM (SRAM), for example, as shown in FIG. 4, two inverters IV1 and IV2 connected in series, an output terminal of the succeeding inverter IV2, and an input terminal of the preceding inverter IV1. And an output transistor Q6 connected to the output terminal of the subsequent inverter.
[0019]
When the signal SPOLB is at a high level, the transistor Q5 is turned on, and the two inverters IV1 and IV2 perform a holding operation. When the signal OUTi is at a high level, the held data is output to the detection line.
[0020]
The display device of the present embodiment can perform a normal display operation, and can also perform image capture similar to a scanner. When a normal display operation is performed, the transistor Q3 is turned off, and no valid data is stored in the buffer 13. In this case, a signal line voltage is supplied from the signal line driving circuit 2 to the signal line, and display according to the signal line voltage is performed.
[0021]
On the other hand, when performing image capture, an image capture target (for example, a paper surface) 22 is disposed on the upper surface side of the array substrate 21 as shown in FIG. 5, and light from the backlight 23 is transmitted to the opposing substrate 24 and the array substrate 21. And irradiate the paper surface 22 via. The light reflected on the paper surface 22 is received by the sensors 12a and 12b on the array substrate 21, and an image is captured. The captured image data is stored in the buffer 13 and then sent to a CPU (not shown) via a detection line. The CPU receives digital signals output from the display device of the present embodiment and performs arithmetic processing such as rearranging data and removing noise in data. Note that the CPU may be constituted by one semiconductor chip or a plurality of semiconductor chips.
[0022]
FIG. 6 is an operation timing chart at the time of image capture. First, since the signals PAR of the sensors 12a and 12b are at a high level, the left transistor in one pixel is selected.
[0023]
Next, from time t1 to t2 in FIG. 6, the pixel array unit 1 is sequentially driven row by row, and all pixels are set to the same color (for example, white).
[0024]
Next, at time t3, the signals RST, SPOLA, and SPOLB are all set to the high level, and all the transistors Q3, Q4, and Q5 are turned on. As a result, initial values are set in the buffer 13 and the capacitor C3.
[0025]
When the signal RST goes low (time t4), the sensors 12a and 12b start capturing images. When the light reflected from the paper surface 22 is received by the photodiodes D1 and D2 in the sensors 12a and 12b, the charge stored in the capacitor C3 flows to the ground terminal GND through the photodiodes D1 and D2. That is, a leak current flows. As a result, the charge stored in the capacitor C3 decreases.
[0026]
At time t5, the signal SPOLA goes high, and the binary data corresponding to the charge stored in the capacitor C3 is stored in the buffer 13.
[0027]
Thereafter, at time t6, the signal SPOLB goes high, and the buffer 13 starts the holding operation. Thereafter, at time t7, the data stored in the buffer 13 is sequentially supplied to the detection line for each pixel and sent to a CPU (not shown).
[0028]
In FIG. 6, the reason why the buffer 13 is provided for each pixel is as follows. The accumulated charge of the capacitor C3 leaks not only by the current flowing through the photodiodes D1 and D2 in the sensors 12a and 12b, but also by the current flowing through the TFT in the pixel. Therefore, the accumulated charge of the capacitor C3 decreases with time, and the voltage across the capacitor C3 also decreases. Therefore, if the buffer 13 is provided for each pixel and the charge stored in the capacitor C3 is transferred to the buffer 13 before it leaks, the image can be captured without being affected by the leak of the capacitor C3.
[0029]
The reason why the SRAM is used as the buffer 13 is that the SRAM does not cause a malfunction such as logical inversion even when irradiated with light of several hundred thousand lux.
[0030]
After time t8, the sensor switching signal PAR becomes low level, and switches between the sensors 12a and 12b to capture an image.
[0031]
Each component formed on the array substrate 21 of the present embodiment is formed using an n-channel TFT and a p-channel TFT.
[0032]
FIG. 7 is a manufacturing process diagram of an n-channel TFT, and FIG. 8 is a manufacturing process diagram of a p-channel TFT. The n-channel TFT and the p-channel TFT are formed by a common manufacturing process.
[0033]
First, an undercoat layer made of SiNx, SiOx, or the like is formed on a glass substrate 31 by a CVD method. The reason for forming the undercoat layer is to prevent impurities from diffusing into elements formed on the glass substrate 31.
[0034]
Next, after an amorphous silicon film is formed on the glass substrate 31 by a PECVD method, a sputtering method, or the like, the amorphous silicon film is irradiated with a laser to be crystallized, thereby forming a polycrystalline silicon film 32.
[0035]
Next, after patterning the polycrystalline silicon film 32, a first insulating layer 33 made of a SiOx film formed by a PECVD method or an ECR-CVD method is formed. Then, low-concentration boron is implanted into predetermined portions of the polycrystalline silicon film 32 (FIGS. 7A and 8A).
[0036]
Next, phosphorus is ion-implanted into a portion where the n-channel TFT is to be formed using the resist 34 as a mask (FIG. 7B).
[0037]
Next, a first metal such as Mo-Ta or Mo-W is deposited and patterned to form a gate electrode 35. Next, using the resist or the like 34 as a mask, boron ions are implanted into the formation location of the p-channel TFT using an ion implantation method (FIG. 8C). The resist 34 is not limited to the resist. A first metal patterned into a predetermined shape may be used. Both the resist and the first metal have the same effect of blocking ion implantation. Considering the various conveniences of the manufacturing process, the more advantageous one may be used.
[0038]
Next, low-concentration phosphorus is ion-implanted into the portion where the n-channel TFT is to be formed using the resist 34 as a mask (FIG. 7D). The other crystalline silicon film immediately below the portion masked by the resist or the like 34 remains as the p− layer. The resist 34 is not limited to the resist. A first metal patterned into a predetermined shape may be used. Both the resist and the first metal have the same effect of blocking ion implantation. Considering the various conveniences of the manufacturing process, the more advantageous one may be used.
[0039]
Next, so-called hydrogenation is performed. Hydrogenation is a process in which a substrate is exposed to a plasma of hydrogen. This step is performed using a CVD device. Dangling bonds in the polycrystalline silicon film 32 where the channel of the TFT is formed by hydrogenation can be terminated. This hydrogenation is performed for the purpose of suppressing the leak current of the TFT. When the substrate is exposed to the plasma of hydrogen, the hydrogen is blocked by the gate electrode and proceeds so as to sneak into the polycrystalline silicon film 32 from a portion without the gate electrode.
[0040]
Subsequent to the hydrogenation, a second insulating layer 36 made of SiOx is formed in the same CVD apparatus, a contact hole for forming an electrode is opened, and a second metal 37 is formed to form a source / drain electrode. Is patterned (FIGS. 7E and 8E). Finally, a SiN film is formed as a passivation film to complete an n-channel TFT and a p-channel TFT.
[0041]
It is desirable that the photodiodes D1 and D2 of the sensor have a PIN structure including a p ⁺ layer, a p ⁻ layer, an n ⁻ layer, and an n ⁺ layer. This is because the PIN structure has a wide depletion layer and good light-current conversion efficiency. The n ⁻ layer is effective in suppressing heat leakage current. As the heat leakage current is suppressed, the ON / OFF ratio of the photocurrent increases.
[0042]
FIG. 9 is a manufacturing process diagram of the photodiodes D1 and D2 having the PIN structure. First, an amorphous silicon film is formed on a glass substrate 31 by a PECVD method, a sputtering method, or the like, and then the amorphous silicon film is irradiated with a laser and crystallized to form a polycrystalline silicon film 32. Then, a low concentration boron is ion-implanted on the upper surface to form a p- layer (FIG. 9A).
[0043]
Next, phosphorus ions are implanted using the resist 34 as a mask to form an n ⁺ layer in a part of the polycrystalline silicon film 32 (FIG. 9B).
[0044]
Next, after forming a first metal to be the gate electrode 35, boron ions are implanted using the resist 34 as a mask to form ap ⁺ layer in a part of the polycrystalline silicon film 32 (FIG. 9C). . The resist 34 is not limited to the resist. A first metal patterned into a predetermined shape may be used. Both the resist and the first metal have the same effect of blocking ion implantation. The more advantageous one may be used in consideration of the matching of the manufacturing process.
[0045]
Next, low-concentration phosphorus is ion-implanted into the polycrystalline silicon film 32 using the resist 34 as a mask (FIG. 9D). The other crystalline silicon film immediately below the portion masked by the resist or the like 34 remains as the p− layer. The resist 34 is not limited to the resist. A first metal patterned into a predetermined shape may be used. Both the resist and the first metal have the same effect of blocking ion implantation. Considering the various conveniences of the manufacturing process and the like, the more advantageous one may be used. Subsequently, the above-mentioned hydrogenation is performed.
[0046]
Next, a contact hole is formed by forming a second insulating layer 36, and a second metal 37 is formed in a predetermined shape (FIG. 9E).
[0047]
The photodiode illustrated in FIG. 9 can be formed in the same manufacturing process as the TFT illustrated in FIGS. That is, FIGS. 7 (a), 8 (a) and 9 (a) are formed in the same step, and similarly, FIGS. 7 (b), 8 (b) and 9 (b) and FIGS. (C), FIGS. 8 (c) and 9 (c), FIGS. 7 (d), 8 (d) and 9 (d), and FIGS. 7 (e), 8 (e) and 9 (E) is formed in the same step.
[0048]
In this way, by making the manufacturing process common, the manufacturing cost can be reduced.
[0049]
In this embodiment, hydrogenation is performed regardless of whether a TFT or a photodiode is formed, but hydrogenation is more advanced when a TFT is formed. The reason is that, for a TFT, it is more preferable to terminate dangling bonds in the polycrystalline silicon film 32 by hydrogenation because the leakage current is reduced, whereas a photodiode is more preferable. This is because when the ring bond is not terminated, the trap level increases and the photoelectric conversion efficiency is improved. More specifically, the light leakage current is generated by generating electrons and holes when light having an energy larger than the predetermined energy gap Eg is incident. Here, if there are many dangling bonds, the state becomes a trap level and reacts to light having an energy smaller than a predetermined energy gap.
[0050]
The present inventor has confirmed through experiments that as shown in FIG. 10, the light leakage current tends to increase as the gate length increases. Therefore, in the present embodiment, in order to cause a difference in the progress of hydrogenation between the TFT and the photodiode, the I layer of the photoelectric conversion element is formed as shown in FIGS. The length Lp (hereinafter, the gate length of the photoelectric conversion element) covered by one metal is set longer than the length LT (hereinafter, the gate length of the TFT) in which the channel portion of the peripheral TFT is covered by the first metal layer. I have. 11A is a plan view and a sectional view of the photodiodes D1 and D2, and FIG. 11B is a plan view and a sectional view of the TFT 11.
[0051]
The reason why the leak current can be variably controlled by the gate length is as follows. Hydrogenation occurs as shown in FIGS. 12A and 12B so as to go around the gate electrode from the end of the gate electrode. Therefore, as the gate length is longer, hydrogenation in the vicinity immediately below the gate electrode is less likely to occur. FIG. 12A shows a state of hydrogenation of the photodiodes D1 and D2, and FIG. 12B shows a state of hydrogenation of the TFT 11.
[0052]
Controlling the hydrogenation time also makes a difference in the progress of the hydrogenation. That is, the shorter the hydrogenation time, the smaller the proportion of the termination of the dangling bond. Therefore, the TFT 11 may have a shorter hydrogenation time than the photodiodes D1 and D2.
[0053]
As described above, in the present embodiment, when the channel portion of the TFT 11 and the I layer of the photodiodes D1 and D2 are both hydrogenated in the manufacturing process of the display device, the hydrogenation between the TFT 11 and the photodiodes D1 and D2 progresses. In order to make a difference, the defect density of the channel portion of the TFT 11 is reduced, and the defect density of the I layer of the photodiodes D1, D2 is increased. The sensitivity to light can be improved.
[0054]
It is also known that heat leakage current occurs even when no light is irradiated. The heat leakage current is suppressed by the LDD layer (n- part in FIG. 9). Further, the longer the gate length is, the more it is suppressed. Usually, a TFT provided in a pixel dislikes deterioration of the pixel potential due to a heat leak current, and is used with a longer total gate length. In the pixel TFT, in order to suppress both the light leakage current and the heat leakage current, a short gate length is connected to form a so-called double gate structure or triple gate structure, so that hydrogenation proceeds easily and the total gate It is better to suppress the heat leakage current by having a long length.
[0055]
For the above reasons, the TFTs Q1 to Q4 in FIG. 3 are double-gate TFTs having a gate length of 3 μm (FIG. 11B), and the photodiodes have a gate length of 6 μm (single gate: FIG. 11A).
[0056]
In the above-described embodiment, an example has been described in which the photoelectric conversion element is configured by the photodiodes D1 and D2, but may be configured by the TFT11. In this case, the length of the portion covered by the first metal may be longer than that of the peripheral TFT 11.
[0057]
【The invention's effect】
As described in detail above, according to the present invention, the defect density of the I layer, which is a part of the photoelectric conversion unit in the pixel, is made higher than the defect density of the channel part of the display element. The leak current of the display element can be suppressed while increasing the sensitivity to light.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of an embodiment of a display device according to the present invention.
FIG. 2 is a block diagram showing a part of a pixel array unit in detail.
FIG. 3 is a circuit diagram showing a part of FIG. 2 in detail;
FIG. 4 is a circuit diagram showing an internal configuration of a buffer.
FIG. 5 is a simplified cross-sectional view illustrating a structure of a display device.
FIG. 6 is an operation timing chart at the time of image capture.
FIG. 7 is a manufacturing process diagram of the n-channel TFT 11.
FIG. 8 is a manufacturing process diagram of the p-channel TFT 11.
FIG. 9 is a manufacturing process diagram of the photodiodes D1, D2D1, and D2 having a PIN structure.
FIG. 10 is a diagram showing a relationship between a gate length and a leakage current.
11A is a plan view and a sectional view of photodiodes D1 and D2, and FIG. 11B is a plan view and a sectional view of TFT 11. FIG.
12A is a diagram illustrating a state of hydrogenation of photodiodes D1 and D2, and FIG. 12B is a diagram illustrating a state of hydrogenation of a TFT 11. FIG.
[Explanation of symbols]
Reference Signs List 1 pixel array unit 2 signal line drive circuit 3 scan line drive circuit 4 detection circuit 41 & output circuit 5 sensor control circuit 11 pixel TFT 11
12a, 12b Sensor 13 Buffer 21 Array substrate 22 Paper surface 23 Backlight 24 Counter substrate

Claims (7)

A display element formed near each intersection of signal lines and scanning lines arranged in rows and columns;
A photoelectric conversion unit that is provided at least one by one corresponding to each of the display elements and receives incident light in a specified range and converts the incident light into an electric signal,
The photoelectric conversion unit has an I layer formed between a p layer and an n layer, and the defect density of the I layer is higher than the defect density of a channel part of the display element. apparatus. A display element formed near each intersection of signal lines and scanning lines arranged in rows and columns;
A photoelectric conversion unit that is provided at least one by one corresponding to each of the display elements and receives incident light in a specified range and converts the incident light into an electric signal,
The photoelectric conversion unit has an I layer including a p ⁻ layer and an n ⁻ layer formed between the p ⁺ layer and the n ⁺ layer,
The defect density of the p ⁻ layer is set higher than the defect density of the channel portion of the display element,
A first gate having a first gate length is arranged above the p- layer,
A display device, wherein a second gate having a second gate length shorter than the first gate length is disposed above the display element. The first and second gates are each arranged at least one in each channel direction,
The display device according to claim 2, wherein the number of the second gates is larger than the number of the first gates. A display element formed near each intersection of signal lines and scanning lines arranged in rows and columns;
A method for manufacturing a display device, comprising: a photoelectric conversion unit that is provided at least one each corresponding to each of the display elements and receives incident light in a specified range and converts the incident light into an electric signal.
Forming an amorphous silicon layer on the insulating substrate;
Irradiating the amorphous silicon layer with a laser to crystallize, forming a polycrystalline silicon layer;
Patterning the polycrystalline silicon layer;
Forming a first insulating layer on an upper surface of the patterned polysilicon layer;
Implanting impurity ions into each region of the polycrystalline silicon layer corresponding to the formation location of the display element and the photoelectric conversion unit;
Forming a first metal layer on an upper surface of the first insulating layer;
Patterning the first metal layer to form a gate electrode;
Implanting impurity ions into each region of the polycrystalline silicon layer corresponding to the formation location of the display element and the photoelectric conversion unit;
Hydrogenating at least a portion of each of the regions corresponding to the display element and the photoelectric conversion portion of the polycrystalline silicon layer,
Exposing a part of each region of the polycrystalline silicon layer corresponding to the display element and the formation part of the photoelectric conversion unit, and forming a second metal layer around the exposed region. A method for manufacturing a semiconductor device. The polycrystalline silicon layer is hydrogenated such that a defect density of a region corresponding to a formation location of the photoelectric conversion unit is higher than a defect density of a region corresponding to a formation location of the display element. Item 5. The method for manufacturing a semiconductor device according to Item 4. The method according to claim 4, wherein a gate length of a gate electrode of the display element is shorter than a gate length of a gate electrode of the photoelectric conversion unit. One or more gate electrodes of the display element and the photoelectric conversion unit are respectively arranged in each channel direction,
The method according to claim 6, wherein the number of gate electrodes of the photoelectric conversion unit is larger than the number of gate electrodes of the display element.

Images