JP2004079654A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device wherein writing speed can be increased even if power source voltage is low. <P>SOLUTION: The nonvolatile semiconductor storage device is provided with: a semiconductor substrate 1 of a first conduction type; a source region 7 and a drain region 8 which are constituted of impurity diffusion layers of a second conduction type which are formed facing a surface of the semiconductor substrate 1; a floating gate 3 which is formed between the source region 7 and the drain region 8 on the semiconductor substrate 1 via an insulating film 2; and a control gate 5 formed on the floating gate 3. A low relative permittivity region 9 having relative permittivity lower than that of the semiconductor substrate 1 is formed in the semiconductor substrate 1 below the drain region 8. A first interface A is positioned in the vicinity of a drain end portion 100, and a second interface B is isolated at least 0.01μm from the surface of the semiconductor substrate 1. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device.
[0002]
[Prior art]
In recent years, demand for digital cameras and mobile phones has rapidly increased, and demand for nonvolatile semiconductor storage devices typified by flash memories used as storage media for these mobile devices is also rapidly expanding.
[0003]
In digital cameras and mobile phones, demands for miniaturization, weight reduction, and high functionality are becoming more and more strict, and accordingly, in nonvolatile semiconductor memory devices, miniaturization, high integration, low power supply voltage, There is an increasing demand for improved reliability.
[0004]
Among the required performances of the above-described nonvolatile semiconductor memory device, lowering the power supply voltage is indispensable for reducing power consumption and improving reliability. However, in the structure of the conventional nonvolatile semiconductor device, if the power supply voltage is lowered as it is, the writing speed is reduced, and the demand for high speed is not satisfied.
[0005]
[Problems to be solved by the invention]
As described above, the conventional nonvolatile semiconductor memory device cannot simultaneously satisfy the two requirements of lowering the power supply voltage and improving the writing speed.
[0006]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a nonvolatile semiconductor memory device capable of improving a writing speed even at a low power supply voltage.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a semiconductor substrate of a first conductivity type,
A source region and a drain region formed on the surface of the semiconductor substrate facing each other and facing each other;
A floating gate formed on the semiconductor substrate between the source region and the drain region via an insulating film;
A control gate formed on the floating gate,
A low relative dielectric constant region having a lower relative dielectric constant than the semiconductor substrate formed in the semiconductor substrate below the drain region,
The low relative dielectric constant region is at least 0.01 μm or more away from the surface of the semiconductor substrate, and an end near the source region exists on the drain region side. .
[0008]
At this time, it is preferable that the low dielectric constant region is a void formed in the semiconductor substrate.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a nonvolatile semiconductor device of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments, and various selections can be made.
[0010]
(Embodiment 1)
FIG. 1 is a sectional view showing an element structure of a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention. FIG. 1 shows the configuration of a cell portion, but this cell structure can be applied to various types of memory cell units of NAND type, NOR type, OR type, and AND type.
[0011]
As shown in FIG. 1, the nonvolatile semiconductor device includes a semiconductor substrate 1 of a first conductivity type and an impurity diffusion layer of a second conductivity type formed on the surface of the semiconductor substrate 1 so as to be separated from and opposed to each other. A source region 7 and a drain region 8 are provided.
[0012]
The floating gate 3 is formed between the source region 7 and the drain region 8 on the semiconductor substrate 1 via the gate insulating film 2. On the floating gate 3, a control gate 5 is formed via an insulating film 4.
[0013]
An insulating film 10 is formed on the surfaces of the floating gate 3 and the control gate 5, and side wall insulating films 11 and 12 are formed on the side walls.
[0014]
The semiconductor substrate 1 is formed of, for example, p-type silicon, and the source region 7 and the drain region 8 are formed of n-type silicon. The floating gate 3 and the control gate 5 are formed of polysilicon. The insulating films 2, 4, 10, and 11 are formed of, for example, silicon oxide.
[0015]
In the semiconductor substrate 1 below the drain region 8, a low dielectric constant region 9 having a lower dielectric constant than the semiconductor substrate 1 is arranged.
[0016]
Of the interface between the low dielectric constant region 9 and the semiconductor substrate 1, the first interface A facing the source region 7 is located at the end 100 of the drain region 8 facing the source region 7 (hereinafter referred to as the drain end). It is formed so as to be located in the vicinity.
[0017]
Further, of the interfaces between the low relative dielectric constant region 9 and the semiconductor substrate 1, the second interface B facing the surface of the semiconductor substrate 1 is at least 0.01 μm or more away from the surface of the semiconductor substrate 1.
[0018]
As described above, the region 9 having a lower relative dielectric constant than the semiconductor substrate 1 is formed near the drain end 100 so as to have the first interface A in contact with the channel region. The electric field concentration inside becomes large. That is, since the drain end 100 is located in a region where the electric field concentration is large, the amount of hot electrons generated here increases, so that the operation speed can be improved.
[0019]
Here, as the low relative dielectric constant region 9, a void formed in the semiconductor substrate 1 can be used. The void has a relative dielectric constant of approximately 1. Therefore, since the dielectric constant is sufficiently smaller than the relative dielectric constant of the semiconductor substrate 1 (for example, silicon), electric field concentration is effectively generated. Alternatively, the void may be filled with an insulator having a low relative dielectric constant.
[0020]
The magnitude of the electric field concentration at the drain end 100 described above varies depending on the positions of the first interface A and the second interface B in the low relative dielectric constant region 9. This will be described below.
[0021]
First, the tz dependence of the electric field concentration at the drain end 100 will be described. Here, tz is the distance between the surface of the semiconductor substrate 1 and the second interface B.
[0022]
FIG. 2 is a diagram showing a lateral electric field distribution at the drain end 100 when tz = 10 nm, tz = 30 nm, and the low relative dielectric constant region 9 does not exist. The drain end 100 has a depth of 1 nm from the surface of the semiconductor substrate 1. The vertical axis of the table in FIG. 2 indicates the electric field (V / cm), and the horizontal axis indicates the midpoint between the end of the source region 7 facing the drain region 8 (hereinafter, referred to as a source end 101) and the drain end 100. .00.
[0023]
As can be seen from FIG. 2, as the position of the second interface B in the low-cost dielectric region 9 becomes shallower, that is, tz = 30 nm and tz = 10 nm, as compared with the case where the low relative dielectric constant region 9 does not exist, The transverse electric field is increasing.
[0024]
3A and 3B show the distribution of the electric field potential near the drain end 100 by contour lines. FIG. 3A shows the case where there is no low relative permittivity region 9, FIG. 3B shows the case where tz is 30 nm, and FIG. Indicates the case where tz is 10 nm.
[0025]
As shown in FIG. 3, the contour lines of the electric field potential on the low relative dielectric constant region 9 decrease tz, that is, as the second interface B of the low relative dielectric constant region 9 approaches the surface of the semiconductor substrate 1, the density increases. You can see that it is.
[0026]
The electric field concentration increases as tz decreases, that is, as the second interface B in the low relative dielectric constant region 9 approaches the surface of the semiconductor substrate 1.
[0027]
FIG. 4 shows the relationship between tz and the maximum value (V / cm) of the lateral electric field at the drain end 100 when the distance tx between the first interface A and the gate end in the low dielectric constant region 9 is 0.03 μm. It is a figure showing a relation.
[0028]
As shown in FIG. 4, it can be seen that the electric field concentration increases as the distance tz between the second interface B and the surface of the semiconductor substrate 1 decreases. However, naturally, if the low dielectric constant region 9 is brought into excessive contact with the surface of the semiconductor substrate 1, the current is blocked because the thickness of the drain region 8 at the drain end 100 becomes thin, and the resistance is increased. turn into. Therefore, it is necessary to make tz large enough not to reduce the drain current.
[0029]
For that purpose, it is necessary to set tz so that the electron concentration in the drain region 8 on the low dielectric constant insulating region 9 does not decrease so much. This may be set, for example, as described below.
[0030]
FIG. 5 is a graph showing tz on the horizontal axis and electron concentration on the vertical axis.
[0031]
As shown in FIG. 5, the electron density distribution in the depth direction n (tz) _shows a maximum at _{Z max.} And
n (tz) / n (Z _max ) = α (1)
far. tz is at a position deeper than Z _max, so that this α is sufficiently small, may be set tz. That is, n (z) is given, for example, as follows.
[0032]
^{n (z) = (b 3} /2) Z 2 e -bz ··· (2)
From the equation (2), it is given that Z _max = 2 / b. The width of the inversion layer is given as <z> = 2 / b. Usually, <z> = about 2 nm. In this case, for example, if tz = 10 nm, α = (15/2) ² e ⁻¹³ from the equation (1), and α is sufficiently small. Alternatively, the value of α may be set in advance, and tz may be obtained from equation (1).
[0033]
As can be seen from the above discussion, it is usually sufficient if tz = about 0.01 μm. However, if the second interface B of the low dielectric constant region 9 is present at a position shallower than 0.01 μm, the electron concentration becomes inadequate. Will be enough. Therefore, the present invention specifies that the second interface B is separated from the surface of the semiconductor substrate 1 by 0.01 μm or more.
[0034]
Next, the tx dependency of the electric field concentration will be described.
[0035]
FIG. 6 shows the first interface A of the low relative dielectric constant region 9 and the gate side wall when the distance tz between the second interface B in the low relative dielectric constant region 9 and the surface of the semiconductor substrate 1 is 0.01 μm. FIG. 5 is a diagram showing a relationship between a distance tx between the first and second electrodes and a maximum value (V / cm) of a lateral electric field at a drain end 100.
[0036]
As shown in FIG. 6, tx dependence is observed in the magnitude of the electric field concentration.
[0037]
7A and 7B show the distribution of the electric field potential near the drain end 100 by contour lines. FIG. 7A shows the case where the low relative dielectric constant region 9 is not provided, FIG. 7B shows the case where tx is 0.1 μm, and FIG. c) shows the case where tx is 34 nm.
[0038]
As shown in FIG. 7, the contour lines of the electric field potential at the drain end 100 located on the low dielectric constant region 9 may become dense as tx approaches the drain end 100 (tx = 0.034 μm). I understand.
[0039]
For this reason, the lateral electric field shows the dependence as shown in FIG.
[0040]
FIG. 8 shows the maximum value of the lateral electric field as a function of tx. When tx is set at the position where the horizontal electric field becomes maximum when there is no low dielectric constant region, that is, when the drain end 100 is set to tx, the horizontal electric field becomes maximum. Therefore, it is desirable to set the first interface A of the low relative dielectric constant region 9 as close to the drain end 100 as possible.
[0041]
In an actual device design, tx and tz are set by the following process.
[0042]
First, the specifications for the threshold fluctuation after the writing / erasing of the hot carrier under the designated control gate voltage / drain voltage are determined from the requirements for the device performance.
[0043]
Next, the magnitude of the gate current that causes the required threshold fluctuation is determined. The maximum value of the lateral electric field is set so that the gate current is at the required level, and tx and tz are determined using FIGS. 4 and 8 so as to provide the maximum value of the lateral electric field.
[0044]
Here, when drawings corresponding to FIGS. 4 and 8 are created for a device different from the present embodiment, the maximum value of the lateral electric field itself and its tx dependency and tz dependency are shown in FIG. Note that it is generally different from that shown in FIG. 4 and 8 need to be created for each device structure.
[0045]
Next, a method for manufacturing the nonvolatile semiconductor memory device of the present invention will be described with reference to FIG.
[0046]
Here, a void filled with air was formed as the low dielectric constant region 9.
[0047]
First, as shown in FIG. 9A, a trench 200 is formed on the surface of the p-type silicon substrate 1. The trench 200 may be formed by forming a mask on the silicon substrate 1 and using anisotropic etching.
[0048]
Next, as shown in FIG. 9B, the substrate 1 is subjected to a heat treatment in a hydrogen atmosphere. By doing so, the trench surface is smoothed, and a void 9 filled with air is formed inside the silicon substrate 1. This is a low relative dielectric constant region having a lower relative dielectric constant than the semiconductor substrate 1.
[0049]
Next, as shown in FIG. 9C, an insulating film 2 is formed on the p-type silicon substrate 1, a floating gate 3 is formed via the first insulating film 2, and further, on the floating gate 3, A second insulating film 4 is formed, and a control gate 5 is formed on the second insulating film 4 in a laminated manner. The floating gate 3 and the control gate 5 may be formed of polysilicon, metal, or the like. The insulating films 2 and 4 may be formed using silicon oxide. The gate portion can be formed by a mask process after successively depositing the respective layers.
[0050]
Next, as shown in FIG. 9D, a region including the floating gate 3 and the control gate 5 is covered with an insulating film 10. Silicon oxide can be used for the insulating film 10. In addition, a film can be formed using a CVD method.
[0051]
Next, as shown in FIG. 9E, an n-type source region 7 and an n-type drain region 8 are formed by ion implantation via the insulating film 10.
[0052]
Next, as shown in FIG. 9F, sidewall nitride films 111 and 12 are formed.
[0053]
Note that the ion implantation for forming the source region 7 and the drain region 8 may be performed after the sidewall nitride films 11 and 12 are formed.
[0054]
Next, another method for manufacturing the nonvolatile semiconductor memory device of the present invention will be described with reference to FIG. In this manufacturing method, the low relative dielectric constant region 9 is made of an insulating film having a dielectric constant smaller than that of silicon.
[0055]
First, as shown in FIG. 10A, a trench 200 is formed on the surface of the p-type silicon substrate 1. The trench 200 may be formed by forming a mask on the silicon substrate 1 and using anisotropic etching.
[0056]
Next, as shown in FIG. 10B, the surface of the silicon substrate 1 in which the trench 200 is formed is oxidized.
[0057]
Next, as shown in FIG. 10C, a mask is formed on the trench 200 by depositing a resist on the silicon substrate 1 and patterning the resist. By performing etching using the mask 14, only the insulating film formed in the region other than the trench 200 is removed.
[0058]
Next, as shown in FIG. 10D, a resist 16 is deposited and patterned.
[0059]
Next, as shown in FIG. 10E, the insulating film 17 is patterned by etching using the resist 16 as a mask. Here, the width of the insulating film 17 can be adjusted by adjusting the position of the resist 16.
[0060]
Next, as shown in FIG. 10F, the low relative dielectric constant region 9 is formed by etching back the insulating film 17. Here, by adjusting the etching amount of the insulating film 17, the position of the low relative dielectric constant region 9 in the depth direction can be adjusted.
[0061]
Next, as shown in FIG. 10 (g), a silicon layer not doped with an impurity is deposited, and the surface is flattened by CMP, so that the silicon substrate 1 is made of a material having a lower relative dielectric constant. A low dielectric constant region 9 is formed. As another method of forming this structure, the silicon region in the trench may be used as a seed for epitaxial growth.
[0062]
In these steps, the nonvolatile semiconductor memory device of the present invention is completed through the steps described in the above manufacturing method.
[0063]
【The invention's effect】
As described above, according to the present invention, the concentration of an electric field near the drain end can be increased, so that a non-volatile semiconductor device in which the gate current due to hot carriers increases and the writing efficiency is improved can be provided.
[Brief description of the drawings]
FIG. 1 is an element structure sectional view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a distribution of a lateral electric field in a channel according to the embodiment of the present invention.
FIG. 3 is a diagram showing a potential distribution in the embodiment of the present invention.
FIG. 4 is a diagram showing the dependence of the maximum value of the channel lateral electric field on the position in the depth direction in the embodiment of the present invention.
FIG. 5 is a diagram showing a distribution of inversion layer electrons in a channel in a depth direction according to the embodiment of the present invention.
FIG. 6 is a diagram showing a distribution of a lateral electric field in a channel according to the embodiment of the present invention.
FIG. 7 is a view showing a potential distribution in the embodiment of the present invention.
FIG. 8 is a diagram showing the dependence of the maximum value of the channel lateral electric field on the position in the lateral direction in the embodiment of the present invention.
FIG. 9 is a diagram showing a manufacturing method according to the embodiment of the present invention.
FIG. 10 is a diagram showing another manufacturing method according to the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Insulating film 3 ... Floating gate 4 ... Insulating film 5 ... Control gate 7 ... Source region 8 ... Drain region 9 ... Low relative permittivity Region 10: insulating film 11: sidewall insulating film 12: sidewall insulating film 100: drain end

Claims (2)

A first conductivity type semiconductor substrate;
A source region and a drain region formed on the surface of the semiconductor substrate facing each other and facing each other;
A floating gate formed on the semiconductor substrate between the source region and the drain region via an insulating film;
A control gate formed on the floating gate,
A low dielectric constant region having a lower dielectric constant than the semiconductor substrate formed in the semiconductor substrate below the drain region,
The non-volatile semiconductor memory device according to claim 1, wherein the low dielectric constant region is at least 0.01 μm or more away from the surface of the semiconductor substrate, and an end near the source region exists on the drain region side. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said low relative permittivity region is a void formed in said semiconductor substrate.

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