JP2004079093A - Timing circuit, and variation method of clock period - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing circuit of which the power consumption is low and the clock period can be varied. <P>SOLUTION: This timing circuit comprises a clock generator 11, comparators 12, 13 comparing inputted control voltage TDV with reference voltage VR, holding circuits 18, 19 holding an output of the comparator, and circuits 20, 21, 22 generating a timing pulse TDT outputted from an output of the holding circuit and a clock outputted by a clock generator. The comparator receives a first clock SS outputted by the clock generator, and is operated only for a time corresponding to a short pulse width of the first clock SS. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
[Industrial applications]
The present invention generally relates to a timing circuit (control method) capable of varying a clock cycle according to an input signal (control voltage), and more particularly, to a DRAM refresh cycle according to temperature. And a timing circuit (method) for controlling the timing.
[0002]
[Prior art]
In a DRAM, data is charged to a capacitor of a cell as electric charge, and the data (electric charge) is lost as a leakage current with time. Therefore, a refresh operation for periodically rewriting (charging) the data (charge) of the cell is required.
[0003]
Generally, the higher the temperature, the faster the data in the DRAM cell is lost. Therefore, a short cycle is generally selected as the cycle of the refresh operation so that data is sufficiently retained even at the maximum operating temperature of the chip including the DRAM. Therefore, irrespective of the actual operating temperature of the chip, the refresh is always performed in the selected short cycle, so that the power consumption accompanying the refresh increases.
[0004]
For example, in general, the data retention characteristics of a DRAM are such that the data retention (retention) time is approximately doubled every time the chip temperature drops by 10 ° C. In other words, refreshing every 15.6 microseconds at the maximum operating temperature of 70 ° C. which is set in the normal specification is good at about 500 microseconds of 32 times (2 × 5) at a low temperature of 20 ° C. Therefore, in many cases, the refresh is performed at a frequency ten times or more than the actually required period (frequency) in the data holding mode, even though the temperature is low, and wasteful power is consumed ten times or more. . Therefore, it is necessary to reduce unnecessary power consumption accompanying refreshing at room temperature or a relatively low temperature.
[0005]
As a method for reducing the wasteful power consumption accompanying the refresh, there is a method of obtaining a refresh cycle corresponding to the temperature of a chip having a DRAM. FIG. 1 is a diagram showing an example of a conventional circuit for monitoring a chip temperature and obtaining a DRAM refresh cycle according to the monitored temperature. FIG. 1A is a block diagram of a circuit. A ring oscillator 1 composed of a multi-stage inverter is provided at the center, and its oscillation cycle is buffered and its output (TDT) 2 is used as a temperature-dependent timer to determine the refresh cycle. In FIG. 1A, an operational amplifier 3 compares and amplifies a difference between a constant reference voltage VR such as a bandgap which does not depend on temperature and a voltage having a temperature dependency such as a threshold voltage Vt of a MOS transistor. Is a method of changing the cycle of FIGS. 1B and 1C show configuration examples for changing the cycle of the ring oscillator 1. (B) is a method of controlling the supply current of the inverter, and (C) is a method of changing the RC constant of the load of each inverter. In these methods, when the temperature decreases, the period for automatically refreshing becomes longer, and the refresh current can be reduced.
[0006]
In the conventional circuit example shown in FIG. 1, an analog circuit such as a current mirror is required for the operational amplifier 3, and a DC current of about several tens of micro-A flows. Normally, since the temperature is constantly monitored, the DC current always flows. As a result, even if the refresh current itself can be reduced, the total current in the data holding mode of the DRAM does not decrease but increases instead due to the increase in current consumption accompanying the circuit operation of FIG. There is also fear. That is, even if the refresh current is reduced, if the temperature monitoring circuit itself consumes a large current, the total current in the data retention mode of the DRAM will not decrease. This problem is particularly serious in a device or the like where the total current in the data holding mode of the DRAM is battery-driven.
[0007]
Further, the range of the cycle that can be controlled by the output voltage range of the operational amplifier 3 in FIG. 1 is limited. That is, at a low temperature, a cycle that is several times longer than the minimum cycle at a high temperature is required. However, in the circuit of FIG. 1, it is difficult to change the cycle in such a wide range, and the ideal refresh current at a low temperature is ideal. Cannot be reduced significantly.
[0008]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the related art, and an object of the present invention is to provide a timing circuit capable of changing a clock cycle with low power consumption.
[0009]
It is another object of the present invention to reduce the current of the temperature monitor circuit and to reduce (reduce) the refresh current by changing (extending) the refresh cycle according to the temperature, thereby reducing the total data holding current of the DRAM. To provide means and methods for doing so.
[0010]
[Means for Solving the Problems]
According to the present invention, there is provided a timing circuit (10) for generating a clock that varies in accordance with a temperature, the detection circuit including a detection circuit capable of detecting a temperature at a predetermined sampling cycle. Provides a timing circuit having a feature of operating only for a time corresponding to a short pulse width of a clock (SS) displaced at a sampling cycle to perform temperature detection.
[0011]
According to the present invention, more specifically, a clock generator (11), comparators (12, 13) for comparing an input control voltage (TDV) with reference voltages (VR1, 2), and outputs of the comparators And a timing circuit (10) including a circuit (19, 20, 21) for generating a timing pulse output from the output of the holding circuit and the clock output from the clock generator. Provided.
[0012]
Further, according to the present invention, there is provided a method for changing a clock cycle, comprising: (a) preparing a basic clock; (b) detecting a temperature at a predetermined sampling cycle; c) changing the period of the basic clock according to the detected temperature.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described by taking a temperature monitor of a chip as an example. However, the present invention is not limited to this, and a physical quantity such as pressure is monitored, and the change is defined as a voltage value (control voltage). It can be applied to anything available. Further, it is needless to say that the timing pulse obtained by the present invention can be applied not only to the refresh cycle of the DRAM but also to any application (apparatus or the like) in which the timing is to be changed according to a changing physical quantity.
[0014]
Prior to a specific description, a description will be given of a knowledge about a change in temperature of an IC chip including a DRAM and the like, which is one starting point of the invention. When monitoring the temperature of the chip and considering changing the refresh cycle, the speed of the temperature change is important. In this regard, the change in chip temperature is relatively slow. When the temperature rises, the heat source is the current consumption of the chip itself, the surrounding heat-generating components, the ambient ambient temperature, etc.The rate of rise is determined by this and the heat capacity including the chip package, so the temperature rises so quickly Does not go up. For example, it generally takes several tens of seconds to several minutes to increase from about 20 ° C. to the maximum operating temperature of 70 ° C. This means that if the temperature rise is slow, there is no need for the temperature monitor to constantly monitor anything, and if the temperature is monitored in a sampling manner at a time interval that is sufficiently short compared to the rise speed, the temperature at that time will be around the time. It is meant to represent the temperature for a significant amount of time. Similarly, when the temperature decreases, the rate of change is low.
[0015]
DRAMs typically have a timer (timing) for refreshing that occurs every 15.6 microseconds. This 15.6 microseconds is a time defined assuming a refresh cycle at the maximum operating temperature of the DRAM. Even if the timer is monitored at the cycle of the timer or at a cycle of n times (n: an arbitrary natural number, for example, n = 2 to 4), this timer is sufficiently shorter than the temperature change rate on the order of seconds or more. Can be used for triggers. In the present invention, utilizing this knowledge, the temperature monitor circuit consuming current is not always operated, but is operated only for a short time (pulse width) of, for example, about 1 microsecond or less, and the refresh cycle is set based on the result. By changing it, the current increase in the control circuit is suppressed, and the data holding current at a relatively low temperature is reduced.
[0016]
FIG. 2 is a diagram showing one embodiment of the timing circuit of the present invention. FIG. 3 is a diagram showing a timing chart of the timing circuit of FIG. FIG. 2 assumes an oscillation output BT from a base timer (oscillator, not shown) having a fixed period of, for example, 15.6 microseconds. The oscillation output BT of the base timer enters the delay & single shot circuit 11. The delay & single shot circuit 11 generates a single shot pulse SS at the rising edge of the oscillation output BT, and delays the oscillation output BT by a time corresponding to the pulse width of the single shot pulse SS. Is generated (see FIG. 3). The pulse width of the shot pulse SS may be several microseconds or less (for example, 1 microsecond). Note that the cycle of the oscillation output BT output from the base timer is not limited to 15.6 microseconds, and any cycle such as n times 15.6 microseconds (n: natural number) can be assumed. Further, the delay & single shot circuit 11 may be provided with a function of generating an arbitrary cycle such as n times 15.6 microseconds (n: natural number).
[0017]
CM1 and CM2 (symbols 12 and 13) in FIG. 2 are analog comparison circuits (comparators) such as current mirrors. The comparators 12 and 13 compare a temperature-dependent monitor voltage TDV such as a threshold voltage Vt of the transistor with reference voltages VR1 and VR2 that do not depend on temperature such as a bandgap voltage. Here, it is assumed that VR1> VR2, and TDV decreases as the temperature decreases like Vt. Further, at a high temperature such as 70 ° C., the outputs of the comparators 12 and 13 are high, the output of the comparator 12 (CM1) becomes low when VR1> TDV, and the output of the comparator 13 (CM2) becomes low when VR2> TDV. . The output stage of each of the comparators 12 and 13 is composed of a buffer circuit, and outputs a CMOS full swing potential.
[0018]
The comparators 12 and 13 are connected to ground (GND) via NMOSs 14 and 15. The outputs of the comparators 12 and 13 are connected to latches 18 and 19 via NMOSs 16 and 17, respectively. The gates of the NOMSs 14 to 17 are all connected to the single shot pulse (SS) output of the delay & single shot circuit 11. Therefore, the analog comparison circuits 12 and 13 operate only when the single shot pulse SS arrives, and for other long periods of time, the NMOSs 14 and 15 on the GND side are OFF and no standby current flows. As a result, unnecessary current consumption can be reduced.
[0019]
The latches 18 and 19 hold the comparison result output of the comparators 12 and 13. The outputs of the latches 18 and 19 are input to a counter 20. The outputs (inverted data) of the latches 18 and 19 are input to C1 and C2 of the counter 20, and are held. Then, it is updated every single shot pulse SS input to the counter 20. The counter 20 is a two-bit counter of C10 and C20. The counter 20 counts up at the edge when the input pulse SS becomes high, and the output C10 becomes LSB and the output C20 becomes MSB. Outputs C10 and C20 of the counter 20 are connected to an AND circuit 21. The AND timer 21 also receives the delay timer output DT of the delay & single shot circuit 11. In FIG. 2, a reset circuit 22 is further provided between the latches 18 and 19 and the counter 20.
[0020]
The operation of the circuit of FIG. 2 will be described with reference to the timing chart of FIG. FIG. 3 shows an example of timing when the temperature of the chip is at a high temperature (maximum operating temperature) such as 70 ° C., and then the temperature decreases over time. In other words, this is a timing example in a case where the cycle becomes longer as the temperature decreases. First, since the temperature is high between times T1 and T2, the outputs C1 and C2 of the latches 18 and 19 are both LOW, and the output TDT of the AND circuit delays the oscillation output BT of the base timer by the pulse width of the single shot SS. Generated at the same cycle of 15.6 microseconds as the signal (DT).
[0021]
When the temperature drops and the comparator 12 senses VR1> TDT at the timing of the SS pulse at time T3, the output of the comparator 12 becomes LOW, and HIGH is latched as the output C1 of the latch 18. When C1 changes from LOW to HIGH, a HIGH pulse is output from the output RS of the reset circuit 22, and both the counter outputs C10 and C20 are reset to HIGH. In FIG. 3, although C10 and C20 do not seem to have changed at T3, both have been HIGH since before, because they have been reset to HIGH. Here, the counter outputs C10 and C20 become “11”, and at T4 when the next SS comes, the LSB C10 becomes LOW. Therefore, at T4, no DT pulse is output as the output TDT of the AND circuit 21. At the next SS of T5, C10 counts up and becomes HIGH. At this time, since the temperature is in the range of VR1>TDV> VR2, since the output of the comparator 13 remains LOW, the output C20 of the latch 19 is output. Is HIGH. Therefore, since a pulse DT is output as the output TDT of the AND circuit 21 at T5, the period is 31.2 microseconds, which is twice as large as 15.6 microseconds.
[0022]
Next, before T6, the temperature further decreases, and when VR2> TDT, the output of the comparator 13 becomes LOW at T6 and the latch output becomes C2HIGH. With the change of C2, the counter is reset by the output RS of the reset circuit 22, and the counter outputs C10 and C20 become "11". Therefore, at T6, a pulse DT is output as the output TDT of the AND circuit 21. Then, since the 2-bit counter operation starts from here, it is T10 at which the outputs C10 and C20 are both HIGH that the TDT next issues a DT high pulse. As a result, when the temperature drops to the extent that VR2> TDV, the TDT pulse has a period of 62.4 microseconds, which is four times 15.6 microseconds.
[0023]
In FIG. 3, in order to explain these operations in a short timing chart, it is assumed that the temperature has passed the reference level at T3 and T6, but the temperature change actually takes more time. The role of the reset circuit 22 is to always count up the counter from 11 when the cycle changes. Otherwise, depending on the timing, the cycle may be longer than the value determined temporarily. For example, when C20 of the counter 20 is LOW at T7 instead of T6, if not reset, both C10 and C20 become LOW at T7, and the counter counts up from "00". Then, C10 and C20 become "11" at T10, but since there is no pulse at T6, only the first cycle is 78 microseconds and 62.4 microseconds determined thereafter, resulting in unstable operation. Cause The reset circuit prevents this unstable operation.
[0024]
In the timing circuit of the present invention, the analog circuits (comparators 12 and 13) that consume current are turned on only during the pulse width of the clock SS, so that power consumption can be significantly reduced. For example, if the width of SS is about 1 microsecond, the analog circuits (comparators 12 and 13) can operate satisfactorily, and this time is sufficiently shorter than 15.6 microseconds of the base timer. The average current consumption is 1 / 15.6. Further, as the temperature sampling interval, several times (for example, 2 to 4 times) as much as the temperature change rate is sufficient, and if sampling is performed at such a period, the average current consumption is 1 even in an analog circuit that flows several tens of microamperes. It can be less than a microampere.
[0025]
In addition, here, for simplicity, a 2-bit counter has been described. However, by increasing the number of bits, the reference voltage VR can be subdivided. The period variable range can be easily expanded to 8 or 16 times. Further, as an embodiment, a multiple conversion of the period by the counter is used, but the present invention is not limited to this, and the temperature is measured by sampling, and the result is directly stored in the latches 18 and 19 in a digital amount. Other methods of changing the period by using can also be used.
[0026]
【The invention's effect】
(1) Includes a detection circuit capable of detecting a physical quantity such as temperature at a predetermined sampling cycle, and the detection circuit operates for a time corresponding to a short pulse width of a clock displaced at the sampling cycle to perform detection. The power consumption at the time of detection can be greatly reduced.
(2) For example, in the embodiment of FIG. 2, the reference voltage VR can be subdivided by increasing the number of bits of the counter, so that 3 bits are 2, 4, 8 times, and 4 bits are 2, 4, 8, The cycle variable range can be easily expanded as 16 times.
(3) When employed for refreshing a DRAM, the refresh cycle can be optimized according to the temperature, and the power consumption during refresh can be reduced.
(4) When the present invention is used in a battery-powered portable terminal or the like, it is possible to contribute to a substantial extension of the battery life by reducing power consumption.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a conventional circuit for obtaining a DRAM refresh cycle corresponding to a monitor temperature of a chip.
FIG. 2 is a diagram showing one embodiment of a timing circuit of the present invention.
FIG. 3 is a diagram showing a timing chart of the timing circuit of FIG. 2 of the present invention.
[Explanation of symbols]
Reference Signs List 1 ring oscillator 3 operational amplifier 10 timing circuit 11 delay & single shot circuit 12, 13 comparator 14, 15, 16, 17 NMOS
18, 19 Latch 20 Counter 21 AND circuit 22 Reset circuit

Claims (14)

A clock generator;
A comparator for comparing the input control voltage with a reference voltage,
A holding circuit for holding an output of the comparator,
A timing circuit comprising: an output of the holding circuit; and a circuit that generates a timing pulse that is output from a clock output by the clock generator. The timing circuit according to claim 1, wherein the comparator receives a first clock output from the clock generator, and operates for a time corresponding to a short pulse width of the first clock. The circuit for generating the timing pulse includes:
A counter receiving the output of the holding circuit and the first clock output by the clock generator;
2. The timing circuit according to claim 1, further comprising: a logic circuit receiving an output of the counter and a second clock output from the clock generator. 4. The timing circuit according to claim 3, further comprising a circuit for receiving an output of said holding circuit and sending a reset signal to said counter. The comparator comprises:
A first comparator receiving a first reference voltage and the control voltage,
A second comparator receiving a second reference voltage and the control voltage,
The timing circuit according to claim 1, further comprising: The holding circuit,
A first latch circuit receiving an output of the first comparator;
A second latch circuit receiving an output of the second comparator;
6. The timing circuit according to claim 5, comprising: 4. The timing circuit according to claim 3, wherein said logic circuit includes an AND circuit. A timing circuit for generating a clock that varies in accordance with temperature, the timing circuit including a detection circuit capable of detecting the temperature at a predetermined sampling period, wherein the detection circuit is displaced at the sampling period. A timing circuit which operates for a time corresponding to a short pulse width of a clock to perform temperature detection. A timing circuit for controlling a refresh cycle of the DRAM in accordance with the temperature, the detection circuit being capable of detecting the temperature at a predetermined sampling cycle; A timing circuit which operates for a time corresponding to a short pulse width of a clock to perform temperature detection. 10. The timing circuit according to claim 9, wherein the sampling cycle is a cycle determined by Txn (n: any natural number) with respect to a refresh cycle T at a maximum operating temperature of the DRAM. A method for changing a period of a clock, the method comprising:
(A) preparing a basic clock;
(B) detecting the temperature at a predetermined sampling cycle;
(C) changing the cycle of the basic clock according to the detected temperature;
A method that includes (B) detecting the temperature;
12. The method of claim 11, comprising detecting temperature for a time corresponding to a short pulse width of a clock displaced at the sampling period. (C) changing the period of the basic clock,
12. The method of claim 11, comprising generating a long-period clock by increasing pulses that are decimated from the base clock in response to the detected decrease in temperature. The sampling period is a period determined by Txn (n: an arbitrary natural number) with respect to the period T of the basic clock. The natural number n is set to a large value when the temperature change speed is slow, and The method of claim 11, wherein the value is set to a small value when the speed is high.

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