JP3870139B2 - Timing circuit for controlling refresh cycle of DRAM - Google Patents

Description

[0001]
[Industrial application fields]
The present invention generally relates to a timing circuit (control method) that can vary a clock cycle according to an input signal (control voltage), and more particularly, a DRAM refresh cycle according to temperature. The present invention relates to a timing circuit (method) for controlling.
[0002]
[Prior art]
In a DRAM, data is charged as a charge in a cell capacitor, and the data (charge) is lost as a leakage current with time. For this reason, a refresh operation for periodically rewriting (charging) cell data (charge) is required.
[0003]
Generally, the higher the temperature is, the faster the data in the DRAM cell is lost. Therefore, as a cycle of the refresh operation, a short cycle is usually selected so that data is sufficiently retained even at the maximum operating temperature of the chip including the DRAM. Therefore, refresh is always performed in the selected short period regardless of the actual operating temperature of the chip, so that the power consumption accompanying the refresh increases.
[0004]
For example, the data retention characteristic of DRAM generally has a data retention (retention) time approximately doubled every time the chip temperature decreases by 10 ° C. In other words, refreshing every 15.6 microseconds at the maximum operating temperature of 70 ° C. set in the normal specification is good every about 500 microseconds, which is 32 times (2 5 times) at a low temperature of 20 ° C. Therefore, in many cases, the data holding mode is refreshed at a frequency 10 times or higher than the actually required cycle (frequency) even though the temperature is low, and the wasteful power is consumed 10 times or more. . Therefore, it is necessary to reduce wasteful power consumption associated with refreshing at room temperature or a relatively low temperature.
[0005]
As a method for reducing wasteful power consumption associated with this refresh, there is a method of obtaining a refresh cycle corresponding to the temperature of a chip having a DRAM. FIG. 1 is a diagram showing an example of a circuit for monitoring a conventional chip temperature and obtaining a DRAM refresh period corresponding to the monitored temperature. FIG. 1A is a block diagram of a circuit. There is a ring oscillator 1 consisting of a multi-stage inverter in the center, and this oscillation cycle is buffered and its output (TDT) 2 is used as means for determining a refresh cycle using a temperature-dependent timer. In FIG. 1A, the operational amplifier 3 compares and amplifies the difference between a constant reference voltage VR that does not depend on temperature, such as a band gap, and a voltage that has temperature dependence, such as a threshold voltage Vt of a MOS transistor, and the ring oscillator 1 This is a method of changing the period of the. 1B and 1C show configuration examples for changing the cycle of the ring oscillator 1. (B) is a method for controlling the supply current of the inverter, and (C) is a method for changing the RC constant of the load of each inverter. In these methods, when the temperature is lowered, the refresh cycle is automatically extended, and the refresh current can be lowered.
[0006]
In the conventional circuit example shown in FIG. 1, the operational amplifier 3 requires an analog circuit such as a current mirror, and a DC current of about several tens of micro-A flows. Usually, since the temperature is constantly monitored, the DC current always flows. As a result, even if the refresh current itself can be reduced, the total current in the data retention mode of the DRAM does not decrease but increases conversely due to the increase in current consumption accompanying the circuit operation of FIG. There is also a fear. That is, even if the refresh current is reduced, if the circuit for monitoring the temperature itself consumes a large current, the total current in the data holding mode of the DRAM will not decrease. This problem is particularly serious in a battery-driven device or the like in which the total current in the data retention mode of the DRAM is.
[0007]
Further, the range of the period that can be controlled by the output voltage range of the operational amplifier 3 in FIG. 1 is limited. In other words, a cycle that is several times longer than the minimum cycle at a high temperature is required at low temperatures, but it is difficult to vary the cycle over such a wide range in the circuit of FIG. Cannot be reduced.
[0008]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a timing circuit that can vary the clock cycle with low power consumption.
[0009]
Furthermore, the object of the present invention is to reduce the current of the temperature monitor circuit and reduce the refresh current by changing (extending) the refresh cycle according to the temperature, thereby reducing the total data retention current of the DRAM. It is to provide means and methods for doing this.
[0010]
[Means for Solving the Problems]
According to the present invention, a timing circuit (10) for generating a clock variable according to temperature, including a detection circuit capable of detecting temperature at a predetermined sampling period, the detection circuit Provides a timing circuit having the feature of operating for a time corresponding to a short pulse width of a clock (SS) that is displaced in a sampling period to detect temperature.
[0011]
More specifically, according to the present invention, the clock generator (11), the comparators (12, 13) for comparing the input control voltage (TDV) and the reference voltages (VR1, 2), and the output of the comparator And a timing circuit (10) including a holding circuit (18, 19) for holding the signal and a circuit (19, 20, 21) for generating a timing pulse output from the output of the holding circuit and the clock output from the clock generator. Provided.
[0012]
According to the present invention, there is also provided a method for varying the clock period, comprising: (a) preparing a basic clock; (b) detecting temperature at a predetermined sampling period; c) A method is provided comprising the step of changing the period of the basic clock in response to the detected temperature.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described by taking a chip temperature monitor as an example. However, the present invention is not limited to this, and a physical quantity such as pressure is monitored, and the change amount is set as a voltage value (control voltage). It can be applied to anything that is available. Needless to say, the timing pulse obtained by the present invention can be applied not only to the refresh cycle of the DRAM but also to any application (device or the like) whose timing is to be varied according to a changing physical quantity.
[0014]
Before going into a specific description, the knowledge about the temperature change of an IC chip including a DRAM or the like, which is one starting point for devising the present invention, will be described. An important factor in monitoring the chip temperature and changing the refresh cycle is the rate of temperature change. In this regard, the change in chip temperature is relatively slow. When the temperature rises, the heat source is the current consumption of the chip itself, the surrounding heat generating components, the ambient atmosphere temperature, etc., and the rate of increase is determined by this and the heat capacity including the chip package, so the temperature is so sudden Does not rise. For example, it generally takes several tens of seconds to several minutes to increase from about 20 ° C. to the maximum operating temperature of 70 ° C. This means that if the temperature rise is slow, the temperature monitor does not need to be always on, and if the sample is monitored at a sufficiently short time interval compared to the rate of rise, the temperature at that time will be It is meant to represent a considerable time of temperature. Similarly, the rate of change is slow when the temperature drops.
[0015]
DRAM has a timer (timing) for refresh that usually comes every 15.6 microseconds. This 15.6 microseconds is a time defined assuming a refresh cycle at the maximum operating temperature of the DRAM. Even if it is monitored at the cycle of this timer or n times (n: any natural number, for example, n = 2 to 4), it is sufficiently short compared to the temperature change rate of the second order or more. Can be used as a trigger. In the present invention, this knowledge is utilized, and the temperature monitoring circuit that consumes current is not operated at all times, but is operated only for a short time (pulse width) of, for example, 1 microsecond or less, and the refresh cycle is set based on the result. By changing, the increase in the current of the control circuit is suppressed, and the data holding current at a relatively low temperature is reduced.
[0016]
FIG. 2 is a diagram showing an embodiment of the timing circuit of the present invention. 3 is a timing chart of the timing circuit of FIG. FIG. 2 assumes an oscillation output BT from a base timer (oscillator, not shown) having a constant period such as 15.6 microseconds. The base timer oscillation output BT enters the delay & single shot circuit 11. The delay & single shot circuit 11 generates a single shot pulse SS at the rising edge of the oscillation output BT, and a delay timer output DT obtained by delaying the oscillation output BT by the time of the pulse width of the single shot pulse SS. (See FIG. 3). The pulse width of the shot pulse SS may be several microseconds or less (for example, 1 microsecond). The period of the oscillation output BT output from the base timer is not limited to 15.6 microseconds, and an arbitrary period such as n times 15.6 microseconds (n: natural number) can be assumed. Further, the delay & single shot circuit 11 may have a function of generating an arbitrary period such as n times (n: natural number) of 15.6 microseconds.
[0017]
CM1 and CM2 (reference numerals 12 and 13) in FIG. 2 are analog comparison circuits (comparators) such as a current mirror. The comparators 12 and 13 compare the temperature-dependent monitor voltage TDV such as the threshold voltage Vt of the transistor with the temperature-independent reference voltages VR1 and VR2 such as a band gap voltage. Here, it is assumed that VR1> VR2, and that the TDV decreases as the temperature decreases as in Vt. Further, at a high temperature such as 70 ° C., the outputs of the comparators 12 and 13 are high, the output of the comparator 12 (CM1) is LOW when VR1> TDV, and the output of the comparator 13 (CM2) is LOW when VR2> TDV. . The output stages of the comparators 12 and 13 are composed of buffer circuits and output CMOS full swing potentials.
[0018]
The comparators 12 and 13 are connected to the ground (GND) via the NMOSs 14 and 15. The outputs of the comparators 12 and 13 are connected to latches 18 and 19 via NMOSs 16 and 17, respectively. The gates of the NOMS 14 to 17 are all connected to the single shot pulse (SS) output of the delay & single shot circuit 11. Therefore, the analog comparison circuits 12 and 13 operate only when the single shot pulse SS is received, and the NMOSs 14 and 15 on the GND side are OFF for the other long time and the standby current does not flow. As a result, useless current consumption can be reduced.
[0019]
The latches 18 and 19 hold the comparison result outputs of the comparators 12 and 13. The outputs of the latches 18 and 19 are input to the counter 20. The outputs (inverted data) of the latches 18 and 19 are input to and held in C1 and C2 of the counter 20. It is updated every single shot pulse SS input to the counter 20. The counter 20 is a counter consisting of 2 bits of C10 and C20, and is counted up at the edge when the input pulse SS becomes high, the output C10 is LSB, and C20 becomes MSB. The outputs C10 and C20 of the counter 20 are connected to the AND circuit 21. The AND circuit 21 also receives the delay timer output DT of the delay & single shot circuit 11. In FIG. 2, a reset circuit 22 is further provided between the latches 18 and 19 and the counter 20.
[0020]
The operation of the circuit of FIG. 2 will be described with reference to the timing chart of FIG. FIG. 3 shows an example of timing when the temperature of the chip is at a high temperature (maximum operating temperature) such as 70 ° C. and the temperature decreases with time. In other words, this is an example of the timing when the cycle becomes longer as the temperature decreases. First, since the temperature is high during time T1-T2, the outputs C1 and C2 of the latches 18 and 19 are both LOW, and the AND circuit output TDT delays the oscillation output BT of the base timer by the pulse width of the single shot SS. Generated at the same period of 15.6 microseconds as the signal (DT).
[0021]
When the temperature drops and the comparator 12 senses VR1> TDV at the timing of the SS pulse at time T3, the output of the comparator 12 becomes LOW, and HIGH is latched as the output C1 of the latch 18. When C1 changes from LOW to HIGH, a HIGH pulse is output to the output RS of the reset circuit 22, and both the counter outputs C10 and C20 are reset to HIGH. In FIG. 3, it appears that C10 C20 does not change at T3, because both of them were HIGH before that, because they were reset to HIGH. Here, the counter outputs C10 and C20 become “11”, and C10 which is the LSB becomes LOW at T4 when the next SS comes. For this reason, the pulse of DT is not output as the output TDT of the AND circuit 21 at T4. At the next SS of T5, C10 is counted up to become HIGH. At this time, since the temperature is in the range of VR1>TDV> VR2, the output of the comparator 13 remains HIGH , so the output C2 of the latch 19 Is LOW . Therefore, since the pulse DT is output as the output TDT of the AND circuit 21 at T5, the cycle is 31.2 microseconds, which is twice as long as 15.6 microseconds.
[0022]
Then, further lower the temperature before the T6, VR2> output of the comparator 13 at comes to T6 in TDV is to LOW, the output C2 of latch 19 is to HIGH. With this change in C2, the counter is reset by the output RS of the reset circuit 22, and the counter outputs C10 and C20 become “11”. Therefore, at T6, a pulse DT is output as the output TDT of the AND circuit 21. Since a 2-bit counter operation starts from here, the TDT next outputs a high pulse of DT at T10 when both outputs C10 and C20 are high. As a result, when the temperature drops to such an extent that VR2> TDV, the TDT pulse has a period of 62.4 microseconds, which is four times 15.6 microseconds.
[0023]
In FIG. 3, in order to explain these operations in a short timing chart, the temperature has passed the reference level at T3 and T6. However, the temperature change actually takes more time. The role of the reset circuit 22 is to increment the counter from 11 whenever the cycle changes. Otherwise, depending on the timing, the cycle will be longer than the temporarily determined value. For example, if C20 of the counter 20 is LOW at T7 instead of T6, if not reset, both C10 and C20 become LOW at T7, and the counter counts up from “00”. Then, C10 and C20 become “11” at T10, but since there is no pulse at T6, only the first period is 78 microseconds and 62.4 microseconds determined thereafter, which is unstable operation. Cause. The reset circuit prevents this unstable operation.
[0024]
In the timing circuit of the present invention, since the analog circuits (comparators 12 and 13) that consume current are turned on only for the time of the pulse width of the clock SS, power consumption can be greatly reduced. For example, if the width of SS is about 1 microsecond, the analog circuit (comparators 12 and 13) can operate sufficiently, and this time is sufficiently shorter than the base timer 15.6 microseconds. The average current consumption is 1 / 15.6. Furthermore, as the temperature sampling interval, several times (for example, 2-4 times) of the temperature change rate is sufficient, and if the sampling is performed at such a cycle, the average current consumption is 1 even in an analog circuit in which several tens of microamperes flow. Can be below Amicroampere.
[0025]
Further, here, for the sake of simplicity, a 2-bit counter has been described, but by increasing the number of bits, the reference voltage VR can also be subdivided, so that 3 bits are 2, 4, 8 times, 4 bits are 2, 4, The period variable range can be easily expanded as much as 8, 16 times. Furthermore, as an example, a multiple conversion of a period by a counter is used. However, the present invention is not limited to this. The temperature is measured by sampling, and the result is directly stored in the latches 18 and 19 as digital quantities. Other methods of changing the period using can also be used.
[0026]
【The invention's effect】
(1) A detection circuit capable of detecting a physical quantity such as temperature at a predetermined sampling period is included, and the detection circuit operates for a time corresponding to a short pulse width of a clock that is displaced at the sampling period, and performs detection. As a result, power consumption during detection can be greatly reduced.
(2) For example, in the embodiment of FIG. 2, the reference voltage VR can be subdivided by increasing the number of bits of the counter, so that 2, 4, 8 times, 3 bits, 2, 4, 8, 4 bits, The period variable range can be easily expanded as much as 16 times.
(3) When employed for DRAM refresh, the refresh cycle can be optimized in accordance with the temperature, and power consumption during refresh can be reduced.
(4) When the present invention is used for a battery-driven portable terminal or the like, it can contribute to extension of the substantial life of the battery by reducing power consumption.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit example for obtaining a refresh period of a DRAM according to a conventional chip monitor temperature.
FIG. 2 is a diagram illustrating an embodiment of a timing circuit according to the present invention.
FIG. 3 is a diagram showing a timing chart of the timing circuit of FIG. 2 of the present invention.
[Explanation of symbols]
1 Ring Oscillator 3 Op Amp 10 Timing Circuit 11 Delay & Single Shot Circuit 12, 13 Comparator 14, 15, 16, 17 NMOS
18, 19 Latch 20 Counter 21 AND circuit 22 Reset circuit

Claims (5)

A timing circuit that controls the refresh cycle of the DRAM according to temperature,
(A) receiving an oscillation output having a minimum refresh period at the maximum operating temperature of the DRAM, generating a single shot pulse at the rising edge of the oscillation output, and reducing the oscillation output by the width of the single shot pulse A clock generator that generates a delayed delay timer output;
(B) A first reference voltage VR1 representing a temperature lower than the maximum operating temperature and a monitor voltage TDV depending on the temperature of the DRAM are input, and a high level output is generated at the maximum operating temperature, and VR1> TDV A first comparison circuit for generating a low-level output, wherein the first comparison circuit is connected to the ground via a first MOS transistor that is turned on when the single shot pulse is applied to the gate;
(C) The second reference voltage VR2 representing the temperature lower than the maximum operating temperature and lower than the first reference voltage VR1 and the monitor voltage TDV are input, and a high level output is generated at the maximum operating temperature; A second comparison circuit for generating a low level output when VR2> TDV, wherein the second comparison circuit is connected to the ground via a second MOS transistor that is turned on by applying the single shot pulse to the gate. When,
(D) a first latch whose input is connected to the output of the first comparison circuit via a third MOS transistor which is turned on when the single shot pulse is applied to the gate, the output of the first comparison circuit; The first latch holding a signal obtained by inverting
(E) a second latch whose input is connected to the output of the second comparison circuit via a fourth MOS transistor which is turned on when the single shot pulse is applied to the gate, the output of the second comparison circuit; The second latch for holding a signal obtained by inverting
(F) The output of the first latch and the output of the second latch are input, and an output RS is generated in response to the output of the first latch changing from a low level to a high level. A reset circuit for generating the output RS in response to the output of the two latches changing from a low level to a high level;
(G) The output of the first latch, the output of the second latch, the output RS of the reset circuit and the single shot pulse are input, and the first counter output and the second counter output are selectively set to the high level. Or a counter that switches to low level,
(H) An input corresponding to the delay timer output when the first counter output and the second counter output are at a high level when the first counter output, the second counter output and the delay timer output are input. A timing circuit comprising a resulting AND circuit;   The counter until the DRAM temperature falls from the maximum operating temperature and the first comparator produces a low level output when VR1> TDV and the output of the first latch changes to a high level. The AND circuit generates an output corresponding to the delay timer output for each minimum refresh period by maintaining the first counter output and the second counter output at a high level. 2. The timing circuit according to 1.   In response to the output RS generated by the reset circuit in response to the first comparator generating a low level output when VR1> TDV and the output of the first latch is changed to a high level. 2. The AND circuit according to claim 1, wherein the AND circuit generates an output corresponding to the delay timer output by setting the first counter output and the second counter output to a high level. 2. The timing circuit according to 2.   Until the second comparator generates a low level output when VR2> TDV and the output of the second latch changes to a high level, the counter counters the first counter every single shot pulse. 3. The output is switched, and the AND circuit generates an output corresponding to the delay timer output when both the first counter output and the second counter output are at a high level. Alternatively, the timing circuit according to claim 3.   In response to the output RS generated by the reset circuit in response to the second comparator producing a low level output when VR2> TDV and the output of the second latch is changed to a high level. The AND circuit generates an output corresponding to the delay timer output by setting the first counter output and the second counter output to a high level, and then the counter starts a 2-bit counter operation. Then, for each single shot pulse, one or both of the first counter output and the second counter output are changed, and the AND is performed when the first counter output and the second counter output are at a high level. 5. A circuit according to claim 1, 2, 3 or 4, characterized in that a circuit generates an output corresponding to the delay timer output. Timing circuit.

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