JP2004078194A

JP2004078194A - Liquid crystal display panel

Info

Publication number: JP2004078194A
Application number: JP2003201064A
Authority: JP
Inventors: Hsin-Ta Lee; 李欣達; ▲呉▼永良; Yuan-Liang Wu; ▲呉▼震乙; Cheng-I Wu; Wen-Chieh Lin; 林文傑
Original assignee: Chi Mei Electronics Corp
Current assignee: Chi Mei Optoelectronics Corp
Priority date: 2002-08-16
Filing date: 2003-07-24
Publication date: 2004-03-11
Anticipated expiration: 2023-07-24
Also published as: TW594347B; TW200403509A; KR20040016377A; JP4078394B2; KR100931876B1

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display panel which provides the respective pixels of the liquid crystal display panel with nearly the same feedthrough voltages by decreasing flickers in order to solve the various problems by the prior art. <P>SOLUTION: The liquid crystal display panel includes an upper substrate, a lower substrate and a plurality of the pixels disposed between both the upper and lower substrates. The respective pixels have at least one compensation capacitor in order to decrease the flickers of the liquid crystal display panel by respectively obtaining the nearly same feedthrough voltages. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
この発明は液晶表示パネルに関し、特にフリッカーを低減する液晶表示パネルに関する。
【０００２】
【従来の技術】
薄膜トランジスター液晶表示パネルはマトリックス配列の薄膜トランジスターとその他の電子デバイスを利用して液晶ピクセルを駆動し、多彩な映像を表示する。薄膜トランジスターは軽量化、低電力消費、低輻射などの特性をもち、ノートブック型コンピューター、パーソナルデジタルアシスタント（ＰＤＡ）などの携帯型情報製品に幅広く応用され、デスクトップ型コンピューターのブラウン管モニターに取って代わりつつある。
【０００３】
図１と図２を参照されたい。図１は従来の薄膜トランジスター液晶表示パネルを表わす説明図であり、図２は薄膜トランジスター液晶表示パネルにある単一ピクセルの等価回路図である。図１によると、液晶表示パネル１０は下基板１２を具え、下基板１２はピクセルアレイ領域１４と、スキャンライン駆動回路領域１６と、データライン駆動回路領域１８とを含む。ピクセルアレイ領域１４は複数のスキャンライン（図示に示されていない）と複数のデータライン（図示に示されていない）を含み、各スキャンラインと各データラインは図１におけるピクセルＡ〜ＣかピクセルＢ’〜Ｃ’など複数のピクセルを定める。そのうちピクセルＡ〜Ｃは同じスキャンラインと電気的に接続され、ピクセルＡ、Ｂ’、Ｃ’は同じデータラインと電気的に接続される。
【０００４】
図１によれば、スキャンライン駆動回路領域１６は複数のドライバー集積回路チップ（例えばチップ１６ａ〜１６ｃ）と、複数のバスライン１７を含む、各バスライン１７は各ドライバー集積回路チップを接続する。各ドライバー集積回路チップはチップ・オン・ガラス（ＣＯＧ）法で下基板１２の表面に直接的に製作され、各バスライン１７は下基板１２に直接的に製作される。これはいわゆるワイヤー・オン・アレイ（ＷＯＡ）法である。
【０００５】
図２によれば、ピクセル２０は少なくとも一つの液晶セルＬＣと一つの薄膜トランジスターＴＦＴを含む。液晶セルＬＣはピクセル電極と、共通電極ＣＥと、液晶分子層とからなる。薄膜トランジスターはスキャンラインＧＬ_０と接続されるゲート電極と、データラインＤＬ_０と接続されるドレイン電極と、液晶セルＬＣと接続されるピクセル電極とを含む。ゲート電極とソース電極は部分的に重なり合うことによって、ゲート電極とソース電極との間に寄生コンデンサーＧＳが形成される。なお、ピクセル２０は液晶セルＬＣとスキャンラインＧＬ_１と接続される保存コンデンサーＳＣを具え、保存コンデンサーＳＣは、リーク電流が液晶セルＬＣへの電圧に与える影響を緩和し、液晶セルＬＣに電荷を保存させる。
【０００６】
液晶セルＬＣに印加する電圧は光の透過度と一定の関連を持つため、所要の画面によって液晶セルＬＣに電圧を印加すれば、各ピクセルの光透過度を適切に制御することが可能である。それに適当な光源を合わせて、予定の画面が表示される。液晶セルＬＣに印加する電圧は共通電極ＣＥとピクセル電極との間の電圧である。薄膜トランジスターがオフにされた場合、ピクセル電極は、電源に接続されておらず、寄生コンデンサーを通してスキャンラインと接続されており、その電圧が変化する。よって液晶セルに印加する電圧は本来の設定値からかけ離れる。この電圧の変動量はフィードスルー電圧（Ｖ_ＦＤ）と呼ばれ、以下の方程式に表わされる。
【数１】

方程式（１）のＣ_ＬＣは液晶セルＬＣの容量、Ｃ_ＳＣは保存コンデンサーの容量、Ｃ_ＧＳは薄膜トランジスターのゲート電極とソース電極との間の寄生容量、Ｖ_Ｇはスキャンラインに印加するパルス電圧の振幅をそれぞれ表わす。一般に、共通電極ＣＥの電圧を調整すればＶ_ＦＤの影響を小さくできるが、スキャンライン内の抵抗と容量により、スキャンラインに印加するパルス電圧の立ち下がりエッジが丸く（ｒｏｕｎｄｅｄ）なり、Ｖ_ＦＤはピクセルとスキャンラインとの距離の増加とともに小さくなる。言い換えれば、図１におけるピクセルＡ、Ｂ、ＣのＶ_ＦＤ関係は（Ｖ_ＦＤ）_Ａ＞（Ｖ_ＦＤ）_Ｂ＞（Ｖ_ＦＤ）_Ｃになる。そのため、ピクセルのＶ_ＦＤのもたらす影響は共通電極ＣＥの調整によって消去されず、液晶表示パネル１０にはフリッカーが発生する。
【０００７】
なお、スキャンライン駆動回路１６内のバスライン１７は相当の抵抗値を具えるため、パルス電圧がバスライン１７から各ドライバー集積回路チップに入力される場合、各ドライバー集積回路の入力電圧は異なり、ドライバー集積回路チップの出力電圧の波形も異なる。図３によれば、ドライバー集積回路チップ１６ａが出力する電圧（Ｖ_ＧＡ）が最も高く、ドライバー集積回路チップ１６ｂが出力する電圧（Ｖ_ＧＢ）はその次、ドライバー集積回路チップ１６ｃが出力する電圧（Ｖ_ＧＣ）は更に次であり、Ｖ_ＦＤはピクセルとデータラインの入力端との距離の増加にともなって小さくなる。言い換えれば、図１におけるピクセルＡ、Ｂ’とＣ’のＶ_ＦＤ関係は（Ｖ_ＦＤ）_Ａ＞（Ｖ_ＦＤ）_Ｂ’＞（Ｖ_ＦＤ）_Ｃ’になり、画面にフリッカーが生じて液晶表示パネルの表示品質は低下する。
【０００８】
【発明が解決しようとする課題】
この発明は前述の問題を解決するため、フリッカーを低減して液晶表示パネルの各ピクセルにほぼ同じＶ_ＦＤを印加できる液晶表示パネルを提供することを課題とする。
【０００９】
【課題を解決するための手段】
この発明による液晶表示パネルは上基板と、下基板と、上下両基板の間に設けられる複数のピクセルとを含む。各ピクセルには、それぞれほぼ同じフィードスルー電圧を得て液晶表示パネルのフリッカーを低減するため、少なくとも一つの補償コンデンサーを具える。
【００１０】
この発明では、各ピクセルに補償コンデンサーをつける。各補償コンデンサーは、各ピクセル電極と、各ピクセル電極が対応するスキャンラインとが重なってなるオーバーラップ領域からなる。更に各補償コンデンサーの容量値を調整することによって各ピクセルのＶ_ＦＤをほぼ一致させ、液晶表示パネルのフリッカーを低減して表示品質を向上させる。
かかる液晶表示パネルの特徴を詳述するために、具体的な実施例を挙げ、図を参照して以下に説明する。
【００１１】
【発明の実施の形態】
図４を参照されたい。図４は、この発明による液晶表示パネルの等価回路図である。図４によれば、等価回路４０は少なくともピクセルＡ、Ｂ、Ｃを含み、ピクセルＡ、Ｂ、Ｃの位置はそれぞれ図１におけるピクセルＡ、Ｂ、Ｃと対応する。ピクセルＡは液晶セルＬＣと薄膜トランジスターＴ_Ａを含む、液晶セルＬＣはピクセル電極と、共通電極ＣＥと、液晶分子層とからなるため、液晶コンデンサーとされる。薄膜トランジスターＴ_Ａは、スキャンラインＧＬ_０と接続されるゲート電極と、データラインＤＬ_０と接続されるドレイン電極と、液晶セルＬＣのピクセル電極と接続されるソース電極とを含む。ゲート電極はソース電極と部分的に重なり合うため、ゲート電極とソース電極との間に寄生コンデンサーＧＳ_Ａが発生する。なお、ピクセルＡは更に補償コンデンサーＣ’_Ａと保存コンデンサーＳＣ_Ａを含み、補償コンデンサーＣ’_Ａは液晶セルＬＣのピクセル電極とスキャンラインＧＬ_０とに接続され、保存コンデンサーＳＣ_Ａは液晶セルＬＣのピクセル電極とスキャンラインＧＬ_１とに接続される。
【００１２】
同じく、ピクセルＢは液晶セルＬＣと、薄膜トランジスターＴ_Ｂと、保存コンデンサーＳＣ_Ｂと、補償コンデンサーＣ’_Ｂとを含む。薄膜トランジスターＴ_Ｂのゲート電極はソース電極と部分的に重なり合って寄生コンデンサーＧＳ_Ｂが発生する。ピクセルＣは液晶セルＬＣと、薄膜トランジスターＴ_Ｃと、保存コンデンサーＳＣ_Ｃと、補償コンデンサーＣ’_Ｃとを含む。薄膜トランジスターＴ_Ｃのゲート電極はソース電極と部分的に重なり合って寄生コンデンサーＧＳ_Ｃが発生する。
【００１３】
図４によれば、各補償コンデンサーＣ’_Ａ、Ｃ’_ＢとＣ’_ＣはそれぞれコンデンサーＧＳ_Ａ、ＧＳ_ＢとＧＳ_Ｃと並列接続されるため、方程式（１）は以下の通りに書き替えられる。
【数２】

Ｃは補償コンデンサーＣ’の容量を表わす。一般に方程式（１）と方程式（２）において、保存コンデンサーＳＣと液晶セルＬＣの容量は寄生コンデンサーＧＳと補償コンデンサーＣ’の約数十倍である。言い換えれば、Ｃ_ＳＣ、Ｃ_ＬＣ＞＞Ｃ_ＧＳ、Ｃであるため、方程式（２）は以下の通り簡素化される。
【数３】

図４と方程式（３）によれば、前述の通りにスキャンラインＧＬ_０内の抵抗と容量によって、仮に（Ｃ_ＧＳ）_Ａ＝（Ｃ_ＧＳ）_Ｂ＝（Ｃ_ＧＳ）_Ｃ、（Ｃ_ＬＣ）_Ａ＝（Ｃ_ＬＣ）_Ｂ＝（Ｃ_ＬＣ）_Ｃ、Ｃ_Ａ＝Ｃ_Ｂ＝Ｃ_Ｃにすれば、ピクセルＡ、Ｂ、ＣのＶ_ＦＤ関係は（Ｖ_ＦＤ）_Ａ＞（Ｖ_ＦＤ）_Ｂ＞（Ｖ_ＦＤ）_Ｃになり、液晶表示パネルにはフリッカーが発生する。液晶表示パネルのフリッカーを低減するため、ピクセルＡ、Ｂ、ＣのＶ_ＦＤをほぼ同じにしなければならない。方程式（３）によれば、各ピクセルの補償コンデンサーＣ’、ゲート電極とソース電極との間の寄生コンデンサーＣ_ＧＳまたは保存コンデンサーＣ_ＳＣを調整することによって各ピクセルのＶ_ＦＤをほぼ同じようにさせる。その調整方法は以下の通りである。
（１）方程式（３）の通りに、Ｃ_Ａ＜Ｃ_Ｂ＜Ｃ_Ｃ、（Ｃ_ＧＳ）_Ａ＝（Ｃ_ＧＳ）_Ｂ＝（Ｃ_ＧＳ）_Ｃ、（Ｃ_ＳＣ）_Ａ＝（Ｃ_ＳＣ）_Ｂ＝（Ｃ_ＳＣ）_Ｃ、（Ｃ_ＬＣ）_Ａ＝（Ｃ_ＬＣ）_Ｂ＝（Ｃ_ＬＣ）_Ｃである場合、ピクセルＡ、Ｂ、ＣのＶ_ＦＤ関係は（Ｖ_ＦＤ）_Ａ≒（Ｖ_ＦＤ）_Ｂ≒（Ｖ_ＦＤ）_Ｃである。そのため、補償コンデンサーＣ’の容量Ｃを、ピクセルとスキャンラインの入力端との距離に従って増加させれば、各ピクセルのＶ_ＦＤをほぼ同じようにさせることが可能である。
（２）方程式（３）の通りに、（Ｃ_ＧＳ）_Ａ＜（Ｃ_ＧＳ）_Ｂ＜（Ｃ_ＧＳ）_Ｃ、Ｃ_Ａ＝Ｃ_Ｂ＝Ｃ_Ｃ、（Ｃ_ＳＣ）_Ａ＝（Ｃ_ＳＣ）_Ｂ＝（Ｃ_ＳＣ）_Ｃ、（Ｃ_ＬＣ）_Ａ＝（Ｃ_ＬＣ）_Ｂ＝（Ｃ_ＬＣ）_Ｃである場合は同じく、ピクセルＡ、Ｂ、ＣのＶ_ＦＤ関係は（Ｖ_ＦＤ）_Ａ≒（Ｖ_ＦＤ）_Ｂ≒（Ｖ_ＦＤ）_Ｃである。そのため、寄生コンデンサーＧＳの容量Ｃ_ＧＳを、ピクセルとスキャンラインの入力端との距離に従って増加させれば、各ピクセルのＶ_ＦＤをほぼ同じようにさせることが可能である。
（３）方程式（３）の通りに、（Ｃ_ＳＣ）_Ａ＞（Ｃ_ＳＣ）_Ｂ＞（Ｃ_ＳＣ）_Ｃ、Ｃ_Ａ＝Ｃ_Ｂ＝Ｃ_Ｃ、（Ｃ_ＧＳ）_Ａ＝（Ｃ_ＧＳ）_Ｂ＝（Ｃ_ＧＳ）_Ｃ、（Ｃ_ＬＣ）_Ａ＝（Ｃ_ＬＣ）_Ｂ＝（Ｃ_ＬＣ）_Ｃである場合は同じく、ピクセルＡ、Ｂ、ＣのＶ_ＦＤ関係は（Ｖ_ＦＤ）_Ａ≒（Ｖ_ＦＤ）_Ｂ≒（Ｖ_ＦＤ）_Ｃである。そのため、保存コンデンサーＳＣの容量Ｃ_ＳＣを、ピクセルとスキャンラインの入力端との距離に従って増加させれば、各ピクセルのＶ_ＦＤをほぼ同じようにさせることが可能である。
【００１４】
注意すべき点は、前述の方法（１）、方法（２）と方法（３）は相互に組み合わせて、各ピクセルのＶ_ＦＤをほぼ同じようにさせることである。これよりこの発明の実施例を説明する。
【００１５】
（第１の実施例）
図５と図６を参照されたい。図５と図６はこの発明の第１の実施例によるピクセルアレイの平面図である。この発明の第１の実施例は前述の方法（１）によるものである。図５によれば、ピクセルアレイ５０はスキャンライン駆動回路５４と電気的に接続される少なくとも一本のスキャンライン５２と、データライン駆動回路（図示されていない）と電気的に接続されるデータライン５６ａ〜５６ｃとを含む。更に、ピクセルアレイ５０はピクセルＡ、Ｂ、Ｃを含む。ピクセルＡ、Ｂ、Ｃはそれぞれ薄膜トランジスターＴ_Ａ、Ｔ_Ｂ、Ｔ_Ｃと、それに対応する液晶セル（図示されていない）を含む。薄膜トランジスターＴ_Ａ、Ｔ_Ｂ、Ｔ_Ｃのドレイン電極６２ａ、６２ｂ、６２ｃはそれぞれデータライン５６ａ、５６ｂ、５６ｃと接続され、ソース電極６４ａ、６４ｂ、６４ｃはそれぞれ液晶セルのピクセル電極５８ａ、５８ｂ、５８ｃと接続される。各ゲート電極と各ソース電極、各ドレイン電極との間には更に半導体層６６ａ、６６ｂ、６６ｃが設けられる。
【００１６】
ピクセルＡ、Ｂ、Ｃはオーバーラップ領域６８ａ、６８ｂ、６８ｃを含む。オーバーラップ領域６８ａはゲート電極６０ａとソース電極６４ａが重なってなり、オーバーラップ領域６８ｂとオーバーラップ領域６８ｃはそれぞれゲート電極６０ｂ、６０ｃとソース電極６４ｂ、６４ｃが重なってなる。その外、ピクセル電極５８ａ、５８ｂ、５８ｃはそれぞれ延伸部分６９ａ、６９ｂ、６９ｃを具え、延伸部分６９ａ、６９ｂ、６９ｃはスキャンラインと重なってオーバーラップ領域７０ａ、７０ｂ、７０ｃを形成する。注意すべき点は、オーバーラップ領域７０ａ、７０ｂ、７０ｃの面積が逓増することである。
【００１７】
この実施例において、オーバーラップ領域６８ａ、６８ｂ、６８ｃは図４における寄生コンデンサーＧＳ_Ａ、ＧＳ_Ｂ、ＧＳ_Ｃとそれぞれ対応し、面積がほぼ同じであり、ゆえに（Ｃ_ＧＳ）_Ａ＝（Ｃ_ＧＳ）_Ｂ＝（Ｃ_ＧＳ）_Ｃである。なお、オーバーラップ領域７０ａ、７０ｂ、７０ｃは図４における補償コンデンサーＣ’_Ａ、Ｃ’_Ｂ、Ｃ’_Ｃとそれぞれ対応し、面積が逓増するため、補償コンデンサーＣ’_Ａ、Ｃ’_Ｂ、Ｃ’_Ｃの容量値Ｃ_Ａ、Ｃ_Ｂ、Ｃ_Ｃも逓増し（Ｃ_Ａ＜Ｃ_Ｂ＜Ｃ_Ｃ）、ピクセルＡ、Ｂ、ＣのＶ_ＦＤをほぼ同じようにさせる。更に、各ピクセル電極とスキャンラインとの間の空間が広いため、大型の液晶表示パネルに対して、各ピクセル電極とスキャンラインとの間はオーバーラップ領域７０ａ、７０ｂ、７０ｃを設けるに充分な空間をもち、よって各ピクセルのＶ_ＦＤをほぼ同じようにさせる。
【００１８】
この発明の第１の実施例は図５に限らず、図６も第１の実施例に属する。図６によれば、ピクセルアレイ５０において、スキャンライン５２は延伸部分７１ａ、７１ｂ、７１ｃを含み、延伸部分７１ａ、７１ｂ、７１ｃはそれぞれピクセル電極５８ａ、５８ｂ、５８ｃの下方にあってピクセル電極５８ａ、５８ｂ、５８ｃと重なってオーバーラップ領域７２ａ、７２ｂ、７２ｃを形成し、そのうちオーバーラップ領域７２ａ、７２ｂ、７２ｃの面積は逓増する。なお、垂直配列液晶などの広視角液晶表示パネルは、一般に液晶の配列を規制する突起部などのような規制手段（ｒｅｇｕｌａｔｉｎｇ　ｍｅａｎｓ）を有するため、かかる表示装置に応用する場合には、ピクセル電極５８ａ、５８ｂ、５８ｃの上側に突起部７３ａ、７３ｂ、７３ｃを設けてもよい。突起部７３ａ、７３ｂ、７３ｃはスキャンライン５２の延伸部分７１ａ，７１ｂ、７１ｃの電場が液晶分子の配列方向への干渉を避けるため、それぞれ延伸部分７１ａ，７１ｂ、７１ｃを一部遮蔽する。この発明のその他の実施例において、突起部７３ａ、７３ｂ、７３ｃは共通電極（図示されていない）に設けてもよい。その共通電極は上基板に設けられ、上基板はピクセルアレイ５０の設ける下基板と平行する。一般に、突起部７３ａ、７３ｂ、７３ｃはフォトレジスト材料からなる。
【００１９】
オーバーラップ領域６８ａ、６８ｂ、６８ｃは図４における寄生コンデンサーＧＳ_Ａ、ＧＳ_Ｂ、ＧＳ_Ｃとそれぞれ対応し、オーバーラップ領域７２ａ、７２ｂ、７２ｃは図４における補償コンデンサーＣ’_Ａ、Ｃ’_Ｂ、Ｃ’_Ｃとそれぞれ対応する。図６によれば、オーバーラップ領域７２ａ、７２ｂ、７２ｃの面積は逓増するため、補償コンデンサーＣ’_Ａ、Ｃ’_Ｂ、Ｃ’_Ｃの容量値Ｃ_Ａ、Ｃ_Ｂ、Ｃ_Ｃも逓増し（Ｃ_Ａ＜Ｃ_Ｂ＜Ｃ_Ｃ）、ピクセルＡ、Ｂ、ＣのＶ_ＦＤをほぼ同じようにさせる。
【００２０】
（第２の実施例）
図７を参照されたい。図７はこの発明の第２の実施例によるピクセルアレイの平面図である。この発明の第２の実施例は前述の方法（１）と方法（２）との組み合わせによるものである。図７によれば、ピクセルアレイ５０は領域Ｉと領域ＩＩを具え、そのうちピクセルＡ、Ｂ、Ｃは領域Ｉにある。薄膜トランジスターＴ_Ａ、Ｔ_Ｂ、Ｔ_Ｃのゲート電極６０ａ、６０ｂ、６０ｃはそれぞれブロック６７ａ、６７ｂ、６７ｃを具え、ブロック６７ａ、６７ｂ、６７ｃはオーバーラップ領域６８ａ、６８ｂ、６８ｃにあり、その面積の逓増に従って、オーバーラップ領域６８ａ、６８ｂ、６８ｃの面積も逓増する。
【００２１】
この発明の第２の実施例において、オーバーラップ領域６８ａ、６８ｂ、６８ｃは図４における寄生コンデンサーＧＳ_Ａ、ＧＳ_Ｂ、ＧＳ_Ｃとそれぞれ対応する。図７によれば、オーバーラップ領域６８ａ、６８ｂ、６８ｃの面積は逓増するため、寄生コンデンサーＧＳ_Ａ、ＧＳ_Ｂ、ＧＳ_Ｃの容量値も逓増し（　（Ｃ_ＧＳ）_Ａ＜（Ｃ_ＧＳ）_Ｂ＜（Ｃ_ＧＳ）_Ｃ）、ピクセルＡ、Ｂ、ＣのＶ_ＦＤをほぼ同じようにさせる。言い換えれば、領域Ｉ内のピクセルはゲート電極とソース電極との間の寄生コンデンサー容量Ｃ_ＧＳを調整することによって、Ｖ_ＦＤがほぼ同じようにされる。
【００２２】
ゲート電極とソース電極の大きさには限りがあり、各ピクセルの寄生コンデンサーＧＳを調整するのみでは大型液晶表示パネルの要求に応じられない。ゆえに、この発明の第２の実施例においては、ピクセルアレイ５０は更に領域ＩＩを含み、領域ＩＩにおけるピクセル（図示されていない）は補償コンデンサーＣ’を調整することによって、Ｖ_ＦＤがほぼ同じようにされる。領域ＩＩにおけるピクセルの構造は第１の実施例と同じであるため、ここで説明を省略する。
【００２３】
（第３の実施例）
図８を参照されたい。図８は、この発明の第３の実施例によるピクセルアレイの平面図である。この発明の第３の実施例は、前述の方法（１）と方法（３）との組み合わせによるものである。図８によれば、ピクセルＡ、Ｂ、Ｃはオーバーラップ領域７０ａ、７０ｂ、７０ｃを具え、ピクセル電極５８ａ、５８ｂ、５８ｃはそれぞれ延伸部分６９ａ、６９ｂ、６９ｃを具える。オーバーラップ領域７０ａは延伸部分６９ａとスキャンライン５２が重なってなり、オーバーラップ領域７０ｂ、７０ｃはそれぞれスキャンライン５２と延伸部分６９ｂ、６９ｃとが重なってなり、オーバーラップ領域７０ａ、７０ｂ、７０ｃの面積は逓増する。更に、ピクセルＡ、Ｂ、Ｃはオーバーラップ領域７４ａ、７４ｂ、７４ｃを具え、オーバーラップ領域７４ａ、７４ｂ、７４ｃはそれぞれピクセル電極５８ａ、５８ｂ、５８ｃとスキャンライン５２とが重なってなる。オーバーラップ領域７４ａの面積はオーバーラップ領域７４ｂの面積を上回り、オーバーラップ領域７４ｂはオーバーラップ領域７４ｃを上回る。
【００２４】
この発明の第３の実施例において、オーバーラップ領域７４ａ、７４ｂ、７４ｃは図４における保存コンデンサーＳＣ_Ａ、ＳＣ_Ｂ、ＳＣ_Ｃとそれぞれ対応し、オーバーラップ領域７０ａ、７０ｂ、７０ｃは図４における補償コンデンサーＣ’_Ａ、Ｃ’_Ｂ、Ｃ’_Ｃとそれぞれ対応する。図８によれば、オーバーラップ領域７０ａ、７０ｂ、７０ｃの面積が逓増するため、補償コンデンサーＣ’_Ａ、Ｃ’_Ｂ、Ｃ’_Ｃの容量値Ｃ_Ａ、Ｃ_Ｂ、Ｃ_Ｃも逓増し（Ｃ_Ａ＜Ｃ_Ｂ＜Ｃ_Ｃ）、オーバーラップ領域７０ａ、７０ｂ、７０ｃの面積が逓減する。ゆえに保存コンデンサーＳＣ_Ａ、ＳＣ_Ｂ、ＳＣ_Ｃの容量値関係は（Ｃ_ＧＳ）_Ａ＜（Ｃ_ＧＳ）_Ｂ＜（Ｃ_ＧＳ）_Ｃになり、ピクセルＡ、Ｂ、ＣのＶ_ＦＤをほぼ同じようにさせる。
【００２５】
保存コンデンサーは、リーク電流が液晶セルの電圧に与える影響を緩和し、液晶セルに電荷を保存させるため、保存コンデンサーの容量が小さければ液晶セルに電荷を保存させる能力も低くなる。そのため保存コンデンサーの容量が減少する余地がない場合、この発明の第３の実施例においては、各補償コンデンサーＣ’を調整することによって、各ピクセルのＶ_ＦＤをほぼ一致させる。かくして各ピクセルのＶ_ＦＤをほぼ一致させるのみならず、保存コンデンサーの液晶セルに電荷を保存させる能力も低下しない。
【００２６】
（第４の実施例）
注意すべき点は、この発明の第１、第２、第３の実施例は同じスキャンラインにおける各ピクセルに対するものであるが、同じデータラインにおける各ピクセルに応用されてもよいことである。図９を参照されたい。図９はこの発明の第４の実施例によるピクセルアレイの平面図である。この発明の第４の実施例は、前述の方法（１）によるものである。図９によれば、ピクセルアレイ８０はスキャンライン駆動回路８４と電気的に接続される複数のスキャンライン８２ａ、８２ｂと、データライン駆動回路８８と電気的に接続されるデータライン８６ａ、８６ｂと、ピクセルＡ、Ｂ’、Ｃ’とを含む。ピクセルＡ、Ｂ’、Ｃ’の位置はそれぞれ図１におけるピクセルＡ、Ｂ、Ｃと対応し、それぞれ薄膜トランジスターＴ_Ａ、Ｔ_Ｂ’、Ｔ_Ｃ’と、それに対応する液晶セル（図示されていない）を含む。薄膜トランジスターＴ_Ａ、Ｔ_Ｂ’、Ｔ_Ｃ’のドレイン電極９４ａ、９４ｂ、９４ｃはそれぞれデータライン８６ａと接続され、ソース電極９６ａ、９６ｂ、９６ｃはそれぞれ液晶セルのピクセル電極９０ａ、９０ｂ、９０ｃと接続される。各ゲート電極と各ソース電極、各ドレイン電極との間には更に半導体層９８ａ、９８ｂ、９８ｃが設けられる。
【００２７】
ピクセル電極９０ａ、９０ｂ、９０ｃはそれぞれ延伸部分９９ａ、９９ｂ、９９ｃを具え、延伸部分９９ａ、９９ｂ、９９ｃは各スキャンライン８２ａと部分的に重なって面積が逓増するオーバーラップ領域１００ａ、１００ｂ、１００ｃを形成する。なお、ピクセル電極９０ａ、９０ｂ、９０ｃは各スキャンライン８２ｂとそれぞれ重なってオーバーラップ領域１０２ａ、１０２ｂ、１０２ｃとなり、ピクセルＡ、Ｂ’、Ｃ’の保存コンデンサーを形成する。
【００２８】
この発明の第４の実施例において、オーバーラップ領域１００ａ、１００ｂ、１００ｃは補償コンデンサーＣ’_Ａ、Ｃ’_Ｂ、Ｃ’_Ｃ（図示されていない）とそれぞれ対応し、面積が逓増するため、対応する補償コンデンサーＣ’_Ａ、Ｃ’_Ｂ、Ｃ’_Ｃの容量値Ｃ_Ａ、Ｃ_Ｂ、Ｃ_Ｃも逓増し（Ｃ_Ａ＜Ｃ_Ｂ＜Ｃ_Ｃ）、ピクセルＡ、Ｂ’、Ｃ’のＶ_ＦＤ関係を（Ｖ_ＦＤ）_Ａ≒（Ｖ_ＦＤ）_Ｂ’　≒（Ｖ_ＦＤ）_Ｃ’にさせる。
【００２９】
この発明の第４の実施例において、各オーバーラップ領域１００ａ、１００ｂ、１００ｃは各スキャンライン８２ａが各ピクセル電極９０ａ、９０ｂ、９０ｃの下側に延伸して形成されることも可能である。
【００３０】
以上は、この発明の好ましい実施例であって、この発明の実施の範囲を限定するものではない。よって、当業者のなし得る修正、もしくは変更であって、この発明の精神の下においてなされ、この発明に対して均等の効果を有するものは、いずれもこの発明の特許請求の範囲に属するものとする。
【００３１】
【発明の効果】
従来の技術と比べ、この発明は各ピクセルに補償コンデンサーをつけ、各補償コンデンサーは各ピクセル電極と、各ピクセル電極が対応するスキャンラインとが重なってなるオーバーラップ領域からなる。更に各補償コンデンサーの容量値を調整することによって各ピクセルのＶ_ＦＤをほぼ一致させ、液晶表示パネルのフリッカーを低減して表示品質を向上させる。
【図面の簡単な説明】
【図１】従来の薄膜トランジスター液晶表示パネルを表わす説明図である。
【図２】薄膜トランジスター液晶表示パネルにある単一ピクセルの等価回路図である。
【図３】各ドライバー集積回路チップの出力電圧の波形を表わす説明図である。
【図４】この発明に液晶表示パネルの等価回路図である。
【図５】この発明の第１の実施例によるピクセルアレイの第一平面図である。
【図６】この発明の第１の実施例によるピクセルアレイの第二平面図である。
【図７】この発明の第２の実施例によるピクセルアレイの平面図である。
【図８】この発明の第３の実施例によるピクセルアレイの平面図である。
【図９】この発明の第４の実施例によるピクセルアレイの平面図である。
【符号の説明】
１０　薄膜トランジスター
１２　下基板
１４　ピクセルアレイ
１６　スキャンライン駆動回路領域
１６ａ、１６ｂ、１６ｃ　ドライバー集積回路チップ
１７　バスライン
１８　データライン駆動回路領域
２０　ピクセル
４０　等価回路
５０、８０　ピクセルアレイ
５２、５２ａ、８２ａ、８２ｂ　スキャンライン
５４、８４　スキャンライン駆動回路領域
５６ａ、５６ｂ、５６ｃ、８６ａ、８６ｂ　データライン
５８ａ、５８ｂ、５８ｃ、９０ａ、９０ｂ、９０ｃピクセル電極
６０ａ、６０ｂ、６０ｃ、９２ａ、９２ｂ、９２ｃゲート電極
６２ａ、６２ｂ、６２ｃ、９４ａ、９４ｂ、９４ｃドレイン電極
６４ａ、６４ｂ、６４ｃ、９６ａ、９６ｂ、９６ｃソース電極
６６ａ、６６ｂ、６６ｃ、９８ａ、９８ｂ、９８ｃ半導体層
６７ａ、６７ｂ、６７ｃ　ブロック
６８ａ、６８ｂ、６８ｃ、７０ａ、７０ｂ、７０ｃ　オーバーラップ領域
６９ａ、６９ｂ、６９ｃ、７１ａ、７１ｂ、７１ｃ　延伸部分
７２ａ、７２ｂ、７２ｃ、７４ａ、７４ｂ、７４ｃ　オーバーラップ領域
８８　データライン駆動回路
９９ａ、９９ｂ、９９ｃ　延伸部分
１００ａ、１００ｂ、１００ｃ、１０２ａ、１０２ｂ、１０２ｃ　オーバーラップ領域[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal display panel, and more particularly to a liquid crystal display panel that reduces flicker.
[0002]
[Prior art]
The thin film transistor liquid crystal display panel uses a matrix arrangement of thin film transistors and other electronic devices to drive liquid crystal pixels to display various images. Thin film transistors have characteristics such as light weight, low power consumption, and low radiation, and are widely applied to portable information products such as notebook computers and personal digital assistants (PDAs), replacing CRT monitors of desktop computers. It is getting.
[0003]
Please refer to FIG. 1 and FIG. FIG. 1 is an explanatory view showing a conventional thin film transistor liquid crystal display panel, and FIG. 2 is an equivalent circuit diagram of a single pixel in the thin film transistor liquid crystal display panel. Referring to FIG. 1, the liquid crystal display panel 10 includes a lower substrate 12, and the lower substrate 12 includes a pixel array region 14, a scan line driving circuit region 16, and a data line driving circuit region 18. The pixel array area 14 includes a plurality of scan lines (not shown) and a plurality of data lines (not shown), and each scan line and each data line is a pixel A to C in FIG. A plurality of pixels such as B 'to C' are determined. Pixels A to C are electrically connected to the same scan line, and pixels A, B ', and C' are electrically connected to the same data line.
[0004]
According to FIG. 1, the scan line driving circuit area 16 includes a plurality of driver integrated circuit chips (for example, chips 16a to 16c) and a plurality of bus lines 17, and each bus line 17 connects each driver integrated circuit chip. Each driver integrated circuit chip is manufactured directly on the surface of the lower substrate 12 by a chip-on-glass (COG) method, and each bus line 17 is manufactured directly on the lower substrate 12. This is a so-called wire-on-array (WOA) method.
[0005]
According to FIG. 2, the pixel 20 includes at least one liquid crystal cell LC and one thin film transistor TFT. The liquid crystal cell LC includes a pixel electrode, a common electrode CE, and a liquid crystal molecular layer. TFT includes a gate electrode connected to the scan lines GL _0, a drain electrode connected to the data lines DL _0, and a pixel electrode connected to the liquid crystal cell LC. When the gate electrode and the source electrode partially overlap, a parasitic capacitor GS is formed between the gate electrode and the source electrode. Incidentally, the pixel 20 comprises a storage capacitor SC is connected to the liquid crystal cell LC and the scan lines GL _1, the storage capacitor SC is to mitigate the effects of leakage current gives a voltage to the liquid crystal cell LC, the charge to the liquid crystal cell LC Let me save.
[0006]
Since the voltage applied to the liquid crystal cell LC has a certain relationship with the light transmittance, if a voltage is applied to the liquid crystal cell LC according to a required screen, the light transmittance of each pixel can be appropriately controlled. . A suitable screen is displayed with an appropriate light source. The voltage applied to the liquid crystal cell LC is a voltage between the common electrode CE and the pixel electrode. When the thin film transistor is turned off, the pixel electrode is not connected to the power supply, but is connected to the scan line through a parasitic capacitor, and its voltage changes. Therefore, the voltage applied to the liquid crystal cell is far from the original set value. This amount of voltage fluctuation is called a feedthrough voltage (V _FD ) and is expressed by the following equation.
(Equation 1)

C _LC is the capacitance of the liquid crystal cell LC equation (1), C _SC is the capacitance of the storage capacitor, C _GS is the parasitic capacitance between the gate electrode and the source electrode of the TFT, V _G is the pulse voltage applied to the scan lines , Respectively. In general, the effect of V _FD can be reduced by adjusting the voltage of the common electrode CE. However, the falling edge of the pulse voltage applied to the scan line is rounded due to the resistance and capacitance in the scan line, and V _FD is reduced. It becomes smaller as the distance between the pixel and the scan line increases. In other words, the V _FD relationship between the pixels A, B, and C in FIG. 1 is (V _FD ) _A > (V _FD ) _B > (V _FD ) _C. Therefore, the effect of the _VFD of the pixel is not eliminated by adjusting the common electrode CE, and flicker occurs in the liquid crystal display panel 10.
[0007]
Since the bus line 17 in the scan line driving circuit 16 has a considerable resistance value, when a pulse voltage is input from the bus line 17 to each driver integrated circuit chip, the input voltage of each driver integrated circuit is different. The output voltage waveform of the driver integrated circuit chip is also different. According to FIG. 3, the voltage (V _GA ) output from the driver integrated circuit chip 16a is the highest, and the voltage (V _GB ) output from the driver integrated circuit chip 16b is the next voltage (V _GB ) output from the driver integrated circuit chip 16c. V _GC ) is then: V _FD decreases as the distance between the pixel and the input end of the data line increases. In other words, the V _FD relationship between the pixels A, B ′ and C ′ in FIG. 1 is (V _FD ) _A > (V _FD ) _{B ′} > (V _FD ) _{C ′} , and a flicker occurs on the screen and the liquid crystal display panel Display quality is degraded.
[0008]
[Problems to be solved by the invention]
An object of the present invention is to provide a liquid crystal display panel capable of applying substantially the same _VFD to each pixel of the liquid crystal display panel while reducing flicker in order to solve the above-mentioned problem.
[0009]
[Means for Solving the Problems]
The liquid crystal display panel according to the present invention includes an upper substrate, a lower substrate, and a plurality of pixels provided between the upper and lower substrates. Each pixel is provided with at least one compensation capacitor to obtain substantially the same feedthrough voltage and reduce flicker of the liquid crystal display panel.
[0010]
In the present invention, each pixel is provided with a compensation capacitor. Each compensation capacitor includes an overlap region where each pixel electrode overlaps a scan line corresponding to each pixel electrode. Further substantially coincide the V _FD of each pixel by adjusting the capacitance value of each compensation capacitor, to improve the display quality by reducing the flicker of the LCD panel.
In order to describe the characteristics of such a liquid crystal display panel in detail, a specific embodiment will be described below with reference to the drawings.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Please refer to FIG. FIG. 4 is an equivalent circuit diagram of the liquid crystal display panel according to the present invention. According to FIG. 4, the equivalent circuit 40 includes at least pixels A, B, and C, and the positions of the pixels A, B, and C correspond to the pixels A, B, and C in FIG. 1, respectively. Pixel A comprises a liquid crystal cell LC and the thin film transistor T _A, the liquid crystal cell LC and the pixel electrodes, a common electrode CE, since composed of a liquid crystal molecule layer is a liquid crystal capacitor. TFT T _A includes a gate electrode connected to the scan lines GL _0, a drain electrode connected to the data lines DL _0, and a source electrode connected to the pixel electrode of the liquid crystal cell LC. Since the gate electrode overlapping the source electrode and the part, the parasitic capacitor GS _A is generated between the gate electrode and the source electrode. Incidentally, the pixel A further 'includes a storage capacitor SC _A and _A, the compensation capacitor C' compensation capacitor C _A is connected to the pixel electrode and the scan line GL ₀ of the liquid crystal cell LC, the storage capacitor SC _A is the liquid crystal cell LC It is connected to the pixel electrode and the scan lines GL _1.
[0012]
Similarly, the pixel B includes a liquid crystal cell LC, and a thin film transistor _{T B,} a storage capacitor SC _B, and a compensating capacitor C _'B. The gate electrode of the thin film transistor T _B is the parasitic capacitor GS _B occurs overlap the source electrode and the part. Pixel C includes a liquid crystal cell LC, and a thin film transistor _{T C,} the storage capacitor SC _C, and a compensation capacitor C _'C. The gate electrode of the thin film transistor T _C is parasitic capacitor GS _C occurs overlap the source electrode and the part.
[0013]
According to FIG. 4, for each compensation capacitor C _'A, C' _B and C _'C is the condenser _GS A respectively, are connected in parallel with the GS _B and GS _C, equation (1) is rewritten as follows .
(Equation 2)

C represents the capacitance of the compensation capacitor C '. In general, in equations (1) and (2), the capacities of the storage capacitor SC and the liquid crystal cell LC are about several tens of times those of the parasitic capacitor GS and the compensation capacitor C ′. In other words, since C _SC , C _LC >> C _GS , C, equation (2) is simplified as follows.
[Equation 3]

According to FIG. 4 and equation (3), (C _GS ) _A = (C _GS ) _B = (C _GS ) _C and (C _LC ) _A by the resistance and the capacitance in the scan line GL _{0 as described} above. _{_{_{_{= (C LC) B = (}}}} C LC) C, C a = C B = if the _{C C,} pixels a, B, is _{V FD} relationship _{_{_{C (V FD) a> (}}} V FD) B> (V _FD ) _C , and flicker occurs on the liquid crystal display panel. To reduce the flicker of the LCD panel, not pixels A, B, unless substantially equal to V _FD of C. According to equation (3), adjusting the compensation capacitor C ′ of each pixel, the parasitic capacitor C _GS or the storage capacitor C _SC between the gate electrode and the source electrode, makes the V _FD of each pixel approximately the same. . The adjustment method is as follows.
(1) As in equation (3), C _A <C _B <C _C , (C _GS ) _A = (C _GS ) _B = (C _GS ) _C , (C _SC ) _A = (C _SC ) _B = If (C _SC ) _C , (C _LC ) _A = (C _LC ) _B = (C _LC ) _C , the V _FD relationship of pixels A, B, C is (V _FD ) _A ≒ (V _FD ) _B ≒ (V _FD ) _C. Therefore, if the capacitance C of the compensation capacitor C ′ is increased according to the distance between the pixel and the input end of the scan line, it is possible to make the _VFD of each pixel substantially the same.
(2) as equation _{_{_{(3), (C GS)}}} A <(C GS) B <(C GS) C, C A = C B = C C, (C SC) A = (C SC) B = Similarly, when (C _SC ) _C , (C _LC ) _A = (C _LC ) _B = (C _LC ) _C , the V _FD relationship of the pixels A, B, and C is (V _FD ) _A ≒ (V _FD ) _B ≒ (V _FD ) _C. Therefore, if the capacitance C _GS of the parasitic capacitor GS is increased according to the distance between the pixel and the input end of the scan line, it is possible to make the V _FD of each pixel substantially the same.
(3) as the equation _{_{_{(3), (C SC)}}} A> (C SC) B> (C SC) C, C A = C B = C C, (C GS) A = (C GS) B = Similarly, when (C _GS ) _C and (C _LC ) _A = (C _LC ) _B = (C _LC ) _C , the V _FD relationship of the pixels A, B, and C is (V _FD ) _A ≒ (V _FD ) _B ≒ (V _FD ) _C. Therefore, if the capacitance C _SC of the storage capacitor SC is increased according to the distance between the pixel and the input end of the scan line, it is possible to make the V _FD of each pixel substantially the same.
[0014]
It should be noted that the above methods (1), (2) and (3) are combined with each other so that the _VFD of each pixel is almost the same. Hereinafter, embodiments of the present invention will be described.
[0015]
(First embodiment)
Please refer to FIG. 5 and FIG. 5 and 6 are plan views of a pixel array according to the first embodiment of the present invention. The first embodiment of the present invention is based on the above-mentioned method (1). Referring to FIG. 5, the pixel array 50 includes at least one scan line 52 electrically connected to a scan line driving circuit 54 and a data line electrically connected to a data line driving circuit (not shown). 56a to 56c. Further, the pixel array 50 includes pixels A, B, and C. Each of the pixels A, B, and C includes a thin film transistor T _A , T _B , and T _C and a corresponding liquid crystal cell (not shown). TFT _{_T} _A, _T _B, _T _C of the

drain electrodes

62a, 62b, 62c are respectively connected

data lines

56a, 56b, 56c and a

source electrode

64a, 64b, of each 64c liquid crystal

cell pixel electrodes

58a, 58b, 58c Is connected to

Semiconductor layers

66a, 66b and 66c are further provided between each gate electrode and each source electrode and each drain electrode.
[0016]
Pixels A, B, C include

overlap regions

68a, 68b, 68c. In the overlap region 68a, the gate electrode 60a and the source electrode 64a overlap, and in the overlap region 68b and the overlap region 68c, the

gate electrodes

60b, 60c and the

source electrodes

64b, 64c overlap, respectively. In addition, the

pixel electrodes

58a, 58b, 58c have extended

portions

69a, 69b, 69c, respectively, and the

extended portions

69a, 69b, 69c overlap the scan lines to form

overlap regions

70a, 70b, 70c. It should be noted that the area of the

overlap regions

70a, 70b, 70c gradually increases.
[0017]
In this embodiment, the

overlap regions

68a, 68b, 68c correspond to the parasitic capacitors GS _A , _{G S B} , _{G S} _C respectively in FIG. 4 and have approximately the same area, thus (C _GS ) _A = (C _GS ) _B = (C _GS ) _C. Incidentally, the

overlap regions

70a, 70b, 70c compensation capacitor C _'A, C' _B in FIG. 4, 'correspond and _C, and the area is gradually increasing, the compensation capacitor _{_{C' C A, C 'B}} , C' _C of the capacitance values _C _a, C B, _{C C} also gradually increasing _{_{_{(C a <C B <C}}} C), the pixel a, B, causing the _{V FD} of C in much the same way. Further, since the space between each pixel electrode and the scan line is large, the space between each pixel electrode and the scan line is sufficient to provide the

overlap regions

70a, 70b, 70c for a large-sized liquid crystal display panel. , So that the V _FD of each pixel is approximately the same.
[0018]
The first embodiment of the present invention is not limited to FIG. 5, and FIG. 6 also belongs to the first embodiment. According to FIG. 6, in the pixel array 50, the scan line 52 includes extended portions 71a, 71b, 71c, and the extended portions 71a, 71b, 71c are below the

pixel electrodes

58a, 58b, 58c, respectively, and the pixel electrodes 58a, The

overlap regions

72a, 72b and 72c are formed so as to overlap with the

regions

58b and 58c, and the areas of the

overlap regions

72a, 72b and 72c gradually increase. Note that a wide viewing angle liquid crystal display panel such as a vertically aligned liquid crystal generally has a regulating means such as a protrusion for regulating the alignment of the liquid crystal. Therefore, when applied to such a display device, the pixel electrode 58a is used. , 58b, 58c may be provided with

protrusions

73a, 73b, 73c. The

projections

73a, 73b, and 73c partially shield the extended portions 71a, 71b, and 71c, respectively, in order to prevent the electric field of the extended portions 71a, 71b, and 71c of the scan line 52 from interfering with the alignment direction of the liquid crystal molecules. In another embodiment of the present invention, the

projections

73a, 73b, 73c may be provided on a common electrode (not shown). The common electrode is provided on the upper substrate, and the upper substrate is parallel to the lower substrate on which the pixel array 50 is provided. Generally, the

protrusions

73a, 73b, 73c are made of a photoresist material.
[0019]
Overlap

region

68a, 68b, 68c are parasitic capacitor _GS A in FIG. _4, GS B, GS _C respectively corresponding, overlapping

regions

72a, 72b, 72c compensation capacitor C _'A, C' in FIG. 4 _B, C 'Corresponds to _C respectively. According to FIG. 6, because the overlapping areas 72a, 72b, the area of 72c to gradually increasing, the compensation capacitor _{_{C 'A, C' B,}} C 'C of the capacitance values _C _A, C B, also _{C C} and gradually increasing (C _A <C _B <C _C ), and the V _FDs of the pixels A, B, C are made almost the same.
[0020]
(Second embodiment)
Please refer to FIG. FIG. 7 is a plan view of a pixel array according to a second embodiment of the present invention. The second embodiment of the present invention is based on a combination of the above methods (1) and (2). According to FIG. 7, the pixel array 50 comprises a region I and a region II, of which the pixels A, B, C are in the region I. TFT _T _A, _T _B, comprises _{T C} of the

gate electrode

60a, 60b, respectively 60c

blocks

67a, 67b, a 67c,

blocks

67a, 67b, 67c is overlapped

region

68a, 68b, to 68c, the area The area of the

overlap regions

68a, 68b, 68c also increases with the increase.
[0021]
In the second embodiment of the present invention, the

overlap regions

68a, 68b, 68c correspond to the parasitic capacitors GS _A , _{G S B} , _{G S} _C in FIG. 4, respectively. According to FIG. 7, since the overlapping

area

68a, 68b, the area of 68c to gradually increasing, parasitic capacitors _GS _A, GS B, the capacitance value of GS _C and gradually increasing _{_{_{((C GS) A <(}}} C GS) B < (C _GS ) _C ), Make the V _FD of pixels A, B, C approximately the same. In other words, the pixels in region I have approximately the same V _FD by adjusting the parasitic capacitance C _GS between the gate and source electrodes.
[0022]
The sizes of the gate electrode and the source electrode are limited, and the adjustment of the parasitic capacitor GS of each pixel cannot meet the requirements of a large liquid crystal display panel. Thus, in a second embodiment of the present invention, pixel array 50 further includes region II, and the pixels in region II (not shown) are adjusted so that _VFD is approximately the same by adjusting compensation capacitor C '. To be. Since the structure of the pixel in the area II is the same as that of the first embodiment, the description is omitted here.
[0023]
(Third embodiment)
Please refer to FIG. FIG. 8 is a plan view of a pixel array according to the third embodiment of the present invention. The third embodiment of the present invention is based on a combination of the above methods (1) and (3). According to FIG. 8, pixels A, B, C have overlapping

areas

70a, 70b, 70c, and

pixel electrodes

58a, 58b, 58c have extending

portions

69a, 69b, 69c, respectively. The overlap region 70a overlaps the extension 69a and the scan line 52, and the

overlap regions

70b and 70c overlap the scan line 52 and the

extension

69b and 69c, respectively, and the area of the

overlap regions

70a, 70b and 70c. Gradually increases. Further, the pixels A, B, and C have

overlap regions

74a, 74b, and 74c, and the

overlap regions

74a, 74b, and 74c overlap the

pixel electrodes

58a, 58b, and 58c with the scan line 52, respectively. The area of the overlap region 74a exceeds the area of the overlap region 74b, and the overlap region 74b exceeds the overlap region 74c.
[0024]
In a third embodiment of the invention, the overlapping

region

74a, 74b, 74c are storage capacitor _SC A in FIG. _4, SC B, correspond with SC _C, the

overlap regions

70a, 70b, 70c compensation in FIG. 4 They correspond to the capacitors C ′ _A , C ′ _B , and C ′ _C , respectively. According to FIG. 8, since the overlapping

area

70a, 70b, the area of 70c to gradually increasing, the compensation capacitor _{_{C 'A, C' B,}} C 'C of the capacitance values _C _A, C B, also _{C C} and gradually increasing (C _{_{_{a <C B <C C)}}} , the

overlap regions

70a, 70b, the area of 70c be decreasing. Therefore, the capacitance value relationship of the storage capacitors SC _A , SC _B , and SC _C is (C _GS ) _A <(C _GS ) _B <(C _GS ) _C , and the V _FD of the pixels A, B, and C is almost the same. Let it.
[0025]
The storage capacitor reduces the influence of the leakage current on the voltage of the liquid crystal cell and stores the electric charge in the liquid crystal cell. Therefore, if the storage capacitor has a small capacity, the ability to store the electric charge in the liquid crystal cell also decreases. Therefore, when there is no room for reducing the capacity of the storage capacitor, in the third embodiment of the present invention, the V _FD of each pixel is made substantially equal by adjusting each compensation capacitor C ′. Thus, not only does the V _FD of each pixel substantially match, but the ability of the storage capacitor to store charge in the liquid crystal cell does not decrease.
[0026]
(Fourth embodiment)
It should be noted that while the first, second and third embodiments of the present invention are for each pixel on the same scan line, they may be applied to each pixel on the same data line. Please refer to FIG. FIG. 9 is a plan view of a pixel array according to a fourth embodiment of the present invention. The fourth embodiment of the present invention is based on the above-mentioned method (1). According to FIG. 9, the pixel array 80 includes a plurality of

scan lines

82a and 82b electrically connected to the scan line driving circuit 84, and data lines 86a and 86b electrically connected to the data line driving circuit 88. Pixels A, B ′, and C ′. Pixels A, B ', C' position of corresponding pixels A respectively, in FIG 1, B, C, the respective thin film transistor _{_{T A, T B ', T}} C' and are not liquid crystal cell (shown corresponding thereto )including. TFT _{_{T A, T B ', T}} C' drain electrode 94a of, 94b, 94c are respectively connected to the data line 86a connected, a

source electrode

96a, 96b, 96c is the pixel electrode 90a of each liquid crystal cell, 90b, 90c and Is done. Semiconductor layers 98a, 98b, 98c are further provided between each gate electrode, each source electrode, and each drain electrode.
[0027]
The

pixel electrodes

90a, 90b, and 90c include

extended portions

99a, 99b, and 99c, respectively, and the

extended portions

99a, 99b, and 99c partially overlap the scan lines 82a to form overlapping

regions

100a, 100b, and 100c whose areas increase gradually. Form. Note that the

pixel electrodes

90a, 90b, and 90c respectively overlap the scan lines 82b to form

overlap regions

102a, 102b, and 102c, and form storage capacitors for the pixels A, B ', and C'.
[0028]
In a fourth embodiment of the present invention, the overlap region 100a, 100b, the 100c compensation capacitor _{_{C 'A, C' B,}} C 'C ( not shown) and correspond, since the area is gradually increasing, the corresponding The capacitance values C _A , C _B , and C _{C of} the compensation capacitors C ′ _A , C ′ _B , and C ′ _C also increase (C _A <C _B <C _C ), and the V _{FD of the} pixels A, B ′, and C ′. Let the relationship be (V _FD ) _A ≒ (V _FD ) _{B '} ≒ (V _FD ) _C' .
[0029]
In the fourth embodiment of the present invention, each of the

overlap regions

100a, 100b, and 100c may be formed by extending each scan line 82a below each of the

pixel electrodes

90a, 90b, and 90c.
[0030]
The above is a preferred embodiment of the present invention, and does not limit the scope of the present invention. Therefore, any modification or alteration that can be made by those skilled in the art and that is made in the spirit of the present invention and that has an equivalent effect on the present invention shall fall within the scope of the claims of the present invention. I do.
[0031]
【The invention's effect】
Compared with the prior art, the present invention attaches a compensation capacitor to each pixel, each compensation capacitor comprising an overlap area where each pixel electrode overlaps a scan line corresponding to each pixel electrode. Further substantially coincide the V _FD of each pixel by adjusting the capacitance value of each compensation capacitor, to improve the display quality by reducing the flicker of the LCD panel.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a conventional thin film transistor liquid crystal display panel.
FIG. 2 is an equivalent circuit diagram of a single pixel in a thin film transistor liquid crystal display panel.
FIG. 3 is an explanatory diagram showing a waveform of an output voltage of each driver integrated circuit chip.
FIG. 4 is an equivalent circuit diagram of a liquid crystal display panel according to the present invention.
FIG. 5 is a first plan view of a pixel array according to the first embodiment of the present invention.
FIG. 6 is a second plan view of the pixel array according to the first embodiment of the present invention.
FIG. 7 is a plan view of a pixel array according to a second embodiment of the present invention.
FIG. 8 is a plan view of a pixel array according to a third embodiment of the present invention.
FIG. 9 is a plan view of a pixel array according to a fourth embodiment of the present invention.
[Explanation of symbols]
Reference Signs List 10 thin film transistor 12 lower substrate 14 pixel array 16 scan line drive circuit area 16a, 16b, 16c driver integrated circuit chip 17 bus line 18 data line drive circuit area 20 pixel 40

equivalent circuit

50, 80

pixel array

52, 52a, 82a,

82b Scan lines

54, 84 Scan line

drive circuit areas

56a, 56b, 56c, 86a,

86b Data lines

58a, 58b, 58c, 90a, 90b,

90c Pixel electrodes

60a, 60b, 60c, 92a, 92b,

92c Gate electrodes

62a, 62b , 62c, 94a, 94b,

94c Drain electrodes

64a, 64b, 64c, 96a, 96b,

96c Source electrodes

66a, 66b, 66c, 98a, 98b, 98c Semiconductor layers 67a, 67b,

67c

8a, 68b, 68c, 70a, 70b,

70c Overlap area

69a, 69b, 69c, 71a, 71b,

71c Extension part

72a, 72b, 72c, 74a, 74b, 74c Overlap area 88 Data

line drive circuits

99a, 99b, 99c stretched

portions

100a, 100b, 100c, 102a, 102b, 102c overlap area

Claims

A liquid crystal display panel including an upper substrate, a lower substrate, and a plurality of pixels provided between the upper substrate and the lower substrate, wherein each of the pixels obtains substantially the same feed-through voltage. A liquid crystal display panel comprising at least one compensation capacitor.

The liquid crystal display panel further includes a first scan line, a second scan line, and a scan line driving circuit, wherein each pixel is between the first scan line and the second scan line, and the first scan line and the second scan line. 2. The liquid crystal display panel according to claim 1, wherein each of the two scan lines has a first input terminal for receiving a signal from the scan line driving circuit.

3. The liquid crystal display panel according to claim 2, wherein the capacitance value of each compensation capacitor increases according to the distance between the first input end of the first scan line and each compensation capacitor.

Each pixel includes a liquid crystal cell and a thin film transistor, and the liquid crystal cell includes a common electrode, a pixel electrode connected to each corresponding compensation capacitor, and a liquid crystal molecular layer provided between the pixel electrode and the common electrode. Wherein the thin film transistor includes a gate electrode electrically connected to the first scan line, a drain electrode electrically connected to the corresponding first data line, and an electrical connection to each corresponding pixel electrode. 4. The liquid crystal display panel according to claim 3, further comprising: a source electrode.

5. The liquid crystal display panel according to claim 4, wherein each of the compensation capacitors comprises a first overlap region overlapping each pixel electrode and the first scan line.

6. The liquid crystal of claim 5, wherein the area of the first overlap region increases according to a distance between a first input end of a first scan line and a pixel corresponding to each first overlap region. Display panel.

5. The liquid crystal display panel according to claim 4, wherein the compensation capacitor includes a second overlap region where each gate electrode overlaps a corresponding source electrode.

The liquid crystal of claim 7, wherein the area of the second overlap region increases according to a distance between a first input end of a first scan line and a pixel corresponding to each second overlap region. Display panel.

The method of claim 7, wherein each pixel further comprises a storage capacitor, and a capacitance value of each storage capacitor decreases with an increase in a distance between a first input end of a second scan line and each storage capacitor. Liquid crystal display panel.

The liquid crystal display panel further includes a second data line and a data line driving circuit, wherein each pixel is connected to the second data line, and the second data line receives a signal from the data line driving circuit and has a second input terminal. The liquid crystal display panel according to claim 1, further comprising:

The liquid crystal display panel according to claim 10, wherein the capacitance value of each storage capacitor increases according to the distance between the second input terminal and each compensation capacitor.

Each pixel is between a third scan line and a fourth scan line, each pixel includes a liquid crystal cell and a thin film transistor, the liquid crystal cell having a common electrode and a pixel electrode connected to each corresponding compensation capacitor. And a liquid crystal molecular layer provided between the pixel electrode and the common electrode, wherein the thin film transistor has a gate electrode electrically connected to the third scan line, and a corresponding second data line. 12. The liquid crystal display panel according to claim 11, further comprising: a drain electrode connected thereto; and a source electrode electrically connected to each corresponding pixel electrode.

13. The liquid crystal display panel according to claim 12, wherein each of the compensation capacitors comprises a first overlap area overlapping a third scan line corresponding to each pixel electrode.

14. The liquid crystal display panel according to claim 13, wherein an area of the first overlap region increases according to a distance between a second input terminal and a pixel corresponding to each first overlap region.

13. The liquid crystal display panel according to claim 12, wherein each of the compensating capacitors includes a second overlap region where each gate electrode overlaps a corresponding source electrode.

16. The liquid crystal display panel according to claim 15, wherein an area of the second overlap region increases according to a distance between a second input terminal and a pixel corresponding to each second overlap region.

13. The liquid crystal display panel according to claim 12, wherein each pixel further comprises a storage capacitor, and a capacitance value of each storage capacitor decreases with an increase in a distance between the second input terminal and each storage capacitor.

A liquid crystal display panel, the liquid crystal display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels, each pixel includes a pixel electrode, a thin film transistor, each thin film transistor A gate electrode connected to the corresponding scan line, a drain electrode connected to the corresponding data line, and a source electrode connected to the pixel electrode, wherein the scan line corresponding to the pixel electrode overlaps the first one; A liquid crystal display panel, wherein an overlap region is formed, and an area of each first overlap region increases along a first direction.

20. The liquid crystal display panel according to claim 18, wherein the first overlap region forms a compensation capacitor for each pixel to obtain substantially the same feed-through voltage to reduce flicker of the liquid crystal display panel.

20. The liquid crystal display panel according to claim 18, wherein each of the pixel electrodes has a first extension portion, and each first extension portion overlaps a corresponding scan line to form a first overlap region.

20. The liquid crystal display panel according to claim 18, wherein each of the pixel electrodes overlaps a second extending portion of a corresponding scan line to form a first overlap region.

22. The liquid crystal display panel according to claim 21, wherein a protrusion is provided above each of the pixel electrodes, and each of the protrusions is on a second extending portion to adjust a direction of liquid crystal molecules.

The liquid crystal display panel further includes a scan line driving circuit and a data line driving circuit, wherein the scan line driving circuit inputs a signal to each scan line through a first input terminal of each scan line, and the data line driving circuit outputs each data line. 19. The liquid crystal display panel according to claim 18, wherein a signal is input to each data line through a second input terminal of the line.

The first direction is parallel to each scan line, and the area of each first overlap region is between each first overlap region and the first input end of the scan line corresponding to each first overlap region. The liquid crystal display panel according to claim 23, wherein the liquid crystal display panel increases with distance.

The first direction is parallel to each scan line, and the area of each first overlap region is between each first overlap region and each second overlap region and the second input end of the corresponding scan line. The liquid crystal display panel according to claim 23, wherein the liquid crystal display panel increases with distance.

24. The liquid crystal display panel according to claim 23, wherein each of the gate electrodes overlaps with each of the corresponding source electrodes to form a second overlap region.

27. The liquid crystal display panel according to claim 26, wherein the second overlap region forms a compensation capacitor for each pixel to obtain substantially the same feedthrough voltage to reduce flicker of the liquid crystal display panel.

28. The area of the second overlap area increases according to a distance between each second overlap area and a first input end of a data line corresponding to each second overlap area. Liquid crystal display panel as described.

28. The area of the second overlap region increases according to a distance between each second overlap region and a second input end of a data line corresponding to each second overlap region. Liquid crystal display panel as described.

A liquid crystal display panel, wherein the liquid crystal display panel forms a first overlap region by overlapping a scan line drive circuit, at least one scan line electrically connected to the scan line drive circuit, and the scan line. At least one first pixel having a first pixel electrode having a first pixel electrode, a first section on a scan line, and at least one second pixel having a second pixel electrode overlapping the scan line to form a second overlap region. A second section of the scan line, wherein the first section is between the scan line driving circuit and the second section, and the area of the second overlap region is larger than the area of the first overlap region. Characteristic liquid crystal display panel.

The first pixel further comprises a first thin film transistor, wherein the first thin film transistor is electrically connected to a scan line, a first drain electrode electrically connected to a first data line, The method of claim 30, further comprising a first source electrode electrically connected to the first pixel electrode, wherein the first gate electrode and the first source electrode overlap to form a third overlap region. Liquid crystal display panel.

The second pixel further includes a second thin film transistor, the second thin film transistor is electrically connected to a scan line, a second gate electrode, a second drain electrode electrically connected to a second data line, The method of claim 30, further comprising a second source electrode electrically connected to the second pixel electrode, wherein the second gate electrode and the second source electrode overlap to form a fourth overlap region. Liquid crystal display panel.

33. The liquid crystal display panel according to claim 32, wherein the area of the fourth overlap region is larger than the area of the third overlap region.

A liquid crystal display panel, wherein the liquid crystal display panel includes a data line driving circuit, at least one data line electrically connected to the data line driving circuit, and a second line electrically connected to the first scan line. One gate electrode, a first drain electrode electrically connected to the data line, and a first source electrode electrically connected to the first pixel electrode, wherein the first pixel electrode and the first scan line are A first section of the data line, a first gate electrode electrically connected to the second scan line, and a first gate electrode electrically connected to the second scan line. A second drain electrode connected to the second pixel electrode, and a first source electrode electrically connected to the second pixel electrode. And at least one second thin film transistor where the second scan line overlaps to form a second overlap region, including a second section in the data line, of which the first section is a scan line driving circuit and a second section. Wherein the area of the second overlap region is greater than the area of the first overlap region.

The first gate electrode and the first source electrode overlap to form a third overlap region, and the second gate electrode and the second source electrode overlap to form a fourth overlap region, of which a fourth overlap region is formed. 35. The liquid crystal display panel according to claim 34, wherein the area is larger than the area of the third overlap region.

The first section includes a plurality of first thin film transistors, and an area of each first overlap region increases according to a distance between the data driving circuit and each first pixel corresponding to each first overlap region. 35. The liquid crystal display panel according to claim 34, wherein:

The second section includes a plurality of second thin film transistors, and an area of each second overlap region increases according to a distance between the data driving circuit and each second pixel corresponding to each second overlap region. 35. The liquid crystal display panel according to claim 34, wherein:

A liquid crystal display panel, comprising: a plurality of scan lines transmitting a scan signal from a scan line driving circuit; a plurality of data lines transmitting a video signal from a data line driving circuit; and a plurality of pixels. Each pixel includes a liquid crystal capacitor, a corresponding scan line, a corresponding data line, a thin film transistor electrically connected between the liquid crystal capacitor, the liquid crystal capacitor, and the thin film transistor. A liquid crystal display panel comprising: a compensation capacitor electrically connected between the scan line to be connected and a compensation capacitor for applying substantially the same feed-through voltage to each pixel.

39. The liquid crystal display panel according to claim 38, wherein a capacitance value of each compensation capacitor increases according to a distance between a pixel corresponding to each compensation capacitor and a scan line driving circuit.

39. The liquid crystal display panel according to claim 38, wherein a capacitance value of each compensation capacitor increases according to a distance between a pixel corresponding to each compensation capacitor and a data line driving circuit.

39. The liquid crystal display panel according to claim 38, wherein the liquid crystal display panel further comprises a storage capacitor electrically connected to the liquid crystal capacitor.

42. The liquid crystal display panel according to claim 41, wherein the capacitance value of each compensation capacitor decreases as the distance between each storage capacitor and the scan line driving circuit increases.

42. The liquid crystal display panel according to claim 41, wherein the capacitance value of each of the compensation capacitors decreases as the distance between each of the storage capacitors and the data line driving circuit increases.