TWI461807B - Pixel structure of in-cell touch display panel and method of forming the same - Google Patents

Pixel structure of in-cell touch display panel and method of forming the same Download PDF

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Publication number
TWI461807B
TWI461807B TW099122451A TW99122451A TWI461807B TW I461807 B TWI461807 B TW I461807B TW 099122451 A TW099122451 A TW 099122451A TW 99122451 A TW99122451 A TW 99122451A TW I461807 B TWI461807 B TW I461807B
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Taiwan
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pixel
capacitance value
gate
lc1
ratio
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TW099122451A
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Chinese (zh)
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TW201202814A (en
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Ko Ruey Jen
Hung Chang Chang
Chao Hui Wu
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Hannstar Display Corp
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Description

Pixel structure of in-cell touch display panel and forming method thereof

The invention relates to a pixel structure of an in-cell touch display panel and a forming method thereof, in particular to adjusting a capacitance ratio of each pixel (C pg + C gd ) / (C st + C lc + C gd + C pg ), a pixel structure of an in-cell touch display panel and a method for forming the same to solve the electrical problem caused by pixels having different light transmission areas.

Recently, due to the increasing use of touch display panels, the technology of in-cell touch sensors has received much attention. The in-cell touch sensing component directly forms the touch sensing component in each pixel, and it is unavoidable to sacrifice part of the aperture ratio. In the prior art, the usual method is to reduce the area of the red sub-pixel, the green sub-pixel, and the blue sub-pixel, and the extra area is used to place the touch sensing element. For example, the light-transparent areas of the original red sub-pixels, green sub-pixels, and blue sub-pixels each account for one-third of the entire area of the pixel, if the red sub-pixel, the green sub-pixel, the blue The area of the sub-pixel is reduced to one-fourth of the entire area of the pixel, and there will be an additional quarter of the area for the touch sensing component, which can be analogized in this way. The key is to make the red color The light transmission area of the pixels, the green sub-pixels, and the blue sub-pixels remain the same. Please refer to Figure 1. FIG. 1 is a schematic diagram of a pixel using an in-cell touch sensing element in the prior art. As shown in FIG. 1 , since the touch sensing element T needs to be disposed in the pixel, the light transmissive area of the three sub-pixels of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B is substantially The same, but the light transmission area is less than one third of the entire area of the pixel. However, this practice causes a decrease in brightness and affects display quality.

One of the objects of the present invention is to provide a pixel structure of an in-cell touch display panel and a method for forming the same to provide a better picture effect.

A preferred embodiment of the present invention provides a pixel structure of an in-cell touch display panel. The pixel structure includes a substrate defining a plurality of sub-pixel regions and a plurality of sub-pixels. Each pixel is set in each pixel area, and the light transmission area of at least one sub-pixel is different from the light transmission area of the other sub-pixels. Wherein, each pixel includes a liquid crystal capacitor having a liquid crystal capacitance value C lc , a thin film transistor having a gate-to-deuterium capacitance value C gd and a gate-to-pixel electrode capacitance value C pg , And a storage capacitor having a storage capacitor value C st . Moreover, each pixel has a capacitance ratio, and the capacitance ratio is defined as (C pg + C gd ) / (C st + C lc + C gd + C pg ), and the capacitance ratio of each pixel is substantially the same.

A preferred embodiment of the present invention further provides a method of forming a pixel structure of an in-cell touch display panel, comprising the following steps. First, a substrate is provided having at least a first pixel region and a second pixel region defined thereon. Then, in the first pixel region, a first pixel is expected to be set, and in the second pixel region, a second pixel is expected to be set. Subsequently, at 0 <C lc1 / C lc2 < 1 , adjusting C lc1, C gd1, C st1 , C pg1, C lc2, C gd2, C st2, C pg2 wherein at least one of the first pixel the capacitance ratio (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the second sub-pixel capacitance ratio of (C pg2 + C gd2 / ( C st2 + C lc2 + C gd2 + C pg2 ) is substantially the same, wherein C lc1 is the first liquid crystal capacitance value of the first pixel, C gd1 is the first gate and the first gate capacitance value of the first pixel, C st1 system It is the first storage capacitor value of the first pixel, C pg1 is the first pixel of the first pixel and the capacitance between the gate electrodes, and C lc2 is the second pixel of the second pixel. The liquid crystal capacitance value, C st2 is the second storage capacitor value of the second pixel, C gd2 is the second gate and the second gate and the drain capacitance value, and the C pg2 is the second after one sub-pixel of the second pixel electrode and the gate electrode capacitance value. the C lc1 after the adjustment, C gd1, C st1, C pg1, in the first pixel region, having a first liquid crystal capacitor formed one value of the first liquid crystal capacitor C LC1, having a first One stored value of the capacitance of the first storage capacitor C st1, and a first capacitance value between the gate and drain electrodes between C gd1 and the capacitance value C pg1 one first thin film transistor having a first pixel electrode and the gate. And, according to the adjusted C lc2 , C gd2 , C st2 , C pg2 , in the second pixel region, forming a second liquid crystal capacitor having a second liquid crystal capacitance value C lc2 and having a second storage capacitor value C one st2 second storage capacitor, and a second gate between the drain and the capacitance value C gd2 one having a capacitance value between a gate electrode and a second pixel C pg2 second thin film transistor.

The pixel structure of the in-cell touch display panel of the present invention and the method for forming the same are used to adjust the capacitance ratio of each pixel (C pg + C gd ) / (C st + C lc + C gd + C pg ), Make the capacitance ratio of each pixel substantially the same. Therefore, the present invention not only can appropriately adjust the aperture ratio of the three sub-pixels of the red sub-pixel, the green sub-pixel, and the blue sub-pixel, thereby reducing the brightness reduction to the slightest and achieving the effect of uniform color mixing. Moreover, it is possible to avoid the extra sub-pixel electrical problem that may be derived when each pixel has a different aperture ratio.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the differences in the functions of the elements as the basis for the distinction. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to".

Please refer to Figure 2. FIG. 2 is a partial schematic diagram showing an equivalent circuit of a pixel structure of an in-cell touch display panel according to a first preferred embodiment of the present invention. As shown in FIG. 2, the pixel structure of the in-cell touch display panel of the embodiment includes a substrate 200 and a plurality of sub-pixels, such as a first pixel P1 and a second pixel P2. And a third pixel P3. For the sake of simplicity, only three sub-pixels are shown in the figure, but not limited to this. Moreover, on the substrate 200, a plurality of sub-pixel regions are defined, such as a first pixel region 201, a second pixel region 202, and a third pixel region 203. Furthermore, each pixel is set in each pixel region, for example, the first pixel P1 is set in the first pixel region 201, and the second pixel P2 is set in the second pixel region 202, The cubic pixel P3 is set in the third pixel area 203. The pixel includes a liquid crystal capacitor having a liquid crystal capacitance value C lc , a gate capacitance between the gate and the drain C gd , and a thin film transistor having a pixel electrode and a gate capacitance C pg . And a storage capacitor having a storage capacitance value C st . For example, taking the first pixel P1 as an example, the first pixel P1 includes a first liquid crystal capacitor having a first liquid crystal capacitance value C lc1 , and a first gate and a drain capacitance value C gd1 . a first thin film transistor having a first pixel electrode and a gate capacitance value C pg1 , and a first storage capacitor having a first storage capacitance value C st1 . Furthermore, each pixel has a capacitance ratio, and the capacitance ratio is defined as (C pg + C gd ) / (C st + C lc + C gd + C pg ), and the capacitance ratio of each pixel is substantially the same. in other words, in the first pixel P1, the second pixel P2 as an example, (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and (C pg2 + C gd2 ) / (C st2 + C lc2 + C gd2 + C pg2 ) is substantially the same. In addition, a touch sensing component 240 can be disposed in the first pixel region 201, but is not limited thereto. Moreover, the present embodiment does not limit the type of the touch sensing element 240 and the constituent elements. Therefore, the equivalent circuit diagram is not shown in FIG. 2 and is only indicated by a frame line. In this embodiment, the touch sensing component 240 can be an optical touch sensing component, or can be other suitable touch sensing components, such as a resistive touch sensing component or a capacitive touch sensing component. Components, etc.

Please refer to Figure 3 and refer to Figure 2 together. FIG. 3 is a partial schematic view showing the configuration of a pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention. 2 and 3 are the same embodiment, the former is represented by an equivalent circuit diagram, the latter is represented by a configuration diagram, and the same elements are denoted by the same symbols. It should be noted that a general display panel may be composed of two transparent substrates, respectively a substrate having a thin film transistor, referred to as a TFT substrate, and a substrate having a color filter, referred to as a color filter. Light substrate (CF substrate). In order to avoid the complexity of the illustration, the configuration diagram of FIG. 3 only shows the thin film transistor substrate and the components located thereon. Taking the first pixel P1 as an example, in the embodiment, the first liquid crystal capacitor in FIG. 2 may be a first pixel electrode 211 (as shown in FIG. 3), a common electrode 250, and A liquid crystal layer (not shown) is interposed between the first pixel electrode 211 and the common electrode 250. The common electrode 250 may be disposed on the color filter substrate and is not disposed on the thin film transistor substrate, and thus is not shown in FIG. Furthermore, the first storage capacitor in FIG. 2 may be a common electrode capacitor (C st on common) formed between a first storage electrode 221 and a first pixel electrode 211 in FIG. 3, but not To this end, it can be configured for other suitable components. For example, in another embodiment, the first storage capacitor of the present invention may be partially overlaps the first pixel electrode formed on the gate electrode on the gate capacitance (C st on gate). Furthermore, the first thin film transistor in FIG. 2 may be a region surrounded by a frame line indicated as 231 in FIG. Similarly, the above description is also applicable to the second pixel P2 and the third pixel P3, and details are not described herein again. In addition, as shown in FIG. 3, the light transmission area of at least one sub-pixel is different from the light transmission area of the other sub-pixels. The light transmissive area may be determined by an area of the pixel element of the sub-pixel that is not obscured by other shading elements. In this embodiment, two adjacent sub-pixels having different light transmission areas may be the first pixel P1 and the second pixel P2, respectively, and the first pixel P1 is located in a first pixel region. 201. The second pixel P2 is located in a second pixel region 202, and the light transmission area of the second pixel P2 is greater than the light transmission area of the first pixel P1. The area of the first pixel area 201 and the second pixel area 202 may be substantially the same, and the light transmission area of the first pixel P1 is smaller than the light transmission area of the second pixel P2, therefore, The primary pixel area 201 may have additional space for setting the touch sensing component 240, but is not limited thereto. Similarly, the present embodiment does not limit the type of the touch sensing element 240 and the constituent elements, and therefore is only indicated by a frame line in FIG.

The rules that can be found between the above-mentioned pixels can be further explained below. Please refer to Figure 2 and Figure 3 together. First, for the first pixel P1 and the second pixel P2, if the first pixel P1 is one of the first liquid crystal capacitance value C lc1 and the second pixel P2 is the second liquid crystal capacitance value C The ratio of lc2 is C lc1 /C 1c2 , and the ratio of the first storage capacitor value C st1 of one of the first pixels P1 to the second storage capacitance value C st2 of the second pixel P2 is C st1 /C st2 Generally, it may be equal to C lc1 /C lc2 , and one of the first gate P1 is between the first gate and the drain capacitance C gd1 and the second pixel P2 is the second gate and the drain capacitance value. the ratio of C gd2 C gd1 / C gd2 may be substantially equal to C lc1 / C lc2, and one of the first pixel P1 of the first pixel electrode and the gate electrode capacitance value C pg1 one second sub-pixel P2 the ratio between the capacitance value of the second pixel electrode and the gate C pg2 C pg1 / C pg2 may be substantially equal to C lc1 / C lc2. For example, as shown in FIG. 3, the area of the first pixel electrode 211 is smaller than the area of the second pixel electrode 212, assuming the same liquid crystal material, the same common electrode, and the same pixel electrode and common electrode. At the pitch, the first liquid crystal capacitance value C lc1 is smaller than the second liquid crystal capacitance value C lc2 . Based C st1 / C st2 can be substantially equal to the condition C lc1 / C lc2, the first storage electrode 221 may be less than the area of the second storage electrode 222; and based on C gd1 / C gd2 may be substantially equal to C lc1 / C lc2 of The size of the first thin film transistor 231 may be smaller than the size of the second thin film transistor 232. Further, the first pixel electrode 211 and the adjusted area and the distance between the gate area and the pixels or adjusting the distance between the second electrode 212 and the gate of the C pg1 / C pg2 may be substantially equal to C lc1 / C Lc2 . Secondly, for the first pixel P1 and the third pixel P3, if the first pixel P1 is one of the first liquid crystal capacitance value C lc1 and the third pixel P3 is the third liquid crystal capacitance value C The ratio of lc3 is C lc1 /C lc3 , and the ratio of the first storage capacitor value C st1 of one of the first pixels P1 to the third storage capacitor value C st3 of the third pixel P3 is generally C st1 /C st3 The upper gate may be equal to C lc1 /C lc3 , and one of the first pixel P1 is between the first gate and the drain capacitance C gd1 and the third pixel P3 is the third gate and the drain capacitance C the GD3 ratio C gd1 / C gd3 may be substantially equal to C lc1 / C lc3, and one of the first pixel P1 of the first pixel electrode and the gate capacitance value C pg1 between the third pixel P3 of one the ratio of the capacitance value between the pixel electrode and the gate three C pg3 of C pg1 / C pg3 may be substantially equal to C lc1 / C lc3. For example, as shown in FIG. 3, the area of the first pixel electrode 211 is smaller than the area of the third pixel electrode 213, assuming that the same liquid crystal material, the same common electrode, and the same pixel electrode and common electrode are At the pitch, the first liquid crystal capacitance value C lc1 is smaller than the third liquid crystal capacitance value C lc3 . The area of the first storage electrode 221 may be smaller than the third storage electrode 223 based on C st1 /C st3 substantially equal to the condition of C lc1 /C lc3 ; and substantially equal to C lc1 /C lc3 based on C gd1 /C gd3 The size of the first thin film transistor 231 may be smaller than the size of the third thin film transistor 233. Similarly, adjust the distance between the third area and the pixel electrode 213 and the gate, so that C pg1 / C pg3 may be substantially equal to C lc1 / C lc3.

In addition, the first pixel P1, the second pixel P2, and the third pixel P3 may be used to display three colors, respectively, and the three colors may include red, green, and blue, but are not limited thereto. For example, each pixel can be used to display other colors, or more than two sub-pixels can be used to display the same color. In this embodiment, the first pixel P1 can be used to display red, the second pixel P2 can be used to display green, and the third pixel P3 can be used to display blue. Moreover, in this embodiment, the light transmission area of the third pixel P3 may be less than or equal to the light transmission area of the second pixel P2, and the light transmission area of the third pixel P3 may be larger than the first painting. The light transmission area of the prime P1, and the second pixel P2 can be used to display green. In other words, in the first pixel P1, the second pixel P2, and the third pixel P3, the secondary pixels having the largest light transmission area can be used to display green. Accordingly, in this example, the aperture ratio of the sub-pixels displaying green can be maximized to reduce the luminance loss, and the ratio of the aperture ratios of the red and blue sub-pixels can be matched to maintain a certain degree of uniform color mixture.

It is worth noting that although the above is only three sub-pixels, it is not limited to this, but it can be two sub-pixels, or four sub-pixels, or five sub-pixels and other implementations. example. In addition, the thin film transistor for charging and discharging the sub-pixel electrode can be such that the sub-pixel electrode can reach the desired potential within the time when the gate line is turned on, and therefore, the thin film transistor corresponding to the area of the different pixel areas Can have different sizes. For example, in the embodiment, for the first pixel P1, the second pixel P2, and the third pixel P3, the area of the first pixel electrode 211 can be the smallest, and the second pixel is The area of the electrode 212 can be the largest, and the area of the third pixel electrode 213 can be centered. If the size of the second thin film transistor 232 corresponding to the second pixel electrode 212 remains unchanged, the size of the first thin film transistor 231 corresponding to the first pixel electrode 211 may be reduced, and corresponds to the third The size of the third thin film transistor 233 of the sub-pixel electrode 213 can also be reduced. The size of the thin film transistor may refer to a channel width/length ratio (W/L), but is not limited thereto, and the scale of the reduction may be determined according to an electrical simulation result. Therefore, the present embodiment can have the advantage of reducing the gate line load and reducing the leakage current.

The method for forming the pixel structure of the in-cell touch display panel of the present embodiment is described below by taking two sub-pixels as an example. Please refer to Figure 4 and refer to Figure 2 and Figure 3 together. FIG. 4 is a flow chart showing a method for forming a pixel structure of an in-cell touch display panel according to a first preferred embodiment of the present invention. As shown in FIG. 4, first, step 40 provides a substrate 200 (shown in FIG. 2) on which at least a first pixel region 201 and a second pixel region 202 can be defined. Next, in step 42 of the first pixel region 201, a first pixel P1 is expected to be set, and in the second pixel region 202, a second pixel P2 is expected to be set. Subsequently, at step 44 0 <C lc1 / C lc2 < 1 , adjusting C lc1, C gd1, C st1 , C pg1, C lc2, C gd2, C st2, C pg2 wherein at least one of the first the ratio of pixel capacitance (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the second sub-pixel capacitance ratio of (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2 ) is substantially the same, wherein C lc1 is the first liquid crystal capacitance value of one of the first pixels P1, C st1 is the first storage capacitance value of the first pixel P1, and the C gd1 system For the first pixel P1, the first gate and the drain capacitance value, C pg1 is the first pixel P1, the first pixel electrode and the gate capacitance value, and the C lc2 system is the second. The second liquid crystal capacitance value of one of the secondary pixels P2, C st2 is the second storage capacitance value of the second pixel P2, and C gd2 is the second gate and the drain of the second pixel P2. The capacitance value and C pg2 are the second pixel electrode and gate capacitance values of the second pixel P2. The condition of 0<C lc1 /C lc2 <1 may be that the area of the first pixel electrode 211 is smaller than the area of the second pixel electrode 212, but is not limited thereto.

As shown in FIG. 4, after step 46, according to the adjusted C lc1 , C gd1 , C st1 , C pg1 , in the first pixel region 201, one of the first liquid crystal capacitance values C lc1 is formed first. the liquid crystal capacitor, a first storage capacitor having a value of one of the first storage capacitor C st1, and a first gate between the drain and the capacitance value C gd1 having a first pixel electrode and the gate capacitance value between one of C pg1 A thin film transistor 231. In this embodiment, the first liquid crystal capacitor has an adjusted first liquid crystal capacitance value C lc1 , which can be adjusted by controlling the area of the first pixel electrode 211 of the first liquid crystal capacitor, but not limited thereto. Other conditions can be adjusted by adjusting the first liquid crystal capacitor. For example, the distance between the first pixel electrode 211 and the common electrode 250 or the type or characteristic of the liquid crystal layer between the first pixel electrode 211 and the common electrode 250 may be adjusted. In addition, in this embodiment, the first storage capacitor has an adjusted first storage capacitor value C st1 , which can be adjusted by controlling the area of the first storage electrode 221 of the first storage capacitor, but not limited thereto. And can adjust other condition parameters of the first storage capacitor. For example, the distance between the first storage electrode 221 and the first pixel electrode 211 or the type or characteristic of the material between the first storage electrode 221 and the first pixel electrode 211 can be adjusted. Similarly, in the embodiment, the first thin film transistor 231 has a first gate-to- deuterium capacitance value C gd1 , which can be adjusted by controlling the size and shape of the first thin film transistor, but not This is limited. Furthermore, the first pixel electrode 231 and the first liquid crystal capacitor have a first pixel electrode and a gate capacitance value C pg1 , and the area and distance between the control gate and the first pixel electrode 211 can be transmitted. To make adjustments, but not to limit it. And, in step 48, according to the adjusted C lc2 , C gd2 , C st2 , C pg2 , in the second pixel region, forming a second liquid crystal capacitor having a second liquid crystal capacitance value C lc2 and having a second storage capacitor A second storage capacitor having a value C st2 and a second thin film transistor 232 having a second gate-to- deuterium capacitance value C gd2 and a second pixel-to-gate capacitance value C pg2 . Similarly, the adjustment manners of the second liquid crystal capacitor, the second storage capacitor, and the second thin film transistor 232 may be similar to the adjustment manners of the first liquid crystal capacitor, the first storage capacitor, and the first thin film transistor 231. This will not be repeated here. In addition, the method for forming the pixel structure of the in-cell touch display panel of the present embodiment may further include forming a touch sensing component 240 in the first pixel region 201, but not limited thereto. For example, the touch sensing component 240 can be formed in other sub-pixel regions, and the number of the touch sensing components 240 is not limited to one, and can be determined according to actual product specifications and requirements.

Further, in FIG. 4, relating to the step of adjusting the 44 C lc1, C gd1, C st1 , C pg1, C lc2, C gd2, C st2, C pg2 wherein at least one of the way, there are at least two ways, But not limited to this. The first way can include the following steps. First, the first liquid crystal capacitance value C lc1 and the second liquid crystal capacitance value C lc2 are first selected. In this embodiment, the area of a suitable first pixel electrode 211 and the area of a suitable second pixel electrode 212 can be selected according to the requirements of color, and the same common liquid crystal material and the same common electrode are fixed. And the distance between the same pixel electrode and the common electrode can further determine the first liquid crystal capacitance value C lc1 and the second liquid crystal capacitance value C lc2 . Next, the ratio of C lc1 /C lc2 is calculated. Subsequently, the first storage capacitor value C st1 and the second storage capacitor value C st2 are adjusted such that the ratio of C st1 /C st2 is substantially equal to C lc1 /C lc2 . Thereafter, the first gate-to- deuterium capacitance value C gd1 and the second gate-to- deuterium capacitance value C gd2 are adjusted such that the ratio of C gd1 /C gd2 is substantially equal to C lc1 /C lc2 . Then, adjusting the first pixel electrode and the capacitance between the gate and the second pixel value C pg1 between the gate electrode and the capacitance value C pg2, so C pg1 / C ratio is substantially equal to the pg2 C lc1 / C lc2. The ratio C st1 / C st2, the ratio C gd1 / C gd2 of, and the ratio C pg1 / C pg2 is substantially equal to the case of C lc1 / C lc2, the capacitance ratio can make the first pixel of the (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the second sub-pixel capacitance ratio of (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2) substantially Same on the same. From another point of view, the first method can select the first pixel as the basis, and scale up or down the second pixel C lc2 , C gd2 , C st2 , C pg2 to make the first painting the ratio of the capacitance element (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the second sub-pixel capacitance ratio of (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2) are substantially the same. Further, the second embodiment, it is adjusted separately C lc1, C gd1, C st1 , C pg1, C lc2, C gd2, C st2, C pg2, to make the pixels of the first capacitance ratio (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the capacitance ratio of the second sub-pixel (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2) are substantially the same. In other words, the second embodiment may not be limited to the ratio C lc1 / C lc2, the ratio that is the ratio C st1 / C st2 of, C gd1 / C ratio of GD2, and C pg1 / C pg2 that it can not The limitation of C lc1 /C lc2 can be adjusted more elasticly , and the reduction of the aperture ratio caused by the intentional amplification of the area of the second storage electrode 222 can be avoided.

The method for forming the pixel structure of the in-cell touch display panel of the present embodiment will be described below by taking another pixel as an example. Please refer to Figure 5. FIG. 5 is a flow chart showing a method for forming another pixel of the pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention. As shown in FIG. 5, first, step 50 defines a third pixel region 203 on the substrate 200, and in the third pixel region 203, a third pixel P3 is expected to be set. Subsequently, at step 52 0 <C lc1 / C lc3 < 1 , adjusting C lc3, C gd3, C st3 , C pg3 wherein at least one of the pixels of the first capacitance ratio (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the third sub-pixel capacitance ratio of (C pg3 + C gd3) / (C st3 + C lc3 + C gd3 + C pg3) is substantially the same, wherein C Lc3 is the third liquid crystal capacitor value of the third pixel, C st3 is the third storage capacitor value of the third pixel, and C gd3 is the third gate of the third pixel. The interelectrode capacitance value and C pg3 are the third pixel element and the interelectrode capacitance value of the third pixel. Thereafter, step 54 forms a third liquid crystal capacitor having a third liquid crystal capacitance value C lc3 in the third pixel region 203 according to the adjusted parameters C lc3 , C gd3 , C st3 , C pg3 , and has a third A storage capacitor value C st3 is a third storage capacitor, and has a third gate-to- deuterium capacitance value C gd3 and a third thin film transistor 233 having a third pixel electrode and inter-gate capacitance value C pg3 . For the same reason, the adjustment of the third storage capacitor value C st3 can be adjusted by controlling the area of the third storage electrode 223, but not limited thereto. Further, the adjustment method of the third gate-to-drain capacitance value C gd3 is adjusted by controlling the size and shape of the third thin film transistor 233. Furthermore, the adjustment method of the third pixel element and the inter-gate capacitance value C pg3 can be adjusted by controlling the area and distance between the third pixel electrode 213 and the gate.

Similarly, in FIG. 5, the manner of adjusting at least one of C lc3 , C gd3 , C st3 , and C pg3 in step 52 may be at least two ways, but not limited thereto. The first way can include the following steps. First, the third liquid crystal capacitance value C lc3 is selected. Next, the ratio of C lc1 /C lc3 is calculated. Subsequently, the third storage capacitor value C st3 is adjusted such that the ratio of C st1 /C st3 is substantially equal to C lc1 /C lc3 . Thereafter, the third gate-to- deuterium capacitance value C gd3 is adjusted such that the ratio of C gd1 /C gd3 is substantially equal to C lc1 /C lc3 . Then, the adjustment between the third pixel electrode and the gate capacitance value C pg3, so C pg1 / C ratio of substantially equal pg3 C lc1 / C lc3. From another point of view, the first method can select the first pixel as the basis, and scale up or down the third pixel C lc3 , C gd3 , C st3 , C pg3 to make the first painting the ratio of the capacitance element (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the third sub-pixel capacitance ratio of (C pg3 + C gd3) / (C st3 + C lc3 + C Gd3 + C pg3 ) is substantially the same. Further, the second embodiment, it is adjusted separately C lc3, C gd3, C st3 , and C pg3, to make the pixels of the first capacitance ratio (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the capacitance ratio of the third sub-pixel (C pg3 + C gd3) / (C st3 + C lc3 + C gd3 + C pg3) are substantially the same. Similarly, the second embodiment may not be limited to the ratio C lc1 / C lc3 of, that is to say the ratio of C st1 / C st3, the ratio C gd1 / C gd3 of, and the ratio C pg1 / C pg2 that it can not C The limitation of lc1 /C lc3 can be adjusted more flexibly to avoid a decrease in aperture ratio caused by deliberate amplification of the area of the third storage electrode 223. It should be noted that the present invention is not limited to forming three sub-pixels, but can be similar to the third pixel forming method to further form a fourth pixel. In other words, it can be deduced to form a plurality of sub-pixels.

The following will use three sub-pixels to display red, green, and blue, respectively, and the first way to adjust the capacitance value in steps 44 and 52 above will be explained. In this embodiment, the first pixel P1 can be used to display red, the second pixel P2 can be used to display green, and the third pixel P3 can be used to display blue. The result is calculated by the color formula. If the area of the second pixel electrode 212 is taken as a standard and is defined as 1, the area of the first pixel electrode 212 can be changed between 0.25 and 1, and the third pixel electrode 213 The area can vary from 0.74 to 1. According to this, the mixed white light is calculated, and the difference between the color CIE coordinates Wx and Wy is not more than 0.26, which can be accepted by the product specification, wherein the difference between Wx and Wy is the red, green, and blue paintings of the same process. Products with the same area are the same. In the same liquid crystal material, the same common electrode, and the distance between the same pixel electrode and the common electrode, the area of each pixel electrode can determine the size of each liquid crystal capacitor. Next, in accordance with a first embodiment to adjust the capacitance value in step 44 and step 52, the C lc2, C gd2, C st2 , and C pg2 reduced to C lc1, C gd1, C st1 , the ratio may be C pg1 varies between 0.25 and 1, while the C lc3, C gd3, C st3 , and C pg3 reduced to C lc1, C gd1, C st1 , and the proportion of C pg1 can vary between 0.74 to 1, so as to satisfy (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1), (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2), and (C pg3 + C The three ratios of gd3 )/(C st3 +C lc3 +C gd3 +C pg3 ) are substantially the same.

It should be noted that in the first preferred embodiment, the pixel electrode of the liquid crystal capacitor covers the gate electrode of the thin film transistor, and the C pg in the capacitance ratio definition cannot be ignored. However, if there is a large enough distance between the pixel electrode of the liquid crystal capacitor and the gate electrode of the thin film transistor, the value of C pg will be small enough to be ignored in the definition of the capacitance ratio. Please refer to Figure 6 and Figure 7. 6 is a partial equivalent circuit diagram of a pixel structure of an in-cell touch display panel according to a second preferred embodiment of the present invention, and FIG. 7 is a second preferred embodiment of the present invention. A schematic diagram of a partial configuration of a pixel structure of an in-cell touch display panel. The former is represented by an equivalent circuit diagram, the latter is represented by a configuration diagram, and the same elements are denoted by the same symbols as the first preferred embodiment. As shown in FIGS. 6 and 7, in the second preferred embodiment, since the pixel electrode of the liquid crystal capacitor has a certain distance from the gate electrode of the thin film transistor, the value of C pg is small. . Therefore, in this embodiment, the C pg in the capacitance ratio definition can be omitted, so that the capacitance ratio of each pixel is set to C gd /(C st +C lc +C gd ). Accordingly, the pixel structure of the in-cell touch display panel of the preferred embodiment and the method of forming the same are similar to the first preferred embodiment, and the difference is only to ignore C pg .

In summary, the present invention not only can appropriately adjust the aperture ratio of the three sub-pixels of the red sub-pixel, the green sub-pixel, and the blue sub-pixel, thereby reducing the brightness reduction to the slightest and achieving uniform color mixing. The effect, and can avoid the extra sub-pixel electrical problem that may be derived when each pixel has a different aperture ratio. More specifically, in the case of different aperture ratios, the pixel may have a large difference in the feedthrough voltage ΔVp (feedthrough voltage) of the red sub-pixel, the green sub-pixel, and the blue sub-pixel. How to adjust the common voltage (Vcom), it is still impossible to make the liquid crystal cross-voltages of the positive and negative polarities of the three sub-pixels of the red sub-pixel, the green sub-pixel, and the blue sub-pixel simultaneously, in other words, if the Vcom voltage is adjusted The liquid crystal cross-pressure of the positive and negative polarities of one of the sub-pixels is equal, and the liquid crystal cross-pressure of the positive and negative polarities of the other two sub-pixels may still have a significant difference, thus causing a problem of picture flicker. The pixel structure of the in-cell touch display panel of the present invention and the method for forming the same, by adjusting the capacitance ratio of each pixel (C pg + C gd ) / (C st + C lc + C gd + C pg ), The capacitance ratio of each pixel is substantially the same, which can effectively avoid the electrical problem of the sub-pixel and obtain a better picture effect. In addition, the thin film transistors corresponding to different sub-pixel areas in the present invention may have different sizes to effectively reduce the gate line load and reduce leakage current.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

R. . . Red sub-pixel

G. . . Green sub-pixel

B. . . Blue subpixel

T. . . Touch sensing component

P1. . . First pixel

P2. . . Second pixel

P3. . . Third pixel

200. . . Substrate

201. . . First pixel area

202. . . Second pixel area

203. . . Third pixel area

211. . . First pixel electrode

212. . . Second pixel electrode

213. . . Third pixel electrode

221. . . First storage electrode

222. . . Second storage electrode

223. . . Third storage electrode

231. . . First thin film transistor

232. . . Second thin film transistor

233. . . Third thin film transistor

240. . . Touch sensing component

250. . . Common electrode

C lc1 . . . First liquid crystal capacitance value

C st1 . . . First storage capacitor value

C pg1 . . . First pixel electrode and gate capacitance

C lc2 . . . Second liquid crystal capacitance value

C pg2 . . . Second pixel electrode and gate capacitance

C st2 . . . Second storage capacitor value

C lc3 . . . Third liquid crystal capacitance value

C st3 . . . Third storage capacitor value

C gd1 . . . First gate and drain capacitance

40,42,44. . . step

C gd2 . . . Second gate and drain capacitance

46,48. . . step

C gd3 . . . The capacitance between the third gate and the drain

50,52,54. . . step

C pg3 . . . The capacitance between the third pixel and the gate

FIG. 1 is a schematic diagram of a pixel using an in-cell touch sensing element in the prior art.

FIG. 2 is a partial schematic diagram showing an equivalent circuit of a pixel structure of an in-cell touch display panel according to a first preferred embodiment of the present invention.

FIG. 3 is a partial schematic view showing the configuration of a pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention.

FIG. 4 is a flow chart showing a method for forming a pixel structure of an in-cell touch display panel according to a first preferred embodiment of the present invention.

FIG. 5 is a flow chart showing a method for forming another pixel of the pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention.

FIG. 6 is a schematic diagram showing a part of an equivalent circuit of a pixel structure of an in-cell touch display panel according to a second preferred embodiment of the present invention.

FIG. 7 is a partial schematic diagram showing the configuration of a pixel structure of an in-cell touch display panel according to a second preferred embodiment of the present invention.

200. . . Substrate

211. . . First pixel electrode

212. . . Second pixel electrode

213. . . Third pixel electrode

221. . . First storage electrode

222. . . Second storage electrode

223. . . Third storage electrode

231. . . First thin film transistor

232. . . Second thin film transistor

233. . . Third thin film transistor

240. . . Touch sensing component

Claims (19)

  1. A pixel structure of an in-cell touch display panel includes: a substrate on which a plurality of sub-pixel regions are defined; and a plurality of sub-pixels, each of the pixels being respectively disposed in each of the sub-pixel regions And the light transmissive area of at least one sub-pixel is different from the light transmissive area of the other sub-pixels, wherein each of the pixels includes: a liquid crystal capacitor having a liquid crystal capacitance value C lc , wherein at least one of the sub-pictures The value of the liquid crystal capacitor is different from the value of the liquid crystal capacitor of the other sub-pixels; a thin film transistor having a capacitance value C gd between the gate and the drain and a capacitance value C pg between the gate and the pixel; and The storage capacitor has a storage capacitor value C st ; wherein each of the pixels has a capacitance ratio, and the capacitance ratio is defined as (C pg + C gd ) / (C st + C lc + C gd + C pg ) And the capacitance ratio of each of the pixels is substantially the same.
  2. The pixel structure of the in-cell touch display panel according to claim 1, wherein two adjacent sub-pixels having different light transmission areas are respectively defined as a first pixel and a second pixel, and The first pixel is located in a first pixel region, and the second pixel is located in a second pixel region, and the light transmittance of the second pixel is greater than the first pixel. Light area.
  3. The pixel structure of the in-cell touch display panel as claimed in claim 2, wherein one touch The sensing element is disposed in the first pixel region.
  4. The pixel structure of the in-cell touch display panel according to claim 2, wherein the first liquid crystal capacitance value C lc1 of the first pixel and the second liquid crystal capacitance value C of the second pixel The ratio of lc2 is C lc1 /C lc2 , and the ratio of the first storage capacitor value C st1 of the first pixel to the second storage capacitor value C st2 of the second pixel is generally C st1 /C st2 The upper is equal to C lc1 /C lc2 , and the first gate and the drain capacitance value C gd1 of the first pixel and the second gate and the drain capacitance value C gd2 of the second pixel The ratio C gd1 /C gd2 is substantially equal to C lc1 /C lc2 , and the first pixel of the first pixel and the inter-gate capacitance value C pg1 and the second pixel are the second picture the ratio between the capacitance value of the pixel and the gate electrodes of the C pg2 C pg1 / C pg2 is substantially equal to C lc1 / C lc2.
  5. The pixel structure of the in-cell touch display panel of claim 2, wherein the sub-pixels further comprise a third pixel adjacent to the first pixel and the second pixel One of the two.
  6. The pixel structure of the in-cell touch display panel according to claim 5, wherein the first liquid crystal capacitance value C lc1 of the first pixel and the third liquid crystal capacitance value C of the third pixel The ratio of lc3 is C lc1 /C lc3 , and the ratio of the first storage capacitor value C st1 of the first pixel to the third storage capacitor value C st3 of the third pixel is generally C st1 /C st3 It is equal to the C lc1 / C lc3, and one of the first pixel between the first gate and drain capacitance value C gd1 capacitance value between the gate and the drain of the third one of the third sub-pixel C gd3 The ratio C gd1 /C gd3 is substantially equal to C lc1 /C lc3 , and the first pixel of the first pixel is the first pixel electrode and the inter-gate capacitance value C pg1 and the third pixel is the third picture the ratio between the capacitance value of the pixel and the gate electrodes of the C pg3 C pg1 / C pg3 substantially equal to C lc1 / C lc3.
  7. The pixel structure of the in-cell touch display panel of claim 5, wherein the first pixel, the second pixel, and the third pixel are respectively used to display three colors, the three colors Colors include red, green, and blue.
  8. The pixel structure of the in-cell touch display panel according to claim 6, wherein the light transmittance of the third pixel is less than or equal to the light transmission area of the second pixel, and the third pixel is The light transmission area is larger than the light transmission area of the first pixel, and the second pixel is used to display green.
  9. A method for forming a pixel structure of an in-cell touch display panel, comprising: providing a substrate having at least a first pixel region and a second pixel region defined thereon; and the first pixel region In the second pixel region, it is expected to set a second pixel; in the condition of 0<C lc1 /C lc2 <1, adjust C lc1 , C gd1 , C st1, C pg1, C lc2, C gd2, C st2, C pg2 wherein at least one of the first one of the first pixel capacitance ratio (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) substantially the same as the second one of the pixel capacitance ratio (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2), wherein for the first line C lc1 Videos One of the first liquid crystal capacitance values, C gd1 is a first gate and a drain capacitance value of the first pixel, and C st1 is a first storage capacitor value of the first pixel. C pg1 is the first pixel of the first pixel and the capacitance between the gate electrodes, C lc2 is the second liquid crystal capacitance value of the second pixel, and C gd2 is the second time. One of the pixels, the second gate and the drain capacitance The value, C st2 is the second storage capacitance value of the second pixel, and C pg2 is the second pixel element and the inter-gate capacitance value of the second pixel; according to the adjusted C lc1 And C gd1 , C st1 , C pg1 , in the first pixel region, forming a first liquid crystal capacitor having the first liquid crystal capacitance value C lc1 and having the first gate and the inter-dip junction capacitance C Gd1 and the first thin film transistor of the first pixel electrode and the inter-gate capacitance value C pg1 , and the first storage capacitor having the first storage capacitance value C st1 ; and according to the adjusted C lc2 , C gd2, C st2, C pg2, in the second sub-pixel region, forming one of a second liquid crystal capacitor C LC2 having capacitance value of the second liquid having a second gate and between the drain and the capacitance value C gd2 a second thin film transistor of the second pixel electrode and a gate capacitance value C pg2 , and a second storage capacitor having the second storage capacitance value C st2 .
  10. The method of claim 9, further comprising forming a touch sensing component in the first pixel region.
  11. The method of claim 9 requests, wherein adjusting C lc1, C gd1, C st1 , C pg1, C lc2, C gd2, C st2, C pg2 wherein at least one of the steps comprising: a first selected value of the first liquid crystal capacitor C Lc1 and the second liquid crystal capacitance value C lc2 ; calculating a ratio of C lc1 /C lc2 ; adjusting the first storage capacitor value C st1 and the second storage capacitor value C st2 such that the ratio of C st1 /C st2 is substantially Equivalent to C lc1 /C lc2 ; adjusting the first gate-to- deuterium capacitance value C gd1 and the second gate-to- deuterium capacitance value C gd2 such that the ratio of C gd1 /C gd2 is substantially equal to C lc1 / C lc2; and adjusting the first pixel electrode and the gate capacitance value C pg1 between the second pixel electrode and the gate electrode capacitance value C pg2, that the ratio C pg1 / C pg2 is substantially equal to the C lc1 / C Lc2 .
  12. The method of claim 9, wherein the first storage capacitor value C st1 and the second storage capacitor value C st2 are adjusted by controlling a storage electrode area of the first storage capacitor and storing the second storage capacitor The electrode area is adjusted.
  13. The method of claim 9, wherein the first gate-to- deuterium capacitance value C gd1 and the second gate-to- deuterium capacitance value C gd2 are adjusted by controlling the first thin film transistor The size and shape and the size and shape of the second film transistor are adjusted.
  14. The method of claim 9, further comprising: defining a third pixel region on the substrate; and in the third pixel region, a third pixel is expected to be set; at 0<C lc1 / under the condition C lc3 <1, adjusting C lc3, C gd3, C st3 , C pg3 wherein at least one of the ratio of the first pixel of the capacitor (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) substantially the same as the one of the third pixel capacitance ratio (C pg3 + C gd3) / (C st3 + C lc3 + C gd3 + C pg3), wherein for the third line C lc3 The third liquid crystal capacitance value of the second pixel, C gd3 is the third gate and the drain capacitance value of the third pixel, and C st3 is the third storage capacitor of the third pixel. The value, C pg3 is the third pixel element electrode and the gate capacitance value of the third pixel; and according to the adjusted C lc3 , C gd3 , C st3 , in the third pixel region, Forming a third liquid crystal capacitor having the third liquid crystal capacitance value C lc3 , having the third gate and inter-electrode capacitance value C gd3 and the third pixel electrode and the inter-gate capacitance value C pg3 Thin film transistor, and having the same Three storage capacitor value C st3 is one of the third storage capacitors.
  15. The method of claim 14, wherein the step of adjusting at least one of C lc3 , C gd3 , C st3 , C pg3 comprises: first selecting the third liquid crystal capacitance value C lc3 ; calculating a ratio of C lc1 /C lc3 ; Adjusting the third storage capacitor value C st3 such that the ratio of C st1 /C st3 is substantially equal to C lc1 /C lc3 ; and adjusting the third gate-to- deuterium capacitance value C gd3 to make C gd1 /C gd3 the ratio is substantially equal to C lc1 / C lc3; and adjusting the pixel electrode and the third inter-gate capacitance value C pg3, so C pg1 / C pg3 ratio is substantially equal to the C lc1 / C lc3.
  16. The method of claim 14, wherein the adjusting of the third storage capacitor value C st3 is performed by controlling a storage electrode area of the third storage capacitor.
  17. The method of claim 14, wherein the adjusting manner of the third gate-to-drain capacitance value C gd3 is adjusted by controlling the size and shape of the third thin film transistor.
  18. The method of claim 14, wherein the first pixel, the second pixel, and the third pixel are respectively used to display three colors, including red, green, and blue.
  19. The method of claim 14, wherein the light transmission area of the third pixel is less than or equal to the light transmission area of the second pixel, and the light transmission area of the third pixel is greater than the first pixel. The light transmission area, the second pixel is used to display green.
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CN103163676B (en) * 2012-09-26 2016-03-09 敦泰电子有限公司 The liquid crystal display touch screen of integrated single-layer capacitance sensor and application apparatus thereof
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