TWI461807B - Pixel structure of in-cell touch display panel and method of forming the same - Google Patents
Pixel structure of in-cell touch display panel and method of forming the same Download PDFInfo
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Description
本發明係關於一種內嵌式觸控顯示面板之畫素結構及其形成方法,尤指利用調整各次畫素之電容比值(Cpg +Cgd )/(Cst +Clc +Cgd +Cpg ),以解決具有不同透光面積之畫素所衍生之電性問題的一種內嵌式觸控顯示面板之畫素結構及其形成方法。The invention relates to a pixel structure of an in-cell touch display panel and a forming method thereof, in particular to adjusting a capacitance ratio of each pixel (C pg + C gd ) / (C st + C lc + C gd + C pg ), a pixel structure of an in-cell touch display panel and a method for forming the same to solve the electrical problem caused by pixels having different light transmission areas.
近來由於觸控顯示面板(touch display panel)的應用越來越廣泛,因而內嵌式觸控感測元件(touch sensor)的技術也就備受重視。內嵌式觸控感測元件是將觸控感測元件直接製作在各畫素中,犧牲掉部分開口率(aperture ratio)是無法避免的。在習知技術中,通常的做法是把紅色次畫素、綠色次畫素、以及藍色次畫素之面積等比例縮小,多出來的面積部分就用來放置觸控感測元件。舉例來說,原本紅色次畫素、綠色次畫素、藍色次畫素之透光面積各佔畫素整個面積的三分之一,若把紅色次畫素、綠色次畫素、藍色次畫素之面積皆縮小為畫素整個面積的四分之一,那就會有額外四分之一的面積可用來放置觸控感測元件,可依此方式來類推,關鍵在於使紅色次畫素、綠色次畫素、藍色次畫素的透光面積仍保持相同。請參考第1圖。第1圖繪示了習知技術中採用內嵌式觸控感測元件的畫素之示意圖。如第1圖所示,由於畫素中需設置觸控感測元件T,因此紅色次畫素R、綠色次畫素G、藍色次畫素B三個次畫素之透光面積大體上相同,但透光面積小於畫素整個面積的三分之一。然而,此一作法會造成亮度下降,而影響顯示品質。Recently, due to the increasing use of touch display panels, the technology of in-cell touch sensors has received much attention. The in-cell touch sensing component directly forms the touch sensing component in each pixel, and it is unavoidable to sacrifice part of the aperture ratio. In the prior art, the usual method is to reduce the area of the red sub-pixel, the green sub-pixel, and the blue sub-pixel, and the extra area is used to place the touch sensing element. For example, the light-transparent areas of the original red sub-pixels, green sub-pixels, and blue sub-pixels each account for one-third of the entire area of the pixel, if the red sub-pixel, the green sub-pixel, the blue The area of the sub-pixel is reduced to one-fourth of the entire area of the pixel, and there will be an additional quarter of the area for the touch sensing component, which can be analogized in this way. The key is to make the red color The light transmission area of the pixels, the green sub-pixels, and the blue sub-pixels remain the same. Please refer to Figure 1. FIG. 1 is a schematic diagram of a pixel using an in-cell touch sensing element in the prior art. As shown in FIG. 1 , since the touch sensing element T needs to be disposed in the pixel, the light transmissive area of the three sub-pixels of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B is substantially The same, but the light transmission area is less than one third of the entire area of the pixel. However, this practice causes a decrease in brightness and affects display quality.
本發明之目的之一在於提供一種內嵌式觸控顯示面板之畫素結構及其形成方法,以提供較佳的畫面效果。One of the objects of the present invention is to provide a pixel structure of an in-cell touch display panel and a method for forming the same to provide a better picture effect.
本發明之一較佳實施例係提供一種內嵌式觸控顯示面板之畫素結構。上述畫素結構包括定義有複數個次畫素區之一基板以及複數個次畫素。各次畫素分別設置於各次畫素區,且至少有一個次畫素之透光面積與其餘次畫素之透光面積大小不同。其中,各次畫素包括具有一液晶電容值Clc 之一液晶電容、具有一閘極與汲極間電容值Cgd 與一閘極與畫素電極間電容值Cpg 之一薄膜電晶體、以及具有一儲存電容值Cst 之一儲存電容。並且,各次畫素分別具有一電容比值,電容比值定義為(Cpg +Cgd )/(Cst +Clc +Cgd +Cpg ),且各次畫素之電容比值大體上相同。A preferred embodiment of the present invention provides a pixel structure of an in-cell touch display panel. The pixel structure includes a substrate defining a plurality of sub-pixel regions and a plurality of sub-pixels. Each pixel is set in each pixel area, and the light transmission area of at least one sub-pixel is different from the light transmission area of the other sub-pixels. Wherein, each pixel includes a liquid crystal capacitor having a liquid crystal capacitance value C lc , a thin film transistor having a gate-to-deuterium capacitance value C gd and a gate-to-pixel electrode capacitance value C pg , And a storage capacitor having a storage capacitor value C st . Moreover, each pixel has a capacitance ratio, and the capacitance ratio is defined as (C pg + C gd ) / (C st + C lc + C gd + C pg ), and the capacitance ratio of each pixel is substantially the same.
本發明之一較佳實施例另提供一種形成內嵌式觸控顯示面板之畫素結構的方法,包括下列步驟。首先,提供一基板,其上至少定義有一第一次畫素區與一第二次畫素區。接著,於第一次畫素區內,預計設置一第一次畫素,且於第二次畫素區內,預計設置一第二次畫素。隨後,在0<Clc1 /Clc2 <1的條件下,調整Clc1 、Cgd1 、Cst1 、Cpg1 、Clc2 、Cgd2 、Cst2 、Cpg2 其中至少一個,使第一次畫素之電容比值(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )與第二次畫素之電容比值(Cpg2 +Cgd2 /(Cst2 +Clc2 +Cgd2 +Cpg2 )大體上相同,其中Clc1 係為第一次畫素之一第一液晶電容值、Cgd1 係為第一次畫素之一第一閘極與汲極間電容值、Cst1 係為第一次畫素之一第一儲存電容值、Cpg1 係為第一次畫素之一第一畫素電極與閘極間電容值、Clc2 係為第二次畫素之一第二液晶電容值、Cst2 係為第二次畫素之一第二儲存電容值、Cgd2 係為第二次畫素之一第二閘極與汲極間電容值、以及Cpg2 係為第二次畫素之一第二畫素電極與閘極間電容值。之後,根據調整後之Clc1 、Cgd1 、Cst1 、Cpg1 ,於第一次畫素區內,形成具有第一液晶電容值Clc1 之一第一液晶電容、具有第一儲存電容值Cst1 之一第一儲存電容、以及具有第一閘極與汲極間電容值Cgd1 與具有一第一畫素電極與閘極間電容值Cpg1 之一第一薄膜電晶體。並且,根據調整後之Clc2 、Cgd2 、Cst2 、Cpg2 ,於第二次畫素區內,形成具有第二液晶電容值Clc2 之一第二液晶電容、具有第二儲存電容值Cst2 之一第二儲存電容、以及具有第二閘極與汲極間電容值Cgd2 與具有一第二畫素電極與閘極間電容值Cpg2 之一第二薄膜電晶體。A preferred embodiment of the present invention further provides a method of forming a pixel structure of an in-cell touch display panel, comprising the following steps. First, a substrate is provided having at least a first pixel region and a second pixel region defined thereon. Then, in the first pixel region, a first pixel is expected to be set, and in the second pixel region, a second pixel is expected to be set. Subsequently, at 0 <C lc1 / C lc2 < 1 , adjusting C lc1, C gd1, C st1 , C pg1, C lc2, C gd2, C st2, C pg2 wherein at least one of the first pixel the capacitance ratio (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the second sub-pixel capacitance ratio of (C pg2 + C gd2 / ( C st2 + C lc2 + C gd2 + C pg2 ) is substantially the same, wherein C lc1 is the first liquid crystal capacitance value of the first pixel, C gd1 is the first gate and the first gate capacitance value of the first pixel, C st1 system It is the first storage capacitor value of the first pixel, C pg1 is the first pixel of the first pixel and the capacitance between the gate electrodes, and C lc2 is the second pixel of the second pixel. The liquid crystal capacitance value, C st2 is the second storage capacitor value of the second pixel, C gd2 is the second gate and the second gate and the drain capacitance value, and the C pg2 is the second after one sub-pixel of the second pixel electrode and the gate electrode capacitance value. the C lc1 after the adjustment, C gd1, C st1, C pg1, in the first pixel region, having a first liquid crystal capacitor formed one value of the first liquid crystal capacitor C LC1, having a first One stored value of the capacitance of the first storage capacitor C st1, and a first capacitance value between the gate and drain electrodes between C gd1 and the capacitance value C pg1 one first thin film transistor having a first pixel electrode and the gate. And, according to the adjusted C lc2 , C gd2 , C st2 , C pg2 , in the second pixel region, forming a second liquid crystal capacitor having a second liquid crystal capacitance value C lc2 and having a second storage capacitor value C one st2 second storage capacitor, and a second gate between the drain and the capacitance value C gd2 one having a capacitance value between a gate electrode and a second pixel C pg2 second thin film transistor.
本發明之內嵌式觸控顯示面板之畫素結構及其形成方法,係利用調整各畫素之電容比值(Cpg +Cgd )/(Cst +Clc +Cgd +Cpg ),使各次畫素之電容比值大體上相同。因此,本發明不但可以適當調整紅色次畫素、綠色次畫素、藍色次畫素三個次畫素的開口率比例,來使亮度減少情況降到最輕微,又達到均勻混色的效果,並且可以避免在各次畫素具有不同開口率比例下,可能衍生的額外次畫素電性問題。The pixel structure of the in-cell touch display panel of the present invention and the method for forming the same are used to adjust the capacitance ratio of each pixel (C pg + C gd ) / (C st + C lc + C gd + C pg ), Make the capacitance ratio of each pixel substantially the same. Therefore, the present invention not only can appropriately adjust the aperture ratio of the three sub-pixels of the red sub-pixel, the green sub-pixel, and the blue sub-pixel, thereby reducing the brightness reduction to the slightest and achieving the effect of uniform color mixing. Moreover, it is possible to avoid the extra sub-pixel electrical problem that may be derived when each pixel has a different aperture ratio.
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解,製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區別元件的方式,而是以元件在功能上的差異來作為區別的基準。在通篇說明書及後續的請求項當中所提及的「包括」係為一開放式的用語,故應解釋成「包括但不限定於」。Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the differences in the functions of the elements as the basis for the distinction. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to".
請參考第2圖。第2圖繪示了本發明第一較佳實施例之內嵌式觸控顯示面板之畫素結構之部份等效電路示意圖。如第2圖所示,本實施例之內嵌式觸控顯示面板之畫素結構包括一基板200、以及複數個次畫素,例如一第一次畫素P1、一第二次畫素P2、以及一第三次畫素P3。圖示中為了簡化,只繪示三個次畫素,但並不以此為限。並且,於基板200上,定義有複數個次畫素區,例如一第一次畫素區201、一第二次畫素區202、以及一第三次畫素區203。再者,各次畫素分別設置於各次畫素區,如第一次畫素P1設置於第一次畫素區201,第二次畫素P2設置於第二次畫素區202,第三次畫素P3設置於第三次畫素區203。其中,各次畫素包括具有一液晶電容值Clc 之一液晶電容、具有一閘極與汲極間電容值Cgd 與具有一畫素電極與閘極間電容值Cpg 之一薄膜電晶體、以及具有一儲存電容值Cst 之一儲存電容。例如,以第一次畫素P1為例,第一次畫素P1包括具有一第一液晶電容值Clc1 之一第一液晶電容、具有一第一閘極與汲極間電容值Cgd1 與具有一第一畫素電極與閘極間電容值Cpg1 之一第一薄膜電晶體、以及具有一第一儲存電容值Cst1 之一第一儲存電容。再者,各次畫素分別具有一電容比值,電容比值定義為(Cpg +Cgd )/(Cst +Clc +Cgd +Cpg ),且各次畫素之電容比值大體上相同,換句話說,以第一次畫素P1、第二次畫素P2為例,(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )與(Cpg2 +Cgd2 )/(Cst2 +Clc2 +Cgd2 +Cpg2 )大體上相同。另外,一觸控感測元件240可以設置於第一次畫素區201內,但不以此為限。並且,本實施例並不限定觸控感測元件240的種類以及組成元件,因此在第2圖中並未繪示出其等效電路圖,僅以框線表示。在本實施例中,觸控感測元件240可以是光學觸控感測元件,也可以為其他合適的觸控感測元件,例如電阻式觸控感測元件、或是電容式觸控感測元件等。Please refer to Figure 2. FIG. 2 is a partial schematic diagram showing an equivalent circuit of a pixel structure of an in-cell touch display panel according to a first preferred embodiment of the present invention. As shown in FIG. 2, the pixel structure of the in-cell touch display panel of the embodiment includes a substrate 200 and a plurality of sub-pixels, such as a first pixel P1 and a second pixel P2. And a third pixel P3. For the sake of simplicity, only three sub-pixels are shown in the figure, but not limited to this. Moreover, on the substrate 200, a plurality of sub-pixel regions are defined, such as a first pixel region 201, a second pixel region 202, and a third pixel region 203. Furthermore, each pixel is set in each pixel region, for example, the first pixel P1 is set in the first pixel region 201, and the second pixel P2 is set in the second pixel region 202, The cubic pixel P3 is set in the third pixel area 203. The pixel includes a liquid crystal capacitor having a liquid crystal capacitance value C lc , a gate capacitance between the gate and the drain C gd , and a thin film transistor having a pixel electrode and a gate capacitance C pg . And a storage capacitor having a storage capacitance value C st . For example, taking the first pixel P1 as an example, the first pixel P1 includes a first liquid crystal capacitor having a first liquid crystal capacitance value C lc1 , and a first gate and a drain capacitance value C gd1 . a first thin film transistor having a first pixel electrode and a gate capacitance value C pg1 , and a first storage capacitor having a first storage capacitance value C st1 . Furthermore, each pixel has a capacitance ratio, and the capacitance ratio is defined as (C pg + C gd ) / (C st + C lc + C gd + C pg ), and the capacitance ratio of each pixel is substantially the same. in other words, in the first pixel P1, the second pixel P2 as an example, (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and (C pg2 + C gd2 ) / (C st2 + C lc2 + C gd2 + C pg2 ) is substantially the same. In addition, a touch sensing component 240 can be disposed in the first pixel region 201, but is not limited thereto. Moreover, the present embodiment does not limit the type of the touch sensing element 240 and the constituent elements. Therefore, the equivalent circuit diagram is not shown in FIG. 2 and is only indicated by a frame line. In this embodiment, the touch sensing component 240 can be an optical touch sensing component, or can be other suitable touch sensing components, such as a resistive touch sensing component or a capacitive touch sensing component. Components, etc.
請參考第3圖,並一併參考第2圖。第3圖繪示了本發明第一較佳實施例之內嵌式觸控顯示面板之畫素結構之部份配置示意圖。其中,第2圖與第3圖係為同一個實施例,前者以等效電路圖來表示,後者以配置示意圖來表示,並且相同元件以相同符號來標示。值得注意的是,一般顯示面板可以由兩透明基板構成,分別為一具有薄膜電晶體的基板,簡稱為薄膜電晶體基板(TFT substrate),以及一具有彩色濾光片的基板,簡稱為彩色濾光片基板(CF substrate)。為了避免圖示過於複雜,第3圖的配置示意圖僅繪示薄膜電晶體基板,以及位於其上的元件。以第一次畫素P1為例,在本實施例中,第2圖中的第一液晶電容可以為一第一次畫素電極211(如第3圖所示)、一共通電極250、以及介於第一次畫素電極211與共通電極250之間的一液晶層(未示於圖中)所構成。其中,共通電極250可以設置於彩色濾光片基板上,因未設置於薄膜電晶體基板,故未於第3圖中繪示。再者,第2圖中的第一儲存電容可以是第3圖中的一第一儲存電極221與第一次畫素電極211間形成的共通電極上電容(Cst on common),但並不以此為限,而可以為其他合適的元件配置。例如,於另一實施例中,本發明之第一儲存電容可以是第一次畫素電極部分重疊在閘極上形成的閘極上電容(Cst on gate)。再者,第2圖中的第一薄膜電晶體可以是第3圖中標示為231的框線所圍的區域。同樣的,以上敘述也可適用於第二次畫素P2與第三次畫素P3,在此不再贅述。此外,如第3圖所示,至少有一個次畫素之透光面積與其餘次畫素之透光面積大小不同。其中,透光面積可以由次畫素之畫素電極中未被其他遮光元件遮蔽的面積來決定。在本實施例中,具有不同透光面積之兩相鄰次畫素可以分別為第一次畫素P1與第二次畫素P2,而第一次畫素P1位於一第一次畫素區201,第二次畫素P2位於一第二次畫素區202,且第二次畫素P2之透光面積大於第一次畫素P1之透光面積。其中,第一次畫素區201與第二次畫素區202之面積可以大體上相同,而第一次畫素P1之透光面積小於第二次畫素P2之透光面積,因此,第一次畫素區201可以有額外的空間用來設置觸控感測元件240,但不以此為限。同樣的,本實施例並不限定觸控感測元件240的種類以及組成元件,因此在第3圖中僅以框線表示。Please refer to Figure 3 and refer to Figure 2 together. FIG. 3 is a partial schematic view showing the configuration of a pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention. 2 and 3 are the same embodiment, the former is represented by an equivalent circuit diagram, the latter is represented by a configuration diagram, and the same elements are denoted by the same symbols. It should be noted that a general display panel may be composed of two transparent substrates, respectively a substrate having a thin film transistor, referred to as a TFT substrate, and a substrate having a color filter, referred to as a color filter. Light substrate (CF substrate). In order to avoid the complexity of the illustration, the configuration diagram of FIG. 3 only shows the thin film transistor substrate and the components located thereon. Taking the first pixel P1 as an example, in the embodiment, the first liquid crystal capacitor in FIG. 2 may be a first pixel electrode 211 (as shown in FIG. 3), a common electrode 250, and A liquid crystal layer (not shown) is interposed between the first pixel electrode 211 and the common electrode 250. The common electrode 250 may be disposed on the color filter substrate and is not disposed on the thin film transistor substrate, and thus is not shown in FIG. Furthermore, the first storage capacitor in FIG. 2 may be a common electrode capacitor (C st on common) formed between a first storage electrode 221 and a first pixel electrode 211 in FIG. 3, but not To this end, it can be configured for other suitable components. For example, in another embodiment, the first storage capacitor of the present invention may be partially overlaps the first pixel electrode formed on the gate electrode on the gate capacitance (C st on gate). Furthermore, the first thin film transistor in FIG. 2 may be a region surrounded by a frame line indicated as 231 in FIG. Similarly, the above description is also applicable to the second pixel P2 and the third pixel P3, and details are not described herein again. In addition, as shown in FIG. 3, the light transmission area of at least one sub-pixel is different from the light transmission area of the other sub-pixels. The light transmissive area may be determined by an area of the pixel element of the sub-pixel that is not obscured by other shading elements. In this embodiment, two adjacent sub-pixels having different light transmission areas may be the first pixel P1 and the second pixel P2, respectively, and the first pixel P1 is located in a first pixel region. 201. The second pixel P2 is located in a second pixel region 202, and the light transmission area of the second pixel P2 is greater than the light transmission area of the first pixel P1. The area of the first pixel area 201 and the second pixel area 202 may be substantially the same, and the light transmission area of the first pixel P1 is smaller than the light transmission area of the second pixel P2, therefore, The primary pixel area 201 may have additional space for setting the touch sensing component 240, but is not limited thereto. Similarly, the present embodiment does not limit the type of the touch sensing element 240 and the constituent elements, and therefore is only indicated by a frame line in FIG.
以下將進一步說明上述各次畫素之間可以具有的規律。請一併參考第2圖以及第3圖。首先,對於第一次畫素P1與第二次畫素P2而言,如果第一次畫素P1之一第一液晶電容值Clc1 與第二次畫素P2之一第二液晶電容值Clc2 之比值係為Clc1 /C1c2 ,則第一次畫素P1之一第一儲存電容值Cst1 與第二次畫素P2之一第二儲存電容值Cst2 之比值Cst1 /Cst2 大體上可以等於Clc1 /Clc2 ,且第一次畫素P1之一第一閘極與汲極間電容值Cgd1 與第二次畫素P2之一第二閘極與汲極間電容值Cgd2 之比值Cgd1 /Cgd2 大體上可以等於Clc1 /Clc2 ,並且第一次畫素P1之一第一畫素電極與閘極間電容值Cpg1 與第二次畫素P2之一第二畫素電極與閘極間電容值Cpg2 之比值Cpg1 /Cpg2 大體上可以等於Clc1 /Clc2 。例如,如第3圖所示,第一次畫素電極211之面積小於第二次畫素電極212之面積,假設在相同液晶材質、相同的共通電極、以及相同的畫素電極與共通電極之間距下,第一液晶電容值Clc1 係小於第二液晶電容值Clc2 。基於Cst1 /Cst2 大體上可以等於Clc1 /Clc2 的條件,第一儲存電極221之面積可以小於第二儲存電極222;而基於Cgd1 /Cgd2 大體上可以等於Clc1 /Clc2 的條件,第一薄膜電晶體231之尺寸可以小於第二薄膜電晶體232之尺寸。再者,可調整第一畫素電極211與閘極間的面積及距離或調整第二畫素電極212與閘極間的面積及距離,使Cpg1 /Cpg2 大體上可以等於Clc1 /Clc2 。其次,對於第一次畫素P1與第三次畫素P3而言,如果第一次畫素P1之一第一液晶電容值Clc1 與第三次畫素P3之一第三液晶電容值Clc3 之比值為Clc1 /Clc3 ,則第一次畫素P1之一第一儲存電容值Cst1 與第三次畫素P3之一第三儲存電容值Cst3 之比值Cst1 /Cst3 大體上可以等於Clc1 /Clc3 ,且第一次畫素P1之一第一閘極與汲極間電容值Cgd1 與第三次畫素P3之一第三閘極與汲極間電容值Cgd3 之比值Cgd1 /Cgd3 大體上可以等於Clc1 /Clc3 ,並且第一次畫素P1之一第一畫素電極與閘極間電容值Cpg1 與第三次畫素P3之一第三畫素電極與閘極間電容值Cpg3 之比值Cpg1 /Cpg3 大體上可以等於Clc1 /Clc3 。例如,如第3圖所示,第一次畫素電極211之面積小於第三次畫素電極213之面積,假設在相同液晶材質、相同的共通電極、以及相同的畫素電極與共通電極之間距下,第一液晶電容值Clc1 係小於第三液晶電容值Clc3 。基於Cst1 /Cst3 大體上可以等於Clc1 /Clc3 的條件,第一儲存電極221之面積可以小於第三儲存電極223;而基於Cgd1 /Cgd3 大體上可以等於Clc1 /Clc3 的條件,第一薄膜電晶體231之尺寸可以小於第三薄膜電晶體233之尺寸。同樣的,可調整第三畫素電極213與閘極間的面積及距離,使Cpg1 /Cpg3 大體上可以等於Clc1 /Clc3 。The rules that can be found between the above-mentioned pixels can be further explained below. Please refer to Figure 2 and Figure 3 together. First, for the first pixel P1 and the second pixel P2, if the first pixel P1 is one of the first liquid crystal capacitance value C lc1 and the second pixel P2 is the second liquid crystal capacitance value C The ratio of lc2 is C lc1 /C 1c2 , and the ratio of the first storage capacitor value C st1 of one of the first pixels P1 to the second storage capacitance value C st2 of the second pixel P2 is C st1 /C st2 Generally, it may be equal to C lc1 /C lc2 , and one of the first gate P1 is between the first gate and the drain capacitance C gd1 and the second pixel P2 is the second gate and the drain capacitance value. the ratio of C gd2 C gd1 / C gd2 may be substantially equal to C lc1 / C lc2, and one of the first pixel P1 of the first pixel electrode and the gate electrode capacitance value C pg1 one second sub-pixel P2 the ratio between the capacitance value of the second pixel electrode and the gate C pg2 C pg1 / C pg2 may be substantially equal to C lc1 / C lc2. For example, as shown in FIG. 3, the area of the first pixel electrode 211 is smaller than the area of the second pixel electrode 212, assuming the same liquid crystal material, the same common electrode, and the same pixel electrode and common electrode. At the pitch, the first liquid crystal capacitance value C lc1 is smaller than the second liquid crystal capacitance value C lc2 . Based C st1 / C st2 can be substantially equal to the condition C lc1 / C lc2, the first storage electrode 221 may be less than the area of the second storage electrode 222; and based on C gd1 / C gd2 may be substantially equal to C lc1 / C lc2 of The size of the first thin film transistor 231 may be smaller than the size of the second thin film transistor 232. Further, the first pixel electrode 211 and the adjusted area and the distance between the gate area and the pixels or adjusting the distance between the second electrode 212 and the gate of the C pg1 / C pg2 may be substantially equal to C lc1 / C Lc2 . Secondly, for the first pixel P1 and the third pixel P3, if the first pixel P1 is one of the first liquid crystal capacitance value C lc1 and the third pixel P3 is the third liquid crystal capacitance value C The ratio of lc3 is C lc1 /C lc3 , and the ratio of the first storage capacitor value C st1 of one of the first pixels P1 to the third storage capacitor value C st3 of the third pixel P3 is generally C st1 /C st3 The upper gate may be equal to C lc1 /C lc3 , and one of the first pixel P1 is between the first gate and the drain capacitance C gd1 and the third pixel P3 is the third gate and the drain capacitance C the GD3 ratio C gd1 / C gd3 may be substantially equal to C lc1 / C lc3, and one of the first pixel P1 of the first pixel electrode and the gate capacitance value C pg1 between the third pixel P3 of one the ratio of the capacitance value between the pixel electrode and the gate three C pg3 of C pg1 / C pg3 may be substantially equal to C lc1 / C lc3. For example, as shown in FIG. 3, the area of the first pixel electrode 211 is smaller than the area of the third pixel electrode 213, assuming that the same liquid crystal material, the same common electrode, and the same pixel electrode and common electrode are At the pitch, the first liquid crystal capacitance value C lc1 is smaller than the third liquid crystal capacitance value C lc3 . The area of the first storage electrode 221 may be smaller than the third storage electrode 223 based on C st1 /C st3 substantially equal to the condition of C lc1 /C lc3 ; and substantially equal to C lc1 /C lc3 based on C gd1 /C gd3 The size of the first thin film transistor 231 may be smaller than the size of the third thin film transistor 233. Similarly, adjust the distance between the third area and the pixel electrode 213 and the gate, so that C pg1 / C pg3 may be substantially equal to C lc1 / C lc3.
此外,第一次畫素P1、第二次畫素P2、以及第三次畫素P3可以分別用來顯示三種顏色,並且三種顏色可以包括紅色、綠色與藍色,但不以此為限。例如,各次畫素可以用來顯示其他顏色,或者是有兩個以上的次畫素可以用來顯示相同的顏色。在本實施例中,第一次畫素P1可以用來顯示紅色,第二次畫素P2可以用來顯示綠色,第三次畫素P3可以用來顯示藍色。並且,在本實施例中,第三次畫素P3之透光面積可以小於或等於第二次畫素P2之透光面積,而第三次畫素P3之透光面積可以大於第一次畫素P1之透光面積,且第二次畫素P2可以用來顯示綠色。換句話說,在第一次畫素P1、第二次畫素P2、以及第三次畫素P3中,具有最大透光面積之次畫素可以用來顯示綠色。據此,本實例可以盡可能使顯示綠色之次畫素開口率為最大,以減少亮度損失,並搭配紅色與藍色之次畫素開口率比例,來維持一定程度均勻混色的效果。In addition, the first pixel P1, the second pixel P2, and the third pixel P3 may be used to display three colors, respectively, and the three colors may include red, green, and blue, but are not limited thereto. For example, each pixel can be used to display other colors, or more than two sub-pixels can be used to display the same color. In this embodiment, the first pixel P1 can be used to display red, the second pixel P2 can be used to display green, and the third pixel P3 can be used to display blue. Moreover, in this embodiment, the light transmission area of the third pixel P3 may be less than or equal to the light transmission area of the second pixel P2, and the light transmission area of the third pixel P3 may be larger than the first painting. The light transmission area of the prime P1, and the second pixel P2 can be used to display green. In other words, in the first pixel P1, the second pixel P2, and the third pixel P3, the secondary pixels having the largest light transmission area can be used to display green. Accordingly, in this example, the aperture ratio of the sub-pixels displaying green can be maximized to reduce the luminance loss, and the ratio of the aperture ratios of the red and blue sub-pixels can be matched to maintain a certain degree of uniform color mixture.
值得注意的是,以上雖僅以三個次畫素為例,但並不以此為限,而可以是兩個次畫素、或四個次畫素、或五個次畫素等其他實施例。另外,對次畫素電極充放電的薄膜電晶體,其只要能在閘極線開啟的時間內使次畫素電極達到所需電位即可,因此,對應不同次畫素電極面積的薄膜電晶體可以有不同的尺寸大小。例如,在本實施例中,對於第一次畫素P1、第二次畫素P2、以及第三次畫素P3而言,第一次畫素電極211之面積可以最小,第二次畫素電極212之面積可以最大,而第三次畫素電極213之面積可以居中。如果對應於第二次畫素電極212之第二薄膜電晶體232之尺寸維持不變,則對應於第一次畫素電極211之第一薄膜電晶體231之尺寸可以縮小,並且對應於第三次畫素電極213之第三薄膜電晶體233之尺寸也可以縮小。其中,薄膜電晶體之尺寸可以指的是通道寬長比(channel width/length ratio,W/L),但不以此為限,並且縮小的比例可以依照電性模擬結果來決定。因此,本實施例可以具有降低閘極線負載以及減小漏電流的優點。It is worth noting that although the above is only three sub-pixels, it is not limited to this, but it can be two sub-pixels, or four sub-pixels, or five sub-pixels and other implementations. example. In addition, the thin film transistor for charging and discharging the sub-pixel electrode can be such that the sub-pixel electrode can reach the desired potential within the time when the gate line is turned on, and therefore, the thin film transistor corresponding to the area of the different pixel areas Can have different sizes. For example, in the embodiment, for the first pixel P1, the second pixel P2, and the third pixel P3, the area of the first pixel electrode 211 can be the smallest, and the second pixel is The area of the electrode 212 can be the largest, and the area of the third pixel electrode 213 can be centered. If the size of the second thin film transistor 232 corresponding to the second pixel electrode 212 remains unchanged, the size of the first thin film transistor 231 corresponding to the first pixel electrode 211 may be reduced, and corresponds to the third The size of the third thin film transistor 233 of the sub-pixel electrode 213 can also be reduced. The size of the thin film transistor may refer to a channel width/length ratio (W/L), but is not limited thereto, and the scale of the reduction may be determined according to an electrical simulation result. Therefore, the present embodiment can have the advantage of reducing the gate line load and reducing the leakage current.
關於本實施例之內嵌式觸控顯示面板之畫素結構的形成方法,先以兩個次畫素為例說明如下。請參考第4圖,並一併參考第2圖以及第3圖。第4圖繪示了本發明第一較佳實施例之形成內嵌式觸控顯示面板之畫素結構的方法之流程示意圖。如第4圖所示,首先,步驟40提供一基板200(如第2圖所示),其上可以至少定義有一第一次畫素區201與一第二次畫素區202。接著,步驟42於第一次畫素區201內,預計設置一第一次畫素P1,且於第二次畫素區202內,預計設置一第二次畫素P2。隨後,步驟44在0<Clc1 /Clc2 <1的條件下,調整Clc1 、Cgd1 、Cst1 、Cpg1 、Clc2 、Cgd2 、Cst2 、Cpg2 其中至少一個,使第一次畫素之電容比值(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )與第二次畫素之電容比值(Cpg2 +Cgd2 )/(Cst2 +Clc2 +Cgd2 +Cpg2 )大體上相同,其中Clc1 係為第一次畫素P1之一第一液晶電容值、Cst1 係為第一次畫素P1之一第一儲存電容值、Cgd1 係為第一次畫素P1之一第一閘極與汲極間電容值、Cpg1 係為第一次畫素P1之一第一畫素電極與閘極間電容值、Clc2 係為第二次畫素P2之一第二液晶電容值、Cst2 係為第二次畫素P2之一第二儲存電容值、Cgd2 係為第二次畫素P2之一第二閘極與汲極間電容值、以及Cpg2 係為第二次畫素P2之一第二畫素電極與閘極間電容值。其中,0<Clc1 /Clc2 <1的條件可以指的是第一次畫素電極211之面積小於第二次畫素電極212之面積,但並不以此為限。The method for forming the pixel structure of the in-cell touch display panel of the present embodiment is described below by taking two sub-pixels as an example. Please refer to Figure 4 and refer to Figure 2 and Figure 3 together. FIG. 4 is a flow chart showing a method for forming a pixel structure of an in-cell touch display panel according to a first preferred embodiment of the present invention. As shown in FIG. 4, first, step 40 provides a substrate 200 (shown in FIG. 2) on which at least a first pixel region 201 and a second pixel region 202 can be defined. Next, in step 42 of the first pixel region 201, a first pixel P1 is expected to be set, and in the second pixel region 202, a second pixel P2 is expected to be set. Subsequently, at step 44 0 <C lc1 / C lc2 < 1 , adjusting C lc1, C gd1, C st1 , C pg1, C lc2, C gd2, C st2, C pg2 wherein at least one of the first the ratio of pixel capacitance (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the second sub-pixel capacitance ratio of (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2 ) is substantially the same, wherein C lc1 is the first liquid crystal capacitance value of one of the first pixels P1, C st1 is the first storage capacitance value of the first pixel P1, and the C gd1 system For the first pixel P1, the first gate and the drain capacitance value, C pg1 is the first pixel P1, the first pixel electrode and the gate capacitance value, and the C lc2 system is the second. The second liquid crystal capacitance value of one of the secondary pixels P2, C st2 is the second storage capacitance value of the second pixel P2, and C gd2 is the second gate and the drain of the second pixel P2. The capacitance value and C pg2 are the second pixel electrode and gate capacitance values of the second pixel P2. The condition of 0<C lc1 /C lc2 <1 may be that the area of the first pixel electrode 211 is smaller than the area of the second pixel electrode 212, but is not limited thereto.
如第4圖所示,之後,步驟46根據調整後之Clc1 、Cgd1 、Cst1 、Cpg1 ,於第一次畫素區201內,形成具有第一液晶電容值Clc1 之一第一液晶電容、具有第一儲存電容值Cst1 之一第一儲存電容、以及具有第一閘極與汲極間電容值Cgd1 與具有第一畫素電極與閘極間電容值Cpg1 之一第一薄膜電晶體231。在本實施例中,要使第一液晶電容具有調整後之第一液晶電容值Clc1 ,可以透過控制第一液晶電容之第一次畫素電極211面積來進行調整,但不以此為限,而可以透過調整第一液晶電容的其他條件參數。例如,可以調整第一次畫素電極211與共通電極250之間距、或是改變介於第一次畫素電極211與共通電極250之間的液晶層種類或特性等。並且,在本實施例中,要使第一儲存電容具有調整後之第一儲存電容值Cst1 ,可以透過控制第一儲存電容之第一儲存電極221面積來進行調整,但不以此為限,而可以透過調整第一儲存電容的其他條件參數。例如,可以調整第一儲存電極221與第一次畫素電極211之間距、或是改變介於第一儲存電極221與第一次畫素電極211間之材質種類或特性等。同樣的,在本實施例中,要使第一薄膜電晶體231具有第一閘極與汲極間電容值Cgd1 ,可以透過控制第一薄膜電晶體之尺寸與形狀來進行調整,但不以此為限。再者,要使第一薄膜電晶體231與第一液晶電容間具有第一畫素電極與閘極間電容值Cpg1 ,可以透過控制閘極與第一次畫素電極211間的面積及距離來進行調整,但不以此為限。並且,步驟48根據調整後之Clc2 、Cgd2 、Cst2 、Cpg2 ,於第二次畫素區內,形成具有第二液晶電容值Clc2 之一第二液晶電容、具有第二儲存電容值Cst2 之一第二儲存電容、以及具有第二閘極與汲極間電容值Cgd2 與具有第二畫素電極與閘極間電容值Cpg2 之一第二薄膜電晶體232。同理,第二液晶電容、第二儲存電容、以及第二薄膜電晶體232之調整方式,可以類似於上述第一液晶電容、第一儲存電容、以及第一薄膜電晶體231之調整方式,在此不再贅述。此外,本實施例之內嵌式觸控顯示面板之畫素結構的形成方法,可以另包括於第一次畫素區201內形成一觸控感測元件240,但不以此為限。例如,可於其他次畫素區內形成觸控感測元件240,且觸控感測元件240之個數並不侷限於一個,可視實際的產品規格與需求來決定。As shown in FIG. 4, after step 46, according to the adjusted C lc1 , C gd1 , C st1 , C pg1 , in the first pixel region 201, one of the first liquid crystal capacitance values C lc1 is formed first. the liquid crystal capacitor, a first storage capacitor having a value of one of the first storage capacitor C st1, and a first gate between the drain and the capacitance value C gd1 having a first pixel electrode and the gate capacitance value between one of C pg1 A thin film transistor 231. In this embodiment, the first liquid crystal capacitor has an adjusted first liquid crystal capacitance value C lc1 , which can be adjusted by controlling the area of the first pixel electrode 211 of the first liquid crystal capacitor, but not limited thereto. Other conditions can be adjusted by adjusting the first liquid crystal capacitor. For example, the distance between the first pixel electrode 211 and the common electrode 250 or the type or characteristic of the liquid crystal layer between the first pixel electrode 211 and the common electrode 250 may be adjusted. In addition, in this embodiment, the first storage capacitor has an adjusted first storage capacitor value C st1 , which can be adjusted by controlling the area of the first storage electrode 221 of the first storage capacitor, but not limited thereto. And can adjust other condition parameters of the first storage capacitor. For example, the distance between the first storage electrode 221 and the first pixel electrode 211 or the type or characteristic of the material between the first storage electrode 221 and the first pixel electrode 211 can be adjusted. Similarly, in the embodiment, the first thin film transistor 231 has a first gate-to- deuterium capacitance value C gd1 , which can be adjusted by controlling the size and shape of the first thin film transistor, but not This is limited. Furthermore, the first pixel electrode 231 and the first liquid crystal capacitor have a first pixel electrode and a gate capacitance value C pg1 , and the area and distance between the control gate and the first pixel electrode 211 can be transmitted. To make adjustments, but not to limit it. And, in step 48, according to the adjusted C lc2 , C gd2 , C st2 , C pg2 , in the second pixel region, forming a second liquid crystal capacitor having a second liquid crystal capacitance value C lc2 and having a second storage capacitor A second storage capacitor having a value C st2 and a second thin film transistor 232 having a second gate-to- deuterium capacitance value C gd2 and a second pixel-to-gate capacitance value C pg2 . Similarly, the adjustment manners of the second liquid crystal capacitor, the second storage capacitor, and the second thin film transistor 232 may be similar to the adjustment manners of the first liquid crystal capacitor, the first storage capacitor, and the first thin film transistor 231. This will not be repeated here. In addition, the method for forming the pixel structure of the in-cell touch display panel of the present embodiment may further include forming a touch sensing component 240 in the first pixel region 201, but not limited thereto. For example, the touch sensing component 240 can be formed in other sub-pixel regions, and the number of the touch sensing components 240 is not limited to one, and can be determined according to actual product specifications and requirements.
另外,於第4圖中,有關步驟44之調整Clc1 、Cgd1 、Cst1 、Cpg1 、Clc2 、Cgd2 、Cst2 、Cpg2 其中至少一個之方式,至少可以有以下兩種方式,但不以此為限。第一種方式可以包括下列步驟。首先,先選定第一液晶電容值Clc1 以及第二液晶電容值Clc2 。其中,本實施例可以依據色彩學上的需求,選定一合適的第一次畫素電極211之面積以及一合適的第二次畫素電極212之面積,在固定相同液晶材質、相同的共通電極、以及相同的畫素電極與共通電極之間距下,可以進而決定第一液晶電容值Clc1 以及第二液晶電容值Clc2 。接著,計算出Clc1 /Clc2 之比值。隨後,調整第一儲存電容值Cst1 與第二儲存電容值Cst2 ,使Cst1 /Cst2 之比值大體上等於Clc1 /Clc2 。之後,調整第一閘極與汲極間電容值Cgd1 與第二閘極與汲極間電容值Cgd2 ,使Cgd1 /Cgd2 之比值大體上等於Clc1 /Clc2 。然後,調整第一畫素電極與閘極間電容值Cpg1 與第二畫素電極與閘極間電容值Cpg2 ,使Cpg1 /Cpg2 之比值大體上等於Clc1 /Clc2 。在Cst1 /Cst2 之比值、Cgd1 /Cgd2 之比值、以及Cpg1 /Cpg2 之比值大體上等於Clc1 /Clc2 的情況下,可使使第一次畫素之電容比值(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )與第二次畫素之電容比值(Cpg2 +Cgd2 )/(Cst2 +Clc2 +Cgd2 +Cpg2 )大體上相同。從另一個角度來看,第一種方式可以選定第一次畫素為基礎,等比例放大或縮小第二次畫素之Clc2 、Cgd2 、Cst2 、Cpg2 ,來使第一次畫素之電容比值(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )與第二次畫素之電容比值(Cpg2 +Cgd2 )/(Cst2 +Clc2 +Cgd2 +Cpg2 )大體上相同。另外,第二種方式,則是分別調整Clc1 、Cgd1 、Cst1 、Cpg1 、Clc2 、Cgd2 、Cst2 、Cpg2 ,來使第一次畫素之電容比值(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )與第二次畫素之電容比值(Cpg2 +Cgd2 )/(Cst2 +Clc2 +Cgd2 +Cpg2 )大體上相同。換句話說,第二種方式可以不侷限於Clc1 /Clc2 之比值,也就是說Cst1 /Cst2 之比值、Cgd1 /Cgd2 之比值、以及Cpg1 /Cpg2 之比值可以不受Clc1 /Clc2 之限制,而可以較為彈性的調整,且可以避免第二儲存電極222之面積的刻意放大所導致的開口率降低。Further, in FIG. 4, relating to the step of adjusting the 44 C lc1, C gd1, C st1 , C pg1, C lc2, C gd2, C st2, C pg2 wherein at least one of the way, there are at least two ways, But not limited to this. The first way can include the following steps. First, the first liquid crystal capacitance value C lc1 and the second liquid crystal capacitance value C lc2 are first selected. In this embodiment, the area of a suitable first pixel electrode 211 and the area of a suitable second pixel electrode 212 can be selected according to the requirements of color, and the same common liquid crystal material and the same common electrode are fixed. And the distance between the same pixel electrode and the common electrode can further determine the first liquid crystal capacitance value C lc1 and the second liquid crystal capacitance value C lc2 . Next, the ratio of C lc1 /C lc2 is calculated. Subsequently, the first storage capacitor value C st1 and the second storage capacitor value C st2 are adjusted such that the ratio of C st1 /C st2 is substantially equal to C lc1 /C lc2 . Thereafter, the first gate-to- deuterium capacitance value C gd1 and the second gate-to- deuterium capacitance value C gd2 are adjusted such that the ratio of C gd1 /C gd2 is substantially equal to C lc1 /C lc2 . Then, adjusting the first pixel electrode and the capacitance between the gate and the second pixel value C pg1 between the gate electrode and the capacitance value C pg2, so C pg1 / C ratio is substantially equal to the pg2 C lc1 / C lc2. The ratio C st1 / C st2, the ratio C gd1 / C gd2 of, and the ratio C pg1 / C pg2 is substantially equal to the case of C lc1 / C lc2, the capacitance ratio can make the first pixel of the (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the second sub-pixel capacitance ratio of (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2) substantially Same on the same. From another point of view, the first method can select the first pixel as the basis, and scale up or down the second pixel C lc2 , C gd2 , C st2 , C pg2 to make the first painting the ratio of the capacitance element (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the second sub-pixel capacitance ratio of (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2) are substantially the same. Further, the second embodiment, it is adjusted separately C lc1, C gd1, C st1 , C pg1, C lc2, C gd2, C st2, C pg2, to make the pixels of the first capacitance ratio (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the capacitance ratio of the second sub-pixel (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2) are substantially the same. In other words, the second embodiment may not be limited to the ratio C lc1 / C lc2, the ratio that is the ratio C st1 / C st2 of, C gd1 / C ratio of GD2, and C pg1 / C pg2 that it can not The limitation of C lc1 /C lc2 can be adjusted more elasticly , and the reduction of the aperture ratio caused by the intentional amplification of the area of the second storage electrode 222 can be avoided.
關於本實施例之內嵌式觸控顯示面板之畫素結構的形成方法,再以增加另一次畫素為例說明如下。請參考第5圖。第5圖繪示了本發明第一較佳實施例之形成內嵌式觸控顯示面板之畫素結構之增加另一次畫素的方法之流程示意圖。如第5圖所示,首先,步驟50於基板200上定義一第三次畫素區203,並於第三次畫素區203內,預計設置一第三次畫素P3。隨後,步驟52在0<Clc1 /Clc3 <1的條件下,調整Clc3 、Cgd3 、Cst3 、Cpg3 其中至少一個,使第一次畫素之電容比值(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )與第三次畫素之電容比值(Cpg3 +Cgd3 )/(Cst3 +Clc3 +Cgd3 +Cpg3 )大體上相同,其中Clc3 係為第三次畫素之一第三液晶電容值、Cst3 係為第三次畫素之一第三儲存電容值、Cgd3 係為第三次畫素之一第三閘極與汲極間電容值、以及Cpg3 係為第三次畫素之一第三畫素電極與閘極間電容值。之後,步驟54根據調整後之參數Clc3 、Cgd3 、Cst3 、Cpg3 ,於第三次畫素區203內,形成具有第三液晶電容值Clc3 之一第三液晶電容、具有第三儲存電容值Cst3 之一第三儲存電容、以及具有第三閘極與汲極間電容值Cgd3 與具有第三畫素電極與閘極間電容值Cpg3 之一第三薄膜電晶體233。同理,第三儲存電容值Cst3 之調整方式可以透過控制第三儲存電極223之面積來進行調整,但不以此為限。並且,第三閘極與汲極間電容值Cgd3 之調整方式係透過控制第三薄膜電晶體233之尺寸與形狀來進行調整。再者,第三畫素電極與閘極間電容值Cpg3 之調整方式可以透過控制第三畫素電極213與閘極間的面積及距離來進行調整。The method for forming the pixel structure of the in-cell touch display panel of the present embodiment will be described below by taking another pixel as an example. Please refer to Figure 5. FIG. 5 is a flow chart showing a method for forming another pixel of the pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention. As shown in FIG. 5, first, step 50 defines a third pixel region 203 on the substrate 200, and in the third pixel region 203, a third pixel P3 is expected to be set. Subsequently, at step 52 0 <C lc1 / C lc3 < 1 , adjusting C lc3, C gd3, C st3 , C pg3 wherein at least one of the pixels of the first capacitance ratio (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the third sub-pixel capacitance ratio of (C pg3 + C gd3) / (C st3 + C lc3 + C gd3 + C pg3) is substantially the same, wherein C Lc3 is the third liquid crystal capacitor value of the third pixel, C st3 is the third storage capacitor value of the third pixel, and C gd3 is the third gate of the third pixel. The interelectrode capacitance value and C pg3 are the third pixel element and the interelectrode capacitance value of the third pixel. Thereafter, step 54 forms a third liquid crystal capacitor having a third liquid crystal capacitance value C lc3 in the third pixel region 203 according to the adjusted parameters C lc3 , C gd3 , C st3 , C pg3 , and has a third A storage capacitor value C st3 is a third storage capacitor, and has a third gate-to- deuterium capacitance value C gd3 and a third thin film transistor 233 having a third pixel electrode and inter-gate capacitance value C pg3 . For the same reason, the adjustment of the third storage capacitor value C st3 can be adjusted by controlling the area of the third storage electrode 223, but not limited thereto. Further, the adjustment method of the third gate-to-drain capacitance value C gd3 is adjusted by controlling the size and shape of the third thin film transistor 233. Furthermore, the adjustment method of the third pixel element and the inter-gate capacitance value C pg3 can be adjusted by controlling the area and distance between the third pixel electrode 213 and the gate.
同樣的,於第5圖中,有關步驟52之調整Clc3 、Cgd3 、Cst3 、Cpg3 其中至少一個之方式,至少可以有以下兩種方式,但不以此為限。第一種方式可以包括下列步驟。首先,選定第三液晶電容值Clc3 。接著,計算出Clc1 /Clc3 之比值。隨後,調整第三儲存電容值Cst3 ,使Cst1 /Cst3 之比值大體上等於Clc1 /Clc3 。之後,調整第三閘極與汲極間電容值Cgd3 ,使Cgd1 /Cgd3 之比值大體上等於Clc1 /Clc3 。然後,調整第三畫素電極與閘極間電容值Cpg3 ,使Cpg1 /Cpg3 之比值大體上等於Clc1 /Clc3 。從另一個角度來看,第一種方式可以選定第一次畫素為基礎,等比例放大或縮小第三次畫素之Clc3 、Cgd3 、Cst3 、Cpg3 ,來使第一次畫素之電容比值(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )與第三次畫素之電容比值(Cpg3 +Cgd3 )/(Cst3 +Clc3 +Cgd3 +Cpg3 )大體上相同。另外,第二種方式,則是分別調整Clc3 、Cgd3 、Cst3 、以及Cpg3 ,來使第一次畫素之電容比值(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )與第三次畫素之電容比值(Cpg3 +Cgd3 )/(Cst3 +Clc3 +Cgd3 +Cpg3 )大體上相同。同理,第二種方式可以不侷限於Clc1 /Clc3 之比值,也就是說Cst1 /Cst3 之比值、Cgd1 /Cgd3 之比值、以及Cpg1 /Cpg2 之比值可以不受Clc1 /Clc3 之限制,而可以較為彈性的調整,來避免第三儲存電極223之面積的刻意放大所導致的開口率降低。值得注意的是,本發明並不侷限於形成三個次畫素,而可以類似於第三次畫素的形成方法,進一步形成一第四次畫素。換句話說,可以依此類推,形成複數個次畫素。Similarly, in FIG. 5, the manner of adjusting at least one of C lc3 , C gd3 , C st3 , and C pg3 in step 52 may be at least two ways, but not limited thereto. The first way can include the following steps. First, the third liquid crystal capacitance value C lc3 is selected. Next, the ratio of C lc1 /C lc3 is calculated. Subsequently, the third storage capacitor value C st3 is adjusted such that the ratio of C st1 /C st3 is substantially equal to C lc1 /C lc3 . Thereafter, the third gate-to- deuterium capacitance value C gd3 is adjusted such that the ratio of C gd1 /C gd3 is substantially equal to C lc1 /C lc3 . Then, the adjustment between the third pixel electrode and the gate capacitance value C pg3, so C pg1 / C ratio of substantially equal pg3 C lc1 / C lc3. From another point of view, the first method can select the first pixel as the basis, and scale up or down the third pixel C lc3 , C gd3 , C st3 , C pg3 to make the first painting the ratio of the capacitance element (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the third sub-pixel capacitance ratio of (C pg3 + C gd3) / (C st3 + C lc3 + C Gd3 + C pg3 ) is substantially the same. Further, the second embodiment, it is adjusted separately C lc3, C gd3, C st3 , and C pg3, to make the pixels of the first capacitance ratio (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1) and the capacitance ratio of the third sub-pixel (C pg3 + C gd3) / (C st3 + C lc3 + C gd3 + C pg3) are substantially the same. Similarly, the second embodiment may not be limited to the ratio C lc1 / C lc3 of, that is to say the ratio of C st1 / C st3, the ratio C gd1 / C gd3 of, and the ratio C pg1 / C pg2 that it can not C The limitation of lc1 /C lc3 can be adjusted more flexibly to avoid a decrease in aperture ratio caused by deliberate amplification of the area of the third storage electrode 223. It should be noted that the present invention is not limited to forming three sub-pixels, but can be similar to the third pixel forming method to further form a fourth pixel. In other words, it can be deduced to form a plurality of sub-pixels.
以下將利用三個次畫素分別用來顯示紅色、綠色、與藍色,並且搭配上述步驟44與步驟52中調整電容值之第一種方式來做說明。在本實施例中,第一次畫素P1可以用來顯示紅色,第二次畫素P2可以用來顯示綠色,而第三次畫素P3可以用來顯示藍色。由色彩學公式計算結果,如果以第二次畫素電極212面積為標準並且定義為1,則第一次畫素電極212面積可以在0.25~1之間變化,且第三次畫素電極213面積可以在0.74~1之間變化。據此,計算出混成的白光,其色彩CIE座標Wx和Wy差異皆不會超過0.26,可被產品規格接受,其中Wx和Wy差異是與同樣條件同樣製程的紅色、綠色、與藍色次畫素面積皆相同的產品比較得來。而在相同液晶材質、相同的共通電極、以及相同的畫素電極與共通電極之間距下,各畫素電極面積可以決定各液晶電容之大小。接著,即可依照步驟44與步驟52中調整電容值之第一種方式,將Clc2 、Cgd2 、Cst2 、與Cpg2 縮小為Clc1 、Cgd1 、Cst1 、與Cpg1 之比例可在0.25~1之間變化,而將Clc3 、Cgd3 、Cst3 、以及Cpg3 縮小為Clc1 、Cgd1 、Cst1 、以及Cpg1 之比例可在0.74~1之間變化,使其滿足(Cpg1 +Cgd1 )/(Cst1 +Clc1 +Cgd1 +Cpg1 )、(Cpg2 +Cgd2 )/(Cst2 +Clc2 +Cgd2 +Cpg2 )、以及(Cpg3 +Cgd3 )/(Cst3 +Clc3 +Cgd3 +Cpg3 )三個比值大體上相同。The following will use three sub-pixels to display red, green, and blue, respectively, and the first way to adjust the capacitance value in steps 44 and 52 above will be explained. In this embodiment, the first pixel P1 can be used to display red, the second pixel P2 can be used to display green, and the third pixel P3 can be used to display blue. The result is calculated by the color formula. If the area of the second pixel electrode 212 is taken as a standard and is defined as 1, the area of the first pixel electrode 212 can be changed between 0.25 and 1, and the third pixel electrode 213 The area can vary from 0.74 to 1. According to this, the mixed white light is calculated, and the difference between the color CIE coordinates Wx and Wy is not more than 0.26, which can be accepted by the product specification, wherein the difference between Wx and Wy is the red, green, and blue paintings of the same process. Products with the same area are the same. In the same liquid crystal material, the same common electrode, and the distance between the same pixel electrode and the common electrode, the area of each pixel electrode can determine the size of each liquid crystal capacitor. Next, in accordance with a first embodiment to adjust the capacitance value in step 44 and step 52, the C lc2, C gd2, C st2 , and C pg2 reduced to C lc1, C gd1, C st1 , the ratio may be C pg1 varies between 0.25 and 1, while the C lc3, C gd3, C st3 , and C pg3 reduced to C lc1, C gd1, C st1 , and the proportion of C pg1 can vary between 0.74 to 1, so as to satisfy (C pg1 + C gd1) / (C st1 + C lc1 + C gd1 + C pg1), (C pg2 + C gd2) / (C st2 + C lc2 + C gd2 + C pg2), and (C pg3 + C The three ratios of gd3 )/(C st3 +C lc3 +C gd3 +C pg3 ) are substantially the same.
值得注意的是,於第一較佳實施例中,液晶電容之畫素電極係覆蓋至薄膜電晶體之閘極電極上方,則電容比值定義中的Cpg 不能忽略。然而,如果液晶電容之畫素電極與薄膜電晶體之閘極電極之間具有夠大的距離,則Cpg 的值將會夠小而得以在電容比值定義中忽略。請參考第6圖與第7圖。第6圖繪示了本發明第二較佳實施例之內嵌式觸控顯示面板之畫素結構之部份等效電路示意圖,而第7圖繪示了本發明第二較佳實施例之內嵌式觸控顯示面板之畫素結構之部份配置示意圖。其中,前者以等效電路圖來表示,後者以配置示意圖來表示,並且相同元件沿用相同於第一較佳實施例之符號來標示。如第6圖與第7圖所示,在第二較佳實施例中,由於液晶電容之畫素電極與薄膜電晶體之閘極電極之間具有一定的距離,使的Cpg 的值較小。故於此實施例中,電容比值定義中的Cpg 可以省略,使得各畫素之電容比值定成為Cgd /(Cst +Clc +Cgd )。據此,此較佳實施例之內嵌式觸控顯示面板的畫素結構及其形成方法,相似於第一較佳實施例,差別僅在忽略Cpg 。It should be noted that in the first preferred embodiment, the pixel electrode of the liquid crystal capacitor covers the gate electrode of the thin film transistor, and the C pg in the capacitance ratio definition cannot be ignored. However, if there is a large enough distance between the pixel electrode of the liquid crystal capacitor and the gate electrode of the thin film transistor, the value of C pg will be small enough to be ignored in the definition of the capacitance ratio. Please refer to Figure 6 and Figure 7. 6 is a partial equivalent circuit diagram of a pixel structure of an in-cell touch display panel according to a second preferred embodiment of the present invention, and FIG. 7 is a second preferred embodiment of the present invention. A schematic diagram of a partial configuration of a pixel structure of an in-cell touch display panel. The former is represented by an equivalent circuit diagram, the latter is represented by a configuration diagram, and the same elements are denoted by the same symbols as the first preferred embodiment. As shown in FIGS. 6 and 7, in the second preferred embodiment, since the pixel electrode of the liquid crystal capacitor has a certain distance from the gate electrode of the thin film transistor, the value of C pg is small. . Therefore, in this embodiment, the C pg in the capacitance ratio definition can be omitted, so that the capacitance ratio of each pixel is set to C gd /(C st +C lc +C gd ). Accordingly, the pixel structure of the in-cell touch display panel of the preferred embodiment and the method of forming the same are similar to the first preferred embodiment, and the difference is only to ignore C pg .
綜上所述,本發明不但可以適當調整紅色次畫素、綠色次畫素、藍色次畫素三個次畫素的開口率比例,來使亮度減少情況降到最輕微,又達到均勻混色的效果,並且可以避免在各次畫素具有不同開口率比例下,可能衍生的額外次畫素電性問題。更明確的說,各次畫素在具有不同開口率比例的情況下,可能使紅色次畫素、綠色次畫素、藍色次畫素的饋通電壓△Vp(feedthrough voltage)差距太大,共通電壓(Vcom)再怎麼調整,還是無法同時使紅色次畫素、綠色次畫素、藍色次畫素三個次畫素的正負極性之液晶跨壓相等,換句話說,如果調整Vcom電壓使其中一個次畫素的正負極性之液晶跨壓相等,而另外兩個次畫素的正負極性之液晶跨壓可能仍有明顯差異,因而產生畫面閃爍問題。而本發明之內嵌式觸控顯示面板之畫素結構及其形成方法,利用調整各畫素之電容比值(Cpg +Cgd )/(Cst +Clc +Cgd +Cpg ),使各次畫素之電容比值大體上相同,可有效避免次畫素之電性問題,而可獲得較佳的畫面效果。此外,本發明中對應不同次畫素電極面積的薄膜電晶體可以有不同的尺寸大小,來有效的降低閘極線負載以及減小漏電流。In summary, the present invention not only can appropriately adjust the aperture ratio of the three sub-pixels of the red sub-pixel, the green sub-pixel, and the blue sub-pixel, thereby reducing the brightness reduction to the slightest and achieving uniform color mixing. The effect, and can avoid the extra sub-pixel electrical problem that may be derived when each pixel has a different aperture ratio. More specifically, in the case of different aperture ratios, the pixel may have a large difference in the feedthrough voltage ΔVp (feedthrough voltage) of the red sub-pixel, the green sub-pixel, and the blue sub-pixel. How to adjust the common voltage (Vcom), it is still impossible to make the liquid crystal cross-voltages of the positive and negative polarities of the three sub-pixels of the red sub-pixel, the green sub-pixel, and the blue sub-pixel simultaneously, in other words, if the Vcom voltage is adjusted The liquid crystal cross-pressure of the positive and negative polarities of one of the sub-pixels is equal, and the liquid crystal cross-pressure of the positive and negative polarities of the other two sub-pixels may still have a significant difference, thus causing a problem of picture flicker. The pixel structure of the in-cell touch display panel of the present invention and the method for forming the same, by adjusting the capacitance ratio of each pixel (C pg + C gd ) / (C st + C lc + C gd + C pg ), The capacitance ratio of each pixel is substantially the same, which can effectively avoid the electrical problem of the sub-pixel and obtain a better picture effect. In addition, the thin film transistors corresponding to different sub-pixel areas in the present invention may have different sizes to effectively reduce the gate line load and reduce leakage current.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
R...紅色次畫素R. . . Red sub-pixel
G...綠色次畫素G. . . Green sub-pixel
B...藍色次畫素B. . . Blue subpixel
T...觸控感測元件T. . . Touch sensing component
P1...第一次畫素P1. . . First pixel
P2...第二次畫素P2. . . Second pixel
P3...第三次畫素P3. . . Third pixel
200...基板200. . . Substrate
201...第一次畫素區201. . . First pixel area
202...第二次畫素區202. . . Second pixel area
203...第三次畫素區203. . . Third pixel area
211...第一次畫素電極211. . . First pixel electrode
212...第二次畫素電極212. . . Second pixel electrode
213...第三次畫素電極213. . . Third pixel electrode
221...第一儲存電極221. . . First storage electrode
222...第二儲存電極222. . . Second storage electrode
223...第三儲存電極223. . . Third storage electrode
231...第一薄膜電晶體231. . . First thin film transistor
232...第二薄膜電晶體232. . . Second thin film transistor
233...第三薄膜電晶體233. . . Third thin film transistor
240...觸控感測元件240. . . Touch sensing component
250...共通電極250. . . Common electrode
Clc1 ...第一液晶電容值C lc1 . . . First liquid crystal capacitance value
Cst1 ...第一儲存電容值C st1 . . . First storage capacitor value
Cpg1 ...第一畫素電極與閘極間電容值C pg1 . . . First pixel electrode and gate capacitance
Clc2 ...第二液晶電容值C lc2 . . . Second liquid crystal capacitance value
Cpg2 ...第二畫素電極與閘極間電容值C pg2 . . . Second pixel electrode and gate capacitance
Cst2 ...第二儲存電容值C st2 . . . Second storage capacitor value
Clc3 ...第三液晶電容值C lc3 . . . Third liquid crystal capacitance value
Cst3 ...第三儲存電容值C st3 . . . Third storage capacitor value
Cgd1 ...第一閘極與汲極間電容值C gd1 . . . First gate and drain capacitance
40,42,44...步驟40,42,44. . . step
Cgd2 ...第二閘極與汲極間電容值C gd2 . . . Second gate and drain capacitance
46,48...步驟46,48. . . step
Cgd3 ...第三閘極與汲極間電容值C gd3 . . . The capacitance between the third gate and the drain
50,52,54...步驟50,52,54. . . step
Cpg3 ...第三畫素電極與閘極間電容值C pg3 . . . The capacitance between the third pixel and the gate
第1圖繪示了習知技術中採用內嵌式觸控感測元件的畫素之示意圖。FIG. 1 is a schematic diagram of a pixel using an in-cell touch sensing element in the prior art.
第2圖繪示了本發明第一較佳實施例之內嵌式觸控顯示面板之畫素結構之部份等效電路示意圖。FIG. 2 is a partial schematic diagram showing an equivalent circuit of a pixel structure of an in-cell touch display panel according to a first preferred embodiment of the present invention.
第3圖繪示了本發明第一較佳實施例之內嵌式觸控顯示面板之畫素結構之部份配置示意圖。FIG. 3 is a partial schematic view showing the configuration of a pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention.
第4圖繪示了本發明第一較佳實施例之形成內嵌式觸控顯示面板之畫素結構的方法之流程示意圖。FIG. 4 is a flow chart showing a method for forming a pixel structure of an in-cell touch display panel according to a first preferred embodiment of the present invention.
第5圖繪示了本發明第一較佳實施例之形成內嵌式觸控顯示面板之畫素結構之增加另一次畫素的方法之流程示意圖。FIG. 5 is a flow chart showing a method for forming another pixel of the pixel structure of the in-cell touch display panel according to the first preferred embodiment of the present invention.
第6圖繪示了本發明第二較佳實施例之內嵌式觸控顯示面板之畫素結構之部份等效電路示意圖。FIG. 6 is a schematic diagram showing a part of an equivalent circuit of a pixel structure of an in-cell touch display panel according to a second preferred embodiment of the present invention.
第7圖繪示了本發明第二較佳實施例之內嵌式觸控顯示面板之畫素結構之部份配置示意圖。FIG. 7 is a partial schematic diagram showing the configuration of a pixel structure of an in-cell touch display panel according to a second preferred embodiment of the present invention.
200...基板200. . . Substrate
211...第一次畫素電極211. . . First pixel electrode
212...第二次畫素電極212. . . Second pixel electrode
213...第三次畫素電極213. . . Third pixel electrode
221...第一儲存電極221. . . First storage electrode
222...第二儲存電極222. . . Second storage electrode
223...第三儲存電極223. . . Third storage electrode
231...第一薄膜電晶體231. . . First thin film transistor
232...第二薄膜電晶體232. . . Second thin film transistor
233...第三薄膜電晶體233. . . Third thin film transistor
240...觸控感測元件240. . . Touch sensing component
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US5235448A (en) * | 1990-07-09 | 1993-08-10 | International Business Machines Corporation | Liquid crystal display having proportional tft channel width |
TW594347B (en) * | 2002-08-16 | 2004-06-21 | Chi Mei Optoelectronics Corp | Liquid crystal display panel having reduced flicker |
TWI308710B (en) * | 2003-04-08 | 2009-04-11 | Samsung Electronics Co Ltd | A display device for displaying images in response to image and control signals |
US20090237369A1 (en) * | 2008-03-19 | 2009-09-24 | Samsung Electronics Co., Ltd. | Touch panel display and method of manufacturing the same |
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