JP2004070691A - Memory controller and memory system having the same, and method for controlling flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller for effectively suppressing a deterioration in performance while saving the capacity of an address conversion table. <P>SOLUTION: A memory controller for performing access to a flash memory dividable into p pieces of zones is provided with an address conversion table having r(r < p) pieces of tables capable of storing address conversion information related with one zone. Then, in response to a request for access to a certain zone in the flash memory, the address conversion information related with a zone next to the pertinent zone from viewed from a host side is prepared in the predetermined table of the address conversion table. When the next zone is actually accessed, it is not necessary to prepare any corresponding address conversion information from the beginning. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory controller and a memory system including the memory controller, and more particularly to a memory controller for controlling a flash memory and a memory system including the memory controller. The present invention also relates to a flash memory control method.
[0002]
[Prior art]
In recent years, flash memories, particularly NAND flash memories, are often used as semiconductor memories used for memory cards, silicon disks, and the like. In the NAND flash memory, when a memory cell is changed from an erased state (logical value = 1) to a written state (logical value = 0), this can be performed in units of memory cells. When changing from the written state (0) to the erased state (1), this cannot be performed in units of memory cells, and this can be performed only in units of blocks composed of a plurality of memory cells. Such a batch erase operation is generally called “block erase”.
[0003]
As described above, in the flash memory, since the memory cell can be changed from the write state (0) to the erase state (1) only in units of blocks, new data can be obtained for the logical address to which data has already been assigned. Even if the old data is overwritten, the new data cannot be directly overwritten on the block storing the old data. For this reason, when the host computer instructs the logical address to which data has already been assigned to overwrite the new data, the data that is not overwritten in the block in which the old data is stored is transferred to the erased block. In addition, a process of writing new data to the erased block is required. Such processing is called “inter-block transfer”, and is executed each time an instruction to overwrite data is given from the host computer. After the inter-block transfer is performed, the transfer source block is erased by a block, whereby the transfer source block becomes a new erased block.
[0004]
Therefore, the relationship between the logical address and the physical address uniquely assigned to each block is not fixed, and these relationships change dynamically every time data overwriting is instructed. For this reason, an address conversion table for maintaining the relationship between the logical address and the physical address is required in the controller for controlling the flash memory, and this is referred to every time data reading is requested from the host computer. Then, address conversion is performed and the contents are updated each time data writing is requested.
[0005]
However, since the recording capacity required for the address conversion table is proportional to the number of blocks to be controlled by the controller, a large capacity address conversion table is required when the number of blocks to be controlled is very large. Become. In addition, since a static random access memory (SRAM) is generally used for the address conversion table, the use of a large-capacity address conversion table greatly increases the product cost of the controller.
[0006]
To solve this problem, instead of storing the address translation information for all the blocks to be controlled in the address translation table, store only the address translation information for some blocks in the address translation table. Is effective. For example, if the address conversion information stored in the address conversion table is only information relating to half of the blocks, the storage capacity required for the address conversion table can be halved, and the product cost of the controller can be reduced. Become.
[0007]
[Problems to be solved by the invention]
However, in the system in which only the address translation information relating to some blocks is developed in the address translation table, when data read is requested for a block in which the address translation information is not developed in the address translation table, the address translation table It is necessary to perform an update operation such as discarding a part of the data and newly storing address conversion information related to the block in the address conversion table. Of course, since the requested data cannot be read until the update operation is completed, the occurrence of the update operation causes the performance of the memory system to deteriorate.
[0008]
The occurrence frequency of such update work is determined by the ratio of the blocks in which the address translation information is stored in the address translation table. The smaller this ratio, the more frequently the update work occurs. In other words, the smaller the proportion of blocks that can store address translation information by saving the capacity of the address translation table, the lower the product cost and performance of the controller, and conversely, the capacity of the address translation table is reduced. As the proportion of blocks that can store address translation information increases, the controller product cost increases and the performance improves. That is, the product cost based on the capacity of the address conversion table and the performance are in a trade-off relationship, and it is difficult to satisfy both.
[0009]
Therefore, an object of the present invention is to provide a memory controller and a memory system including the memory controller that can effectively suppress a decrease in performance while saving the capacity of an address conversion table.
[0010]
Another object of the present invention is to provide a flash memory control method capable of effectively suppressing a decrease in performance while saving the capacity of an address conversion table.
[0011]
[Means for Solving the Problems]
A memory controller according to an aspect of the present invention is a memory controller for accessing a flash memory that can be divided into p zones, and has r tables for storing address conversion information related to one zone of the flash memory. (R <p), and in response to a request for access to the flash memory, the address conversion information related to a second zone different from the first zone to be accessed is the address conversion. The table is created in a predetermined table.
[0012]
According to the present invention, since the address translation information related to the second zone is created in the address translation table before the second zone is actually accessed, the second zone is thereafter Therefore, it is not necessary to create corresponding address translation information from the beginning. As a result, it is possible to effectively suppress a decrease in performance while saving the capacity of the address conversion table.
[0013]
In addition, when access (especially data read) is requested to a certain zone, access to the subsequent zone is often requested thereafter, so the second zone is viewed from the host side. It is preferable that it is a zone next to the first zone. The memory controller according to the present invention further includes means for displaying the priority order of the r tables, and the predetermined table is preferably selected from a table having the lowest priority order and a table having the next lowest priority order. .
[0014]
A memory controller according to another aspect of the present invention is a memory controller for accessing a flash memory that can be divided into p zones, and stores a table that can store address conversion information about one zone of the flash memory. And a second zone following the first zone as seen from the host side in response to a request for access to the first zone of the flash memory. It is determined whether or not the address conversion information is stored in any one of the address conversion tables.
[0015]
According to the present invention, it is possible to improve performance by determining in advance whether or not the address translation information related to the second zone that is likely to be accessed next is stored in the address translation table. Further, in response to determining that the address conversion information related to the second zone is not stored in any of the address conversion tables, the address related to the second zone is assigned to any of the tables. If overwriting of conversion information is started, it is not necessary to create corresponding address conversion information from the beginning even if the second zone is actually accessed thereafter. As a result, it is possible to effectively suppress a decrease in performance while saving the capacity of the address conversion table.
[0016]
According to still another aspect of the present invention, a memory controller temporarily stores an address conversion table used for conversion from a logical address belonging to an address on the host computer side to a physical address belonging to an address on the flash memory side, and data read from the flash memory. A temporary memory for storing the address conversion table, and updating the contents of the address conversion table during a period in which the data stored in the temporary memory is transferred to the host computer.
[0017]
According to the present invention, it is possible to improve performance by updating the contents of the address conversion table during a period in which the memory controller is originally in a waiting state. The temporary memory is preferably a FIFO.
[0018]
A flash memory system according to an aspect of the present invention is a flash memory system including a flash memory that can be divided into p zones and a memory controller that accesses the flash memory, wherein the memory controller includes: A first zone that is an access target in response to a request for access to the flash memory, the address conversion table having r (r <p) tables capable of storing address conversion information related to one zone; The address conversion information relating to the second zone different from the above is created in a predetermined table of the address conversion table.
[0019]
Also in the present invention, since the address translation information related to the second zone is created in the address translation table before the second zone is actually accessed, the second zone is thereafter When actually accessed, it is not necessary to create corresponding address translation information from the beginning. As a result, it is possible to effectively suppress a decrease in performance while saving the capacity of the address conversion table.
[0020]
A flash memory system according to another aspect of the present invention includes a flash memory that can be divided into p zones and a memory controller that accesses the flash memory, wherein the memory controller includes the flash memory. In response to a request for access to the first zone of the flash memory, the host side is provided with an address conversion table having r (r <p) tables capable of storing address conversion information related to one zone. It is determined whether or not address conversion information related to a second zone following the first zone is stored in any one of the address conversion tables.
[0021]
The present invention also makes it possible to improve performance by determining in advance whether or not the address translation information related to the second zone that is likely to be accessed next is stored in the address translation table.
[0022]
A flash memory control method according to an aspect of the present invention is a flash memory control method that can be divided into a plurality of zones, in response to a request for access to the first zone of the flash memory. Determining whether address translation information relating to the second zone following the first zone as viewed from the side is stored in an address translation table; and address translation information relating to the second zone is the address translation information If not stored in the table, the method includes a step of starting storing address conversion information related to the second zone in the address conversion table.
[0023]
Also in the present invention, storage of address translation information related to the second zone is started in the address translation table before the second zone is actually accessed. When the zone is actually accessed, it is not necessary to create corresponding address translation information from the beginning. As a result, it is possible to effectively suppress a decrease in performance while saving the capacity of the address conversion table.
[0024]
A flash memory control method according to another aspect of the present invention is a flash memory control method that can be divided into a plurality of zones, in response to a request for access to a predetermined zone of the flash memory. A first step of determining whether or not address conversion information relating to a predetermined zone is stored in the address conversion table; and determining that address conversion information relating to the predetermined zone is stored in the address conversion table. And a second step of determining whether this is complete address translation information or incomplete address translation information. In response to determining that the address translation information is incomplete in the second step, the corresponding address translation information is obtained by completing the incomplete portion by supplementing it. Since it is no longer necessary to create from the beginning, it is possible to effectively suppress a decrease in performance.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0026]
FIG. 1 is a block diagram schematically showing a configuration of a flash memory system 1 according to a preferred embodiment of the present invention. As shown in FIG. 1, a flash memory system 1 according to this embodiment includes a flash memory 2 and a controller 3. Although not particularly limited, the flash memory system 1 is configured by integrating the flash memory 2 and the controller 3 in one card, and can be used as a kind of external storage device that can be attached to and detached from the host computer. . Examples of the host computer include various information processing apparatuses such as a personal computer and a digital still camera that process various kinds of information such as characters, sounds, and image information.
[0027]
The flash memory 2 is composed of one or more semiconductor chips including a large number of memory cells, and is configured by n (for example, 8192) blocks. Each of these n blocks includes k (for example, 32) pages (sectors), and each page is used as a minimum access unit having a recording capacity of, for example, 512 bytes. So, as in the example above,
n = 8192 (= 8K)
k = 32
In this case, the flash memory 2 includes an address space of 256K pages. Therefore, in order to access a specific page from the host computer side, address information of at least 18 bits is required. In this specification, address information supplied from the host computer to the flash memory system 1 is referred to as a “host address”.
[0028]
The controller 3 is composed of various functional blocks including at least a CPU 4, a RAM 5, a ROM 6 and a FIFO 7. Although not particularly limited, the controller 3 is preferably integrated on one semiconductor chip. The CPU 4 is a functional block for controlling the operation of the entire functional blocks constituting the controller 3. The RAM 5 is a work area in which data necessary for the control of the flash memory 2 by the CPU 4 is temporarily stored. Although not particularly limited, the RAM 5 is preferably composed of a plurality of SRAM cells. As will be described in detail below, the address conversion table is also stored in the RAM 5. The ROM 6 is a functional block for storing a control program (firmware) to be executed by the CPU 4. The FIFO 7 is a memory for temporarily storing data to be written to the flash memory 2 and data read from the flash memory 2.
[0029]
Next, a specific structure of the memory cell included in the flash memory 2 will be described.
[0030]
FIG. 2 is a cross-sectional view schematically showing the structure of each memory cell 10 included in the flash memory 2. As shown in FIG. 2, the memory cell 10 includes an N-type source diffusion region 12 and a drain diffusion region 13 formed in a P-type semiconductor substrate 11, and a P-type between the source diffusion region 12 and the drain diffusion region 13. Tunnel oxide film 14 formed over semiconductor substrate 11, floating gate electrode 15 formed on tunnel oxide film 14, insulating film 16 formed on floating gate electrode 15, and formed on insulating film 16 And the control gate electrode 17 thus formed. A plurality of memory cells 10 having such a configuration are connected in series in the flash memory 2 to form a NAND flash memory.
[0031]
The memory cell 10 is in an “erased state” or a “written state” depending on whether or not electrons are injected into the floating gate electrode 15. That the memory cell 10 is in the erased state means that the data “1” is held in the memory cell 10, and that the memory cell 10 is in the written state indicates that the data “0” is stored in the memory cell 10. "Is held. That is, the memory cell 10 can hold 1-bit data.
[0032]
As shown in FIG. 2, the erased state refers to a state where electrons are not injected into the floating gate electrode 15. The memory cell 10 in the erased state becomes a depletion type transistor, and a P-type semiconductor substrate 11 between the source diffusion region 12 and the drain diffusion region 13 regardless of whether or not a read voltage is applied to the control gate electrode 17. A channel 18 is formed on the surface. Therefore, the source diffusion region 12 and the drain diffusion region 13 are always electrically connected by the channel 18 regardless of whether or not the read voltage is applied to the control gate electrode 17.
[0033]
FIG. 3 is a cross-sectional view schematically showing the memory cell 10 in the written state. As shown in FIG. 3, the writing state refers to a state where electrons are accumulated in the floating gate electrode 15. Since the floating gate electrode 15 is sandwiched between the tunnel oxide film 14 and the insulating film 16, the electrons once injected into the floating gate electrode 15 stay in the floating gate electrode 15 for a very long time. The memory cell 10 in the written state is an enhancement type transistor, and when the read voltage is not applied to the control gate electrode 17, the surface of the P type semiconductor substrate 11 between the source diffusion region 12 and the drain diffusion region 13 is formed. When a read voltage is applied to the control gate electrode 17, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 11 between the source diffusion region 12 and the drain diffusion region 13. Is done. Therefore, the source diffusion region 12 and the drain diffusion region 13 are electrically insulated when the read voltage is not applied to the control gate electrode 17, and the source diffusion is performed when the read voltage is applied to the control gate electrode 17. The region 12 and the drain diffusion region 13 are electrically connected.
[0034]
Here, whether the selected memory cell 10 is in the erased state or the written state can be read as follows. That is, among the plurality of memory cells 10 connected in series, a read voltage is applied to the control gate electrodes 17 of all the memory cells 10 other than the selected memory cell 10, and in this state, the memory cells 10 are connected in series. Detects whether current flows through the body. As a result, if a current flows through the series body, it can be determined that the selected memory cell 10 is in an erased state. If no current flows through the series body, the selected memory cell 10 is written. It can be determined that the state is present. In this way, it is possible to read out whether the data held in any memory cell 10 included in the serial body is “0” or “1”. However, in the NAND flash memory, data held in two or more memory cells 10 included in one serial body cannot be read simultaneously.
[0035]
When the memory cell 10 in the erased state is changed to the written state, a positive high voltage is applied to the control gate electrode 17, whereby electrons are injected into the floating gate electrode 15 through the tunnel oxide film 14. The Electrons can be injected into the floating gate electrode 15 by FN tunnel current. On the other hand, when the memory cell 10 in the write state is changed to the erase state, a negative high voltage is applied to the control gate electrode 17, whereby electrons accumulated in the floating gate electrode 15 through the tunnel oxide film 14 are applied. Is discharged.
[0036]
Next, a specific configuration of the address space that the flash memory 2 has will be described.
[0037]
FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory 2. As shown in FIG. 4, the address space of the flash memory 2 is composed of n blocks including blocks # 0 to # n-1. Here, each block is a data erasing unit. That is, in the flash memory 2, for each memory cell 10, the state cannot be changed from the written state to the erased state. When the memory cell 10 is changed from the written state to the erased state, the memory cell All the memory cells 10 included in the block to which 10 belongs need to be collectively erased. Conversely, the state of each memory cell 10 can be changed from the erased state to the written state.
[0038]
Further, as shown in FIG. 4, each block # 0 to # n−1 configuring the flash memory 2 includes k pages each including pages # 0 to # k−1. Each of these pages is an access unit for reading and writing data. As shown in FIG. 4, 8 bits consisting of bits b0 to b7 are 1 byte, for example, a user area 21 of 512 bytes and a redundant area 22 of 16 bytes, respectively. Consists of. The user area 21 is an area in which user data supplied from the host computer is stored.
[0039]
Here, n blocks # 0 to # n-1 are divided into p zones consisting of zones # 0 to # p-1 (p is an integer equal to or greater than 3 and a divisor of n). being classified. Therefore, each zone is constituted by n / p (= m) blocks. Zone #q (q is one of 0 to p-1) is configured by blocks # m × q to # m × q + m−1. For example,
n = 8192 (= 8K)
p = 8
In this case, each zone is configured by m = 1024 blocks, and specifically, zone #q is configured by blocks # 1024q to # 1024q + 1023. The reason why the address space of the flash memory 2 is classified into p zones is to save the recording capacity of the address conversion table, details of which will be described later.
[0040]
FIG. 5 is a diagram schematically showing the data structure of the redundant area 22. As shown in FIG. 5, the redundant area 22 includes a logical block address storage area 23 and an area 24 for storing other additional information.
[0041]
The logical block address storage area 23 is an area for storing a logical block address corresponding to the block, and is at least x (x = log). ₂ m) memory cells 10 are allocated. Here, the logical block address is an address generated based on a part of the host address or a part of the host address, and indicates a block number in each zone viewed from the host computer side. Therefore, the logical block address is uniquely assigned in each zone and is composed of at least x bits. The logical block address storage area 23 is an element that is commonly provided in the redundant area 22 included in each page. However, since one block includes k pages, the logical block addresses of all pages constituting one block are included. It is not necessary to store the logical block address in the storage area 23, and it is sufficient to store the logical block address in the logical block address storage area 23 of at least the first page (page # 0) of each block. In addition, since all the memory cells 10 in the erased block are in the erased state (1), if the logical block address storage area 23 is composed of x memory cells 10, the logical block address storage area 23 The stored value is m-1 (= 2 ^x -1). On the other hand, for a block in which some user data is stored, the corresponding logical block address value is stored in the logical block address storage area 23.
[0042]
The area 24 stores additional information (error collection code) for correcting an error in user data stored in the corresponding user area 21, a block status for displaying an abnormality about the block, and the like. However, since these are not directly related to the gist of the present invention, description thereof is omitted.
[0043]
As described above, the flash memory 2 is composed of n blocks, each of which is classified into p zones each consisting of m blocks. Of the m blocks included in each zone, m is the number of blocks. '(<M) blocks are treated as actual used blocks that can actually store data, and the remaining mm' blocks are treated as redundant blocks. The address space of the flash memory 2 is composed only of actual use blocks. When a defect occurs in a certain block and becomes unusable, the number of blocks used as redundant blocks is reduced by the number of defective blocks. It is.
[0044]
Next, various tables created in the RAM 5 will be described.
[0045]
The various tables created in the RAM 5 include at least an address conversion table, a management table, a priority link, and a write queue, which are stored in the ROM 6 when the controller 3 is turned on or reset. It is created by the CPU 4 based on the firmware that has been set.
[0046]
The address conversion table is a table for holding the correspondence between the logical block address generated based on the host address and the physical block address uniquely assigned to each block, and has the following structure: Yes.
[0047]
FIG. 6 is a diagram showing the data structure of the address conversion table 31 created in the RAM 5. As shown in FIG. 6, the address conversion table 31 includes r tables including tables # 0 to # r-1 (r is an integer of 2 to p-1). Each table # 0 to # r-1 is an area for storing address conversion information related to any one of zone # 0 to zone # p-1, and r <p as described above. In the address conversion table 31, all (p) zone address conversion information cannot be stored, and only some (r) zone address conversion information can be stored. This is nothing but to reduce the product cost by saving the storage capacity required for the address conversion table 31.
[0048]
Each table # 0 to # r-1 corresponds to each of m physical block address storage areas consisting of physical block address storage areas # 0 to # m-1 and these physical block address storage areas. M flags provided. Here, the area number (# 0 to # m-1) uniquely assigned to each physical block address storage area indicates a logical block address, and the contents stored in each physical block address storage area correspond to Indicates the physical block address to be executed. Therefore, for example, if the physical block address stored in the physical block address storage area #i (i is one of 0 to m−1) is #j, the logical block address = # i is the physical block address = # j. It will correspond to.
[0049]
Flags # 0 to # m-1 indicate whether or not the contents (physical block addresses) of the corresponding physical block address storage areas are valid. Specifically, if the flag is “0”, it means that the contents of the corresponding physical block address storage area are valid, and if the flag is “1”, the contents of the corresponding physical block address storage area. Means that is invalid. Of course, conversely, when the contents of the physical block address storage area are valid, the corresponding flag may be set to “1”.
[0050]
The management table is a table for indicating which zone the address conversion information stored in each of the tables # 0 to # r-1 is address conversion information, and has the following structure.
[0051]
FIG. 7 is a diagram showing the data structure of the management table 32 created in the RAM 5. As shown in FIG. 7, the management table 32 includes r zone number storage areas including zone number storage areas # 0 to # r-1. The zone number storage areas # 0 to # r-1 correspond to the tables # 0 to # r-1, respectively, and the values stored here indicate the corresponding zone numbers. As an example, when the address conversion information stored in the table # 2 is address conversion information related to the zone # 5, “5” is stored as the zone number in the zone number storage area # 2. Therefore, by referring to the management table 32, it is possible to know the relationship between each table # 0 to # r-1 and each zone # 0 to # p-1.
[0052]
The priority link is an element indicating the priority order of the tables # 0 to # r-1 constituting the address conversion table 31, and has the following structure.
[0053]
FIG. 8 is a diagram showing the data structure of the priority link 33 created in the RAM 5. As shown in FIG. 8, the priority link 33 is composed of r pointers composed of pointers # 0 to # r-1. Before describing a specific method for indicating the priority order of the r tables # 0 to # r-1 constituting the address conversion table 31 by the priority link 33, the r tables # 0 to # r-1 are described. The necessity to set the priority order will be described.
[0054]
As described above, the number (r) of tables constituting the address conversion table 31 is smaller than the number of zones (p) constituting the address space of the flash memory 2, and is therefore expanded in the address conversion table 31. The address translation information is limited to address translation information related to some zones. Therefore, when the host computer requests access to a zone in which the address conversion information is not expanded in the address conversion table 31, the contents of the address conversion table 31 need to be updated. That is, the CPU 4 selects any one of the r tables # 0 to # r-1 constituting the address conversion table 31, erases the contents thereof, and addresses related to the zone requested to be accessed. It is necessary to newly store the conversion information in the table. Accordingly, in order to select a table whose contents are to be deleted from among the tables # 0 to # r-1, a priority order is provided for the tables # 0 to # r-1, and the table having the lowest priority order is selected. The contents need to be erased.
[0055]
For this reason, priority is given to the r tables # 0 to # r-1 constituting the address conversion table 31, and a priority link 33 is provided to store the priority. A method of storing the priority order of the tables # 0 to # r-1 using the priority link 33 is as follows.
[0056]
That is, the pointers # 0 to # r-1 constituting the priority link 33 are stored so that any one of the values "0" to "r-1" and the data "NULL" does not overlap each other as the link destination pointer number. As a result, the table corresponding to the value (0 to r-1) not stored in any pointer becomes the highest priority table. For example, when the value “2” is not stored in any pointer, the table # 2 is the highest priority table.
[0057]
Next, the table corresponding to the value (0 to r-1) stored in the pointer having the same number as the highest priority table becomes the second highest priority table. As in the above example, when the table # 2 is the highest priority table, the table corresponding to the value (for example, “0”) stored in the pointer # 2 is the second highest priority table. Become.
[0058]
Similarly, the table corresponding to the value (0 to r-1) stored in the pointer having the same number as the second highest priority table becomes the third highest priority table. By sequentially performing the link work, it is possible to specify priorities for all the tables # 0 to # r-1. Data “NULL” is stored in the pointer having the same number as the table with the lowest priority, and thus the table with the lowest priority can be immediately identified by referring to the priority link 33.
[0059]
The write queue is a registration table of erased empty blocks, and has the following structure.
[0060]
FIG. 9 is a diagram showing the data structure of the write queue 34 created in the RAM 5. As shown in FIG. 9, the write queue 34 is composed of r queues including queue # 0 to queue # r-1, and each queue has a physical block address of an erased block included in the corresponding zone. Stored. Here, the corresponding zone refers to a zone in which address conversion information is stored in a table having the same number as the queue number of each queue. For example, if the address conversion information related to the zone # 7 is stored in the table # 1, the zone corresponding to the queue # 1 is the zone # 7, and the erased block among the blocks constituting the zone # 7 Are stored in the queue # 1.
[0061]
Although the write queue 34 shown in FIG. 9 is composed of r queues, a plurality of physical block addresses of erased blocks included in the corresponding zone are stored by using queues that are integer multiples of r. You may comprise.
[0062]
The above is the configuration of the flash memory system according to this embodiment. Next, the operation of the flash memory system 1 according to this embodiment will be described.
[0063]
FIG. 10 is a flowchart showing a new creation method of the address conversion table 31. The new creation of the address conversion table 31 is an operation performed by the CPU 4 executing the firmware stored in the ROM 6 in response to the power-on or reset operation being performed on the controller 3. Alternatively, it constitutes one of the initial setting operations of the controller 3 in response to the reset operation.
[0064]
First, when the controller 3 is powered on or reset, the CPU 4 resets all the bits constituting the address conversion table 31 in the RAM 5 to “1” (step S1). Next, the CPU 4 resets the values of the internal variables a and b to 0 (step S2), and the block number is
a × m + b
The logical block address stored in the first page (page # 0) of the block that matches is read (step S3). As described above, “m” is a value (= n / p) obtained by dividing the total number of blocks n by the number of zones p (= n / p), and represents the number of blocks constituting one zone. In this case, since the internal variable a = b = 0, the logical block address stored in page # 0 of block # 0 is read out.
[0065]
Next, the CPU 4 determines whether or not the read logical block address is “all 1”, that is, m−1 (step S4). As a result, the read logical block address is If it is other than “all 1 (= m−1)” (S4: NO), among the tables whose table number matches the internal variable a, the flag whose flag number matches the logical block address is rewritten to “0”. Along with (Step S5), the internal variable b is stored in the physical block address storage area whose area number matches the logical block address (Step S6). On the other hand, if the read logical block address is “all 1 (= m−1)” in step S4 (S4: YES), steps S5 and S6 are not executed.
[0066]
Then, after incrementing the internal variable b (step S7), the CPU 4 determines whether or not the internal variable b matches m (step S8). As a result, if the internal variable b is not m (S8) : NO), the process returns to step S3, and the logical block address is read using the internal variables a and b. On the other hand, when the internal variable b matches m (S8: YES), after the internal variable a is incremented (step S9), it is determined whether or not the internal variable a matches r (step S9). S10) As a result, if the internal variable a is not r (S10: NO), the process returns to step S3 to read the logical block address using the internal variables a and b. On the other hand, if the internal variable a matches r (S10: YES), a series of processing is completed. As described above, “r” represents the number of tables constituting the address conversion table 31.
[0067]
As described above, steps S3 to S10 are repeatedly executed until the internal variable a matches r, thereby completing the address conversion table 31. That is, by repeating the loop consisting of steps S3 to S8 until the internal variable b matches m, the address translation information relating to one zone is stored in a predetermined table, and steps S3 to S3 are repeated until the internal variable a matches r. By repeating the loop consisting of S10, the address conversion information is stored in all the tables. Specifically, by executing the operation shown in FIG. 10, the address conversion information related to zone # 0 to zone # r-1 is stored in tables # 0 to # r-1, respectively.
[0068]
In the above example, zone # 0 to zone # r-1 are selected as targets for storing the address translation information in the address translation table 31, but this operation is executed immediately after the controller 3 is turned on or immediately after the reset. Therefore, the present invention is not limited to zone # 0 to zone # r-1, and any zone may be targeted.
[0069]
In addition, after the new creation operation of the address translation table 31 is completed, or in parallel with the new creation operation of the address translation table 31, other operations in the initial setting operation, that is, creation of the management table 32, priority link 33 A creation and write queue 34 is created.
[0070]
That is, zone numbers # 0 to # r-1 are stored as zone numbers in the zone number storage areas # 0 to # r-1 constituting the management table 32, and address conversion relating to zone # 0 to zone # r-1 is thereby performed. The fact that the information is stored in tables # 0 to # r-1 is displayed.
[0071]
Also, “1” to “r−1” are stored in the pointers # 0 to # r-2 constituting the priority link 33, respectively, and data “NULL” is stored in the pointer # r-1. Thereby, the priorities of the tables # 0 to # r-1 are in this order. However, since the access is not actually made at this time and there is no clue for determining the priority order, the priority order determined here is only temporary. Therefore, it is not essential that the priorities of the tables # 0 to # r-1 be in this order, and a different order may be used.
[0072]
Then, erased blocks included in the zones # 0 to # r-1 are selected one by one, and the physical block addresses are registered in the queues # 0 to # r-1 constituting the write queue 34.
[0073]
Thus, the initial setting operation of the controller 3 in response to the power-on or reset operation is completed.
[0074]
Next, a method of accessing the flash memory 2 after the address conversion table 31 and the like are created, that is, after the initial setting is completed, will be described in the order of data read operation and data write operation. As for the data write operation, when data is newly assigned to a logical block address to which no data is assigned (new data write operation), and for a logical block address to which data has already been assigned. A case where data is added or overlapped (data overwriting operation) will be described separately.
[0075]
First, a data read operation will be described.
[0076]
FIG. 11 is a flowchart showing a data read operation. Such an operation is also performed by the CPU 4 executing the firmware stored in the ROM 6.
[0077]
In a data read operation, when a host address is supplied from the host computer, the CPU 4 first sets the READY / BUSY signal (see FIG. 1) to the BUSY state, and based on the host address, the zone address, logical block address, and page An address is created (step S11). Specifically, the upper bits of the host address are divided by m ′ (the number of actually used blocks included in one zone), the zone address is specified based on the quotient, and the logical block address is specified based on the remainder. . As an example, eight flash memories 2 (p = 2) ³ ) Zones, and each zone is 1024 (m = 2) ¹⁰ ) Blocks, and 32 blocks (k = 2) ⁵ ), A host address of at least 18 bits is used, and a quotient obtained by dividing the upper 13 bits by m ′ (for example, 1000) is a zone address, and a remainder is a logical block address. In addition, the lower 5 bits of the host address directly become the page address.
[0078]
Next, the CPU 4 refers to the management table 32 created in the RAM 5 to determine whether or not the address translation information regarding the zone to be accessed is stored in the address translation table 31 (step S12). Here, the zone to be accessed is specified by the zone address obtained in step S11, and corresponds to the zone having the same number as the zone address. The above determination is made based on whether or not the same value as the zone address is stored in any of the zone number storage areas # 0 to # r-1 constituting the management table 32. Is determined that the address conversion information related to the zone to be accessed is stored in the address conversion table 31, and if not stored, the address conversion information related to the zone to be accessed is stored in the address conversion table 31. It is judged that it is not.
[0079]
As a result, when it is determined that the address conversion information related to the zone to be accessed is stored in the address conversion table 31 (S12: YES), the CPU 4 further determines whether the table corresponding to the zone to be accessed is complete. It is determined whether it is incomplete (step S13). Here, the table corresponding to the zone to be accessed refers to a table having the same number as the zone number storage area in which the same value as the zone address is stored. For example, if the same value as the zone address is stored in the zone number storage area # 1, the table for determining whether or not it is complete is the table # 1. A specific method for determining whether or not the table is complete is not particularly limited. For example, a flag indicating whether or not the table is complete may be provided and referred to.
[0080]
As a result, when it is determined that the table corresponding to the zone to be accessed is complete (S13: YES), the CPU 4 refers to this table to convert the logical block address into the physical block address (step S14). A specific address conversion method is as follows. That is, the conversion is performed by accessing the physical block address storage area whose area number matches the logical block address from the selected table and reading the physical block address stored therein. Note that this example is a data read operation, and in principle, user data should be allocated to the block corresponding to the host address, so the corresponding flag should be “0 (valid)”. It is. However, some host computers may make a read request to a host address to which no user data is assigned.
[0081]
On the other hand, when it is determined in step S12 that the address conversion information regarding the zone to be accessed is not stored in the address conversion table 31 (S12: NO), the table update operation is executed. The table update operation will be described later.
[0082]
If it is determined in step S13 that the table corresponding to the zone to be accessed is incomplete (S13: NO), a table completion operation is executed. The table completion operation will also be described later.
[0083]
Next, the CPU 4 accesses the flash memory 2 based on the zone address, the physical block address read from the address conversion table 31 and the page address, and reads the data stored in the corresponding page (step S15). . In this case, the accessed block is specified by the zone address and the physical block address, and the accessed page is specified by the page address.
[0084]
Then, the read data is temporarily stored in the FIFO 7, and the READY / BUSY signal is set to the READY state (step S16). The READY state means that the controller 3 is in a waiting state and can accept access from the host computer, and the host computer reads the user data stored in the FIFO 7 in response to this. When the host computer reads user data stored in the FIFO 7, the data transfer is generally executed byte by byte. Therefore, when one page consists of 512 bytes of user data, the host computer completes a series of data transfers by executing 512 readings.
[0085]
During this time, the CPU 4 updates the priority link 33 (step S17). The specific update procedure of the priority link 33 is as follows. First, it is stored in the pointer that stores the same value as the table number of the currently used table (the table corresponding to the accessed zone), and in the pointer that has the same number as the table number of the currently used table. Overwrite the value. Next, the table number of the table with the highest priority is overwritten as the link destination pointer number on the pointer having the same number as the table number of the currently used table. As a result, the update of the priority link 33 is completed, and the priority of the table corresponding to the currently accessed zone becomes the highest.
[0086]
To explain using a specific example, r, which is the number of tables constituting the address conversion table 31 (= the number of pointers constituting the priority link 33) is “4”, and is a state immediately after the initialization operation is completed. When table # 2 is used in a state where “1” to “3” are stored in pointers # 0 to # 2 and data “NULL” is stored in pointer # 3, respectively, the table that is currently used The value “3” stored in the pointer # 2 having the same number as the table number “2” of the currently used table is overwritten on the pointer # 1 storing the table number “2”. To do. Then, “0”, which is the table number of the table with the highest priority, is overwritten on the pointer # 2 having the same number as “2”, which is the table number of the currently used table. As a result, the contents of the pointers # 0 to # 3 are “1”, “3”, “0”, and “NULL”, respectively, so the priorities of the tables # 0 to # 3 are the tables # 2, # 0, and # 1. , # 3.
[0087]
Further, the CPU 4 determines whether or not the address conversion information related to the zone next to the currently accessed zone is stored in the address conversion table 31 (step S18). Here, the zone next to the currently accessed zone refers to the zone located next to the currently accessed zone when viewed from the host side, and the currently accessed zone is the zone #q (q is 0 to p−). 1), it indicates zone # q + 1. Therefore, when the zone accessed now is the last zone, zone # p-1, there is no next zone. Further, the above determination is made according to whether or not the value “q + 1” is stored in any of the zone number storage areas # 0 to # r−1 constituting the management table 32, as in the determination in step S12. If it is determined that the address conversion information related to the next zone is stored in the address conversion table 31, otherwise, the address conversion information related to the next zone is stored in the address conversion table 31. It is determined that it is not stored in Here, the reason why it is determined whether or not the address conversion information related to the next zone is stored in the address conversion table 31 is as follows. This is because the address conversion table 31 is speculatively updated before the data reading for the next zone is actually requested because there is a high possibility that the data reading for the next zone is requested.
[0088]
As a result, when it is determined that the address conversion information related to the next zone is stored in the address conversion table 31 (S18: YES), the table corresponding to the next zone is complete or incomplete. Is determined (step S19). As a result, when it is determined that the table corresponding to the next zone is incomplete (S19: NO), a table completion operation to be described later is executed. If it is determined in step S19 that the table corresponding to the next zone is complete (S19: YES), a series of processing is completed.
[0089]
On the other hand, if it is determined in step S18 that the address conversion information related to the next zone is not stored in the address conversion table 31 (S18: NO), the table update operation is executed.
[0090]
Next, the table update operation will be described.
[0091]
FIG. 12 is a flowchart showing the table update operation. As described above, the table update operation is performed when it is determined in step S12 shown in FIG. 11 that the address conversion information related to the zone to be accessed is not stored in the address conversion table 31, or in step S18 shown in FIG. When the address conversion information on the next zone after the currently accessed zone is determined not to be stored in the address conversion table 31, the process is executed. Such an operation is also performed by the CPU 4 executing the firmware stored in the ROM 6.
[0092]
In the table update operation, the CPU 4 first specifies the table with the lowest priority by referring to the priority link 33 created in the RAM 5 (step S21). Here, the table with the lowest priority is specified by searching for the pointer storing the data “NULL” among the pointers # 0 to # r−1 constituting the priority link 33, and the data “NULL”. It is determined that the table having the same number as the pointer number of the pointer storing “is the table with the lowest priority. Hereinafter, the description will be continued assuming that the zone address of the zone in which the address conversion information is newly stored is “c”. Here, the zone in which the address translation information is newly stored is a zone to be accessed in the case of branching from step S12 shown in FIG. 11 (S12: NO) (zone corresponding to the zone address obtained in step S11). In the case of branching from step S18 shown in FIG. 11 (S18: NO), it indicates the zone next to the currently accessed zone.
[0093]
Next, the CPU 4 updates the contents of the management table 32, and associates the table determined to have the lowest priority in step S21 with the zone in which the address translation information is newly stored (step S22). That is, “c” is stored in the corresponding zone number storage area.
[0094]
Next, the CPU 4 resets the value of the internal variable d to 0 (step S23), and the block number is
c × m + d
The logical block address stored in the first page (page # 0) of the block that matches is read (step S24). In this case, since the internal variable d = 0, the logical block address stored in page # 0 of the first block # (c × m) of the zone in which the address conversion information is newly stored is read out.
[0095]
Next, the CPU 4 determines whether or not the read logical block address is “all 1”, that is, m−1 (step S25), and as a result, the read logical block address is If it is other than “all 1 (= m−1)” (S25: NO), the flag whose flag number matches the logical block address in the table determined to have the lowest priority in step S21 is “0”. (Step S26) and the internal variable d is stored in the physical block address storage area whose area number matches the logical block address (step S27). On the other hand, if the read logical block address is “all 1 (= m−1)” in step S25 (S25: YES), among the tables determined to have the lowest priority in step S21, the flag The flag whose number matches the logical block address is rewritten to “1” (step S28).
[0096]
Then, the CPU 4 increments the internal variable d (Step S29).
), It is determined whether or not the internal variable d matches m (step S30). As a result, if the internal variable d is not m (S30: NO), the process returns to step S24, and the internal variable d and the like. The logical block address is read using. On the other hand, if the internal variable d matches m (S30: YES), the table update operation is completed, and if the process branches from step S12 shown in FIG. 11 (S12: NO), the process returns to step S14. If the process branches off from step S18 shown in FIG. 11 (S18: NO), the series of processing ends.
[0097]
As described above, by repeating the loop consisting of step S24 to step S30 until the internal variable d matches m, the contents of the table with the lowest priority are updated to the address conversion information related to the zone to be accessed. The
[0098]
In the above example, the contents of the table are updated regardless of which zone corresponds to the table with the lowest priority, but the zone corresponding to the table with the lowest priority is the first zone. In the case of a certain zone # 0, it is preferable to set a table with the next lowest priority as an update target. This is because, as described above, a frequently accessed file is often stored in the first zone, zone # 0. For this reason, if address conversion information related to zone # 0 is discarded, the performance may be degraded. It is.
[0099]
Further, the write queue 34 is created after the table update operation is completed or in parallel with the table update operation. That is, one erased block included in the zone #c is selected, and its physical block address is registered in the queue corresponding to the updated table among the queues # 0 to # r-1 constituting the write queue 34. The
[0100]
Now, when the table update operation shown in FIG. 12 branches from step S12 shown in FIG. 11 (S12: NO), it is executed until it is determined in step S30 that the internal variable d matches m. However, if the process branches off from step S18 shown in FIG. 11 (S18: NO), the READY / BUSY signal is already in the READY state in step S16, so there is a possibility of receiving the next access from the host computer. . Further, when the data requested by the host computer (FIG. 11) is for a plurality of continuous pages, the controller 3 starts reading the data for the next page when the transfer of the data stored in the FIFO 7 is completed. There is a need to. In such a case, the table update operation shown in FIG. 12 is temporarily interrupted, and the controller 3 performs a process newly requested by the host computer (for example, the next data reading process) or reading data for the next page. Execute. When interrupting the table update operation, it is necessary to store the internal variable d in the RAM 5. The incomplete table is generated mainly for this reason.
[0101]
If this interruption is due to the next access from the host computer, if the requested process is a read process for the same zone, the process is executed and the READY / BUSY signal is again set to the READY state and then interrupted. The table update operation may be resumed. If this interruption is due to the next access from the host computer and the requested process is a read process for the next zone, that is, a zone in which the corresponding table is incomplete, FIG. In step S13, it is determined that the table is incomplete (S13: NO), and a table completion operation to be described later is performed. However, if the process requested by the host computer is a read process for a zone that is neither the same zone nor the next zone, the contents of the incomplete table are discarded.
[0102]
If the interruption is to read data for the next page, the updating operation of the interrupted table can be resumed in response to the data of the next page being read and stored in the FIFO 7. Good. This will be described in more detail with reference to a timing diagram.
[0103]
FIG. 13 is a timing chart showing the timing of interrupting / resuming the table update operation when a plurality of pages in which data requested by the host computer is continuously read are targeted.
[0104]
As shown in FIG. 13, when an address and a command are first issued from the host computer and the controller 3 receives them (address reception, command reception), the READY / BUSY signal changes from the READY state to the BUSY state, and the internal address is changed. Generated (address generation). Here, the address supplied from the host computer is an address for specifying the first page among a plurality of pages to be read, and the command supplied from the host computer indicates a read command, This is a command for specifying the number of pages to be read (for example, 100 pages from the first page). The address generation is an operation corresponding to steps S11 to S14 shown in FIG. 11. As described above, when necessary address conversion information is not stored in the address conversion table 31 (S12: NO). The table updating operation shown in FIG. 12 is included. If the table to be referred to is incomplete (S13: NO), a table completion operation to be described later is included.
[0105]
When the internal address is generated, reading to the flash memory 2 is actually executed using the internal address, and the read user data is stored in the FIFO 7 (Read). Such an operation corresponds to steps S15 and S16 shown in FIG.
[0106]
When the user data is stored in the FIFO 7, the READY / BUSY signal changes to the READY state, and in response to this, the host computer reads the data stored in the FIFO 7. That is, data transfer from the flash memory 2 to the host computer is performed. During this time, a table update operation for storing the address conversion information related to the next zone in the address conversion table 31 is performed (table update). Although it depends on the data transfer speed to the host computer and the operation speed of the flash memory 2 and the controller 3, it is generally difficult to complete the table update operation while transferring one page of data to the host computer. It is. That is, since the data transfer to the host computer is completed in the middle of the table update operation, the controller 3 needs to interrupt the table update operation and read the data for the next page and store it in the FIFO 7.
[0107]
In this way, by alternately performing the actual read operation (Read) and the table update operation (table update), the address related to the next zone is utilized by utilizing the data transfer period that is originally free for the controller 3. Part or all of the conversion information can be speculatively stored in the address conversion table 31.
[0108]
Here, the address conversion information related to the next zone is stored in the address conversion table 31. When data is read from a certain zone, there is a possibility that data read from the next zone is requested thereafter. This is because the performance in the case where the reading of data for the next zone is actually requested is improved. In other words, if a part or all of the address conversion information related to the next zone is stored in the address conversion table 31 by utilizing the data transfer period which is a free time, the data reading for the next zone is actually requested. In this case, since it is determined in step S12 shown in FIG. 11 that necessary address conversion information is stored (S12: YES), a series of data read operations can be completed at high speed.
[0109]
However, if data reading for the next zone is actually requested before the speculative table update operation is completely completed, only a part of the address translation information related to the zone is stored in the predetermined table. In this state, that is, because the table is in an incomplete state (S13: NO), it is necessary to perform a table completion operation described next.
[0110]
FIG. 14 is a flowchart showing a table completion operation. As described above, the table completion operation is executed when it is determined in step S13 shown in FIG. 11 that the table corresponding to the zone to be accessed is incomplete. Such an operation is also performed by the CPU 4 executing the firmware stored in the ROM 6.
[0111]
In the table completion operation, the CPU 4 first loads the value of the internal variable d stored in the RAM 5 (step S31), and the block number is
c × m + d
The logical block address stored in the first page (page # 0) of the block that matches is read (step S32). This operation is the same as step S24 shown in FIG.
[0112]
Next, the CPU 4 determines whether or not the read logical block address is “all 1”, that is, m−1 (step S33). As a result, the read logical block address is If it is other than “all 1 (= m−1)” (S33: NO), the flag whose flag number matches the logical block address in the target table is rewritten to “0” (step S34), and the area number is The internal variable d is stored in the physical block address storage area that matches the logical block address (step S35). On the other hand, if the read logical block address is “all 1 (= m−1)” in step S33 (S33: YES), the flag whose flag number matches the logical block address in the target table is set to “ 1 "(step S36). The operations in steps S33 to S36 are the same as steps S25 to S28 shown in FIG.
[0113]
Then, after incrementing the internal variable d (step S37), the CPU 4 determines whether or not the internal variable d matches m (step S38). As a result, if the internal variable d is not m (S38) : NO), the process returns to step S32, and the logical block address is read using the internal variable d or the like. On the other hand, if the internal variable d matches m (S38: YES), the table completion operation is completed, and the process returns to step S14 shown in FIG. The operations of steps S37 and S38 are the same as steps S29 and S30 shown in FIG.
[0114]
As described above, by repeating the loop consisting of step S32 to step S38 until the internal variable d matches m, the incomplete table is completed and the address can be converted.
[0115]
Further, after the completion operation of the table is completed, or in parallel with the completion operation of the table, the write queue 34 is created. That is, one erased block included in the currently accessed zone is selected, and its physical block address is registered in the queue corresponding to the target table among the queues # 0 to # r-1 constituting the write queue 34. Is done.
[0116]
As described above, when the reading of data for the next zone is actually requested before the speculative table update operation is completely completed, it is necessary to perform the above-described table completion operation. The table completion operation can be completed faster than the table update operation shown in FIG. 12 by loading the internal variable d. Therefore, even in the above case, a series of data read operations can be performed at a higher speed than when the corresponding address conversion information is not stored in the address conversion table 31 at all.
[0117]
Next, a data write operation will be described. As described above, the data write operation is divided into a new data write operation and a data overwrite operation. When a data write request is made from the host computer, first, is this a new data write? A determination is made as to whether the data is overwritten.
[0118]
FIG. 15 is a flowchart showing such a determination operation. Such an operation is also performed by the CPU 4 executing the firmware stored in the ROM 6.
[0119]
In the data write operation, when a host address is supplied from the host computer, the CPU 4 first creates a zone address, a logical block address, and a page address based on the host address (step S41). The generation method is as described above. Next, the CPU 4 refers to the management table 32 created in the RAM 5 to determine whether or not the address translation information related to the zone to be accessed is stored in the address translation table 31 (step S42). The determination method is also as described above.
[0120]
As a result, when it is determined that the address conversion information related to the zone to be accessed is stored in the address conversion table 31 (S42: YES), the CPU 4 selects among the flags in the table corresponding to the zone to be accessed. A flag whose flag number matches the logical block address is read (step S43), and by referring to the contents, it is determined whether or not a block corresponding to the logical block address has already been assigned (step S44). This is equivalent to determining whether the data write operation is a new data write operation or a data overwrite operation.
[0121]
As a result, if the read flag is “1 (invalid)” (S44: NO), the block corresponding to the logical block address has not been allocated yet, that is, the write operation of this data is a new data. Since it can be determined that it is a write operation, the new data write operation shown in FIG. 16 is executed. Conversely, if the read flag is “0 (valid)” (S44: YES). Since it can be determined that the block corresponding to the logical block address has already been allocated, that is, the data write operation is the data overwrite operation, the data overwrite operation shown in FIG. 17 is executed. .
[0122]
On the other hand, when it is determined in step S42 that the address conversion information regarding the zone to be accessed is not stored in the address conversion table 31 (S42: NO), the table update operation shown in FIG. 12 is executed. Then, the above steps S43 and S44 are executed.
[0123]
First, a new data writing operation will be described with reference to FIG. Such an operation is also performed by the CPU 4 executing the firmware stored in the ROM 6.
[0124]
In the new data writing operation, the CPU 4 first accesses the write queue 34 and reads the physical block address stored in the corresponding queue (step S51). Here, the corresponding queue refers to a queue having the same number as the table number of the table from which the flag was read out in step S43.
[0125]
Next, the CPU 4 accesses the flash memory 2 based on the zone address, the physical block address read from the write queue 34, and the page address, and is necessary for the corresponding page and the first page (page # 0) of the block. The data is stored (step S52). Here, data to be stored in the corresponding page includes at least user data, and data to be stored in the first page (page # 0) includes at least a logical block address. Among these, the user data is stored in the user area 21 of the corresponding page, and the logical block address is stored in the logical block address storage area 23 of the first page (page # 0) of the block.
[0126]
Then, the CPU 4 updates the contents of the address conversion table 31, the priority link 33, and the write queue 34 (Steps S53, S54, S55). Specifically, for updating the address conversion table 31, the value of the flag whose flag number matches the logical block address in the corresponding table is rewritten to “0 (valid)” and the corresponding physical block address storage area is updated. The physical block address read from the write queue 34 is stored. The update of the priority link 33 is the same as the operation in step S17. Further, the write queue 34 is updated by overwriting the queue with the physical block address of another erased empty block included in the accessed zone.
[0127]
Thus, the new data writing operation is completed.
[0128]
The address conversion table 31, the priority link 33, and the write queue 34 need not be updated in the order shown in FIG. 16, and may be performed in a different order.
[0129]
Next, the data overwrite operation will be described with reference to FIG. Such an operation is also performed by the CPU 4 executing the firmware stored in the ROM 6.
[0130]
In the data overwriting operation, the CPU 4 first accesses the physical block address storage area whose area number matches the logical block address among the physical block address storage areas in the corresponding table, and stores the physical block stored therein. The address is read (step S61). Hereinafter, the physical block address obtained in step S61 is referred to as a “transfer source block address”.
[0131]
Next, the CPU 4 accesses the write queue 34 and reads the physical block address stored in the corresponding queue (step S62). Hereinafter, the physical block address obtained in step S62 is referred to as a “transfer destination block address”.
[0132]
Next, the CPU 4 resets the value of the internal variable e to 0 (step S63), and determines whether or not the value of the internal variable e matches the page address (step S64). As a result, if the value of the internal variable e matches the page address (S64: YES), the flash memory 2 is accessed based on the zone address, transfer destination block address, and page address, and the data required for the corresponding page. Is stored (step S65). Here, the data stored in the corresponding page includes at least user data, and the user data is stored in the user area 21 of the corresponding page. On the other hand, if the value of the internal variable e does not match the page address, “transfer between blocks” is performed (step S66). In inter-block transfer, the content of the page specified by the internal variable e in the block specified by the zone address and the transfer source block address is determined by the internal variable e in the block specified by the zone address and the transfer destination block address. Forwarded to the specified page. When the internal variable e is “0”, the first page (page) of the block specified by the zone address and the transfer destination block address regardless of whether step S65 or step S66 is executed. The logical block address is stored in the logical block address storage area 23 of # 0).
[0133]
Next, after incrementing the internal variable e (step S67), the CPU 4 determines whether or not the internal variable e matches k (step S68). As a result, if the internal variable e is not k, Returns to step S64 to compare the internal variable e with the page address. If the internal variable e matches k, the steps described below are executed. As described above, “k” is the number of pages included in one block. As described above, steps S64 to S68 are repeatedly executed until the internal variable e matches k, whereby the user data given from the host computer is written to a predetermined page of the transfer destination block. Data that is not overwritten and stored in the transfer source block is written to the same page of the transfer destination block.
[0134]
If the internal variable e coincides with k in step S68, the CPU 4 updates the contents of the address conversion table 31, the priority link 33, and the write queue 34 (steps S69 to S71). Such an operation is the same as steps S53 to S55 described above. Therefore, the address translation table 31, the priority link 33, and the write queue 34 need not be updated in the order shown in FIG. 17, and may be performed in a different order.
[0135]
Then, the CPU 4 erases the block specified by the zone address and the transfer source block address (step S72), and the series of data overwrite operations is completed.
[0136]
As described above, in the present embodiment, only the address translation information related to a part of the blocks is expanded in the address translation table, and in response to a request for reading data from a certain zone, the next zone Since the creation of the address translation information for the zone is started, it is not necessary to create the address translation information for the zone from the beginning even when access to the next zone is actually requested. That is, in the conventional flash memory system, when the address conversion information related to the next zone is not stored in the address conversion table, when access to this zone is requested, all the blocks constituting this zone are transferred. On the other hand, it is necessary to create the address conversion information from the beginning by performing reading, but in the present embodiment, it is not necessary to create the address conversion information from the beginning, so the period of the BUSY state can be shortened. For this reason, it is possible to read data from consecutive host addresses, which is often required during actual use, at high speed, effectively reducing the performance while saving the capacity of the address translation table. It becomes possible to suppress.
[0137]
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.
[0138]
For example, in the above embodiment, whether or not the address conversion information related to the next zone is stored in the address conversion table 31 is always determined at the time of data reading (step S18). You can do it only below. For example, such a determination may be made only when the corresponding logical block address of the data reading target block is greater than or equal to a predetermined value, and may be omitted when the corresponding logical block address is less than the predetermined value. If such a condition is provided, speculative table creation will not be performed earlier than necessary, so the contents of the table currently stored in the address translation table 31 may be unnecessarily discarded. Can be lowered. Therefore, in this case, it is preferable that the predetermined value of the corresponding logical block address serving as a threshold value is determined in consideration of the time required for table creation.
[0139]
In the present invention, the means does not necessarily mean a physical means, but includes cases where the functions of the means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.
[0140]
The present invention can be realized as a PC card based on a unified standard published by PCMCIA (Personal Computer Memory Card International Association). Furthermore, in recent years, with the development of high integration technology of semiconductor elements, more compact miniaturized memory cards such as “CompactFlash” proposed by CFA (CompactFlash Association) and “MMC (MultiMediaCard)” proposed by MultiMediaCardAssociation. The present invention can be applied to “Memory Stick” proposed by Sony Corporation and “SD Memory Card” proposed by Matsushita Electric Industrial Co., Ltd.
[0141]
【The invention's effect】
As described above, according to the present invention, it is possible to effectively suppress a decrease in performance while saving the capacity of the address conversion table. In addition, in the present invention, since the speculative creation of the address translation information is performed during the period in which the controller is originally waiting, this work does not degrade the performance of the flash memory system.
[0142]
Therefore, the present invention is particularly effective when the period during which the controller is originally waiting is long, for example, when the operation of the host computer is slow or when the capacity of the FIFO is small.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a configuration of a flash memory system 1 according to a preferred embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing a memory cell 10 in an erased state.
FIG. 3 is a cross-sectional view schematically showing a memory cell 10 in a write state.
FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory 2;
FIG. 5 is a diagram schematically showing a data structure of a redundant area 22;
6 is a diagram showing a data structure of an address conversion table 31. FIG.
7 is a diagram showing a data structure of a management table 32. FIG.
8 is a diagram showing a data structure of a priority link 33. FIG.
9 is a diagram showing a data structure of a write queue 34. FIG.
10 is a flowchart showing a new creation method of an address conversion table 31. FIG.
FIG. 11 is a flowchart showing a data read operation.
FIG. 12 is a flowchart showing a table update operation.
FIG. 13 is a timing chart showing the timing of interrupting / resuming the table update operation when a plurality of pages in which data requested by the host computer is read are targeted.
FIG. 14 is a flowchart showing a table completion operation.
FIG. 15 is a flowchart for determining whether a data write request from the host computer is a new data write or a data overwrite.
FIG. 16 is a flowchart showing a new data writing operation.
FIG. 17 is a flowchart showing a data overwrite operation.
[Explanation of symbols]
1 Flash memory system
2 Flash memory
3 Controller
4 CPU
5 RAM
6 ROM
7 FIFO
10 memory cells
11 P-type semiconductor substrate
12 Source diffusion region
13 Drain diffusion region
14 Tunnel oxide film
15 Floating gate electrode
16 Insulating film
17 Control gate electrode
18 channels
21 User area
22 Redundant area
23 Logical block address storage area
24 Area for storing other additional information
31 Address conversion table
32 Management table
33 Preferred links
34 Write queue

Claims (13)

A memory controller for accessing a flash memory that can be divided into p zones, an address conversion table having r (r <p) tables capable of storing address conversion information related to one zone of the flash memory And preparing address translation information related to a second zone different from the first zone to be accessed in a predetermined table of the address translation table in response to a request for access to the flash memory. A memory controller featuring. The memory controller according to claim 1, wherein the second zone is a zone next to the first zone when viewed from the host side. 3. The apparatus according to claim 1, further comprising means for displaying a priority order of the r tables, wherein the predetermined table is selected from a table having the lowest priority order and a table having the next lowest priority order. Memory controller. The memory controller according to claim 1, wherein the access request is a data read request to a flash memory. A memory controller for accessing a flash memory that can be divided into p zones, an address conversion table having r (r <p) tables capable of storing address conversion information related to one zone of the flash memory In response to the request for access to the first zone of the flash memory, the address conversion information regarding the second zone following the first zone as viewed from the host side is one of the address conversion tables. It is judged whether it is stored in the table. In response to determining that the address conversion information related to the second zone is not stored in any of the address conversion tables, the address conversion related to the second zone is performed on any of the tables. 6. The memory controller according to claim 5, wherein overwriting of information is started. An address conversion table used for conversion from a logical address belonging to an address on the host computer side to a physical address belonging to an address on the flash memory side, and a temporary memory for temporarily storing data read from the flash memory, A memory controller, wherein the contents of the address conversion table are updated during a period in which data stored in a memory is transferred to the host computer. The memory controller according to claim 7, wherein the temporary memory is a FIFO. A flash memory system comprising a flash memory that can be divided into p zones, and a memory controller that accesses the flash memory, wherein the memory controller can store address conversion information relating to one zone of the flash memory An address conversion table having r tables (r <p), and in response to a request for access to the flash memory, address conversion information relating to a second zone different from the first zone to be accessed Is created in a predetermined table of the address conversion table. A flash memory system comprising a flash memory that can be divided into p zones, and a memory controller that accesses the flash memory, wherein the memory controller can store address conversion information relating to one zone of the flash memory An address conversion table having r tables (r <p), and a second following the first zone as viewed from the host side in response to a request for access to the first zone of the flash memory. And determining whether or not address conversion information relating to the zone is stored in any one of the address conversion tables. A method of controlling a flash memory that can be divided into a plurality of zones, the second method following the first zone as viewed from the host side in response to a request for access to the first zone of the flash memory Determining whether address conversion information relating to a second zone is stored in the address conversion table; and if address conversion information relating to the second zone is not stored in the address conversion table, the address conversion table And a step of starting storing address translation information relating to the second zone. A method of controlling a flash memory that can be divided into a plurality of zones, wherein address conversion information relating to the predetermined zone is stored in an address conversion table in response to a request for access to the predetermined zone of the flash memory In response to determining that the address conversion information related to the predetermined zone is stored in the address conversion table, this is complete address conversion information. And a second step of determining whether the address translation information is incomplete or incomplete address translation information. In response to determining that the address translation information is incomplete in the second step, the method further comprises a third step of completing the address translation information by supplementing the incomplete part. The flash memory control method according to claim 12.

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