JP2004063921A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a device isolation structure having proper semiconductor device characteristics, in a manufacturing method for the semiconductor device. <P>SOLUTION: In the manufacturing method for a semiconductor device, a semiconductor substrate, with an insulating film taken as a mask, is etched using a gas comprising HBr and CHF3, and a reaction product with the semiconductor substrate is deposited gradually on a mask side wall, to form a trench having sufficient radius on the upper end of the trench. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a trench in a semiconductor substrate using plasma.
[0002]
[Prior art]
With the increase in the degree of integration of semiconductor elements, it has become essential to reduce the element separation interval by a trench isolation technique as an element isolation technique of a semiconductor device. According to the trench isolation technique, a trench is formed on a semiconductor substrate. If the junction between the top surface of the semiconductor substrate and the sidewall of the trench and the bottom of the trench has a linearly joined shape, electric field concentration occurs at the junction (end). It is known to happen. This may be caused by a crystal defect at the end portion, an uneven thickness of the pad oxide film, or the like. As a solution, it has been proposed to make the upper end and the lower end of the trench round.
[0003]
For example, in Japanese Patent Application Laid-Open No. 2001-345375, the upper end of the trench is rounded using HBr and CF4 as reactive gases with the resist mask left.
[0004]
[Problems to be solved by the invention]
As described above, when processing a semiconductor substrate using a resist as a mask for rounding the upper end portion of the trench, in consideration of the possibility that contamination of the semiconductor substrate from the resist affects element characteristics, In some cases, the insulating film is opened using the resist as a mask, and then the resist is removed, and the semiconductor substrate is trenched using the insulating film as a mask. However, in this case, it is difficult to form a sufficient roundness at the upper end portion of the trench by using an etching gas that expects a reaction product with the resist.
[0005]
An object of the present invention is to solve the above-described problem, remove the resist after opening it using a resist as a mask, and process a sufficiently large roundness at the upper end of the trench of the semiconductor substrate using the insulating film as a mask. A method for manufacturing a semiconductor device is provided.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a vacuum vessel and a means for generating plasma therein, a sample table on which a sample to be surface-processed by the plasma is installed, and a high-frequency voltage applied to the sample table. Using a surface processing apparatus including a power supply, while etching the semiconductor substrate using a mixed gas of HBr gas and CHF3 gas on the semiconductor substrate using the insulating film as a mask, the reaction product is attached to a pattern side wall, and the deposition is performed. The purpose of the present invention is to form a sufficiently large roundness at the upper end portion of the trench by microetching the formed sidewall.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
[0008]
FIG. 1 is a diagram showing details of a plasma generation unit of the plasma processing apparatus. This embodiment is an example in which UHF waves and a magnetic field are used as means for generating plasma. In FIG. 1, reference numeral 1 denotes an antenna for introducing a UHF wave, 2 denotes a solenoid coil for generating a magnetic field, 3 denotes a UHF wave transmission window (for example, a quartz flat plate), 4 denotes a vacuum vessel, and 5 denotes a sample on which a wafer as a sample is placed. The table, 6 is a drive mechanism for moving the sample table up and down, 7 is a high frequency power supply for applying a high frequency bias voltage to the sample table during plasma processing, for example, etching, and 8 is electrostatically attracting a wafer placed on the sample table. Is a power supply for electrostatic attraction. An earth electrode 9, which is a member having a ground potential, is arranged near the sample stage 5, which is an electrode, inside the vacuum vessel 4. The ground electrode 9 is at a ground potential and is mounted inside the vacuum vessel 4 and has a function of ensuring electrical conductivity between the vacuum vessel 4 and the plasma 10.
[0009]
In the above-described apparatus configuration, when etching a wafer (sample), a process gas is introduced into the vacuum chamber 4 which is depressurized by a vacuum pump (not shown) and a turbo molecular pump (not shown). The pressure inside the vacuum vessel is regulated by a variable valve (not shown), and a UHF wave is introduced from the antenna 1.
[0010]
Electrons in the process gas are efficiently given energy by the action of the UHF wave introduced from the antenna 1 and incident through the UHF wave transmitting window 3 and the magnetic field of the solenoid coil 2 wound outside the vacuum vessel 4, A high-density plasma 10 is generated by electron cyclotron resonance (hereinafter abbreviated as “ECR”). After the plasma 10 is generated, a DC voltage for causing the wafer to be attracted to the sample table 5 is output from the electrostatic attraction power supply 8. After the wafer is attracted to the sample table 5, a high frequency bias voltage is further output from the high frequency power supply 7 to start the process.
[0011]
FIG. 2 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention using the device of FIG.
[0012]
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
[0013]
As shown in FIG. 2, the resist 15 is already patterned according to the exposure area. Using the patterned resist 15 as a pattern, a mask made of the pad oxide film 12 and the silicon nitride 11 was etched by a dedicated etching apparatus. Then, after the resist was removed by another ashing apparatus, the silicon substrate 13 was etched by using the above-described etching apparatus or another etching apparatus, using a mixed gas containing CHF3 and HBr as an etching gas.
[0014]
The etching conditions were such that the pressure was 2.0 Pa, the gas flow ratio of HBr / CHF3 was about 5/1 (the ratio of the amount of CHF3 gas to the amount of HBr gas was about 20%), and the reaction products in the wafer surface were changed. For control, O2 gas was added at about 3 mL / min, and the first etching was performed for about 15 seconds. Thereafter, a second etching was performed using CL2, O2, and HBr gases to form a main trench portion.
[0015]
By the first etching, a reaction product composed of the silicon substrate 13 and the etching gas gradually adheres to the side surface of the mask as a sidewall 14. At this time, since the silicon substrate 13 is anisotropically etched, the silicon substrate 13 is finished to have a forward taper.
[0016]
The shape of the forward taper can be controlled by the added O2 gas, the total gas flow rate, the pressure, and the like.
[0017]
After that, element isolation is formed by second etching. At this time, the side wall 14 attached by the first etching is also slightly etched, so that the tip protruding into the element isolation region is also etched, and is smoothly connected to the second etching portion.
[0018]
If the tip protruding into the element isolation region is not to be greatly etched, a mixed gas containing HBr, O2, and CF4 can be used as a condition for forming the main trench portion.
[0019]
Next, a case in which the tip protruding into the element isolation region is to be largely etched will be described with reference to FIG.
[0020]
The difference between the embodiment of FIG. 3 and the embodiment of FIG. 2 is that the first etching time is reduced from about 15 seconds to about 5 seconds (a wafer bias of about 100 W is not changed) and the wafer bias is reduced from about 100 W to the embodiment of FIG. This is an embodiment in which the power is reduced to about 20 W and the etching is performed for about 10 seconds. By using such etching conditions and etching steps, it is possible to change the angle of the taper and aggressively round.
[0021]
Further, since the lower end of the trench needs to be sufficiently rounded, it is also possible to adjust the power of the high-frequency power source and to etch the bottom of the trench under conditions using HBr, O2, and CF4 gas.
[0022]
Next, a case where it is desired to perform etching for rounding the bottom surface of the trench portion will be described with reference to FIG.
[0023]
As compared with the embodiment of FIG. 4 where the desired trench depth can be obtained from about 80% to 90%, the wafer bias can be reduced from about 100 W to about 20 W as described above, and rounded by etching.
[0024]
As described above, according to the present example, a sufficient roundness could be formed at the upper end of the trench formed in the semiconductor substrate without relying on the deposition and thermal oxidation, which are steps other than the etching of the semiconductor substrate.
[0025]
Although the present embodiment has been described with respect to the case where UHF waves and magnetic fields are used as means for generating plasma, the present invention is not limited to this structure. In other words, the present invention is applicable not only to an ECR plasma type apparatus but also to a semiconductor device using another type of plasma such as RF plasma.
【The invention's effect】
According to the present invention, after opening using a resist as a mask, the resist is removed, and the semiconductor substrate using the insulating film as a mask is etched while attaching a reaction product to a mask side wall, so that a sufficient amount is formed at the upper end of the trench. Roundness can be formed.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing an etching apparatus used for explaining an embodiment of the present invention.
FIG. 2 is an essential part cross-sectional view of the semiconductor substrate for explaining the embodiment of the present invention.
FIG. 3 is an essential part cross-sectional view of a semiconductor substrate for explaining another embodiment of the present invention.
FIG. 4 is an essential part cross-sectional view of a semiconductor substrate for explaining another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Antenna, 2 ... Solenoid coil, 3 ... UHF wave transmission window, 4 ... Vacuum container, 5 ... Sample stage, 6 ... Sample stage drive mechanism, 7 ... High frequency power supply, 8 ... Electrostatic adsorption power supply, 9 ... Earth electrode, 10 plasma, 11 silicon nitride, 12 pad oxide film, 13 silicon substrate, 14 sidewall

Claims (12)

A step of forming a multilayer film including an insulating film on a semiconductor substrate, a step of patterning a resist applied on the multilayer film to form a resist mask, and a step of etching the multilayer film with the resist mask; A method of manufacturing a semiconductor device, comprising: a step of removing the resist mask after the etching; and a step of performing trench processing of a semiconductor substrate using the multilayer film from which the resist has been removed as a mask. 2. The method according to claim 1, wherein said multilayer film comprises at least a silicon nitride film and a silicon oxide film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said multilayer film includes polycrystalline silicon or amorphous silicon (amorphous silicon). 2. The method for manufacturing a semiconductor device according to claim 1, wherein the gas for processing the semiconductor substrate includes a halogen-based reaction gas (e.g., CHF3, CxFy, F2, HF, Cl, HCl, HBr, HI, etc.). Semiconductor device manufacturing method. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a desired roundness on an upper end portion of the trench in a process of processing the semiconductor substrate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in a process of processing the semiconductor substrate, a reaction product comprising at least a semiconductor substrate and a reaction gas is attached to a side portion of the multilayer film, thereby forming roundness at an upper end portion of the trench. A method of manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the process of processing the semiconductor substrate, a trench upper portion of the semiconductor substrate is rounded using a reaction gas containing hydrogen. . 8. The method for manufacturing a semiconductor device according to claim 1, wherein a reaction product, a gas type, a gas flow rate, and the like are controlled by the rounding of the upper portion of the trench or the rounding of the bottom of the trench. A method for manufacturing a semiconductor device, wherein desired rounding is performed. After forming a multilayer film including an insulating film on a semiconductor substrate, patterning a resist to form a resist mask, etching the multilayer film, then removing the resist mask, and removing the resist mask from the multilayer. A method of manufacturing a semiconductor device, wherein trench processing of a semiconductor substrate is performed using a film as a mask. Forming a multilayer mask layer having an opening corresponding to an element isolation region on the semiconductor substrate, and etching the semiconductor substrate using a mixed gas containing CHF3 and HBr using the multilayer mask layer as a mask; 1. A method of manufacturing a semiconductor device, comprising: an etching step of (1); and a second etching step of etching the semiconductor substrate using a mixed gas containing CL2, O2, and HBr using the multilayer mask layer as a mask. Method. 11. The method of manufacturing a semiconductor device according to claim 10, wherein in the process of processing the semiconductor substrate, the mixed gas ratio including CHF3 and HBr is 1: 5, and the mixed gas ratio including CL2, O2, and HBr is: A method of manufacturing a semiconductor device, wherein the ratio is 5: 1: 20. Forming a mask layer having an opening corresponding to an element isolation region on a semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, and forming an upper end portion of the trench in a tapered shape; Etching the semiconductor substrate using the layer as a mask to form a main trench portion.

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