JP2004062578A - Multiphase output clock generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems wherein when an existing PLL/DLL circuit needs a fine phase, if more delay circuits are used, the delay circuits in N-stage design each provide such a delay of 1/N × 360° as becomes smaller for a larger N value, and a higher clock frequency needs a more complicated design, and if an interpolator serving for fine phase division is used, a low range of input frequency needs a large internal load capacity, which leads to degradation of a characteristic and weakness to power fluctuation. <P>SOLUTION: For giving an input of high frequency to an interpolator, a multiphase output oscillator is used in the preceding stage, so that an arbitrary phase output is possible. The use of a phase shifter can facilitate the design of an internal configuration. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to the field of a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop), and more particularly to a high-resolution arbitrary phase clock using an interpolator that inputs a clock generated by a multi-phase output multiplying PLL. The present invention relates to a configuration in which a shift register is used as a feedback clock frequency dividing circuit inside a PLL / DLL circuit capable of outputting data.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, PLL / DLL circuits have been used in all situations in which data is transferred between chips and macros by a clock. However, in recent years, problems related to clock skew due to an increase in clock frequency and diversification of transfer modes have increased the number of devices that require a different phase relationship between a clock on a data transmission side and a clock on a data reception side. However, a general conventional circuit as shown in FIG. 18 does not have a mechanism for arbitrarily selecting an output phase and has a fixed output phase, so that even fine tuning can be performed after siliconization. If the output phase must be shifted, the design must be performed again. If it is desired to output a different phase, it is necessary to redesign a new macro in accordance with the target phase. A conventional circuit as shown in FIG. 18 has four stages of delay circuits having the same configuration, to which a reference clock 100 is input. The phase after all the delay circuits are output is set to the phase of the original reference clock. By performing the matching operation, the total delay value becomes one cycle of the reference clock. As a result, the phase after passing through one stage of the delay circuit has a phase delayed by 90 degrees with respect to the reference clock 1, and the control circuit B17b operates so that the phase of the feedback clock 110 matches the phase of the 90 degrees. The delay value of the delay circuit 18b is controlled. At this time, if the control value of the delay circuit 18b is passed to the slave DLL side in a state where the phases are matched, a plurality of slave DLLs can output the same 90-degree phase.
[0003]
[Problems to be solved by the invention]
In the above-mentioned conventional PLL / DLL circuit, however, if 180 ° is required instead of 90 °, a mechanism capable of selecting 180 ° by an external terminal is provided in advance, or only 180 ° is supported. In this case, the phase after passing through the second stage of the delay circuit is used. Further, for example, when 45 degrees is required, the configuration of the delay circuit needs to be 8 × n stages (n is an integer), and when a finer phase is required, the delay circuit 18b needs to be increased. Assuming that the number of stages of all the delay circuits is N, the delay per stage of the delay circuit 18b is 1 / N × 360 °. As N increases, the delay value per stage decreases as the N increases, and the clock frequency decreases. Obviously, the higher is the more difficult the design is. With such a configuration, it is difficult to obtain an arbitrary output phase every several degrees. Also, when using an interpolator that performs fine phase division, it is a well-known fact that the load capacity required internally becomes large in the range where the input frequency is low, and that the characteristics are deteriorated and the power supply is vulnerable. is there.
Therefore, in the present invention, in order to provide a high-frequency input to the interpolator, an arbitrary phase output is enabled by using a multi-phase output oscillator at the preceding stage, and by using a phase shifter in its internal configuration. Another major feature is that the design is easy.
[0004]
[Means for Solving the Problems]
A multi-phase output clock generation circuit according to the present invention includes: a multi-phase output oscillation circuit that supplies an output clock to an interpolator;
A reference 0-phase output and the interpolator having a mechanism capable of outputting an arbitrary X-phase output, which can be set and controlled by an external terminal;
An external terminal for setting an arbitrary Y phase with respect to the reference clock, outputting a control signal for setting the arbitrary X phase output with respect to the multiplied clock to the interpolator, and simultaneously performing the number of phase shifts of the phase shifter and A first control circuit that outputs a select signal for selecting input of phase shift data;
A frequency divider that divides the reference 0-phase output from the interpolator and sets a frequency division ratio;
The frequency-divided clocks of two different phases from the frequency divider are input to the phase shift data input of the phase shifter, and the arbitrary X-phase output clock is input to the phase shift clock input from the interpolator. A phase shifter having a mechanism for selecting the number of shifts for the phase shift clock;
A first phase comparator that compares the phase of the divided output of the frequency divider with the reference clock and controls the oscillation frequency for the multi-phase output oscillation circuit;
A second phase comparator that outputs the X phase via the phase shifter as an output as a reference delay of a delay circuit;
A second control circuit for adjusting a delay value of the reference clock delay circuit;
And generating a feedback clock having a different X phase from the reference clock.
Further, a delay circuit control set value is externally output from the second control circuit.
2. The multi-phase output clock generation circuit according to claim 1, wherein a plurality of slave DLLs for the master DLL are connected to the master slave.
In addition, a phase comparator newly provided with a clock obtained by extracting the output from the phase shift circuit once in the number of times of shifting is provided so that the delay value of the newly provided delay circuit is in phase with the reference clock. By performing phase matching in the third control circuit, it is possible to set an output having a different phase by one cycle with respect to the multiplied clock.
Further, the present invention is characterized in that the delay circuit is omitted and the device is used as a frequency synthesizer capable of outputting an arbitrary phase.
The X-phase output is output from an external terminal.
Further, the selector circuit has a mechanism capable of outputting a new X2 phase which is a phase that can be controlled independently of the 0 phase and the X phase from the interpolator. It is characterized in that output or selection can be made.
[0005]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described with reference to the drawings. FIG. 1 shows a DLL configuration example as one embodiment of the present invention. This DLL has a multiphase output oscillation circuit 10, an interpolator 11, a frequency divider 12, a phase shifter 15, phase comparators 13 and 16, a control circuit A14, and a control circuit B17. The output clock 120 from the multi-phase output oscillation circuit 10 is supplied to the interpolator 11. The interpolator 11 has a mechanism capable of outputting a reference 0-phase output 130 and an arbitrary X-phase output 140 that can be set and controlled by an external terminal. The control circuit A14 has an external terminal for setting the Y phase with respect to the reference clock 100, and outputs a control signal 190 for setting the X phase output with respect to the multiplied clock to the interpolator. At the same time, the control circuit A14 outputs the number of phase shifts of the phase shifter and the select signal 250 for selecting the input of the phase shift data. The zero-phase output 130 from the interpolator 11 is frequency-divided by the frequency divider 12. The frequency divider 12 has a mechanism that can set the frequency division ratio. The phase comparator 13 compares the signal of the reference clock 100 via the delay element 20 having the same delay time as the divider and the phase shifter with the phase of the first divided output 170 of the divider 12. Based on the phase comparison result 180, the oscillation cycle is controlled inside the multi-phase output oscillation circuit 10.
In the case where the frequency division ratio is set to 2 in the frequency divider 12, the multi-phase output oscillation circuit 10 controlled by the phase comparison result 180 performs double-frequency oscillation. When N division is set, the multi-phase output oscillation circuit performs N-multiplied oscillation, and the setting of the N division determines the oscillation cycle of the PLL. By these operations, the reference clock and the 0-phase output clock have the same phase, and a desired oscillation cycle can be obtained. The X-phase output 140 set by the control circuit A14 is output from the interpolator with respect to the 0-phase output 130 obtained here. The X phase obtained here becomes a reference delay of the delay circuit 18, and is input to the second phase comparator 16 via the phase shifter 15.
Here, referring to FIG. 2, an example of the configuration of the frequency divider 12 of FIG. 1 is shown. That is, there is a mechanism for selecting the frequency-divided clock Fn by an external N-frequency division select signal so that the frequency-divided clock can be output in the same cycle as the reference clock 100 with respect to the frequency-divider input clock. , Any first divided output 170 is possible. In addition, a second frequency-divided output 171 having a phase which is earlier than the frequency-divided output by 180 degrees in terms of an input clock is provided. That is, the fractionator 12 has a divided output clock having two different phases, that is, a first divided output 170 and a second divided output 171 that is earlier by an input clock half cycle. The two different frequency-divided clocks are input to a phase shifter.
Here, referring to FIG. 3, the phase shifter 15 of FIG. 1 is configured as follows. It has two phase-shift data inputs, a first frequency-divided output 170 and a second frequency-divided output 171. Either of the two phase-shift data is selected by a select signal 250 from outside the phase shifter. Have a mechanism that can do it. Further, there is a mechanism for selecting how many times the phase shift data selected here is shifted with respect to the phase shift clock. The frequency-divided clocks of two different phases from the frequency divider 12 are input to the phase shift data of the phase shifter. An X-phase output clock is input from the interpolator to the phase shift clock. By shifting the selected phase shift data using the phase shift clock, a reference clock for the phase comparator 16 is generated. By adjusting the delay value of the reference clock 100 in the delay circuit 18 to the reference clock, a feedback clock 110 having a different X phase from the reference clock 100 is generated. The interpolator 11 shown in FIG. 1 is also described in Japanese Patent Application Laid-Open No. 2001-273048, is well known to those skilled in the art, and the detailed configuration is omitted.
Hereinafter, the operation of this embodiment will be described. The multi-phase output oscillation circuit 10 such as a PLL starts multi-phase output oscillation. The oscillation frequency of the multiphase output 120 is not stable in the initial stage of oscillation. This multiphase output 120 is supplied to the interpolator 11. If the output of the earliest phase of the interpolator 11 is defined as a zero-phase output 130, the zero-phase output 130 is input to the frequency divider 12, and the frequency divider 12 sets the frequency division ratio to a set value. Divided. Now, assuming that the setting of frequency division by 4 is selected in the frequency divider 12, the 0-phase signal / 4-frequency signal is input to the phase comparator 13 and compared with the reference clock 100. The phase comparison result 180 in the phase comparator 13 is returned to the multi-phase output oscillation circuit 10, and the oscillation of the multi-phase output oscillation circuit 10 is controlled. Eventually, the oscillation is stabilized when the quadrupled output is obtained, and the multi-phase output 120 and the zero-phase output 130 have a quadrupled frequency with respect to the reference clock 100. At this time, the phase of the 0-phase output 130 is the same as that of the reference clock 100.
FIG. 4 shows a timing chart in the case of quadruple output and eight-phase output. The eight-phase clock having continuous continuous phase intervals of the multi-phase outputs 120P1 to 120P8 shown in this timing chart is further divided in detail by the interpolator 11, and more detailed phases having the same phase interval can be obtained. This will be described with reference to a timing chart of FIG. For example, in a case where the interpolator 11 divides two adjacent phases into 16 parts, it is possible to output different phases of 4 times × 8 phases × 16 divisions = 512 phases with respect to the reference clock 100. Taking the case where the polyphase output 120P1 and the polyphase output 120P2 are divided into 16 as an example, the 0-phase output 130 is output with a delay of δt with respect to the polyphase output 120P2. Further, an output that is one phase later than the zero phase is output with a delay of (δt + T / 512) with respect to the multiphase output 120P2. Further, the frequency divider 12 has a frequency-divided output clock having two different phases, that is, a first frequency-divided output 170 and a second frequency-divided output 172 that is earlier by an input clock half cycle. FIG. 6 shows a timing chart of the frequency divider 12 during the divide-by-4 operation.
Next, details of the operation when an arbitrary Y phase out of 512 phases is selected with respect to the reference clock 100 by the Y phase designation external terminal 160 will be described. First, the case where Y = 64 will be specifically described with reference to FIG. In the multi-phase output oscillation circuit, a quadrupled clock is output, and each multiplied clock is equally divided into 128 phases. Here, since 64 phases with respect to the reference clock are values that do not exceed one cycle of the multiplied clock, the phase is also 64 phases with respect to the multiplied clock. Therefore, a 64/512 phase output with respect to the reference clock 100 is obtained by shifting the phase once with the 64 phase output from the interpolator.
Further, a case where Y = 192 will be described with reference to FIG. The 192 phases with respect to the reference clock correspond to one cycle + 64 phases in the multiplied clock. That is, the phase is a phase shifted by one phase of the multiplied clock from the phase of Y = 64. Therefore, the output of the 192/512 phase with respect to the reference clock 100 is obtained by performing the phase shift twice with the 64 phase output from the interpolator.
In FIG. 9, when the Y phase is selected by the Y phase designation external terminal 160, since 128 phases are included in one cycle of the multiplied clock, the number S of shift clocks in the multiplied clock is divided (Y / 128). ) +1. Then, the interpolator outputs Y-128 × division (Y / 128) = X phase output 140 with respect to the multiplied clock. This corresponds to the X phase output 140 in FIG. Again, the Y phase is a value set with respect to the reference clock cycle. On the other hand, since the interpolator interpolates the multiplied multiphase output 120 generated from the reference clock 100, the reference of the interpolated output is the multiphase output oscillation 120, and the X phase is one cycle of the reference clock. Within, the number of multiplied clocks appears.
Using the X-phase output 140 obtained up to this point, the phase shifter 15 uses the frequency-divided output selected from the first frequency-divided output 170 and the second frequency-divided output 171 of the frequency divider 12 as described above. Is shifted by the number of shifts S. With this operation, the signal 200 to the phase comparator 16 is generated. Which of the first divided output 170 or the second divided output 171 from the frequency divider 12 in the phase shifter 15 is selected as phase shift data depends on only the Setup value with the X phase output 140. This value is determined only by the setting of the Y-phase designation external terminal 160. This value is output as the select signal 250 by the control circuit A14. This detailed description will be described with reference to the timing chart of FIG. The first frequency-divided output 170 and the second frequency-divided output 171 have phases different from each other by a half cycle (180 degrees). If the SETUP time of the second divided output 171 with respect to the X phase output 140 when 0 Degree is selected is designed to be the strictest, when the phase of the X phase output 140 advances, the second The margin for the divided output 171 becomes large. Further, when the phase of the X-phase output 140 has advanced to 180 Degree, the HOLD of the first frequency-divided output 170 with respect to the X-phase output 140 becomes stricter, and the first frequency-divided output 171 is delayed by 180 Degrees from the second frequency-divided output 171. Is used as the phase shift data. Since the second frequency-divided output 171 has a phase delayed by 180 degrees from the first frequency-divided output 170, the SETUP condition is satisfied by the phase of the X-phase output 140 delayed by 180 degrees. Similarly to the first divided output 170, when the signal reaches 360 degrees, the HOLD of the second divided output 171 with respect to the X-phase output 140 becomes strict, so the first divided output 170 is used as phase shift data. In summary, the second frequency-divided output 171 is set as the phase shift data from 0 to less than 180 degrees, and the first frequency-divided output 170 is used as the phase shift data from 180 to less than 360 degrees.
Thus, the generated phase shift signal 200 in FIG. 1 is a clock delayed by Y phase with respect to the reference clock. Here, the reference clock 100 is input to the delay circuit 18, and the feedback clock 110 is matched with the phase shift output 200 by the phase comparator 16. At this time, the control circuit B17 controls the delay circuit 18 based on the result of the phase comparison performed by the phase comparator 16. Here, since the phase shift signal 200 is a clock delayed by Y phase with respect to the reference clock, it is understood that the feedback clock 110 also has a phase delayed by Y phase with respect to the reference clock 100. Here, the effectiveness of the phase shifter 15 will be described. In the case where a general frequency divider similar to the frequency divider 12 is used instead of the phase shifter 15, the X phase output 140 from the interpolator is obtained by multiplying the reference clock. On the other hand, there are as many clock edges as the number of multiplied clocks. In the case where the quadrupled output is divided by four, there are four different phases with respect to the reference clock due to the division start edge. However, since only one of the four phases is desired by the external setting, the frequency division start edge is only one of the four phases. It is difficult to easily set the division start edge. As a means, the division start timing signal can be generated by counting the number of clocks from the rising edge of the reference clock. If the circumference start edges are close or overlap, the frequency division start timing signal may be erroneous. If an error occurs, a phase shifted by one phase of the multiplied clock is output, so that the influence is large. Therefore, as described above, a desired phase can be safely and easily obtained by using a phase shifter instead of a frequency divider. FIG. 11 shows a timing chart in the case where a 270-degree phase output is desired.
[0006]
In the above-described embodiment, the multi-phase output oscillation circuit 10 in the case of quadruple output and eight-phase output has been described. However, the number of multiplications and the number of output phases are not limited to this. Further, the description is made by limiting the number of divisions of the interpolator to 16, but the number of divisions is a value determined by the resolution of the interpolator, and is not particularly limited to 16.
Next, as a second embodiment, the basic configuration is as described above. As shown in FIG. 12, a delay circuit control set value 240 is externally output from the control circuit B17, thereby forming a master DLL. Operable. The master DLL is configured to provide a delay circuit control set value for outputting a Y phase with respect to a reference clock to a slave DLL 2 having the same delay circuit 18 according to a delay circuit control set value. Will be delayed by Y phase. That is, the same delay is obtained on the slave side by the delay set on the master side.
As the third embodiment, the basic configuration is the same as that of the second embodiment, but the number of slave DLLs for the master DLL is not limited to one, and a plurality of slave DLLs can be controlled. By connecting a slave DLL as shown in FIG. 13 to a plurality of master slaves as shown in FIG. 14, it is possible to supply the same control setting value to a plurality of slave DLLs. DLL having a delayed clock output of
As a fourth embodiment, as shown in FIG. 15, a newly provided delay circuit is provided in a phase comparator 16-2 newly provided with a clock obtained by taking out the output from the phase shift circuit once at an earlier shift count. By performing the phase adjustment in the control circuit B17-2 so that the delay value of 18-2 matches the phase with respect to the reference clock 100, it is possible to set the output whose phase differs by one cycle from the multiplied clock. Become. Thus, by having a plurality of outputs from the phase shifter, a plurality of slave DLLs having different phases can be used for one master DLL. In FIG. 15, two phases are output from the phase shifter. However, it is naturally possible to extract phases having different numbers of multiplied clocks at the maximum.
As a fifth embodiment, as shown in FIG. 16, it is possible to use a frequency synthesizer that can output an arbitrary phase without mounting the delay circuit 18. In addition, even when the delay circuit 18 is mounted, the operation is naturally possible by outputting the X-phase output as an external terminal.
As a sixth embodiment, a configuration as shown in FIG. 17 can be considered. This is provided with a mechanism that can output a new X2 phase signal 260 from the interpolator. This is a phase that can be controlled independently of the X0 and X phases. A feature of this embodiment is that the selector circuit 21 can select whether the feedback clock 110 is the X2 phase signal 260 via the frequency divider 20 or the delay circuit output 230. When the X2 phase signal 260 is selected, it operates as a PLL having an arbitrary multi-phase output. On the other hand, when the delay circuit output 230 is selected, it operates as a DLL. Therefore, with such a configuration, exclusive use is possible as a master DLL and as a multi-phase output PLL. Therefore, if it is mounted on a master such as an ASIC or an FPGA, either of them can be used. It becomes possible and can be used for general purposes.
[0007]
【The invention's effect】
As described above, since the present invention has a configuration in which an arbitrary phase can be selected by external setting, it is possible to obtain an arbitrary phase with respect to a reference clock and setting information of a delay circuit in the phase by the external setting. it can. Therefore, the present invention can be used for all PLLs and DLLs that desire a clock having an arbitrary phase different from the reference clock. Next, when the X-phase output clock is input to the phase comparator 2, a design can be performed without worrying about the division start timing by providing a phase shift circuit instead of a frequency divider. It has become easier. Also, in a circuit using a frequency divider instead of a phase shifter, if the division start timing is incorrect, a phase shift occurs in units of one cycle of the divided clock. Has a stable phase shift configuration, so that there is also an effect that a phase can be accurately output for a desired phase. It is a known fact that an interpolator exhibits good characteristics at a high frequency input. In the present invention, a high-frequency input is realized by inputting the clock after the multiplication to the interpolator, which is also a usage method utilizing characteristics of the interpolator.
[Brief description of the drawings]
FIG.
FIG. 1 is a configuration diagram illustrating a configuration of a first exemplary embodiment of the present invention.
FIG. 2
It is a figure showing the example of composition of the frequency divider in a 1st embodiment of the present invention.
FIG. 3
FIG. 2 is a configuration diagram of a phase shifter according to the first embodiment of the present invention.
FIG. 4
4 is a timing chart in the case of quadruple output and eight-phase output in one embodiment of the present invention.
FIG. 5
5 is a timing chart in a case where an interpolator divides two adjacent phases into 16 parts according to the embodiment of the present invention.
FIG. 6
6 is a timing chart of the frequency divider at the time of a divide-by-4 operation in one embodiment of the present invention.
FIG. 7
5 is a timing chart according to the embodiment of the present invention.
FIG. 8
5 is a timing chart according to the embodiment of the present invention.
FIG. 9
5 is a timing chart according to the embodiment of the present invention.
FIG. 10
It is a timing chart figure in one embodiment of the present invention.
FIG. 11
5 is a timing chart when a 270-degree phase output is desired in one embodiment of the present invention.
FIG.
FIG. 11 is a configuration diagram when operating as a master DLL according to the second embodiment of the present invention.
FIG. 13
FIG. 14 is a configuration diagram of a slave DLL according to a third embodiment of the present invention.
FIG. 14
FIG. 11 is a configuration diagram of a DLL according to a third embodiment of the present invention.
FIG.
It is a lineblock diagram of a 4th embodiment of the present invention.
FIG.
FIG. 14 is a configuration diagram when functioning as a frequency synthesizer according to a fifth embodiment of the present invention.
FIG.
It is a lineblock diagram in a 6th embodiment of the present invention.
FIG.
FIG. 3 is a configuration diagram of a conventional DLL circuit.
[Explanation of symbols]
1 Master DLL
2 Slave DLL
Reference Signs List 10 multiphase output oscillation circuit 11 interpolator 12 frequency divider 13 phase comparator 13b phase comparator 14 control circuit A
14b Control circuit A
15 phase shifter 16 phase comparator 16b phase comparator 17 control circuit B
17b Control circuit B
Reference Signs List 18 delay circuit 18b delay circuit 19 buffer 20 delay element 100 reference clock 110 feedback clock 120 multi-phase output 120P1 to 120P8 multi-phase output 130 0-phase output 140 X-phase output 160 Y-phase designation external terminal 170 First divided output 171 2 divided output 180 phase comparison result 190 control signal 200 phase shift signal 230 delay circuit output 240 delay circuit control set value 250 select signal 260 X2 phase signal

Claims (7)

A multi-phase output oscillation circuit that supplies an output clock to the interpolator;
A reference 0-phase output and the interpolator having a mechanism capable of outputting an arbitrary X-phase output, which can be set and controlled by an external terminal;
Having an external terminal capable of setting an arbitrary Y phase with respect to a reference clock, outputting a control signal for setting the arbitrary X phase output with respect to a multiplied clock to an interpolator, and simultaneously outputting a phase shift of a phase shifter; A first control circuit for outputting a select signal for selecting the number of times and input of phase shift data;
A frequency divider that divides the reference 0-phase output from the interpolator and sets a frequency division ratio;
The divided clocks of two different phases from the divider are input to the phase shift data input of the phase shifter, and the arbitrary X phase output clock is input to the phase shift clock input from the interpolator. A phase shifter having a mechanism for selecting the number of shifts for the phase shift clock;
A first phase comparator that compares the phase of the divided output of the frequency divider with the reference clock and controls the oscillation frequency for the multi-phase output oscillation circuit;
A second phase comparator that outputs the X phase via the phase shifter as an output as a reference delay of a delay circuit;
A second control circuit for adjusting a delay value of the reference clock delay circuit;
And generating a feedback clock having a different X phase with respect to the reference clock. 2. The multi-phase output clock generation circuit according to claim 1, wherein the second control circuit externally outputs a delay circuit control set value. 3. The multi-phase output clock generation circuit according to claim 1, wherein a plurality of slave DLLs for the master DLL are connected to the master slave. A third phase comparator newly provided with a clock obtained by taking out the output from the phase shift circuit once at the number of times of shifting is used to set the third delay circuit so that the delay value of the newly provided delay circuit matches the phase of the reference clock. 2. The multi-phase output clock generation circuit according to claim 1, wherein an output having a phase different from that of the multiplied clock by one period can be set by performing phase adjustment by said control circuit. 2. The multi-phase output clock generation circuit according to claim 1, wherein the delay circuit is omitted and used as a frequency synthesizer capable of outputting an arbitrary phase. 6. The multi-phase output clock generation circuit according to claim 1, wherein the X-phase output is output from an external terminal. The interpolator has a mechanism capable of outputting a new X2 phase, which is a phase that can be controlled independently of the 0 phase and the X phase. The selector circuit outputs the feedback clock to the X2 phase output or the delay circuit output. 2. The multi-phase output clock generation circuit according to claim 1, wherein the selection can be made.

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