JP2004056882A - Multilevel pwm inverter controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a maximum output voltage value drops to disable the adjusting of a DC voltage balance at a neutral point between the lower side and the upper side, if a fluctuation in the total average value of output terminal voltages of a multi-level PWM inverter controller is suppressed in a PWM conversion output mode in order to reduce a leaking current. <P>SOLUTION: The multi-level PWM inverter controller is equipped with three output terminals, wherein four IGBT transistors are connected in series and the connection point of second and third IGBT transistors, when counted from top, is taken as an output terminal. Two output terminals are connected to a motor 2 while remaining one output terminal is connected to an output line 4 which is not connected to a load. The output terminal connected to the output line 4 is subjected to voltage output operation so that the fluctuation in the total average value of the output voltages from three output terminals is suppressed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multi-level PWM inverter control device that performs variable-speed driving of a motor or the like and system linking.
[0002]
[Prior art]
In the multilevel PWM inverter control device shown in FIG. 2, 5 is a controller, 6 is a DC power supply, 11 and 12 are smoothing capacitors, 101 to 112 are IGBT transistors as switch elements, 201 to 212 are freewheel diodes, and 301 to 306. Indicates an intermediate level output clamp diode.
Assuming that a set of four switches each composed of an IGBT transistor and a freewheel diode connected in anti-parallel are connected in series as one phase and S1, S2, S3, and S4 from the upper side, the upper two switches, S1 and S2, The ON state is a + E state that outputs the positive bus voltage of the DC bus voltage, the middle two switches, the S2 and S3 ON states are the 0 state that outputs the neutral point voltage, the lower two switches, The state in which S3 and S4 are ON is the −E state in which the negative bus voltage of the DC bus is output, and the output voltage is controlled by combining them. FIG. 10 shows the switching pattern of each phase at this time. The phases of the output voltage is V1, V2, V3, but shows this total value is V _123, leakage current flowing to ground via the stray capacitance between the output cable and the ground by the voltage variation of the V ₁₂₃ is appear.
In particular, in recent years, the use of shielded cable lines as output cable lines has been increasing in order to reduce noise emitted from the PWM inverter control device. In this case, there is a problem that a large leakage current is generated for the above-described reason.
In order to suppress such a leakage current, it is necessary to use a common mode choke or an active filter, which has hindered downsizing and cost reduction of the entire device including the PWM inverter control device.
[0003]
As a prior art example for such a problem, there is one disclosed in JP-A-10-23760. FIGS. 11 and 12 show the configuration of this conventional technique.
The prior art focuses on the fact that the three-phase sum of the three-phase sine wave voltage vector is always zero, and the three-phase sum of the PWM converted output voltage can be zero, in other words, the neutral point voltage. And a specific method of generating such a gate signal. Thus, the three-phase sum of the output voltages of the respective phases is always fixed to zero, in other words, to the neutral point voltage, thereby making it possible to suppress the occurrence of leakage current.
[0004]
[Problems to be solved by the invention]
When the three-phase sum of the output voltages of the respective phases is fixed to zero voltage, that is, the neutral point voltage as in the conventional example, the maximum output voltage of the PWM inverter control device is limited to √3 / 2 of the AC input voltage. Problem.
In a general PWM inverter control device, a three-harmonic voltage is superimposed on each phase output voltage to fluctuate the three-phase output voltage in the in-phase mode, thereby enabling the same voltage output as the AC input voltage. However, in the conventional configuration, since the three-phase sum of the PWM conversion output voltage is set to zero, the three-phase output voltage cannot be changed up and down in the in-phase mode. Therefore, the maximum output voltage of the PWM inverter control device is limited. It will be lost.
Further, in the multi-level PWM inverter control device, two DC voltages are provided on the upper side and the lower side on the basis of the neutral point. However, during the operation of the inverter, the two DC voltage balances may be lost. Also in this case, the three-phase output voltage is fluctuated up and down in the in-phase mode to correct the distorted voltage balance.
Therefore, the conventional example has a problem that such a voltage balance correction operation cannot be performed.
There is also a problem that the number of times of switching increases and switch loss increases.
Therefore, the present invention has no limitation on the inverter output voltage, can correct two DC voltage balances, suppresses the fluctuation of the three-phase sum of the inverter output voltage without increasing the number of switching times, and reduces the leakage current. It is an object of the present invention to provide a multi-level PWM inverter control device capable of suppressing the above.
[0005]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, according to the present invention, a switch having a positive bus, a negative bus, and a neutral wire, and comprising a rectifying element connected in anti-parallel with a switching element is connected to the positive bus and the negative bus. And a rectifying element is connected between the neutral point and the connection point between the first and second switches from the upper side of the four switching elements connected in series. Connected in the direction from the neutral line to the connection point of the switch, and among the four switches connected in series, between the connection point of the third and fourth switches from the top and the neutral line A switch element configuration group having a rectifying element connected in a direction in which a current flows from a connection point of the switch to a neutral line, and having a connection point of the second and third switches from the upper side as an output terminal; The terminals are the four series-connected The first state in which the first and second switches are turned on from the upper side to output the voltage of the positive bus, and the neutral state in which the second and third switches are turned on from the upper side. The switch element having three output states: a second state in which the voltage of the line is output, and a third state in which the third and fourth switches from the upper side are turned on to output the voltage of the negative bus. Two configuration groups are connected in parallel to the positive bus, the negative bus, and the neutral wire as first and second switch element configuration groups, and a load is applied from each of the output terminals of the first and second switch element configuration groups. A multi-level PWM inverter control device configured to supply power to
A third switch element group connected in parallel with the positive bus, the negative bus, and the neutral line; a cable line not connected to a load is connected to an output terminal of the third switch element group; The output terminal selects, from among the first, second, and third output states, a state in which the total average value of the output terminal voltages of the first and second switch element configuration groups is closest to the intermediate line voltage. And output it.
Assuming that the output voltage in the first state is + E, the output voltage in the second state is 0, and the output voltage in the third state is −E, each output of the first and second switch element configuration groups is provided. The combination of terminal voltages is
(+ E, 0), (+ E, -E)
(0, + E), (0, -E)
(-E, + E), (-E, 0)
, And the return mode without power supply is (+ E, + E), (0, 0), (−E, −E).
A cable line not connected to a load is connected to the output terminal of the third switch element configuration group, and the cable line is bundled together with the other two cable lines connected to the load. It is installed after being insulated.
In order to suppress the fluctuation of the sum of the output terminal voltages of the first and second switch element groups, the output terminal of the third switch element group is the output terminal of the first and second switch element groups. A state in which the total average value with the voltage is closest to the intermediate line voltage is selected and output. For example, -E for (+ E, 0), 0 for (+ E, -E), -E for (0, + E), + E for (0, -E), 0 for (-E, + E), (-E , 0), + E for (+ E, + E), 0 for (0, 0), and + E for (-E, -E).
By doing so, the total output voltage can be reduced to the fluctuation range of ± E, and the leakage current can be reduced.
[0006]
According to a second aspect of the present invention, in the multilevel PWM inverter control device according to the first aspect, an output terminal of the first switch element group and an output terminal of the second switch element group are simultaneously connected to the second terminal. It is characterized in that the state is No. 1 and that the state is not simultaneously in the third state.
According to the first aspect of the present invention, the output states (+ E, + E), (0, 0), and (-E, -E) in the reflux mode are not particularly limited. Among them, (+ E, + E) and (-E, -E) are prohibited.
Thereby, the output terminal state of the third switch element configuration group is selected such that the total average value of the output terminal voltages of the first and second switch element configuration groups is fixed to the neutral point voltage. Becomes possible. As a result, it is possible to completely suppress the occurrence of leakage current.
[0007]
According to the third aspect of the present invention, four switches each having a positive bus, a negative bus, and a neutral wire, each including a switching element and a rectifying element connected in anti-parallel are connected in series between the positive bus and the negative bus. Connected, and among the four switches connected in series, a rectifying element is provided between the neutral point and the connection point between the first and second switches from the upper side, and the current flows from the neutral line to the switch of the switch. The rectifying element is connected between the neutral point and the connection point between the third and fourth switches from the upper side of the four switches connected in series in the direction in which the current flows to the connection point. A switch element configuration group connected in a direction from the connection point of the switch to the neutral line and having a connection point of the second and third switches from the upper side as an output terminal, wherein the output terminals are connected in series. Of the four switches A first state in which the first and second switches are turned on to output the voltage of the positive bus, and a second state in which the second and third switches are turned on from the upper side to output the voltage of the neutral line. The switch element configuration group having three output states, namely, a second state and a third state in which the third and fourth switches from the upper side are turned on to output the voltage of the negative bus, are referred to as the positive bus. Fourth, fifth, and sixth switch element groups are connected in parallel to the negative bus and the neutral line, and power is supplied from the output terminals of the fourth, fifth, and sixth switch element groups to the load. In a multi-level PWM inverter control device configured to supply
A seventh switch element group connected in parallel to the positive bus, the negative bus, and the neutral line; a cable line not connected to a load is connected to an output terminal of the seventh switch element group; In the first, second, and third output states, the output terminal of the seventh switch element group has a total average value of the output terminal voltages of the fourth, fifth, and sixth switch element groups. It is characterized in that the state closest to the intermediate line voltage is selected and output.
This embodiment is different from the first embodiment in that the number of output phases for supplying power to the load is set to three, and the operation principle is the same as that of the first embodiment.
[0008]
According to a fourth aspect of the present invention, in the multilevel PWM inverter control device according to the third aspect, an output terminal of the fourth switch element group, an output terminal of the fifth switch element group, and the sixth terminal are connected to each other. It is characterized in that the output terminals of the switch element configuration group are simultaneously in the first state, and are not simultaneously in the third state.
This means that the output terminals of the fourth, fifth, and sixth switch element configuration groups all have a reflux mode output (+ E, + E, + E), (0, 0, 0). , (-E, -E, -E), the two states of (+ E, + E, + E) and (-E, -E, -E) are prohibited.
By doing so, the total value of the output voltages can be reduced to the fluctuation range of ± E, and the leakage current can be reduced.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a first embodiment of the present invention.
The multi-level PWM inverter control device 1 in FIG. 1 has a configuration shown in FIG. 2, in which two output terminals of the multi-level PWM inverter control device 1 are connected to the motor 2 and the remaining one output terminal is connected to a load. An output line 4 not connected to the motor 2 is connected, and the output line 4 is bundled together with the other two output lines connected to the motor 2, is insulated near the motor 2, and is fixedly installed.
In FIG. 2, when a set of four switches each including an IGBT transistor and an anti-parallel-connected freewheel diode connected in series is defined as one phase, and S1, S2, S3, and S4 are determined from the upper switch, the upper two S1 ON state of S2 and S2 is a + E state in which the positive bus voltage of the DC bus voltage is output, middle two S2 and S3 are ON states in which the neutral point voltage is output, and two lower S3 states. , S4 are in the -E state in which the negative bus voltage of the DC bus is output, and the output voltage is controlled by combining them. When a three-phase output is obtained, the three sets of outputs are controlled to obtain an arbitrary output voltage. Here, in order to obtain a single-phase output voltage, as shown in FIG. The terminal is connected to the motor 2 as a load.
The third set not connected to the motor 2 performs a switching operation to cancel the voltages of the first and second sets, bundles the output line 4 with the other two output lines, and installs the output line 4 near the connected device. Thereby, the average value of the voltage sum of the connection lines is made closer to or equal to the neutral point voltage to suppress the leakage current.
FIG. 3 shows the switching patterns of the first, second, and third combined phase output terminals.
In FIG. 3, V1, V2, and V3 indicate the first, second, and third combined phase output terminal voltages, and V12 is the first output terminal voltage as viewed from the second output terminal. _{Numeral 123} indicates the total value of the three output terminal voltages.
[0010]
Next, a second embodiment of the present invention will be described. The configuration of the second embodiment is the same as the configuration of FIG. 1 shown in the first embodiment, but in the second embodiment, the + E state and the + E state are simultaneously applied to the first and second set output terminals. There is a constraint that the state will not be -E.
FIG. 4 shows a switching pattern of each of the first, second, and third combined phase output terminals in a state where this restriction is applied.
The switching operation of the third set of output terminals can completely cancel the voltages of the first and second sets due to the addition of the constraint, and can reduce the average value of the voltage sum of the connection lines to the neutral point voltage. And the leakage current is further suppressed.
[0011]
Next, a third embodiment of the present invention will be described. FIG. 5 shows the overall configuration of the third embodiment, and FIG. 6 shows a multi-level PWM inverter control device in the third embodiment.
In the third embodiment, since the three-phase motor 12 is used as a load, the number of output terminals of the multi-level PWM controller 11 is four.
Three of the four output terminals are connected to the motor 12, and the output terminals not connected to the motor 12 perform switching so as to cancel the three output terminal voltages connected to the motor 12, and average the sum of the voltage sums of the output lines. The leakage current is suppressed by bringing the value closer to or equal to the neutral point voltage.
FIG. 7 shows switching patterns of the four sets of output terminals. In FIG. 7 V1, V2, V3 is shows the three output terminal voltage connected to the motor, V4 is shows the output terminal voltage which is not connected to the motor, the solid line waveform indicated by V ₁₂₃₄ wherein four output The dotted line waveform indicated by _V1234 indicates the total value of terminal voltages, and indicates the total value of V1, V2, and V3.
[0012]
Next, a fourth embodiment of the present invention will be described. The fourth embodiment is the same as the configuration of FIG. 5 shown in the third embodiment, except that the three phase output terminals connected to the motor 12 are simultaneously in the + E state or the −E state. There is a restriction that there is no.
FIG. 8 shows a switching pattern of each set output terminal in a state where this restriction is added.
The restriction that the three phase output terminals connected to the motor 12 do not simultaneously enter the + E state or the -E state is that the output voltages of the three output terminals are simultaneously varied in the common mode in the fourth embodiment. It is realized by. Each switching pattern in FIG. 8 is obtained by moving the output voltages of V1, V2, and V3 shown in FIG. 7 by a predetermined voltage toward the −E side in the common mode, and FIG. It is the same.
By the switching operation of the output terminal not connected to the motor 12 due to the restriction, the average value of the voltage sum of the output line can be made closer to the neutral point voltage as compared with the third embodiment, and the leakage current can be reduced. It can be further suppressed.
[0013]
【The invention's effect】
As described above, according to the present invention, in a multi-level PWM inverter control device, the generation of leakage current accompanying the operation of the control device is suppressed, the operation of the device is performed safely, and other devices are not adversely affected. Power supply, and does not require expensive and large-sized devices such as a common mode choke coil and an active filter. Can be corrected, and there is an effect that the number of times of switching is not increased.
[Brief description of the drawings]
FIG. 1 shows an overall configuration of first and second embodiments of the present invention.
FIG. 2 shows a configuration of a multilevel PWM inverter control device according to first and second embodiments of the present invention.
FIG. 3 shows a switching pattern operation of each output terminal according to the first embodiment of the present invention.
FIG. 4 shows a switching pattern operation of each output terminal in a second embodiment of the present invention.
FIG. 5 shows the overall configuration of the third and fourth embodiments of the present invention.
FIG. 6 shows a configuration of a multi-level PWM inverter control device according to third and fourth embodiments of the present invention.
FIG. 7 shows a switching pattern operation of each output terminal according to a third embodiment of the present invention.
FIG. 8 shows a switching pattern operation of each output terminal according to a fourth embodiment of the present invention.
FIG. 9 shows the entire configuration of a conventional general example.
FIG. 10 shows a switching pattern operation of each output terminal of a general example in the related art.
11 shows a configuration example according to JP-A-10-23760 as a conventional technique. [FIG. 12] shows an implementation flow in the configuration example shown in FIG.
1, 11 Multi-level PWM inverter control device 2, 12 Motor 3 Stray capacitance 4 Output line 5 not connected to load 5 Controller 6 DC power supply 101-116 IGBT transistor 201-216 Freewheel diode 301-308 Clamp diode 401 Commercial power supply 402 Rectifier diode Modules 403, 404 Smoothing capacitor 405 Voltage-type PWM converter 406 Induction motor 407 PWM control circuits 501-504 IGBT transistors 505-508 Freewheel diodes 509, 510 Clamp diodes

Claims (4)

A positive bus, a negative bus, and a neutral wire,
Four switches each including a switching element and a rectifying element connected in anti-parallel are connected in series between the positive bus and the negative bus, and among the four switches connected in series, the first and second switches from the upper side A rectifying element is connected between a connection point with a switch and the neutral line in a direction in which a current flows from the neutral line to the connection point of the switch, and a third one of the four switches connected in series from the upper side A rectifying element is connected between the connection point of the fourth and fourth switches and the neutral line in a direction in which a current flows from the connection point of the switch to the neutral line, and the second and third rectifiers are connected from the upper side. A switch element configuration group having a connection point of a third switch as an output terminal, wherein the output terminal turns on a first switch and a second switch from the upper side of the four switches connected in series, and Output the voltage of And a second state in which the second and third switches are turned on from the upper side to output the voltage of the neutral line, and a third state and the fourth switch are turned on from the upper side and the Two switch element configuration groups each having three output states, ie, a third state for outputting a voltage of the negative bus, are provided as the first and second switch element configuration groups for the positive bus, the negative bus, and the neutral wire. A multi-level PWM inverter control device connected in parallel and configured to supply power to a load from the output terminals of the first and second switch element configuration groups,
A third switch element group connected in parallel with the positive bus, the negative bus, and the neutral line; a cable line not connected to a load is connected to an output terminal of the third switch element group; The output terminal selects, from among the first, second, and third output states, a state in which the total average value of the output terminal voltages of the first and second switch element configuration groups is closest to the intermediate line voltage. A multi-level PWM inverter control device, characterized in that it outputs the output. The output terminal of the first switch element configuration group and the output terminal of the second switch element configuration group are simultaneously in the first state, and are not simultaneously in the third state. The multilevel PWM inverter control device according to claim 1, wherein A positive bus, a negative bus, and a neutral wire,
Four switches each including a switching element and a rectifying element connected in anti-parallel are connected in series between the positive bus and the negative bus, and among the four switches connected in series, the first and second switches are arranged from the upper side. A rectifying element is connected between the connection point of the switch and the neutral line in a direction in which a current flows from the neutral line to the connection point of the switch. A rectifying element is connected between the connection point of the fourth and fourth switches and the neutral line in a direction in which a current flows from the connection point of the switch to the neutral line, and the second and third rectifiers are connected from the upper side. A switch element configuration group having a connection point of a third switch as an output terminal, wherein the output terminal turns on a first switch and a second switch from the upper side of the four switches connected in series, and Output the voltage of And a second state in which the second and third switches are turned on from the upper side to output the voltage of the neutral line, and a third state and the fourth switch are turned on from the upper side and the The switch element configuration group having three output states, that is, a third state for outputting the voltage of the negative bus, and fourth, fifth, and sixth switch element configuration groups for the positive bus, the negative bus, and the neutral line. In a multilevel PWM inverter control device, three of which are connected in parallel and configured to supply power to a load from the output terminals of the fourth, fifth, and sixth switch element configuration groups,
A seventh switch element group connected in parallel to the positive bus, the negative bus, and the neutral line; a cable line not connected to a load is connected to an output terminal of the seventh switch element group; In the first, second, and third output states, the output terminal of the seventh switch element group has a total average value of the output terminal voltages of the fourth, fifth, and sixth switch element groups. A multi-level PWM inverter control device for selecting and outputting a state closest to an intermediate line voltage. The output terminal of the fourth switch element group, the output terminal of the fifth switch element group, and the output terminal of the sixth switch element group are simultaneously in the first state, and 4. The multi-level PWM inverter control device according to claim 3, wherein the third state does not occur.

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