JP2004056492A - Image reader - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent invalid data that occur due to the difference in the numbers of pixels of respective shift registers from being written to a memory in an image reader provided with an image sensor consisting of: first and second sensors each with photodetectors arranged in one line; a first shift register for outputting pixel signals to all of the photodetectors of the first sensor and second; and a third shift register for outputting even number and odd number pixel signals of the photodetetors of the second sensor, respectively. <P>SOLUTION: Pixel signals outputted from the first to third shift registers constituting a CCD image sensor 20 in the same transfer clock are selectively obtained with time division through an AFE 75, and the obtained pixel data are sequentially sampled by a data sampling block 44 and stored into the memory 70. The timing of the sampling is controlled in an obtained signal generation circuit 50, then, pixel data stored in the memory 70 are limited to the numbers of pixels of the each of the shift registers. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image reading apparatus, such as a scanner, a facsimile, a copier, and a multifunction machine for reading an image of a document as electronic data using an image sensor equipped with a one-dimensional array of light receiving elements.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there are known image reading apparatuses such as scanners, fax machines, copiers, and multifunction machines for reading an image of a document as electronic data using an image sensor equipped with a one-dimensional array of light receiving elements.
[0003]
By the way, in the image reading by the image reading apparatus, for example, when it is desired to read with high accuracy even if the data amount such as a photographic image is large, and when it is desired to reduce the data amount of the read image more than the accuracy because it is used for data transfer such as FAX. If you have a large number of originals and want to read as fast as possible even if the image quality is slightly degraded, or if you want to read the image quality and data volume there as well, the desired method of reading image data depends on the intended use of the scanned image and , Because of the situation at the time of reading.
[0004]
On the other hand, conventionally, by changing the resolution of read image data and outputting it, the image quality and the amount of data are changed to meet various uses.
As one of the methods corresponding to this, as shown in FIG. 2, two sensors (first sensor 21 and second sensor 21) each including a plurality of light receiving elements arranged in the main scanning direction so as to be used for various purposes. 2 sensor 22), a first shift register 25 that outputs all pixel signals (17 in the example of FIG. 2) of the light receiving elements of the first sensor 21, and an even-numbered pixel signal of the light receiving element of the second sensor 22 (17). A second shift register 26 that outputs eight (in the example of FIG. 2) a third shift register 27 that outputs an odd-numbered pixel signal (nine in the example of FIG. 2) of the light receiving element of the second sensor 22. CCD linear image sensors have been developed.
[0005]
[Problems to be solved by the invention]
On the other hand, in the transmission of the pixel signal from the CCD image sensor, the charges accumulated in the light receiving elements are sequentially output as pixel signals by the shift register, and when the outputs from the three shift registers are simultaneously output, Since the number of pixel signals output from the shift register is different, some shift registers lose pixel signals quickly. However, since the output control from the three CCD image sensors is normally performed by one system, the output operation of the pixel signal continues as long as there is at least one shift register in which the output pixel signal remains. Therefore, the operation of outputting the pixel signal is performed even for the shift register from which the pixel signal has disappeared, and invalid data is transmitted and recorded in the memory.
[0006]
In the conventional image reading apparatus, as shown in FIG. 8, a pixel signal read by the CCD linear image sensor 20 (hereinafter referred to as CCD sensor 20), which is the above-described CCD linear image sensor, is selected by a selector 76, and A The image data is converted into a digital signal by the / D converter 77, the pixel data is received by the data sampling block 44 in the image reading control unit 40, and the pixel data is stored in the memory 70 by the memory interface circuit 46 in the image reading control unit 40. It is configured to write, and the image signal transmission in this image reading device is as follows.
[0007]
First, as shown in FIG. 3, the CCD sensor 20 outputs a voltage corresponding to the charge transferred from the shift register to the output terminals OUT1 to OUT3 at each edge of the transfer clocks φ1 and φ2. That is, the pixel signal of the image received by the light receiving element is output. At this time, the second shift register has the ninth edge of the transfer clock, and the third shift register has no pixel information in the tenth and subsequent signals.
[0008]
Next, the pixel signals output from the CCD sensor 20 are received by the selector 76, and the three-channel pixel signals received by the selector 76 are transmitted at the intervals of the transfer clocks φ1 and φ2 as shown in FIG. 4 and output to the A / D converter 77. The A / D converter 77 converts the analog signal to the digital signal at the same cycle as the cycle output from the selector 76 as shown in FIG. It is converted and output as a serial data string.
[0009]
At this time, although the output from the second shift register after the ninth edge portion of the transfer clock and the output from the third shift register after the tenth edge do not contain pixel information, the selector 76 has Since the channels of the second shift register and the third shift register are selected, the A / D converter 77 performs a digital signal operation on the channel that does not contain the pixel information, and the serial data stream ( It is transmitted as a hatched part in FIG. 4) and recorded in the memory as shown in FIG.
[0010]
As described above, there is a problem that invalid data having no pixel information uses the memory area, and the memory capacity is reduced. In addition, invalid data is included in image processing using pixel data recorded in the memory, so that it takes time to read from the memory or invalid data is selected at the stage of image processing. There is a problem that processing is required.
[0011]
The present invention has been made in view of such a problem, and has two sensors, a first shift register that outputs pixel signals of all light receiving elements of one sensor, and an even-numbered light receiving element of another sensor. An image reading apparatus using a CCD image sensor, comprising: a second shift register that outputs a pixel signal; and a third shift register that outputs an odd-numbered pixel signal of a light receiving element of the same sensor as the second shift register. An object of the present invention is to prevent invalid data generated due to the difference in the number of pixels output from the memory from being written to the memory.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the image reading apparatus according to claim 1, wherein the first sensor including a plurality of light receiving elements arranged in the main scanning direction and the plurality of light receiving elements arranged in the main scanning direction. A second sensor disposed at a predetermined interval in the sub-scanning direction with respect to the first sensor, and a pixel signal obtained from each light receiving element of the first sensor in a predetermined cycle in the order of arrangement of the light receiving elements. A first output unit, a second output unit that outputs pixel signals obtained from even-numbered light-receiving elements of the light-receiving elements constituting the second sensor at a predetermined cycle in the arrangement order of the light-receiving elements, Among the light-receiving elements constituting the sensor, the third output means for outputting the pixel signals obtained from the odd-numbered light-receiving elements in a predetermined cycle in the arrangement order of the light-receiving elements, and the pixel signal from each output means, Pixel data as digital signal Comprising conversion means for converting the data, and the pixel data storage means for storing pixel data outputted from the conversion means.
[0013]
A pixel number information storage unit in which pixel number information indicating the number of pixels output by each output unit per scan is stored for each output, and a pixel data number stored in the pixel data storage unit is determined by the output unit. And a pixel data storage restricting unit that restricts the pixel data stored in the pixel data storage unit based on the pixel number information so as to correspond to the number of pixels output by the pixel data storage unit.
[0014]
As a result, according to the image reading device of the present invention, each output unit can store only the number of pixels output per scan in the pixel data storage unit. This eliminates waste of the storage area in the pixel data storage means. Further, the number of processes in the image processing apparatus using the pixel data stored in the pixel data storage unit can be reduced.
[0015]
By the way, the number of pixels output by each output means is the same as the number of first sensors when the number of light receiving elements of the first and second sensors is even. On the other hand, the number of pixels output by the second and third output means is half of the number of light receiving elements of the second sensor (that is, half of the number of pixels output by the first output means). Further, when the number of light receiving elements of the first and second sensors is odd, the second output means subtracts one from the number of pixels of the second sensor and divides by two with respect to the number of pixels output by the first output means. The number of pixels of the third output means is a number obtained by subtracting 1 from the number of pixels of the second sensor, dividing by 2 and adding 1 to the number. As described above, there is a relationship between the number of pixels output by each output means, and if the number of pixels output by the first output means is known, the number of pixels output by the other two output means can be easily calculated. It can be set by means. By utilizing this relationship, an image reading apparatus according to the second aspect can be provided.
[0016]
That is, in the image reading apparatus according to the second aspect, the pixel number information storage means stores information on the number of pixels output by the first output means per one scan as the pixel number information. The means obtains the number of pixels output by each output means per one scan from the pixel number information, and limits the pixel data stored in the pixel data storage means based on the number of pixels.
[0017]
As a result, according to the image reading apparatus of the present invention (claim 2), the pixel number storage means can have only one information. Therefore, the storage area of the pixel number storage means can be reduced, and the device can be simplified.
In addition, the limitation of the pixel data stored in the pixel data storage means may be performed at any time after the output by the output means, but the processing performed more upstream does not perform the processing for invalid data in the processing performed downstream. You can do it.
[0018]
Therefore, in the image reading device according to the third aspect, the pixel data storage limiting unit limits the pixel data stored in the pixel data storage unit immediately after the output from the conversion unit to the pixel data storage unit.
As a result, according to the image reading apparatus of the present invention (claim 3), it is possible to limit the pixel data immediately after the output of the conversion unit. As a result, invalid data does not flow on the pixel data transmission path after the restriction is performed, so that when a pixel data processing device is on the transmission path, unnecessary processing due to invalid data can be reduced.
[0019]
Further, on the transmission path of the pixel data, the transmission restriction of the pixel data stored in the pixel information storage means may be performed further downstream, and the transmission to the pixel data storage means may be performed as in the image reading apparatus according to claim 4. It may be performed at the writing stage.
That is, in the image reading device according to claim 4, the pixel data storage unit includes a storage unit that stores the pixel data, and a writing unit that writes the pixel data output from the conversion unit into the storage unit. The storage restricting unit restricts the writing operation of the pixel data to the storage unit by the writing unit.
[0020]
As a result, according to the image reading apparatus of the present invention (claim 4), it is possible to restrict writing at the stage of writing to the storage unit.
In addition, while invalid pixel data is flowing, it is desirable to minimize unnecessary operations in order to reduce power consumption.
[0021]
On the other hand, in the image reading apparatus according to the fifth aspect, the conversion unit is configured to execute conversion of the pixel signal from each output unit into pixel data in accordance with a conversion command input from the outside. The data storage limiting unit controls the input of the conversion command to the converting unit such that the converting unit converts only the pixel signal output from each output unit into pixel data.
[0022]
As a result, according to the image reading apparatus of the present invention (claim 5), the conversion unit is not performed at the time of invalid data, and power consumption can be reduced.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First embodiment]
FIG. 1 is a block diagram illustrating an internal configuration of an image reading apparatus 1 to which the present invention has been applied.
[0024]
The image reading apparatus 1 of the present embodiment converts a pixel signal of a document image sensed by a CCD (Charge Coupled Diode) linear image sensor 20 into a digital signal (pixel data) by an AFE (Analog Front End) 75 and outputs the digital signal. This is an image reading apparatus that receives pixel data in a data sampling block 44 in the image reading control unit 40 and writes the pixel data in a memory 70 by a memory interface circuit 46 in the image reading control unit 40.
[0025]
As shown in FIG. 1, the image reading device 1 of the present embodiment includes a CCD linear image sensor (hereinafter referred to as a CCD sensor) 20, a CPU 80 for controlling the operation of the entire image reading device 1, and three of the CCD sensor 20. AFE 75 for converting the output analog data into a digital signal while switching it with a selector 76 and outputting the digital signal, memory 70 for recording (storing) pixel data, CCD sensor 20, image reading control unit 40 for controlling the operation of AFE 75 and memory 70, etc. It is composed of
[0026]
The CCD sensor 20 includes a first sensor 21, a second sensor 22, a first shift register 25, a second shift register 26, and a third shift register 27, as shown in FIG.
The first sensor 21 has a one-dimensionally arranged light receiving element that accumulates charges according to the amount of light received. Further, the second sensor 22 separates the same light receiving element array as the first sensor 21 from the first sensor 21 by a predetermined line in the sub-scanning direction (this time for six lines) and half the element in the main scanning direction. It is set out of place.
[0027]
Further, the first shift register 25 individually receives all the electric charges accumulated by the light receiving elements of the first sensor 21, shifts the electric charges toward the output terminal OUT1, and outputs a voltage proportional to the electric charges as a pixel signal as an output terminal. OUT1 sequentially, and the second shift register 26 individually receives the charges of the even-numbered light receiving elements of the second sensor 22 and sequentially outputs the charges to the output terminal OUT2 in the same manner as the first shift register 25. The shift register 27 individually receives the charges of the odd-numbered light receiving elements of the second sensor 22 and sequentially outputs the charges to the output terminal OUT3 in the same manner as the first shift register.
[0028]
In the first and second sensors 21 and 22, in the example shown in FIG. 2, the number of light receiving elements is 17. Therefore, the number of pixel signals output from the first shift register is 17, the number of pixel signals output from the second shift register is 8, and the number of pixel signals output from the third shift register is 9.
[0029]
The AFE 75 includes a selector 76 for selecting and outputting an output from the output terminals OUT1 to OUT3 of the CCD sensor 20, and an A / D converter 77 for converting a signal from the selector 76 into a digital signal. The AFE 75 samples and holds the input from the CCD sensor 20 and has three channels each having an adjustable gain and an offset correction function. The output from the output terminal OUT1 of the CCD sensor 20 is used as a channel CH1. Receiving the output of the output terminal OUT2 as the channel CH2, receiving the output of the output terminal OUT3 as the channel CH3, selecting the channel of the signal to be output based on an instruction from the outside by the selector 76, and switching the output every predetermined time to output. I do.
[0030]
The image reading control unit 40 includes a so-called ASIC (Application Specific Integrated Circuit), an AFE control block 42 that controls the operation of the AFE 75, a device control block 43 that controls the operation of the CCD sensor 20, a FIFO (First In First). Out) a data sampling block 44 that has a memory, samples pixel data from the AFE 75, and records the sampled data in the FIFO memory, a capture signal generation circuit 50 that generates a timing signal for sampling pixel data in the data sampling block 44, A read data processing circuit 45 for applying a correction such as shading to the sampled pixel data, and the pixel data from the read data processing circuit 45 is written to the memory 70. Is constituted by such as a register group 60 for storing setting values of the operating conditions in each block of the memory interface circuit 46, and the image reading control unit 40 performs the write.
[0031]
Note that the capture signal generation circuit 50 includes a counter 53 for counting up with a pulse signal from the device control block 43 for each of the channels CH1 to CH3, and a value of the capture pixel number setting register and the counter 53 for the corresponding channel. And a AND element 51 that outputs the logical product of the output of the comparator 52 and the pulse signal from the device control block 43.
[0032]
The register group 60 includes a channel 1 capture pixel number setting register 61 that stores the number of pixel signals output from the output terminal OUT1 of the CCD sensor 20, and a channel that stores the number of pixel signals output from the output terminal OUT2. The register 2 includes a register 2 for setting the number of pixels to be taken, a register 63 for setting the number of pixels to be taken which stores the number of pixel signals output from the output terminal OUT3, and the like. Is written.
[0033]
The device control block 43 includes a shift gate signal SH, which is a pulse signal having a cycle determined by the output time of the pixel signal from the CCD sensor 20, and two rectangular waves having phases different from each other by 180 degrees in a cycle determined by the characteristics of the shift register. , And a reset signal RS, which is a pulse signal generated at the same cycle as the transfer clock, is output to the CCD sensor 20. Further, the device control block 43 outputs a pulse signal to a line to the counter 53 of the capture signal generation circuit 50 corresponding to the channel selected by the selector 76. This pulse signal is synchronized with the timing at which the channel is switched by the selector 76 of the AFE 75. At the timing of the shift gate signal SH, the counter 53 and the like of the capture signal generation circuit 50 are reset.
[0034]
Here, in the image reading apparatus, pixel signals from the first and second sensors 21 and 22 of the CCD sensor 20 are output from the first to third shift registers 25 to 27 and written into the memory 70 as pixel data. The operation up to will be described.
The pixel data read in this operation is pixel data obtained by alternately arranging pixel data from the second sensor 22 and pixel data from the first sensor 21 when the CCD sensor 20 is moved by six lines. By handling, it is used as pixel data of twice the resolution of one sensor.
[0035]
First, in the CCD sensor 20, the first sensor 21 receives the light from the document during the period from the previous shift gate signal SH to the current shift gate signal SH, and accumulates the electric charge of each light receiving element. Moves to the first shift register 25 at the falling edge of. Also in the second sensor 22, the charges of the even-numbered light receiving elements move to the second shift register 26, and the charges of the odd-numbered light receiving elements move to the third shift register 27.
[0036]
Next, as shown in FIG. 3, the output of each of the output terminals OUT1 to OUT3 of the CCD sensor 20 clears the charge at the rise of the reset signal RS and returns to the reference voltage. Then, at the edges of the transfer clocks φ1 and φ2, the charge of each shift register is shifted toward the output terminal, and the charge of the shift register closest to the output terminal is shifted to the output terminal. The voltage is output to the output terminals OUT1 to OUT3. That is, a pixel signal of an image received by the light receiving element is output.
[0037]
Then, the pixel signals of the output terminals OUT1 to OUT3 are sampled and held in each of the channels CH1 to CH3 of the AFE 75 from the time when the voltage change at the output terminals OUT1 to OUT3 is stabilized until the next reset signal RS comes. The sampled and held pixel signal is multiplied by a preset gain via the AFE control block 42 to perform offset correction.
[0038]
The operation until the charges of these sensors are shifted by the respective shift registers, sampled and held for each of the channels CH1 to CH3 of the AFE 75, and the offset correction is repeated for each edge of the transfer clocks φ1 and φ2.
Next, the signals sampled and held in each of the channels CH1 to CH3 of the AFE 75 and subjected to the offset correction are sequentially transferred to the three channels by the selector 76 within the cycle of the transfer clocks φ1 and φ2 as shown in FIG. Select and output.
[0039]
Next, the signal output from the selector 76 is converted by an A / D converter 77 from an analog signal to a digital signal at the same cycle as the output of the selector 76 as shown in FIG. Are sequentially output as digital signals (pixel data) of 8 bits.
[0040]
On the other hand, in the capture signal generation circuit 50, at the timing when the A / D converter 77 outputs the pixel data, the device control block 43 sends the pixel data to the circuit corresponding to the channel of the pixel data output from the A / D converter 77. Upon receiving the pulse signal, a sampling trigger signal is output to the data sampling block 44 according to the value of the counter 53.
[0041]
For example, when the pixel data of the channel CH2 is output from the A / D converter 77, a pulse signal is output from the device control block 43 to the counter 53 corresponding to the channel CH2, and the counter 53 counts up the value of the counter. I do. Then, the value of the counter 53 is compared with the value of the channel 2 capturing pixel number setting register 62 by the comparator 52, and the value of the counter 53 is “8” which is the value of the channel 2 capturing pixel number setting register 62. In the following cases, the output of the comparator 52 becomes “1”. At this time, the pulse signal from the device control block 43 also enters the AND element 51, and while the pulse signal is coming, the AND element 51 becomes "1".
[0042]
Similarly, when the output of the counter 53 is less than or equal to the value “17” of the channel 1 capture pixel number setting register 61 for the pixel data of the channel CH1, and for the pixel data of the channel CH3, Is less than or equal to the value "9" of the channel 3 capture pixel number setting register 63, the AND element 51 is "1" while the pulse signal from the device control block 43 is coming.
[0043]
Next, the pixel data output from the AFE 75 is sampled by the data sampling block 44 at a timing when one of the outputs of the three AND elements 51 of the capture signal generation circuit 50 becomes “1”, and is stored in the FIFO memory. Is stored in At this time, channel information is added to the pixel data based on the received channel of the AND element 51. For example, 2-bit data representing channel information is added to the pixel data.
[0044]
Next, the pixel data stored in the FIFO memory of the data sampling block 44 is taken out by the read data processing circuit 45, and arithmetic processing of shading processing, gamma correction, and dark correction corresponding to the channel of the pixel data is performed.
Next, the pixel data calculated by the read data processing circuit 45 is sequentially written to a predetermined address of the memory 70 by the memory interface circuit 46.
[0045]
Next, when the next shift gate signal SH is output, each counter in the image reading control unit 40 is reset, and the CCD sensor 20 outputs the first and second signals while outputting the previous pixel signal. The electric charges accumulated in the two sensors 21 and 22 are transferred to each shift register again. Then, similarly, the operation until the pixel signal is output from the CCD sensor 20 and the pixel signal is recorded (stored) in the memory 70 is repeated.
[effect]
The counter 53 of the capture signal generation circuit 50 sets the number of pixels set in the channels 1 to 3 capture pixel number setting registers 61 to 63 (that is, 17 for channel CH1, 8 for channel CH2, and 9 for channel CH3). After that, since the output of the comparator 52 becomes “0”, the enable signal from the AND element 51 is not output for the pixel data of the channel output from the AFE 75, and the data sampling block 44 Not sampled. Therefore, as shown in FIG. 5B, only the pixel data of the number of pixels output from the first to third shift registers 25 to 27 is recorded (stored) in the memory.
[0046]
As a result, the recording (storage) of invalid pixel data in the memory 70 can be reduced, and the need for an unnecessarily large memory 70 can be eliminated. Also, when outputting data in the memory to an external image processing device or the like, the data amount is reduced and the data can be output quickly, and processing in the external image processing device or the like can be reduced.
[Second embodiment]
The purpose and use of the second embodiment are the same as those of the first embodiment, and the configuration of the image reading control unit 40 is changed. In the second embodiment, the pixel data to be written into the memory 70 by the memory interface circuit 46 is limited by the capture signal generation circuit 54, whereas the pixel data to be transmitted by controlling the sampling timing is limited. It is.
[0047]
As shown in the overall configuration of FIG. 6, the device control block 43 outputs a sampling timing signal to a data sampling block 44, and the capture signal generation circuit 54 sends a memory 70 to a memory interface circuit 46. A signal for permitting the writing of the pixel data to the pixel is output.
[0048]
Further, the memory interface circuit 46 has a counter function, and every time it receives three data (ie, signal data for three channels of the CCD sensor 20), it sends a pulse for counting up to the capture signal generation circuit 54. Output a signal.
Then, the capture signal generation circuit 54 counts up the counter 53 by the pulse signal from the memory interface circuit 46, and sets the value of the channel 1 capture pixel number setting register 61 and the value of the channel 2 capture pixel number setting register 62. , The value of the register 3 for setting the number of pixels to be taken in channel 3 is compared by each comparator 52. If the value of the counter 53 is equal to or smaller than the set value, the corresponding comparator 52 sets “1” to each input of the memory interface circuit 46. Output to port.
[0049]
When there is a signal of “1” at the input port from the capture signal generation circuit 54 corresponding to the channel information of the received pixel data, the memory interface circuit 46 performs writing to the memory 70.
[effect]
The data to be written to the memory 70 by the memory interface circuit 46 is larger than the number of pixels set in the channel 1 to 3 capture pixel number setting registers 61 to 63. Since it is “0”, writing to the memory 70 is not performed. Therefore, only the pixel data of the number of pixels output from the first to third shift registers 25 to 27 is recorded (stored) in the memory.
[0050]
As a result, the same effect as in the first embodiment can be obtained.
[Correspondence with the present invention]
The first sensor 21, the second sensor 22, the first shift register 25, the second shift register 26, and the third shift register 27 of the CCD sensor 20 are the first sensor, the second sensor, and the third One output means, second output means, and third output means.
[0051]
The AFE 75 is a conversion unit in the present invention, the memory 70 is an image data storage unit, the capture pixel number setting registers 61 to 66 are pixel number information storage units, and the capture signal generation circuits 50 and 54 are This is a pixel data storage limiting unit.
[Modification]
As described above, the embodiments of the present invention have been described. However, the present invention is not limited to the above specific embodiments, and can be implemented in various other modes.
[0052]
For example, in the description of the first embodiment, a case has been described in which all three outputs from the CCD sensor 20 are recorded (stored) in the memory 70, but the AFE control block 42 is instructed to select a channel to be selected by the AFE 75. By switching the channel selected by the selector 76 according to the signal from the AFE control block 42, only the pixel data of the signal of one of the channels is recorded (stored) in the memory 70, and the channel CH2 and CH3 are Only the pixel data of the two signals can be recorded (stored) in the memory 70. As a result, the reading resolution was changed, such as recording (storing) pixel data at the resolution of the first sensor and the second sensor and recording (storing) pixel data at half the resolution of the second sensor. Data can be obtained.
[0053]
In the first and second embodiments, the number of pixels to be captured is provided in each of the three registers of channels 1 to 3 for setting the number of pixels to be captured. Since there is a relationship between the channels, as shown in FIG. 7, the information in the register group is only the channel 1 capture pixel number setting register 61 and the binary data of the value of the channel 1 capture pixel number setting register 61 is 1 An arithmetic circuit 55 that shifts in the direction of dropping the bit (that is, division by 2) and a value that comes out by the bit shift in the arithmetic circuit 55 (if the value of the channel 1 capture pixel number setting register 61 is an even number, “ It may be configured by a +1 setting register 56 in which "0" is set, and "1" is set if the number is odd. In the comparator 52 of the channel CH2, the value of the arithmetic circuit 55 is used as the number of pixels captured in the channel 2, and in the comparator 52 of the channel CH3, the value of the arithmetic circuit 55 is set to +1 as the number of pixels captured in the channel 3. The value obtained by adding the value of the register 56 is used. As described above, an image reading apparatus that requires only the setting of the channel 1 capture pixel number setting register 61 can be provided.
[0054]
Further, the difference in the number of pixels taken in between the channels CH2 and CH3 is only one pixel, and the number of pixels in the channel CH2 is set to be the same as that of the larger channel CH3. The output of the comparator 52 for the channel CH2 may be input, and the comparator 52 and the counter 53 for the channel CH2 may be omitted. Thereby, a simpler device configuration can be obtained.
[0055]
As shown by the dotted line in FIG. 1, the signal from the capture signal generation circuit 50 is input to the AFE controller 42, and the A / D converter converts the signal of the channel in which the signal from the capture signal generation circuit 50 enters. The control of 77 may be performed. As a result, while invalid data is flowing, the A / D converter 77 does not operate, thereby reducing power consumption.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an overall configuration of an image reading apparatus according to a first embodiment.
FIG. 2 is a diagram illustrating a configuration of a CCD linear image sensor 20 according to the first embodiment.
FIG. 3 is a timing chart illustrating a state of a signal in the CCD sensor 20 of the first embodiment.
FIG. 4 is a diagram illustrating a state of pixel data according to the first embodiment.
FIG. 5 is a diagram illustrating a recording state of pixel data in a memory 70 according to the first embodiment.
FIG. 6 is a diagram illustrating an overall configuration of an image reading apparatus according to a second embodiment.
FIG. 7 is a diagram illustrating an entire configuration of a modification of the image reading apparatus according to the first embodiment.
FIG. 8 is a diagram illustrating an entire configuration of a conventional image reading apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Image reading device, 20 ... CCD linear image sensor, 21 ... 1st sensor, 22 ... 2nd sensor, 25 ... 1st shift register, 26 ... 2nd shift register, 27 ... 3rd shift register, 40 ... Image reading Control unit, 42: AFE control block, 43: Device control block, 44: Data sampling block, 45: Read data processing circuit, 46: Memory interface circuit, 50: Capture signal generation circuit, 51: AND element, 52: Comparison , 53 ... counter, 54 ... capture signal generation circuit, 60 ... register group, 61 ... channel 1 capture pixel number setting register, 62 ... channel 2 capture pixel number setting register, 63 ... channel 3 capture pixel number setting Register, 70: memory, 75: AFE, 76: selector, 77: A / D converter.

Claims (5)

A first sensor including a plurality of light receiving elements arranged in the main scanning direction;
A second sensor comprising a plurality of light receiving elements arranged in the main scanning direction and arranged at a predetermined interval in the sub scanning direction with respect to the first sensor;
First output means for outputting a pixel signal obtained from each light receiving element of the first sensor in a predetermined cycle in the arrangement order of the light receiving elements;
Among the light-receiving elements constituting the second sensor, second output means for outputting a pixel signal obtained from the light-receiving elements arranged in even-numbered order in the arrangement order of the light-receiving elements in the cycle,
A third output unit that outputs pixel signals obtained from the odd-numbered light-receiving elements among the light-receiving elements constituting the second sensor, in the arrangement order of the light-receiving elements in the cycle;
A conversion unit that converts the pixel signal from each of the output units into pixel data as a digital signal and outputs the pixel data;
Pixel data storage means for storing pixel data output from the conversion means,
An image reading device comprising:
Pixel number information storage means in which pixel number information indicating the number of pixels output by each output means per scan is stored for each output,
Pixel data storage that limits the pixel data stored in the pixel data storage unit based on the pixel number information so that the number of pixel data stored in the pixel data storage unit corresponds to the number of pixels output by each of the output units. Limiting means;
An image reading apparatus comprising: The pixel number information storage unit stores, as the pixel number information, information on the number of pixels output by the first output unit per scan,
The pixel data storage limiting unit determines the number of pixels output by each of the output units per scan from the pixel number information, and limits the pixel data stored in the pixel data storage unit based on the number of pixels. The image reading device according to claim 1, wherein: 3. The pixel data storage limiting unit according to claim 1, wherein the pixel data storage limiting unit limits the pixel data stored in the pixel data storing unit immediately after the conversion unit outputs the pixel data to the pixel data storing unit. Image reading device. The pixel data storage unit includes a storage unit that stores pixel data, and a writing unit that writes the pixel data output from the conversion unit into the storage unit.
The image reading apparatus according to claim 1, wherein the pixel data storage restricting unit restricts an operation of writing the pixel data to the storage unit by the writing unit. The conversion unit is configured to execute conversion of a pixel signal from each of the output units into pixel data in accordance with a conversion command input from the outside,
The pixel data storage limiting unit controls input of a conversion command to the conversion unit such that the conversion unit converts only a pixel signal output from each of the output units into pixel data. The image reading device according to claim 1.

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