JP2004055908A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a process cost when both of an insulated isolating trench of a deep trench structure and a shallow trench by an STI technique are formed in a semiconductor layer. <P>SOLUTION: (b) A trench etching mask 32 of a layered structure which comprises an opening 30 for the insulated isolating trench and an opening 31 for the shallow trench is formed. (d) A thermal oxide film 33 is formed in only a region facing the opening 31 for the shallow trench in a monocrystalline silicon layer 21C. (e) A reactive ion etching utilizing the trench etching mask 32 is carried out by using a reactive gas having a high etching selection ratio between a monocrystalline silicon and a silicon oxide, thereby performing an anisotropic etching for the monocrystalline silicon layer 21C. The reactive ion etching is carried out by replacing with the reactive gas having a low etching selection ratio between the monocrystalline silicon and the silicon oxide, thereby performing the anisotropic etching for the thermal oxide film 33 and the monocrystalline silicon layer 21C. <P>COPYRIGHT: (C)2004,JPO

Description

【００３６】
要するに、本実施例による半導体装置の製造方法は、以下に述べるような特徴を有するものである。
単結晶シリコン層２１Ｃに対してディープトレンチ構造の絶縁分離トレンチ２３及び浅部トレンチ２４の双方を形成するに当たって、絶縁分離トレンチ２３を形成するための第１のエッチング工程と、浅部トレンチ２４を形成するための第２のエッチング工程とを、同一の反応性イオンエッチング装置を利用して実行できる。具体的には、第１及び第２のエッチング工程は、ワーク（ＳＯＩ基板２１）を反応性イオンエッチング装置のエッチング室内に設置したままの状態で、反応性ガスを、単結晶シリコン及び酸化シリコン間のエッチング選択比が高いものから低いものへ切り替えることにより連続して実行できる。また、絶縁分離トレンチ２３及び浅部トレンチ２４を形成する際に、トレンチエッチングマスク３２のための成膜工程（図１（ａ））及び開口部形成工程（図１（ｂ））、ディープトレンチ２３ａ及びトレンチ２４ａを酸化シリコン膜３４により埋め戻すためのトレンチ埋め戻し工程（図２（ｇ））、その酸化シリコン膜３４及び酸化シリコン膜２９を化学的機械的研磨法などにより除去する平坦化工程（図２（ｈ））、トレンチエッチングマスク３２を構成する窒化シリコン膜２８及び酸化シリコン膜２７を除去するための除去工程（図２（ｉ）、（ｊ））、単結晶シリコン層２１Ｃの表面に熱酸化膜２６を形成するための熱酸化工程（図２（ｋ））を互いに兼用できるようになる。この結果、単結晶シリコン層２１Ｃに対しディープトレンチ構造の絶縁分離トレンチ２３及びＳＴＩ技術による浅部トレンチ２４の双方を形成する場合、それら絶縁分離トレンチ２３及び浅部トレンチ２４の製造工程を個別に行う場合に比べて、必要となる製造工程が格段に減ることになり、従って、プロセスコストの大幅な抑制が可能になる。
【００３７】
（他の実施の形態）
その他、本発明は上記した実施例に限定されるものではなく、以下に述べるような変形或いは拡張が可能である。
単結晶シリコン基板２１Ａを支持基板としたＳＯＩ基板２１を利用する例で説明したが、支持基板の材料としては、単結晶シリコン基板に限らず、他の半導体基板或いは絶縁性を有するセラミック基板やガラス基板などを用いることができ、特に、絶縁性を有する基板を用いる場合には絶縁分離層（上記した各実施例の場合、酸化シリコン膜より成る絶縁分離層２１Ｂ）が不要になる（例えば、ＳＯＳ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｓａｐｐｈｉｒｅ　）基板を用いる場合が該当する）。
【図面の簡単な説明】
【図１】本発明の一実施例による製造工程の流れを示す模式的断面図その１
【図２】製造工程の流れを示す模式的断面図その２
【図３】製造対象の半導体装置の模式的断面図
【図４】従来例による製造工程の流れを示す模式的断面図その１
【図５】従来例による製造工程の流れを示す模式的断面図その２
【図６】従来例による製造工程の流れを示す模式的断面図その３
【図７】従来例による製造工程の流れを示す模式的断面図その４
【符号の説明】
２１はＳＯＩ基板、２１Ａは単結晶シリコン基板（支持基板）、２１Ｂは絶縁分離層、２１Ｃは単結晶シリコン層（半導体層）、２３は絶縁分離トレンチ、２３ａはディープトレンチ、２４は浅部トレンチ、２４ａはトレンチ、２６は熱酸化膜、２７は酸化シリコン膜（絶縁膜）、２８は窒化シリコン膜（ストッパ膜）、２９は酸化シリコン膜（マスク膜）、３０は絶縁分離トレンチ用開口部、３１は浅部トレンチ用開口部、３２はトレンチエッチングマスク、３３は熱酸化膜、３４は酸化シリコン膜を示す。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having an insulating isolation trench having a deep trench structure and a shallow trench by STI (Shallow Trench Isolation) technology.
[0002]
[Prior art]
In recent years, there has been an increasing demand for semiconductor devices using bipolar CMOS technology for applications such as communication LSIs. In such a semiconductor device, an SOI substrate useful for a low-power device is used, and an isolation trench having a deep trench structure is formed in order to enhance the insulating property of a bipolar transistor region. In order to reduce the separation width and increase the degree of integration, it has been considered to form a shallow trench by the STI technique instead of the LOCOS film which has been generally used in the related art. In the case of manufacturing such a semiconductor device, a manufacturing method has conventionally been employed in which a process of forming an insulating trench and a process of forming a shallow trench are individually executed.
[0003]
Specifically, the insulating isolation trench is formed through a manufacturing process schematically illustrated in FIGS. 4 and 5, and the shallow trench is formed through a manufacturing process schematically illustrated in FIGS. Hereinafter, the contents of each step will be individually described. However, the dimensional ratios in FIGS. 4 to 7 are not accurate.
[0004]
(1) Manufacturing Step of Insulating Isolation Trench (1) Film Forming Step First, as shown in FIG. 4A, a single-crystal silicon layer is formed on a single-crystal silicon substrate 1A via an insulating separation layer 1B made of a silicon oxide film. An SOI substrate 1 on which a layer 1C is formed is prepared, a silicon oxide film 2 serving as an insulating film is formed on the single crystal silicon layer 1C by thermal oxidation, and then a silicon nitride film 3 serving as a stopper film and a mask film are formed. A silicon oxide film 4 is sequentially formed by a CVD method or the like.
[0005]
{Circle around (2)} Opening forming step After that, as shown in FIG. 4B, a predetermined structure is formed by patterning the three-layer structure film of the silicon oxide film 2, the silicon nitride film 3, and the silicon oxide film 4 by a photo-etching technique. A trench etching mask (not numbered) having a layer structure with openings 5 at positions is formed.
[0006]
{Circle around (3)} Trench etching step After the above mask forming step, anisotropic dry etching using the silicon oxide film 4 as a mask is performed on the single-crystal silicon layer 1C, as shown in FIG. As shown, a deep deep trench 6 reaching the insulating isolation layer 1B is formed.
[0007]
(4) Sidewall Oxidation Step After the trench etching step is performed, the side wall of the deep trench 6 is thermally oxidized to form a side wall oxide film 7 (see FIG. 4D).
[0008]
{Circle around (5)} Trench backfilling step By depositing polysilicon by CVD over the entire surface of the silicon oxide film 4, a polysilicon film 8 in which the deep trench 6 is backfilled is formed (see FIG. 4E). ).
[0009]
{Circle around (6)} First etch-back step The polysilicon film 8 is etched back to the surface of the silicon oxide film 4 by performing a CMP (chemical mechanical polishing) process or anisotropic etching using the silicon oxide film 4 as a stopper. (See FIG. 5 (f)).
[0010]
{Circle around (7)} Mask removing step The silicon oxide film 4 used as the trench etching mask is removed by wet etching using the silicon nitride film 3 as a stopper (see FIG. 5G).
[0011]
{Circle around (8)} Second etch-back step The polysilicon film 8 projecting above the deep trench 6 is removed to the surface of the silicon oxide film 2 by dry etching using the silicon nitride film 3 as a mask (FIG. 5 (h)). reference).
[0012]
(9) Mask Removal and Oxidation Step After the silicon nitride film 3 and the silicon oxide film 2 are sequentially removed by wet etching, the surface of the single crystal silicon layer 1C is thermally oxidized to form an oxide film 9 (FIG. 5 (i)). reference).
[0013]
(2) Manufacturing process of shallow trench {circle around (1)} Film forming process As in the above-described manufacturing process of the isolation trench, the silicon oxide film 2, the silicon nitride film 3, and the silicon oxide film 4 as shown in FIG. Are sequentially formed on the single-crystal silicon layer 1C.
[0014]
{Circle around (2)} Opening forming step Thereafter, as shown in FIG. 6 (b), the three-layered structure film is patterned by a photoetching technique to thereby form a trench etching mask having a layered structure having openings 10 at predetermined positions. (No sign).
[0015]
{Circle around (3)} Trench etching step After the above mask forming step, anisotropic dry etching is performed on the single crystal silicon layer 1C using the silicon oxide film 4 as a mask. A trench 11 as shown is formed.
[0016]
{Circle around (4)} Trench backfilling process By depositing silicon oxide on the entire surface of the silicon oxide film 4 by the CVD method, a silicon oxide film 12 with the trench 11 backfilled is formed (see FIG. 6D). .
[0017]
{Circle around (5)} Etch-back step [0107] By performing a CMP process using the silicon nitride film 3 as a stopper, the silicon oxide films 12 and 4 are etched back to the surface of the silicon nitride film 3 (see FIG. 7E).
[0018]
(6) Mask Removal and Oxidation Step After the silicon nitride film 3 and the silicon oxide film 2 are sequentially removed by wet etching, the surface of the single crystal silicon layer 1C is thermally oxidized to form an oxide film 13 (FIG. 7F). reference).
[0019]
[Problems to be solved by the invention]
The process of forming the isolation trench having the deep trench structure is extremely complicated, and the process of forming the shallow trench is also complicated accordingly. Therefore, the isolation trench and the shallow trench are individually formed. The conventional method of manufacturing a semiconductor device described above has a problem that the process cost is increased and it is difficult to reduce the product cost.
[0020]
The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the process cost when forming both an isolation trench having a deep trench structure and a shallow trench by STI technology in a semiconductor layer. To provide a method for manufacturing a semiconductor device.
[0021]
[Means for Solving the Problems]
According to the method of manufacturing a semiconductor device according to claim 1, in forming both the isolation trench and the shallow trench having the deep trench structure in the semiconductor layer, the first etching step for forming the isolation trench is performed. And a second etching step for forming a shallow trench can be performed using the same reactive ion etching apparatus. Specifically, the first and second etching steps can be continuously performed by switching the reactive gas while the work is installed in the etching chamber of the reactive ion etching apparatus. Further, when forming the insulating isolation trench and the shallow trench, a film forming step and an opening forming step for a trench etching mask, a removing step for removing a stopper film and an insulating film constituting the trench etching mask, In addition to a thermal oxidation process for forming a thermal oxide film on the surface of the semiconductor layer, a shallow trench backfill by deep trench / STI technology, an etch back (flattening) process, and the like can also be used for each other. As a result, in forming both the isolation trench having the deep trench structure and the shallow trench by the STI technique in the semiconductor layer, the necessity for forming the isolation trench and the shallow trench is smaller than in the case where the manufacturing steps of the isolation trench and the shallow trench are individually performed. This significantly reduces the number of manufacturing steps, and thus makes it possible to significantly reduce process costs.
[0022]
According to the method of manufacturing a semiconductor device according to claim 2, the oxide semiconductor film covering the region facing the shallow trench opening in the semiconductor layer is removed from the insulating layer opening and the shallow portion in the semiconductor layer. A thermal oxidation step of forming a thermal oxide film in a region facing the trench opening and an oxide film removing step of removing a portion of the thermal oxide film corresponding to the insulating isolation trench opening are more reliably performed. Can be formed.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
FIG. 3 schematically shows a partial cross-sectional structure of a semiconductor device manufactured by the manufacturing method of this embodiment (the dimensional ratio is not accurate). In FIG. 3, the semiconductor device to be manufactured is, for example, a bipolar CMOS, and is formed on a single-crystal silicon substrate 21A (corresponding to a support substrate in the present invention) via an insulating separation layer 21B made of a silicon oxide film. It is formed using an SOI substrate 21 on which a silicon layer 21C (corresponding to a semiconductor layer) is formed. In this case, in the single crystal silicon layer 21C, an element formation region 22a for forming a bipolar transistor which is a circuit element for driving a large current and operating at high speed, and a CMOS which is a circuit element for high integration and low power consumption are provided. In order to electrically isolate the element formation regions 22a and 22b, an insulation isolation trench 23 having a deep trench structure reaching the insulation isolation layer 21B is formed. You. In the CMOS element formation region 22b, a shallow trench 24 is formed by STI (Shallow Trench Isolation) technology. The silicon oxide 25 is buried in the insulating isolation trench 23 and the shallow trench 24, and a thermal oxide film 26 is formed on the single crystal silicon layer 21C.
[0024]
1 and 2 are schematic cross-sectional views (dimension ratios are not accurate) of respective steps for manufacturing the above-described semiconductor device. Hereinafter, the contents of each step will be individually described. explain.
[0025]
(1) Film forming process As shown in FIG. 1A, a silicon oxide film 27 (corresponding to an insulating film) is formed on a single crystal silicon layer 21C of an SOI substrate 21 by thermal oxidation, and then a silicon nitride film is formed. 28 (corresponding to a stopper film) and a silicon oxide film 29 (corresponding to a mask film) are sequentially formed in a laminated shape. Here, the silicon oxide film 29 functions as an etching mask when the single crystal silicon layer 21C is anisotropically etched to form a trench. The silicon nitride film 28 functions as a stopper when the silicon oxide film 29 is removed, and the silicon oxide film 27 plays a role in relieving stress when the silicon nitride film 28 is formed. Things.
[0026]
{Circle around (2)} Opening forming step With respect to the three-layer laminated film formed by the above film forming step, as shown in FIG. By forming the opening 30 for the insulating isolation trench and the opening 31 for the shallow trench, the trench etching mask 32 having a layer structure is formed.
[0027]
{Circle around (3)} Oxide film formation step This step is constituted by sequentially executing a thermal oxidation step and an oxide film removal step. In the thermal oxidation step, by performing an oxidation process using a thermal oxidation apparatus, as shown in FIG. 1C, the opening 30 for the isolation trench and the opening 31 for the shallow trench 31 in the single crystal silicon layer 21C. A thermal oxide film 33 is formed in a region facing. Further, in the oxide film removing step, for example, dry etching is performed in a state where a mask having an opening only at a portion corresponding to the insulating isolation trench opening 30 is formed, so that the insulating isolation trench opening 30 of the thermal oxide film 33 is formed. Is removed, and thereafter the mask is also removed by etching (see FIG. 1D). Therefore, the portion of the thermal oxide film 33 corresponding to the opening 31 for the shallow trench is left as it is.
[0028]
{Circle around (4)} First Etching Step Reactive ion etching (RIE) using the trench etching mask 32 is performed using a reactive gas (for example, bromine (Br 2)) having a high etching selectivity between single crystal silicon and silicon oxide. Of the single crystal silicon layer 21C corresponding to the opening 30 for the isolation trench, thereby forming a deep trench 23a corresponding to the isolation trench 23. (See FIG. 1E). In this case, the bottom of the deep trench 23a does not need to reach the insulating isolation layer 21B as shown in the figure, and the bottom thereof has a thickness determined by an etching amount in a second etching step described later. It is desirable to leave the single crystal silicon layer 21C.
[0029]
{Circle around (5)} Second Etching Step [0113] Reactive ion etching using the trench etching mask 32 is performed by using a reactive gas (for example, a fluorine-based chemical gas) having a low etching selectivity between single crystal silicon and silicon oxide. By performing the switching, the thermal oxide film 33 and the single-crystal silicon layer 21C corresponding to the shallow trench opening 31 are anisotropically etched, thereby forming the trench 24a corresponding to the shallow trench 24 (FIG. 9). 1 (f)). The bottom of the deep trench 23a reaches the insulating separation layer 21B in accordance with the execution of the second etching step.
[0030]
{Circle around (6)} Trench backfilling step The deep trench 23a and the trench 24a are backfilled by depositing a silicon oxide film 34 by a chemical vapor deposition (CVD) method (see FIG. 2 (g)).
[0031]
{Circle around (7)} Flattening step The silicon oxide film 34 and the silicon oxide film 29 deposited in the above-mentioned trench backfilling step are removed by a chemical mechanical polishing (CMP) method using the silicon nitride film 28 as a stopper, etc. Is flattened (see FIG. 2 (h)). Note that, according to this flattening, the silicon oxide film 34 becomes the buried silicon oxide 25 shown in FIG.
[0032]
(8) Removal Step First, the silicon nitride film 28 is removed by performing wet etching with a phosphoric acid-based etchant (see FIG. 2 (i)). Next, the silicon oxide film 27 is removed by performing wet etching with a hydrofluoric acid-based etchant (see FIG. 2J).
[0033]
{Circle around (9)} Thermal oxidation process By performing an oxidation process using a thermal oxidation apparatus, a thermal oxide film 26 is formed on the surface of the single crystal silicon layer 21C (see FIG. 2 (k)), and as shown in FIG. Such a semiconductor device is completed.
[0034]
The reactive gas and the flow rate used in the reactive ion etching can be determined in consideration of the characteristics shown in the table below.
[0035]
[Table 1]

[0036]
In short, the method of manufacturing a semiconductor device according to the present embodiment has the following features.
In forming both the isolation trench 23 having a deep trench structure and the shallow trench 24 with respect to the single crystal silicon layer 21C, a first etching step for forming the isolation trench 23 and the formation of the shallow trench 24 are performed. And a second etching step for performing the same can be performed using the same reactive ion etching apparatus. Specifically, in the first and second etching steps, the reactive gas is supplied between the single crystal silicon and the silicon oxide while the work (SOI substrate 21) is kept in the etching chamber of the reactive ion etching apparatus. Can be continuously performed by switching from a high etching selectivity to a low etching selectivity. Further, when forming the insulating isolation trench 23 and the shallow trench 24, a film forming step (FIG. 1A) and an opening forming step (FIG. 1B) for the trench etching mask 32 are performed. And a trench backfilling step (FIG. 2 (g)) for backfilling the trench 24a with the silicon oxide film 34, and a flattening step (FIG. 2G) for removing the silicon oxide film 34 and the silicon oxide film 29 by a chemical mechanical polishing method or the like. FIG. 2 (h)), a removing step for removing the silicon nitride film 28 and the silicon oxide film 27 constituting the trench etching mask 32 (FIGS. 2 (i) and 2 (j)). The thermal oxidation step (FIG. 2 (k)) for forming the thermal oxide film 26 can be used for both. As a result, when both the isolation trench 23 having the deep trench structure and the shallow trench 24 formed by the STI technique are formed in the single crystal silicon layer 21C, the steps of manufacturing the isolation trench 23 and the shallow trench 24 are individually performed. As compared with the case, the number of required manufacturing steps is significantly reduced, and therefore, the process cost can be significantly reduced.
[0037]
(Other embodiments)
In addition, the present invention is not limited to the above-described embodiment, and can be modified or expanded as described below.
Although the example using the SOI substrate 21 using the single-crystal silicon substrate 21A as a support substrate has been described, the material of the support substrate is not limited to the single-crystal silicon substrate, but may be another semiconductor substrate, an insulating ceramic substrate, or glass. A substrate or the like can be used. In particular, when a substrate having an insulating property is used, the insulating separation layer (the insulating separation layer 21B made of a silicon oxide film in each of the above-described embodiments) becomes unnecessary (for example, SOS). (The case where a Silicon On Sapphire substrate is used).
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a flow of a manufacturing process according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing a flow of a manufacturing process;
FIG. 3 is a schematic cross-sectional view of a semiconductor device to be manufactured. FIG. 4 is a schematic cross-sectional view showing a flow of a manufacturing process according to a conventional example.
FIG. 5 is a schematic cross-sectional view showing a flow of a manufacturing process according to a conventional example.
FIG. 6 is a schematic sectional view 3 showing a flow of a manufacturing process according to a conventional example.
FIG. 7 is a schematic cross-sectional view showing a flow of a manufacturing process according to a conventional example.
[Explanation of symbols]
21 is an SOI substrate, 21A is a single crystal silicon substrate (supporting substrate), 21B is an insulating isolation layer, 21C is a single crystal silicon layer (semiconductor layer), 23 is an insulating isolation trench, 23a is a deep trench, 24 is a shallow trench, 24a is a trench, 26 is a thermal oxide film, 27 is a silicon oxide film (insulating film), 28 is a silicon nitride film (stopper film), 29 is a silicon oxide film (mask film), 30 is an opening for insulating isolation trench, 31 Denotes a shallow trench opening, 32 denotes a trench etching mask, 33 denotes a thermal oxide film, and 34 denotes a silicon oxide film.

Claims (2)

For a semiconductor layer formed on a supporting substrate in a state of being electrically insulated from the supporting substrate, both an insulating isolation trench having a deep trench structure reaching the insulating function portion and a shallow trench by STI (Shallow Trench Isolation) technology are provided. A method of manufacturing a semiconductor device, comprising:
A film forming step of sequentially forming an insulating film, a stopper film made of a material having etching selectivity with respect to an oxide semiconductor, and a mask film made of an oxide semiconductor on the semiconductor layer,
A trench etching mask having a layer structure is formed by forming an insulating isolation trench opening and a shallow trench opening corresponding to the formation positions of the insulating isolation trench and the shallow trench, respectively, in the laminated film formed by this film forming process. Forming an opening,
An oxide film forming step of covering a region of the semiconductor layer facing the shallow trench opening with an oxide semiconductor film;
The semiconductor layer is anisotropically etched by performing a reactive ion etching using the trench etching mask by using a reactive gas having a high etching selectivity between a semiconductor and an oxide semiconductor, thereby opening the insulating isolation trench. A first etching step of forming a deep trench at a position corresponding to the portion;
The reactive ion etching using the trench etching mask is performed using a reactive gas having a low etching selectivity between a semiconductor and an oxide semiconductor, whereby the oxide semiconductor film and the semiconductor layer are anisotropically etched to form the shallow surface. A second etching step of forming a trench at a position corresponding to the partial trench opening;
A trench filling step of filling the deep trench and the trench by depositing an oxide semiconductor film by a chemical vapor deposition method;
A planarization step of removing the oxide semiconductor film and the mask film deposited in the trench backfilling step by a chemical mechanical polishing method or the like using the stopper film as a stopper to planarize a processed surface;
A removing step of removing the stopper film and the insulating film;
Performing a thermal oxidation step of forming a thermal oxide film on the surface of the semiconductor layer. The oxide film forming step,
A thermal oxidation step of forming a thermal oxide film in a region facing the insulating trench opening and the shallow trench opening in the semiconductor layer;
2. The method of manufacturing a semiconductor device according to claim 1, wherein a combination of the thermal oxide film and an oxide film removing step of removing a portion corresponding to the insulating isolation trench opening is provided.

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