JP2004055848A - Method of connecting terminal between chips, circuit board manufactured by the method, and fire detector provided with the circuit board - Google Patents

Method of connecting terminal between chips, circuit board manufactured by the method, and fire detector provided with the circuit board Download PDF

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Publication number
JP2004055848A
JP2004055848A JP2002211651A JP2002211651A JP2004055848A JP 2004055848 A JP2004055848 A JP 2004055848A JP 2002211651 A JP2002211651 A JP 2002211651A JP 2002211651 A JP2002211651 A JP 2002211651A JP 2004055848 A JP2004055848 A JP 2004055848A
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Prior art keywords
chip
optical element
integrated circuit
electrode
light
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JP2002211651A
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Japanese (ja)
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JP4603231B2 (en
Inventor
Sadayuki Sumi
角 貞幸
Mitsuhiro Kani
可児 充弘
Takamasa Sakai
酒井 孝昌
Shigenari Takami
高見 茂成
Shoichi Oka
岡 昭一
Naoyuki Nishikawa
西川 尚之
Koji Sakamoto
阪本 浩司
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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Priority to JP2002211651A priority Critical patent/JP4603231B2/en
Publication of JP2004055848A publication Critical patent/JP2004055848A/en
Application granted granted Critical
Publication of JP4603231B2 publication Critical patent/JP4603231B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of connecting terminals between chips, by which the noise resistances of connected terminals can be improved and, at the same time, the sizes of circuit boards can be reduced, and to provide a circuit board manufactured by the method and a fire detector provided with the circuit board. <P>SOLUTION: On the circuit board 2, composed of a printed board, a photodiode PD having a light-receiving surface for receiving light and formed in a chip and an integrated circuit chip IC1 for optical element which processes the output of the photodiode PD into signals, are mounted close to each other. The electrodes of the photodiode PD and those of the integrated circuit chip IC1 are connected directly to each other via wires 80 and 80', composed of extra fine metallic wires by the wiring bonding method. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、受光面又は発光面の内の少なくとも何れか一方を備えた光素子チップと、光素子チップの出力を信号処理する光素子用集積回路チップとを同一の基板に実装し、両チップの端子間を電気的に接続するチップ間端子接続方法及びそれを用いて作製した回路基板とそれを具備する火災感知器に関するものである。
【0002】
【従来の技術】
従来より、例えば煙感知器のような光素子と光素子用集積回路とを組み合わせた電子機器モジュールでは、光素子と光素子用集積回路の両方、或いは何れか一方が半導体チップをリードフレームなどに実装したディスクリートの状態で組み立てられていた。図21は従来のチップ間端子接続方法を用いて作製された回路基板の断面図であり、1枚の回路基板100にディスクリートの光素子101と光素子用集積回路102とが実装されていた。
【0003】
【発明が解決しようとする課題】
上述した従来のチップ間端子接続方法では、光素子101と光素子用集積回路102とにディスクリート部品を使用しているため、光素子101と光素子用集積回路102との間の配線長Lが長くなっていた。一般的に光素子101の出力インピーダンスはハイインピーダンスであるから、光素子101と光素子用集積回路102との間の配線長Lが長くなると、ノイズが重畳しやすくなり、耐ノイズ性が悪化するという問題があった。また、耐ノイズ性を確保するために光素子101と光素子用集積回路102の周囲全体をシールドケース103で覆う必要があり、その結果、回路基板全体が大型化し、材料コストが高くなるという問題があった。
【0004】
本発明は上記問題点に鑑みて為されたものであり、その目的とするところは、耐ノイズ性を向上させるとともに回路基板の小型化を図ったチップ間端子接続方法及びそれを用いて作製した回路基板を具備する火災感知器を提供することにある。
【0005】
【課題を解決するための手段】
上記目的を達成するために、請求項1の発明では、受光面又は発光面の内の少なくとも何れか一方を有する光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子チップの電極と光素子用集積回路チップの電極とをワイヤボンディング法により直接接続することを特徴とする。
【0006】
請求項2の発明では、請求項1の発明において、光素子チップの電極又は光素子用集積回路チップの電極の内、少なくとも何れか一方に金属突起を形成して、この金属突起にボンディングワイヤを接続することを特徴とする。
【0007】
請求項3の発明では、受光面又は発光面の内の少なくとも何れか一方を有する光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、回路基板の表面に光素子チップの実装部位付近から光素子用集積回路チップの実装部位付近まで配線パターンを形成し、当該配線パターンに光素子チップの電極と光素子用集積回路チップの電極とをそれぞれワイヤボンディング法で接続したことを特徴とする。
【0008】
請求項4の発明では、受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子チップの受光面又は発光面の何れかが設けられた面に電極を設けるとともに、回路基板に、当該回路基板を厚み方向に貫通し光素子チップの受光面又は発光面の何れかを露出させる貫通孔と、光素子チップの電極に電気的に接続される光素子用電極と、光素子用集積回路チップの電極が電気的に接続される集積回路用電極と、光素子用電極と集積回路用電極との間を直線的に接続する配線パターンとを設け、貫通孔から受後面又は発光面の何れかが露出するようにして光素子チップを回路基板上に配置し、光素子チップ及び光素子用集積回路チップの電極をそれぞれ光素子用電極及び集積回路用電極にフリップチップボンディングによって接続したことを特徴とする。
【0009】
請求項5の発明では、請求項4の発明において、光素子用集積回路チップをフィルムタイプのアンダーフィル樹脂で封止したことを特徴とする。
【0010】
請求項6の発明では、受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子チップの受光面又は発光面の何れかが設けられた面に電極を設けるとともに、回路基板に、当該回路基板を厚み方向に貫通し光素子チップの受光面又は発光面の何れかを露出させる貫通孔を設けるとともに、光素子用集積回路チップの電極とこの電極に接続される光素子チップの電極とが回路基板の厚み方向において重なるようにして光素子用集積回路チップが埋め込まれる凹部を貫通孔の近傍に設け、この凹部内に光素子用集積回路チップを埋め込んだ後、貫通孔から受光面又は発光面の何れかが露出するように光素子チップを回路基板及び光素子用集積回路チップ上に配置して、光素子チップの電極と、回路基板の電極及び光素子用集積回路チップの電極とをそれぞれフリップチップボンディングによって直接接続したことを特徴とする。
【0011】
請求項7の発明では、請求項4乃至請求項6の何れかに記載の発明において、貫通孔を、赤外線帯域から可視光帯域までの光に対して透光性を有する略透明の封止材料で封止したことを特徴とする。
【0012】
請求項8の発明では、受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子集積回路チップにおける実装面と反対側の表面に電極を設け、光素子用集積回路チップの表面の所定位置に、受光面又は発光面の何れかを光素子用集積回路チップと反対側に向けた状態で光素子チップを載置固定した後、光素子チップの電極と光素子用集積回路チップの電極とをワイヤボンディング法により直接接続したことを特徴とする。
【0013】
請求項9の発明では、受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、回路基板には光素子用集積回路チップの実装位置の周辺に中継用の配線パターンを設けるとともに、光素子集積回路チップにおける実装面と反対側の表面に電極を設け、光素子用集積回路チップの表面の所定位置に、受光面又は発光面の何れかを光素子用集積回路チップと反対側に向けた状態で光素子チップを載置固定した後、光素子チップ及び光素子用集積回路チップの電極をそれぞれ配線パターンにワイヤボンディング法により接続したことを特徴とする。
【0014】
請求項10の発明では、請求項9の発明において、光素子用集積回路チップを封止するアンダーフィル樹脂を、光素子用集積回路チップの外周の少なくとも一部において、光素子用集積回路チップの端面から外側にはみ出ないように設けたことを特徴とする。
【0015】
請求項11の発明では、請求項1乃至請求項10の何れかに記載の発明において、光素子用集積回路チップを、光素子チップの指向角度を狭めないように遮光性を有する略黒色の封止材料で封止した後に、封止材料で封止された光素子用集積回路チップとともに光素子チップの受光面又は発光面の何れかを赤外線帯域から可視光帯域までの光に対して透光性を有する略透明の封止材料で封止したことを特徴とする。
【0016】
請求項12の発明では、請求項11に記載の発明において、遮光性を有する略黒色の封止材料として略黒色のエポキシ樹脂を用いたことを特徴とする。
【0017】
請求項13の発明では、請求項11又は請求項12に記載の発明において、透光性を有する略透明の封止材料として赤外線帯域から可視光帯域までの光に対して透光性を有するエポキシ樹脂を用いたことを特徴とする。
【0018】
請求項14の発明は、請求項1乃至請求項13の何れかに記載のチップ間端子接続方法を用いて作製された回路基板である。
【0019】
請求項15の発明では、外部からの煙の侵入を許容するとともに外光の入射を防止する隔壁が形成されたラビリンス壁と、ラビリンス壁によって囲まれる煙感知室に発光素子からの光を配光する発光側の光学部材と、受光した光の光量に応じた電気信号を発生する光素子チップと、煙感知室に侵入した煙により散乱された発光素子からの光を光素子チップに集光させる受光側の光学部材と、光素子チップの出力を信号処理する光素子用集積回路チップを含み光素子チップの出力から火災の発生を検出する検出回路と、光素子チップ及び光素子用集積回路チップを含む検出回路の回路部品が実装され、請求項1乃至請求項13の何れかに記載のチップ間端子接続方法を用いて作製された回路基板とを備えて成ることを特徴とする。
【0020】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて説明する
(実施形態1)
本発明に係るチップ間端子接続方法を火災感知器の具備する回路基板に適用した実施形態について、図1及び図9〜図20を参照して説明する。
【0021】
先ず、火災感知器の回路構成を図20に基づいて説明する。この火災感知器は煙を感知する煙感知機能と、熱を感知する熱感知機能の両方を備えた複合型のものであり、後述する煙感知室Sに赤外光を照射する発光ダイオードLEDと、発光ダイオードLEDから照射された赤外光の煙感知室S内に侵入した煙による散乱光を受光するフォトダイオードPDと、投受光回路50と、マイクロコンピュータ(以下、マイコンと言う)60と、伝送回路61とで構成される。
【0022】
投受光回路50は、発光ダイオードLEDに流す電流を制御する発光電流制御回路51と、フォトダイオードPDの出力電流を電圧信号に変換するI/V変換回路52とを備え、I/V変換回路52の出力電圧はゲイン切り替え回路53によって所定のゲインで増幅され、ゲイン調整回路54によって電圧レベルが調整され、さらにオフセット調整回路55によってオフセット電圧が調整された後、マイコン60に出力される。マイコン60では投受光回路50の出力をA/D変換して、予め設定されたしきい値レベルと比較しており、投受光回路50の出力がしきい値レベルを超えると、煙の濃度が所定の濃度に達したことを示す発報信号を伝送回路61に出力し、伝送回路61はこの発報信号を多重伝送信号により図示しない火災受信器へ送信する。また、投受光回路50は、マイコン60から入力されるテスト信号に応じて、発光電流制御回路51の出力を変化させるとともに、ゲイン切り替え回路53のゲインを選択的に切り替える感度調整制御回路56を備えている。また、図20では図示を省略しているが、マイコン60にはサーミスタ6の出力が入力されており、サーミスタ6の出力から周囲の温度を監視している。
【0023】
次に火災感知器の構造を図9〜図19に基づいて説明する。この火災感知器は図9〜図11に示すように天井面などの造営面に取着されるボディ1と、プリント基板からなり発光ダイオードLEDやチップ化されたフォトダイオードPDや後述する煙検知回路の回路部品が実装される回路基板2と、外部からの煙の侵入を許容するとともに外光の入射を防止するラビリンス壁9によって周りが囲まれた水平断面が略円形の煙感知室Sを下面側に具備し、煙感知室S内に光学系の部品が取着されるとともに、発光ダイオードLED及びフォトダイオードPDを光学系の部品と対向させた状態で回路基板2が上面に取り付けられる光学基台3と、光学基台3に設けた煙感知室Sの内部に虫などが侵入するのを防止する防虫カバー4と、保護カバー5とで構成される。
【0024】
ボディ1は略円板状の主部1aと、主部1aの外周縁から上方に突出する側壁1bとを連続一体に形成して構成され、主部1aの下面略中央には丸穴1cが開口し、この丸穴1c内に回路基板2が固定された光学基台3及び防虫カバー4を保持した保護カバー5の上端部が挿入され、固定される。
【0025】
回路基板2の下面には発光ダイオードLED及びサーミスタ6が、それぞれ発光面及び熱感知部を下方に突出させた状態で実装されている。また、図1(a)に示すように、回路基板2の下面にはチップ化されたフォトダイオードPD(光素子チップ)と、上述のI/V変換回路52などをチップ化した光素子用集積回路チップIC1が近接して実装されている。なお、フォトダイオードPD及び光素子用集積回路チップIC1の裏面には電極が形成されており、回路基板2の表面に形成された導体パターン2a,2aにそれぞれダイボンドされている。また、フォトダイオードPD及び光素子用集積回路チップIC1の上面にはそれぞれ電極(図示せず)が形成されており、両電極間はワイヤボンディング法によりアルミニウムや金などの金属細線からなるワイヤ80を介して直接接続されている。このように、本実施形態では同一の回路基板2にチップ化されたフォトダイオードPDと光素子用集積回路チップIC1とをダイボンドし、出力電流が微少であるフォトダイオードPDの電極と光素子用集積回路チップIC1の電極とをワイヤボンディングにより直接接続しているので、従来のチップ間端子接続方法に比べて両電極間を短い距離で接続することができ、したがって回路基板の小型化を図るとともに、両電極間を接続するボンディングワイヤにノイズがのりにくくなって、耐ノイズ性が向上する。
【0026】
ここで、ワイヤボンディング法は超音波法と熱圧着超音波併用法の二つに大別されるが、何れの手法を用いてワイヤボンディングを行っても良いことは言うまでもない。この場合、線材を通す貫通孔が中心に設けられた円柱状で先端部の形状が円錐形状に形成された治具(キャピラリ)を用いて施工される。尚、超音波法の場合には主としてアルミニウムの線材が、熱圧着超音波併用法の場合には主として金の線材が用いられる。
【0027】
熱圧着超音波併用法により例えば直径が約20μmの金のワイヤ80を用いてボンディングする場合は、最初に接続する(1stボンディングとも言う)方は、ワイヤ80の先端に直径が約60μmの微少なボールを形成して、その先端を熱圧着超音波併用法によりボンディングした後、キャピラリを次に接続する(2ndボンディングとも言う)電極の位置に移動させて、キャピラリの先端を電極に押し当てた上で、熱圧着超音波併用法によりボンディングする。なお、ベアチップ上の電極と基板或いはリードフレームとの間をボンディングワイヤにより接続する場合は、一般的にベアチップ上の電極に1stボンディングを行い、主に基板やリードフレームなどの接続先に2ndボンディングを行うのであるが、本実施形態の場合には図1(a)に示すように光素子用集積回路チップIC1の電極に1stボンディングしても良いし、図1(b)に示すようにフォトダイオードPDの電極に1stボンディングしても良い。
【0028】
また、図1(c)に示すようにアルミニウム細線よりなるワイヤ80’を用いて超音波法でボンディングする場合は、チップ電極と基板側の電極とが同じであり、工程の順番はあるもののボンディング自体を1stボンディング、2ndボンディングというように捉えていない。従って、超音波法ではフォトダイオードPDの電極と光素子用集積回路チップIC1の電極との接続方法について特に規定はなく、また工程上の順番も何れを最初にしても良い。
【0029】
尚、フォトダイオードPD及び光素子用集積回路チップIC1を樹脂封止する場合に、フォトダイオードPDと光素子用集積回路チップIC1を別々の樹脂で封止すると、封止樹脂が硬化する際に発生する熱応力の違いによってワイヤ80の接合部に引っ張り応力が加わるという問題があるが、フォトダイオードPD及び光素子用集積回路チップIC1を透光性を有する1種類の樹脂で封止するようにすれば、ワイヤ80の接合部に熱応力が加わって不具合となるのを防止できる。
【0030】
光学基台3は図12〜図14に示すように黒色の合成樹脂により、略円板状の底板7と、底板7の上面に突設された四角枠状の側壁8と、底板7下面の外周部に沿って配置された水平断面が略く字形の複数の隔壁9aからなるラビリンス壁9とを一体に形成して構成される。
【0031】
ラビリンス壁9を構成する隔壁9aは反射が生じないように黒色に形成されており、中間部の屈曲部位が突出する方向を隣接する隔壁9aと同じ向きにし、中間部の屈曲部位が隣接する隔壁9aの両端部の間に入り込むようにして所定の間隔をおいて配置されている。隣接する隔壁9aの間にできる煙導入路は、一端が外部と連通して煙導入口となり、他端が煙感知室Sに連通しており、煙導入路の中間部を屈曲させることによって、外光が煙感知室S内に入射しにくくなっている。
【0032】
光学基台3の底板7と側壁8とで囲まれる凹所10内には、発光ダイオードLED、フォトダイオードPD、光素子用集積回路チップIC1及びサーミスタ6が実装された面を底板7側にして回路基板2が納装される。光学基台3の底板7には発光ダイオードLED及びフォトダイオードPDにそれぞれ対応する部位に下方に突出する突台部19,20が突設されており、これらの突台部19,20には底板7を貫通する貫通孔11a,11bが形成されている。各突台部19,20には、貫通孔11a,11bにそれぞれ連続し、光学基台3の中心方向に向かって延びる溝19a,20aが形成されており、これらの溝19a,20a内に発光側及び受光側の光学部材としてのプリズムレンズ12,13が取り付けられる。ここで、プリズムレンズ12,13は一方の面を貫通孔11a,11bと対向させ、他方の面を煙感知室Sの中心方向に向けた状態で光学基台3に取り付けられ、プリズムレンズ12,13の上側及び左右両側が突台部19,20によって覆われる。すなわち、プリズムレンズ12,13は、図12(a)に示すようにそれぞれの光軸L1,L2が煙感知室Sの中心方向を向き、且つ所定の角度で交差するように配置されている。
【0033】
上述のようにプリズムレンズ12,13は発光ダイオードLEDの発光面、フォトダイオードPDの受光面にそれぞれ対向しており、発光ダイオードLEDの発光はプリズムレンズ12によって集光されて煙感知室Sに照射される。そして、煙感知室S内に煙が侵入すると、煙の粒子によってプリズムレンズ12から照射された光が散乱され、プリズムレンズ13に入射する。プリズムレンズ13に入射した光は、プリズムレンズ13によってフォトダイオードPDの受光面に集光されるので、フォトダイオードPDの出力の増加から煙の侵入を検出することができる。尚、プリズムレンズ12,13はそれぞれの光軸L1,L2が所定の角度で交差するように配置されているので、プリズムレンズ12から照射された発光ダイオードLEDの光が直接プリズムレンズ13に入射することはない。
【0034】
ところで、フォトダイオードPDからの出力電流は微少であり、静電ノイズのような外来ノイズに対して弱いため、このような外来ノイズからフォトダイオードPDをシールドする必要がある。そこで、本実施形態ではフォトダイオードPDと対向する光学基台3の部位に、一面が開口した箱状のシールドカバー14をインサート成形しており、凹所10内に回路基板2を納装すると、回路基板2に実装されたフォトダイオードPD及び煙検出回路の周りをシールドカバー14が覆い、フォトダイオードPDと煙検出回路とを静電遮蔽するようになっている。なお、シールドカバー14には回路基板2側に突出するアースピン14aが設けられており、このアースピン14aは回路基板2に設けたスルーホールに挿通され、回路基板2のグランドライン(図示せず)に半田付けされる。また、シールドカバー14には、貫通孔11bに連通する連通孔14bが形成されており、この連通孔14bを通ってプリズムレンズ13で集光された光がフォトダイオードPDの受光面に照射される。
【0035】
また、光学基台3には4本の端子ピン15がインサート成形されており、各端子ピン15は回路基板2に設けたスルーホール(図示せず)に挿通され、半田付けされることによって、各端子ピン15が回路基板2の配線パターンに電気的に接続されるとともに、回路基板2から反対側に突出する各端子ピン15の先端部が外部接続端子となる。また、光学基台3にインサート成形された端子ピン15を回路基板2に半田付けすることによって、光学基台3に回路基板2が保持される。
【0036】
ここで、光学基台3の製造工程を図15〜図19を参照して簡単に説明する。まず、図15に示すように金属材料により帯板状に形成されたフープ材40を打ち抜き、さらに図15中の斜線部分を紙面の奧側に折り曲げて、図16(a)(b)に示すようにシールドカバー14を箱状に形成するとともに、端子ピン15をフープ材40の平面方向と略直交する方向に突出させる。その後、図17(a)(b)に示すようにフープ材40に底板7及び側壁8からなる基台部分をインサート成形(一次成形)し、図18(a)(b)に示すようにラビリンス壁9を二次成形した後、フレーム部分を切断することにより図19(a)(b)に示すような形状に形成される。尚、フープ材40に底板7及び側壁8からなる基台部分とラビリンス壁9とを一度にインサート成形するようにしても良いことは言うまでもない。
【0037】
このように、シールドカバー14及び端子ピン15と光学基台3とは同時成形(インサート成形)により一体化されているので、部品点数を削減して、組立作業の作業性を向上させることができる。また、光学基台3とラビリンス壁9とを一体化しており、部品点数を少なくして組立作業性を向上させるとともに、ラビリンス壁9と光学基台3との位置決め精度が高くなって、迷光の発生を抑制することができる。また、シールドカバー14と端子ピン15とは1枚の板金を打ち抜き、曲げ加工を施すことによって形成されているので、シールドカバー14と端子ピン15とを加工する工程を容易に自動化することができ、製造コストを低減できる。
【0038】
また、防虫カバー4は、図9〜図11に示すように絶縁性を有する合成樹脂により有底円筒状に形成される。防虫カバー4の底板4aには光学基台3に設けた挿通孔11cと連通し、回路基板2に実装されたサーミスタ6を挿通するための貫通孔4dが形成され、周壁4bには複数の孔が格子状に開口するメッシュ部4cが形成されている。この防虫カバー4は光学基台3の下端部を筒内に挿入した状態で光学基台3に取り付けられており、ラビリンス壁9の周りをメッシュ部4cが形成された周壁4bで覆っているので、ラビリンス壁9で囲まれた煙感知室Sに虫等の異物が侵入するのを防止できる。また、防虫カバー4の底板4aには、図11に示すように、光学基台3の底板7に設けた突台部19,20と対向する部位に上側(光学基台3側)に向かって突出し、突台部19,20に設けた溝19a,20aと嵌合する蓋部21,22が一体に形成されている。而して、光学基台3に防虫カバー4を被せると、防虫カバー4に設けた蓋部21,22が光学基台3に設けた溝19a,20aとそれぞれ嵌合し、プリズムレンズ12の出射面及びプリズムレンズ13の入射面の周りを突台部19,20及び蓋部21,22で囲むことにより、光学的に密閉することができるから、外光などの余計な光が入射するなどして誤動作するのを防止できる。
【0039】
また、保護カバー5は合成樹脂により有底円筒状に形成されており、周壁5aの上端部には外側に突出する係合爪16が突設され、周壁5aの略下半分には円周方向に沿って延びる帯状の開口17が複数開口し、底板5bからは上方に向かって突出し、先端部が防虫カバー4の底板4aと当接する複数のリブ18が突設されている。この火災感知器を組み立てた状態では、サーミスタ6が防虫カバー4の貫通孔4dから下方に突出し、サーミスタ6の先端部が防虫カバー4の底板4aと保護カバー5の底板5bとの間に配置される。尚、複数のリブ18はサーミスタ6を中心として放射状に配置されており、開口5cから内部に流入した空気がサーミスタ6の感熱部に当たるよう、空気の流れを整流している。
【0040】
この火災感知器を組み立てる際は、先ず回路基板2に発光ダイオードLED、フォトダイオードPD、光素子用集積回路チップIC1、サーミスタ6及び煙感知回路の回路部品を実装し、この回路基板2を光学基台3の凹所10内に挿入して、シールドカバー14のアースピン14a及び端子ピン15を回路基板2に半田付けし、回路基板2を光学基台3に固定する。次に、保護カバー5の筒内に防虫カバー4と、回路基板2が取り付けられた光学基台3とを挿入して、防虫カバー4及び光学基台3を保護カバー5に保持させた後、この保護カバー5の上端部をボディ1の丸穴1c内に挿入すると、保護カバー5の上端部に突設した係合爪16と丸穴1cの内周面に形成された係合段部1dとが凹凸係合して、保護カバー5がボディ1に結合されるのである。
【0041】
(実施形態2)
本発明の実施形態2を図2(a)(b)に基づいて説明する。上述した実施形態1では、フォトダイオードPDの電極と光素子用集積回路チップIC1の電極とをワイヤボンディングにより直接接続しているのに対して、本実施形態では図2(a)に示すように、フォトダイオードPDの電極上に金属突起70を形成し、この金属突起70と光素子用集積回路チップIC1の電極との間をワイヤボンディング法によりワイヤ80を介して電気的に接続している。尚、フォトダイオードPDの電極と光素子用集積回路チップIC1の電極との接続方法以外は実施形態1と同様であるので、同一の構成要素には同一の符号を付してその説明は省略する。
【0042】
上述のように本実施形態ではフォトダイオードPDの電極上に形成した金属突起70にワイヤ80を接続しているので、ボンディングの強度が安定して、両電極間の電気的接続の信頼性を向上させることができる。尚、本実施形態ではフォトダイオードPDの電極上に金属電極70を形成して、この金属電極70にワイヤ80を接続しているが、図2(b)に示すようにフォトダイオードPDの電極と光素子用集積回路チップIC1の電極の両方に金属突起70,70’を形成し、両金属突起70,70’間をワイヤ80で直接接続しても良いし、光素子用集積回路チップIC1の電極のみに金属の突起を設け、この突起とフォトダイオードPDの電極との間をワイヤ80で直接接続しても良い。
【0043】
尚、この場合はワイヤボンディング法として実施形態1で説明した熱圧着超音波併用法を用い、1stボンディングを行う際にボールを形成した直後に、ワイヤを引っ張り、キャピラリによって突起に変形したボールのみを残す方法で金属突起70が形成される。ここに、金属突起70の材料としては、ワイヤボンディングが行える材料(例えば金、アルミニウム、銀、ニッケルなど)であれば、どのような材料でも良い。
【0044】
また、フォトダイオードPD及び光素子用集積回路チップIC1を樹脂封止する場合に、フォトダイオードPDと光素子用集積回路チップIC1を別々の樹脂で封止すると、封止樹脂が硬化する際に発生する熱応力の違いによってワイヤ80の接合部に引っ張り応力が加わるという問題があるが、フォトダイオードPD及び光素子用集積回路チップIC1を透光性を有する1種類の樹脂で封止するようにすれば、ワイヤ80の接合部に熱応力が加わって不具合となるのを防止できる。
【0045】
(実施形態3)
本発明の実施形態3を図3(a)(b)に基づいて説明する。上述した実施形態1では、フォトダイオードPDの電極と光素子用集積回路チップIC1の電極とをワイヤボンディング法により直接接続しているのに対して、本実施形態では図3(a)(b)に示すように、フォトダイオードPD及び光素子用集積回路チップIC1の電極を、それぞれ回路基板2の基板面に形成された電解メッキ用の給電配線2b(配線パターン)にボンディングワイヤを介して接続している。尚、フォトダイオードPDの電極と光素子用集積回路チップIC1の電極との接続方法以外は実施形態1と同様であるので、同一の構成要素には同一の符号を付してその説明は省略する。
【0046】
図3(b)に示すように、回路基板2の基板面(上面)には、フォトダイオードPD及び光素子用集積回路チップIC1の背面電極が実装される正方形状の導体パターン2a,2aを形成してあり、両導体パターン2a,2aの間の部位には電解メッキ用の給電配線2bを形成してある。この給電配線2bは略T形であって、横棒部分の両端が導体パターン2a,2aの近傍に位置するように配置されている。そして、給電配線2bの横棒部分と縦棒部分の分岐部Aを切断することによって、給電配線2bの横棒部分を所望の長さに形成し、この横棒部分にフォトダイオードPDの電極と光素子用集積回路チップIC1の電極(図示せず)とをそれぞれワイヤボンディング法により接続し、両電極間を給電配線2bを介して電気的に接続してある。このように、フォトダイオードPDの電極と給電配線2bとの間、光素子用集積回路チップIC1の電極と給電配線2bとの間をそれぞれワイヤボンディング法で接続しているので、従来のチップ間端子接続方法に比べて両電極間を短い距離で接続することができ、したがって回路基板2の小型化を図るとともに、両電極間を接続するボンディングワイヤにノイズがのりにくくなって、耐ノイズ性が向上する。また、給電配線2bの分岐部Aを分断して、両電極間を接続する配線パターンを形成しているので、給電配線がアンテナとなってノイズがのるのを防止できる。また、フォトダイオードPD及び光素子用集積回路チップIC1を樹脂封止する場合に、フォトダイオードPDと光素子用集積回路チップIC1を別々の樹脂で封止すると、封止樹脂が硬化する際に発生する熱応力の違いによってワイヤ80の接合部に引っ張り応力が加わるという問題があるが、フォトダイオードPD及び光素子用集積回路チップIC1を透光性を有する1種類の樹脂で封止するようにすれば、ワイヤ80の接合部に熱応力が加わって不具合となるのを防止できる。
【0047】
ここで、給電配線2bの横棒部分と縦棒部分との分岐部Aを分断する方法としては、例えば金型によるパンチング(抜き加工)や、ドリル或いはルータなどを用いた機械加工により貫通孔を形成することで分断すれば良いが、貫通していない穴を形成するようにしても良い。尚、ワイヤボンディング後に、外部環境から光素子を保護するために光素子を透明な樹脂で封止する場合、一般的に透明な樹脂は低粘度で流れやすいから、回路基板2の裏面側へ流れ出るのを防ぐために、貫通していない穴を形成することで給電配線2bを分断するのが好ましい。
【0048】
(実施形態4)
本発明の実施形態4を図4(a)(b)を参照して説明する。本実施形態では、図4(a)に示すようにフォトダイオードPDの指向角度を妨げないよう光素子用集積回路チップIC1を遮光性の略黒色の封止材料(以下、遮光性封止剤と言う)71で封止した後、封止後の光素子用集積回路チップIC1とともに、フォトダイオードPDの受光面を赤外線帯域から可視光帯域の光に対して透光性を有する略透明の封止材料(以下、透光性樹脂と言う)72で封止している。尚、遮光性封止剤71及び透光性樹脂72以外の構成は実施形態1と同様であるので、同一の構成要素には同一の符号を付してその説明は省略する。
【0049】
ここに、遮光性封止剤71としては、通常半導体ベアチップの封止に用いるエポキシ樹脂を用いれば良く、本実施形態では熱硬化型の液状のエポキシ樹脂(松下電工株式会社製の型番CV5181D)を使用している。なお、樹脂封止の範囲で決まる実装エリアを小型化するために、高粘度で高チクソ性を有する樹脂を用いるのが好ましく、そのため樹脂中のシリカに代表されるフィラーによって粘度やチクソ性を調整している。
【0050】
また、透光性樹脂72としては、通常半導体ベアチップの封止に用いるエポキシ樹脂を用いれば良く、本実施形態では熱硬化型のエポキシ樹脂(松下電工株式会社製の型番CV5130A)を使用している。このエポキシ樹脂は赤外線帯域から可視光帯域の光に対して透光性を有しており、主剤と硬化剤からなる二液型のものである。
【0051】
以下に樹脂封止の手順について簡単に説明する。先ず、光素子用集積回路チップIC1の周囲に略黒色の遮光性封止剤71を塗布する。ここで、遮光性封止剤71は高粘度で高チクソ性の樹脂であるから、光素子用集積回路チップIC1の電極とワイヤ80との接続部分という最低限の範囲のみを封止することができる。これは、単位時間当たりの塗布量が少ない、空気圧による樹脂押し出し(ディスペンス法)という液状樹脂塗布方法において生産性を向上させるためである。尚、一旦固形に成形し、その後加熱することで一時的に液状とした後、再び硬化させるようなタイプの従来周知の封止剤を用い、封止したい部分を除いてマスクで保護した上で基板全体を加熱し、この基板を上部が開口した密閉容器内に配置し、この密閉容器内に送風撹拌している状態で開口部に封止樹脂を置いて、加熱された基板にぶつかった粉状の樹脂がその熱で溶融付着することで必要な部分にだけ樹脂を付着させる方法や、図4(b)に示すように金型を用いたトランスファ成形によって必要な部分のみを封止する方法で封止しても良い。
【0052】
このように、光素子用集積回路チップIC1の周囲に略黒色の遮光性封止剤71を塗布し、加熱硬化した後に略透明の封止剤72を用いて、光素子チップを含み、光素子チップと光素子用集積回路チップの入出力端子や、それに対応した基板上の配線パターンの露出部や、実施形態1〜3で説明したボンディングワイヤを覆うように塗布することで、光素子チップの指向角度を妨げることなく、光素子チップやボンディングワイヤを保護できる。尚、暗黒色の遮光性封止剤71が略透明の封止剤72から露出するように塗布されていても良い。
【0053】
(実施形態5)
本発明の実施形態5を図5(a)〜(d)を参照して説明する。上述した実施形態1ではフォトダイオードPDと光素子用集積回路チップIC1とをフェースアップの状態で回路基板2に実装しているが、本実施形態ではフォトダイオードPDと光素子用集積回路チップIC1とをフェースダウンの状態で回路基板2に実装している。尚、フォトダイオードPD及び光素子用集積回路チップIC1の実装方法以外は実施形態1と同様であるので、同一の構成要素には同一の符号を付して、その説明は省略する。
【0054】
本実施形態では回路基板2に、回路基板2を厚み方向に貫通する貫通孔2cを設けており、フォトダイオードPDの受光面を貫通孔2cに臨ませるようにしてフォトダイオードPDを配置し、受光面と同じ面にある電極に設けたバンプ73を回路基板2に形成された基板側電極(図示せず)にフリップチップボンディングすることで、フォトダイオードPDの電極と回路基板2との間を電気的に接続する。なお、図5(b)に示すようにフォトダイオードPDには、受光面と同じ面の4隅に電極を形成してあり、各電極にバンプ73を形成しているので、回路基板2に取り付けた状態で回路基板2に対する平行度を確保することができる。
【0055】
また、光素子用集積回路チップIC1の実装面にもバンプ74を形成してあり、バンプ74を回路基板2に形成された基板側電極(図示せず)にフリップチップボンディングすることで、光素子用集積回路チップIC1の電極と回路基板2との間を電気的に接続する。ここで、フォトダイオードPDと光素子用集積回路チップIC1との間を電気的に接続する配線パターン2aは、フォトダイオードPDの電極と光素子用集積回路チップIC1の電極との間を最短距離で接続するようにパターニングされている。
【0056】
また、フリップチップ実装を行った回路基板2とフォトダイオードPDとの間の隙間から受光面に光が差し込むのを防止するとともに、バンプ73,74と基板側電極との接合強度を保持して信頼性を向上させるために、フリップチップ実装したフォトダイオードPD及び光素子用集積回路チップIC1と回路基板2との間の隙間にアンダーフィル樹脂75を注入し、硬化させている。尚、図5(c)に示すようにフリップチップ実装の前に回路基板2の上面にアンダーフィル樹脂75を塗布し、その後バンプ73,74がそれぞれ形成されたフォトダイオードPD及び光素子用集積回路チップIC1を回路基板2に押し付けて、基板側電極と接触させた状態で樹脂を加熱硬化するようにしても良い(先塗り法)。
【0057】
ここに、光素子には光が入射する必要があるため、光素子の受光面或いは発光面を保護するアンダーフィル樹脂に透明樹脂を用いているが、さらにその外側から暗黒色の遮光樹脂を塗布して、外側からの光の入射を遮断するようにしても良い。また、フォトダイオードPDに隣接して実装される光素子用集積回路チップIC1のフリップチップ部に塗布して、この光素子用集積回路チップIC1を封止する暗黒色の遮光樹脂の一部でフォトダイオードPDの透明封止剤の外側を封止する封止剤を兼用しても良い。尚、上記構成でバンプ及び回路基板2側の接続端子を覆う樹脂は略黒色の遮光樹脂でも良いし、透明な樹脂でも良い。
【0058】
(実施形態6)
上述した実施形態5では回路基板2の表面に液状のアンダーフィル樹脂75を塗布し、フォトダイオードPD及び光素子用集積回路チップIC1を回路基板2に押し付けて、回路基板2の電極と接触させた状態で樹脂を加熱硬化させることで、封止しているが、本実施形態では図6(a)(b)に示すようにフィルムタイプのアンダーフィル樹脂76で封止している。フィルムタイプの場合にはアンダーフィル樹脂76を予め所定の形状に形成しておくことで、封止帯域を最低限の帯域に限定することができ、図6(a)(b)では光素子用集積回路チップIC1の下面の略全面とフォトダイオードPDのボンディング部のみをカバーするような形状に形成してある。尚、アンダーフィル樹脂76以外は実施形態5と同様であるので、同一の構成要素には同一の符号を付して、その説明は省略する。
【0059】
ここに、フィルムタイプのアンダーフィル樹脂76は絶縁性樹脂あるいは異方性導電性樹脂であり、図6(a)に示すように回路基板2の配線パターン2a上にフィルムタイプのアンダーフィル樹脂76を載置して、バンプ73,74がそれぞれ形成されたフォトダイオードPD及び光素子用集積回路チップIC1を回路基板2の配線パターン2aと位置合わせした上で加圧及び加熱することにより、バンプ73,74と基板側電極とを接合する。
【0060】
アンダーフィル樹脂76が絶縁性樹脂の場合は、フィルム状のアンダーフィル樹脂76を加熱することで軟化させ、さらにフォトダイオードPD及び光素子用集積回路チップIC1を回路基板2に押し付けることで、フォトダイオードPD及び光素子用集積回路チップIC1にそれぞれ設けたバンプ73,74がアンダーフィル樹脂76を貫通して回路基板2上の配線パターン2aに達し、電気的に接触する。この状態でフィルム状のアンダーフィル樹脂76を硬化させると、常温時ではアンダーフィル樹脂76の硬化、収縮もあって、バンプ73,74と回路基板2の電極との電気的接続が維持され、導通が確保できる。
【0061】
また、アンダーフィル樹脂76が異方性導電樹脂の場合、絶縁性樹脂の中に導電粒子を分散させているため、加熱によってアンダーフィル樹脂76が軟化した状態で、フォトダイオードPD及び光素子用集積回路チップIC1を回路基板2に押し付けることで、フォトダイオードPD及び光素子用集積回路チップIC1にそれぞれ形成したバンプ73,74がフィルム状のアンダーフィル樹脂76を貫通して回路基板2の電極と接触するか、又は、導電粒子を介して回路基板2の電極に電気的に接続されることで、回路基板2の電極と導通する。そして、この状態でフィルム状のアンダーフィル樹脂76を硬化させると、導電粒子を介した導通及びアンダーフィル樹脂76の硬化、収縮によって、バンプ73,74と回路基板2の電極との電気的接続が維持され、導通が確保できる。
【0062】
ところで、本実施形態において、図6(c)に示すように回路基板2に形成した貫通孔2c内に、赤外線帯域から可視光帯域にかけて透光性を有する略透明の封止剤77を充填して、フォトダイオードPDの受光面を封止し、フォトダイオードPDの受光面を保護しても良い。尚、この場合はアンダーフィル樹脂76にフォトダイオードPDの受光面を露出させる孔(例えば正方形の孔)を開けて、枠状に形成するのが望ましく、アンダーフィル樹脂76で封止剤77の流れ出しを防止できる。
【0063】
(実施形態7)
本発明の実施形態7を図7を参照して説明する。上述した実施形態5では回路基板2の上面にフォトダイオードPDと光素子用集積回路チップIC1とをフリップチップ実装しているのに対して、本実施形態では、回路基板2に光素子用集積回路チップIC1を埋め込んだ状態で固定し、フォトダイオードPDを回路基板2にフリップチップ実装して、フォトダイオードPDのバンプ73を光素子用集積回路チップIC1の電極に直接接続している。尚、光素子用集積回路チップIC1の実装方法以外は実施形態5と同様であるので、同一の構成要素には同一の符号を付して、その説明は省略する。
【0064】
本実施形態では回路基板2を貫通して貫通孔2cを形成するとともに、貫通孔2cに隣接して光素子用集積回路チップIC1を埋め込んだ状態で固定するための凹部2dを予め形成してある。そして、この凹部2d内に光素子用集積回路チップIC1を埋め込み、フォトダイオードPDとの接続端子が形成された上面が回路基板2の表面と略面一になるように、例えば接着剤78で固定する。その後、フォトダイオードPDに設けたバンプ73と、回路基板2上の配線パターン2a及び光素子用集積回路チップIC1の電極(図示せず)とをフリップチップボンディングにより導通している。尚、図7では図示を省略しているが、フォトダイオードPD及び光素子用集積回路チップIC1のフリップチップ実装部やフォトダイオードPDの受光面を保護するために、実施形態5と同様の方法でアンダーフィル樹脂75を塗布しても良い。
【0065】
(実施形態8)
本発明の実施形態8を図8(a)〜(c)に基づいて説明する。本実施形態では、回路基板2にフェースアップの状態で実装された光素子用集積回路チップIC1の上面に、受光面を上向きにしてフォトダイオードPDをダイボンドし、光素子用集積回路チップIC1の上面に形成された電極とフォトダイオードPDの上面に形成された電極とをワイヤボンディング法により回路基板2の配線パターン2aにそれぞれ接続している。尚、フォトダイオードPD及び光素子用集積回路チップIC1の実装方法以外は実施形態1と同様であるので、同一の構成要素には同一の符号を付して、その説明は省略する。
【0066】
ここで、フォトダイオードPDを光素子用集積回路チップIC1の上面にダイボンドする際は、光の入射を回避する必要がある回路部分を覆うようにしてダイボンドする。但し、光素子用集積回路チップIC1の上面に形成された電極と回路基板2の電極とをワイヤボンディング法により接続する必要があるので、フォトダイオードPDをダイボンドする際は回路エリアを覆っても良いが、周辺にあるボンディングエリアに侵入しないようにする必要がある。
【0067】
そして、光素子用集積回路チップIC1の電極及びフォトダイオードPDの電極を回路基板2の配線パターン2aとワイヤボンディングにて接続し、フォトダイオードPDの受光面にかからないようにボンディング部を遮光性封止剤71で封止した後、フォトダイオードPDの受光面を覆うようにして透光性封止剤72を塗布する。この時、フォトダイオードPDの受光面に塗布する透光性封止剤72の流れ出しを防止するために、フォトダイオードの上面よりも上方に突出し、フォトダイオードPDの周りを囲む枠を形成するように遮光性封止剤71を塗布しても良い。尚、本実施形態では光素子用集積回路チップIC1及びフォトダイオードPDの電極を回路基板2の配線パターン2aとワイヤボンディングにて接続し、両電極間を配線パターン2aを介して接続しているが、光素子用集積回路チップIC1の電極とフォトダイオードPDの電極との間を直接ワイヤボンディング法により接続しても良い。
【0068】
また、本実施形態ではフォトダイオードPD及び光素子用集積回路チップIC1をフェースアップの状態で回路基板2に重ねてダイボンドしているが、図8(b)に示すように回路基板2に光素子用集積回路チップIC1をフェースダウンの状態でダイボンドして、光素子用集積回路チップIC1の上面にフェースアップの状態でフォトダイオードPDをダイボンドし、フォトダイオードPDの電極と回路基板2の配線パターン2aとをワイヤ80を介して接続し、光素子用集積回路チップIC1及びフォトダイオードPDの電極間を配線パターン2aを介して電気的に接続するようにしても良い。ここで、光素子用集積回路チップIC1は回路基板2の上面にフリップチップ実装されて、基板電極と光素子用集積回路チップIC1のバンプ74とを導通させており、光素子用集積回路チップIC1の表面にはアンダーフィル樹脂75が塗布され、外部環境や光の入射から保護されている。また、フォトダイオードPDは受光面を上にした状態で光素子用集積回路チップIC1の背面(上面)にダイボンディングされて、チップ電極と回路基板2の配線パターン2aとをワイヤボンディング法で接続しており、その後にフォトダイオードPDと基板側電極とを覆うようにして透光性封止剤72で封止している。
【0069】
尚、光素子用集積回路チップIC1を封止する際に、図8(c)に示すようにフィルムタイプのアンダーフィル樹脂76で封止しても良く、フィルム状のアンダーフィル樹脂76の形状を予め所定の形状に形成しておくことで、アンダーフィル樹脂76が光素子用集積回路チップIC1の外側にはみ出さないようにすることができ、フォトダイオードPDのチップ電極と基板電極との間をワイヤボンディングする際に、光素子用集積回路チップIC1を封止するアンダーフィル樹脂76が邪魔になることはなく、回路基板2側の電極をより近接して配置することができる。
【0070】
尚、上述の各実施形態では受光面を有するフォトダイオードPDとフォトダイオードPDの出力を信号処理する光素子用集積回路チップIC1とを回路基板2に実装する場合を例に説明したが、光素子チップをフォトダイオードPDのような受光素子に限定する趣旨のものではなく、各実施形態において発光面を有するLEDチップなどの発光素子と、発光素子に信号を出力する光素子用集積回路チップとを同一の回路基板に実装して、両チップの電極間をワイヤボンディングにより直接接続するようにしても良い。
【0071】
【発明の効果】
上述のように、請求項1の発明は、受光面又は発光面の内の少なくとも何れか一方を有する光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子チップの電極と光素子用集積回路チップの電極とをワイヤボンディング法により直接接続することを特徴とし、出力電流が微少であるハイインピーダンスの光素子チップの電極と光素子用集積回路チップの電極とをワイヤボンディング法により直接接続しているので、従来のチップ間端子接続方法に比べて両電極間を短い距離で接続することができ、したがって回路基板の小型化を図るとともに、両電極間を接続するボンディングワイヤにノイズがのりにくくなって、耐ノイズ性が向上するという効果がある。
【0072】
請求項2の発明は、請求項1の発明において、光素子チップの電極又は光素子用集積回路チップの電極の内、少なくとも何れか一方に金属突起を形成して、この金属突起にボンディングワイヤを接続することを特徴とし、電極に金属突起を形成し、この金属突起にボンディングワイヤを接続しているので、ボンディングの強度が安定して、両電極間の電気的接続の信頼性を向上させることができる。
【0073】
請求項3の発明は、受光面又は発光面の内の少なくとも何れか一方を有する光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、回路基板の表面に光素子チップの実装部位付近から光素子用集積回路チップの実装部位付近まで配線パターンを形成し、当該配線パターンに光素子チップの電極と光素子用集積回路チップの電極とをそれぞれワイヤボンディング法で接続したことを特徴とし、光素子チップの電極と配線パターンとの間、光素子用集積回路チップの電極と配線パターンとの間をそれぞれワイヤボンディング法で接続しているので、従来のチップ間端子接続方法に比べて両電極間を短い距離で接続することができ、したがって回路基板の小型化を図るとともに、両電極間を接続するボンディングワイヤにノイズがのりにくくなって、耐ノイズ性が向上するという効果がある。
【0074】
請求項4の発明は、受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子チップの受光面又は発光面の何れかが設けられた面に電極を設けるとともに、回路基板に、当該回路基板を厚み方向に貫通し光素子チップの受光面又は発光面の何れかを露出させる貫通孔と、光素子チップの電極に電気的に接続される光素子用電極と、光素子用集積回路チップの電極が電気的に接続される集積回路用電極と、光素子用電極と集積回路用電極との間を直線的に接続する配線パターンとを設け、貫通孔から受後面又は発光面の何れかが露出するようにして光素子チップを回路基板上に配置し、光素子チップ及び光素子用集積回路チップの電極をそれぞれ光素子用電極及び集積回路用電極にフリップチップボンディングによって接続したことを特徴とし、回路基板の貫通孔から受光面又は発光面の何れかが露出するようにして光素子チップを回路基板にフリップチップ実装するとともに、光素子用集積回路チップを光素子チップと同じ回路基板に実装しているので、チップ実装に必要な面積を小さくして、小型化を図ることができ、且つ従来のチップ間端子接続方法に比べて光素子チップ及び光素子用集積回路チップの電極間を短い距離で接続することができるから、光素子チップと光素子用集積回路チップとの間を接続する電路にノイズがのりにくくなり、耐ノイズ性が向上するという効果がある。
【0075】
請求項5の発明は、請求項4の発明において、光素子用集積回路チップをフィルムタイプのアンダーフィル樹脂で封止したことを特徴とし、請求項4の発明の効果に加えて、光素子用集積回路チップと回路基板との間の隙間をアンダーフィル樹脂で封止することができ、且つアンダーフィル樹脂にフィルムタイプのものを使用しているので、アンダーフィル樹脂の形状を予め所定の形状に形成しておくことで、封止する帯域を最小限の帯域に限定できるから、回路基板の小型化が図れるという効果もある。
【0076】
請求項6の発明は、受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子チップの受光面又は発光面の何れかが設けられた面に電極を設けるとともに、回路基板に、当該回路基板を厚み方向に貫通し光素子チップの受光面又は発光面の何れかを露出させる貫通孔を設けるとともに、光素子用集積回路チップの電極とこの電極に接続される光素子チップの電極とが回路基板の厚み方向において重なるようにして光素子用集積回路チップが埋め込まれる凹部を貫通孔の近傍に設け、この凹部内に光素子用集積回路チップを埋め込んだ後、貫通孔から受光面又は発光面の何れかが露出するように光素子チップを回路基板及び光素子用集積回路チップ上に配置して、光素子チップの電極と、回路基板の電極及び光素子用集積回路チップの電極とをそれぞれフリップチップボンディングによって直接接続したことを特徴とし、回路基板に設けた凹部に光素子用集積回路チップを埋め込んだ後、光素子チップを回路基板にフリップチップ実装することにより、光素子チップの電極と光素子用集積回路チップの電極とを直接接続しているので、従来のチップ間端子接続方法に比べて光素子チップ及び光素子用集積回路チップの電極間を短い距離で接続することができるから、光素子チップと光素子用集積回路チップとの間を接続する電路にノイズがのりにくくなり、耐ノイズ性が向上するという効果がある。また、光素子用集積回路チップを回路基板の凹部に埋め込んだ状態で、光素子チップの電極と光素子用集積回路チップの電極とを直接接続しており、光素子用集積回路チップと光素子チップの一部を回路基板の厚み方向に重ねて配置しているので、チップ実装に必要な面積を小さくして、回路基板の小型化が図れるという効果もある。
【0077】
請求項7の発明は、請求項4乃至請求項6の何れかに記載の発明において、貫通孔を、赤外線帯域から可視光帯域までの光に対して透光性を有する略透明の封止材料で封止したことを特徴とし、請求項4乃至請求項6の発明の効果に加えて、透光性を有する略透明の封止材料により光素子チップの受光面又は発光面を保護できるという効果がある。
【0078】
請求項8の発明は、受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子集積回路チップにおける実装面と反対側の表面に電極を設け、光素子用集積回路チップの表面の所定位置に、受光面又は発光面の何れかを光素子用集積回路チップと反対側に向けた状態で光素子チップを載置固定した後、光素子チップの電極と光素子用集積回路チップの電極とをワイヤボンディング法により直接接続したことを特徴とし、光素子用集積回路チップの表面に光素子チップを載置固定しているので、チップ実装に必要な面積を小さくでき、且つ光素子用集積回路チップの電極と光素子チップの電極とをワイヤボンディング法により直接接続しているので、従来のチップ間端子接続方法に比べて光素子チップ及び光素子用集積回路チップの電極間を短い距離で接続することができるから、光素子チップと光素子用集積回路チップとの間を接続する電路にノイズがのりにくくなり、耐ノイズ性が向上するという効果がある。
【0079】
請求項9の発明は、受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、回路基板には光素子用集積回路チップの実装位置の周辺に中継用の配線パターンを設けるとともに、光素子集積回路チップにおける実装面と反対側の表面に電極を設け、光素子用集積回路チップの表面の所定位置に、受光面又は発光面の何れかを光素子用集積回路チップと反対側に向けた状態で光素子チップを載置固定した後、光素子チップ及び光素子用集積回路チップの電極をそれぞれ配線パターンにワイヤボンディング法により接続したことを特徴とし、光素子用集積回路チップの表面に光素子チップを載置固定しているので、チップ実装に必要な面積を小さくでき、且つ光素子用集積回路チップ及び光素子チップの電極をそれぞれ配線パターンにワイヤボンディング法により接続することで、両電極間を配線パターンを介して接続しているので、従来のチップ間端子接続方法に比べて光素子チップ及び光素子用集積回路チップの電極間を短い距離で接続することができるから、光素子チップと光素子用集積回路チップとの間を接続する電路にノイズがのりにくくなり、耐ノイズ性が向上するという効果がある。
【0080】
請求項10の発明は、請求項9の発明において、光素子用集積回路チップを封止するアンダーフィル樹脂を、光素子用集積回路チップの外周の少なくとも一部において、光素子用集積回路チップの端面から外側にはみ出ないように設けたことを特徴とし、請求項9の発明の効果に加えて、封止する帯域を小さくして回路基板の小型化を図ることができるという効果がある。
【0081】
請求項11の発明は、請求項1乃至請求項10の何れかに記載の発明において、光素子用集積回路チップを、光素子チップの指向角度を狭めないように遮光性を有する略黒色の封止材料で封止した後に、封止材料で封止された光素子用集積回路チップとともに光素子チップの受光面又は発光面の何れかを赤外線帯域から可視光帯域までの光に対して透光性を有する略透明の封止材料で封止したことを特徴とし、遮光性を有する略黒色の封止材料で、光素子チップの指向角度を狭めないように光素子用集積回路チップを封止しているので、光素子用集積回路チップに光が当たってノイズが発生するのを防止できる。しかも、遮光性を有する略黒色の封止材料は、透光性を有する略透明の封止材料に比べて一般的に高粘度で高チクソ性であるため、封止する範囲を必要な範囲のみに限定することができ、その結果、封止材料を塗布するのに必要な時間を短縮して生産性を向上させることができる。
【0082】
請求項12の発明は、請求項11に記載の発明において、遮光性を有する略黒色の封止材料として略黒色のエポキシ樹脂を用いたことを特徴とし、請求項11の発明と同様の効果を奏する。
【0083】
請求項13の発明は、請求項11又は請求項12に記載の発明において、透光性を有する略透明の封止材料として赤外線帯域から可視光帯域までの光に対して透光性を有するエポキシ樹脂を用いたことを特徴とし、請求項11又は請求項12の発明と同様の効果を奏する。
【0084】
請求項14の発明は、請求項1乃至請求項13の何れかに記載のチップ間端子接続方法を用いて作製された回路基板であり、耐ノイズ性を向上させた小型の回路基板を実現できる。
【0085】
請求項15の発明は、外部からの煙の侵入を許容するとともに外光の入射を防止する隔壁が形成されたラビリンス壁と、ラビリンス壁によって囲まれる煙感知室に発光素子からの光を配光する発光側の光学部材と、受光した光の光量に応じた電気信号を発生する光素子チップと、煙感知室に侵入した煙により散乱された発光素子からの光を光素子チップに集光させる受光側の光学部材と、光素子チップの出力を信号処理する光素子用集積回路チップを含み光素子チップの出力から火災の発生を検出する検出回路と、光素子チップ及び光素子用集積回路チップを含む検出回路の回路部品が実装され、請求項1乃至請求項13の何れかに記載のチップ間端子接続方法を用いて作製された回路基板とを備えて成ることを特徴とし、耐ノイズ性を向上させた火災感知器を実現できる。
【図面の簡単な説明】
【図1】(a)〜(c)は実施形態1のチップ間端子接続方法を説明する回路基板の断面図である。
【図2】(a)(b)は実施形態2のチップ間端子接続方法を説明する回路基板の断面図である。
【図3】実施形態3のチップ間端子接続方法により作製した回路基板を示し、(a)は断面図、(b)は上面図である。
【図4】(a)(b)は実施形態4のチップ間端子接続方法を説明する回路基板の断面図である。
【図5】(a)は実施形態5のチップ間端子接続方法により作製した回路基板の断面図、(b)は光素子チップの下面図、(c)(d)は製造工程を説明する断面図である。
【図6】(a)〜(c)は実施形態6のチップ間端子接続方法を説明する回路基板の断面図である。
【図7】実施形態7のチップ間端子接続方法を説明する回路基板の断面図である。
【図8】(a)〜(c)は実施形態8のチップ間端子接続方法を説明する回路基板の断面図である。
【図9】同上のチップ間端子接続方法を用いて作製した回路基板を具備する火災感知器を組み立てる前の状態の断面図である。
【図10】同上の分解斜視図である。
【図11】同上の断面図である。
【図12】同上の光学基台を示し、(a)は平面図、(b)はA−A’断面図である。
【図13】同上の光学基台の裏面図である。
【図14】同上の光学基台を示し、図12のC部拡大図である。
【図15】同上の光学基台の製造工程を説明する説明図である。
【図16】(a)(b)は同上の光学基台の別の製造工程を説明する説明図である。
【図17】(a)(b)は同上の光学基台のまた別の製造工程を説明する説明図である。
【図18】(a)(b)は同上の光学基台の更に別の製造工程を説明する説明図である。
【図19】(a)(b)は同上の光学基台のまた更に別の製造工程を説明する説明図である。
【図20】同上の回路ブロック図である。
【図21】従来のチップ間端子接続方法を用いて作製された回路基板の断面図である。
【符号の説明】
2   回路基板
PD  フォトダイオード
IC1 光素子用集積回路チップ
80,80’ワイヤ
[0001]
BACKGROUND OF THE INVENTION
According to the present invention, an optical element chip having at least one of a light receiving surface and a light emitting surface and an integrated circuit chip for an optical element that performs signal processing on the output of the optical element chip are mounted on the same substrate. The present invention relates to an inter-chip terminal connection method for electrically connecting the terminals of the circuit board, a circuit board manufactured using the same, and a fire detector including the circuit board.
[0002]
[Prior art]
Conventionally, in an electronic device module that combines an optical element such as a smoke detector and an integrated circuit for an optical element, for example, either or both of the optical element and the integrated circuit for the optical element are used as a semiconductor chip as a lead frame. It was assembled in the state of discrete mounted. FIG. 21 is a cross-sectional view of a circuit board fabricated by using a conventional interchip terminal connection method. A discrete optical element 101 and an optical element integrated circuit 102 are mounted on one circuit board 100.
[0003]
[Problems to be solved by the invention]
In the conventional interchip terminal connection method described above, since discrete components are used for the optical element 101 and the optical element integrated circuit 102, the wiring length L between the optical element 101 and the optical element integrated circuit 102 is reduced. It was long. In general, since the output impedance of the optical element 101 is high impedance, when the wiring length L between the optical element 101 and the optical element integrated circuit 102 is increased, noise is easily superimposed and noise resistance is deteriorated. There was a problem. Further, in order to ensure noise resistance, it is necessary to cover the entire periphery of the optical element 101 and the optical element integrated circuit 102 with the shield case 103. As a result, the entire circuit board becomes large and the material cost increases. was there.
[0004]
The present invention has been made in view of the above problems, and its object is to improve the noise resistance and to reduce the size of the circuit board and to produce the inter-chip terminal connection method. It is an object of the present invention to provide a fire detector having a circuit board.
[0005]
[Means for Solving the Problems]
To achieve the above object, according to the first aspect of the present invention, there is provided an optical element chip having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip. An inter-chip terminal connection method for mounting an optical element integrated circuit chip that performs signal processing on at least one of them close to the same circuit board and electrically connecting electrodes of both chips, The electrode of the optical element chip and the electrode of the integrated circuit chip for optical element are directly connected by a wire bonding method.
[0006]
According to a second aspect of the present invention, in the first aspect of the invention, a metal protrusion is formed on at least one of the electrode of the optical element chip or the electrode of the integrated circuit chip for the optical element, and a bonding wire is formed on the metal protrusion. It is characterized by connecting.
[0007]
In the invention of claim 3, an optical element chip having at least one of a light receiving surface or a light emitting surface, and at least one of an output signal from the optical element chip or an output signal to the optical element chip An inter-chip terminal connection method in which an integrated circuit chip for optical elements for signal processing is mounted close to the same circuit board and the electrodes of both chips are electrically connected, and the optical element chip is formed on the surface of the circuit board. A wiring pattern was formed from the vicinity of the mounting part to the vicinity of the mounting part of the integrated circuit chip for optical elements, and the electrodes of the optical element chip and the electrodes of the integrated circuit chip for optical elements were respectively connected to the wiring pattern by wire bonding. It is characterized by.
[0008]
According to a fourth aspect of the present invention, there is provided an optical element chip including an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip. An inter-chip terminal connection method for mounting an optical element integrated circuit chip that performs signal processing on at least one of them close to the same circuit board and electrically connecting electrodes of both chips, An electrode is provided on the surface provided with either the light receiving surface or the light emitting surface of the optical element chip, and either the light receiving surface or the light emitting surface of the optical element chip is exposed through the circuit board in the thickness direction. A through-hole, an optical element electrode electrically connected to the electrode of the optical element chip, an integrated circuit electrode electrically connected to the electrode of the optical element integrated circuit chip, and an integrated optical element electrode Between the circuit electrodes The optical element chip is arranged on the circuit board so that either the receiving surface or the light emitting surface is exposed from the through hole, and the optical element chip and the integrated circuit chip for the optical element are arranged. The electrodes are respectively connected to the electrodes for optical elements and the electrodes for integrated circuits by flip chip bonding.
[0009]
The invention of claim 5 is characterized in that, in the invention of claim 4, the integrated circuit chip for optical elements is sealed with a film type underfill resin.
[0010]
According to the sixth aspect of the present invention, an optical element chip having an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip An inter-chip terminal connection method for mounting an optical element integrated circuit chip that performs signal processing on at least one of them close to the same circuit board and electrically connecting electrodes of both chips, An electrode is provided on the surface provided with either the light receiving surface or the light emitting surface of the optical element chip, and either the light receiving surface or the light emitting surface of the optical element chip is exposed through the circuit board in the thickness direction. The optical element integrated circuit chip is buried so that the electrode of the optical element integrated circuit chip and the electrode of the optical element chip connected to the electrode overlap in the thickness direction of the circuit board. A concave portion is provided in the vicinity of the through-hole, and after the optical circuit integrated circuit chip is embedded in the concave portion, the optical element chip is mounted on the circuit board and the light so that either the light receiving surface or the light emitting surface is exposed from the through-hole It is arranged on the element integrated circuit chip, and the electrode of the optical element chip, the electrode of the circuit board and the electrode of the integrated circuit chip for the optical element are directly connected by flip chip bonding, respectively.
[0011]
According to a seventh aspect of the present invention, in the invention according to any one of the fourth to sixth aspects, the through-hole is a substantially transparent sealing material having translucency for light from the infrared band to the visible light band. It is sealed with.
[0012]
According to the eighth aspect of the present invention, an optical element chip including an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip An inter-chip terminal connection method for mounting an optical element integrated circuit chip that performs signal processing on at least one of them close to the same circuit board and electrically connecting electrodes of both chips, An electrode is provided on the surface opposite to the mounting surface of the optical element integrated circuit chip, and either the light receiving surface or the light emitting surface is opposite to the optical element integrated circuit chip at a predetermined position on the surface of the optical element integrated circuit chip. After the optical element chip is mounted and fixed in the state of being directed, the electrode of the optical element chip and the electrode of the integrated circuit chip for optical elements are directly connected by a wire bonding method.
[0013]
According to the ninth aspect of the present invention, an optical element chip having an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip An inter-chip terminal connection method for mounting an optical element integrated circuit chip that performs signal processing on at least one of them close to the same circuit board and electrically connecting electrodes of both chips, The circuit board is provided with a wiring pattern for relay around the mounting position of the optical element integrated circuit chip, and an electrode is provided on the surface opposite to the mounting surface of the optical element integrated circuit chip. After the optical element chip is placed and fixed at a predetermined position on the surface with either the light receiving surface or the light emitting surface facing away from the optical element integrated circuit chip, the optical element chip and the optical element integrated circuit chip Characterized by being connected by a wire bonding method, each wiring pattern poles.
[0014]
According to a tenth aspect of the invention, in the ninth aspect of the invention, the underfill resin for sealing the optical element integrated circuit chip is formed on at least a part of the outer periphery of the optical element integrated circuit chip. It is provided so as not to protrude outward from the end face.
[0015]
According to an eleventh aspect of the present invention, in the invention according to any one of the first to tenth aspects, the integrated circuit chip for an optical element is sealed with a substantially black seal having a light shielding property so as not to narrow the directivity angle of the optical element chip. After sealing with a stop material, the light receiving surface or the light emitting surface of the optical element chip is transmitted with respect to light from the infrared band to the visible light band together with the integrated circuit chip for optical elements sealed with the sealing material. It is characterized by being sealed with a substantially transparent sealing material having properties.
[0016]
The invention of claim 12 is characterized in that, in the invention of claim 11, a substantially black epoxy resin is used as a substantially black sealing material having a light shielding property.
[0017]
According to the invention of claim 13, in the invention of claim 11 or claim 12, the substantially transparent sealing material having translucency is an epoxy having translucency for light from the infrared band to the visible light band. It is characterized by using a resin.
[0018]
A fourteenth aspect of the present invention is a circuit board manufactured using the interchip terminal connecting method according to any one of the first to thirteenth aspects.
[0019]
According to the fifteenth aspect of the present invention, the light from the light emitting element is distributed to the labyrinth wall formed with a partition wall that allows intrusion of smoke from outside and prevents the entrance of external light, and the smoke sensing chamber surrounded by the labyrinth wall. A light-emitting optical member that emits light, an optical element chip that generates an electrical signal corresponding to the amount of received light, and condensing light from the light-emitting element scattered by smoke that has entered the smoke sensing chamber onto the optical element chip An optical member on the light receiving side, an optical element integrated circuit chip that performs signal processing on the output of the optical element chip, a detection circuit that detects the occurrence of a fire from the output of the optical element chip, an optical element chip, and an optical element integrated circuit chip And a circuit board manufactured by using the inter-chip terminal connection method according to any one of claims 1 to 13.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
An embodiment in which the interchip terminal connection method according to the present invention is applied to a circuit board provided in a fire sensor will be described with reference to FIGS. 1 and 9 to 20.
[0021]
First, the circuit configuration of the fire detector will be described with reference to FIG. This fire detector is a composite type having both a smoke sensing function for sensing smoke and a heat sensing function for sensing heat, and a light emitting diode LED for irradiating infrared light to a smoke sensing chamber S described later; A photodiode PD that receives scattered light from the smoke that has entered the smoke detection chamber S of infrared light irradiated from the light emitting diode LED, a light projecting / receiving circuit 50, a microcomputer (hereinafter referred to as a microcomputer) 60, And a transmission circuit 61.
[0022]
The light emitting / receiving circuit 50 includes a light emission current control circuit 51 that controls a current flowing through the light emitting diode LED, and an I / V conversion circuit 52 that converts an output current of the photodiode PD into a voltage signal. The output voltage is amplified with a predetermined gain by the gain switching circuit 53, the voltage level is adjusted by the gain adjustment circuit 54, the offset voltage is further adjusted by the offset adjustment circuit 55, and then output to the microcomputer 60. The microcomputer 60 A / D-converts the output of the light projecting / receiving circuit 50 and compares it with a preset threshold level. When the output of the light projecting / receiving circuit 50 exceeds the threshold level, the smoke concentration is increased. A notification signal indicating that the predetermined concentration has been reached is output to the transmission circuit 61, and the transmission circuit 61 transmits this notification signal to a fire receiver (not shown) by a multiplex transmission signal. The light projecting / receiving circuit 50 includes a sensitivity adjustment control circuit 56 that changes the output of the light emission current control circuit 51 in accordance with a test signal input from the microcomputer 60 and selectively switches the gain of the gain switching circuit 53. ing. Although not shown in FIG. 20, the output of the thermistor 6 is input to the microcomputer 60, and the ambient temperature is monitored from the output of the thermistor 6.
[0023]
Next, the structure of the fire detector will be described with reference to FIGS. As shown in FIGS. 9 to 11, the fire detector includes a body 1 attached to a construction surface such as a ceiling surface, a light emitting diode LED made of a printed circuit board, a chip-formed photodiode PD, and a smoke detection circuit described later. The smoke detection chamber S having a substantially circular horizontal cross section surrounded by a circuit board 2 on which the circuit components are mounted and a labyrinth wall 9 that allows intrusion of smoke from the outside and prevents the entrance of external light And an optical base on which the circuit board 2 is mounted on the upper surface with the light emitting diode LED and the photodiode PD facing the optical system components. The base 3 is composed of an insect repellent cover 4 for preventing insects and the like from entering the smoke sensing chamber S provided on the optical base 3, and a protective cover 5.
[0024]
The body 1 is formed by integrally forming a substantially disc-shaped main portion 1a and a side wall 1b protruding upward from the outer peripheral edge of the main portion 1a. A round hole 1c is formed at a substantially center of the lower surface of the main portion 1a. The optical base 3 to which the circuit board 2 is fixed and the protective cover 5 holding the insect-proof cover 4 are inserted and fixed in the round hole 1c.
[0025]
A light emitting diode LED and a thermistor 6 are mounted on the lower surface of the circuit board 2 with the light emitting surface and the heat sensing part protruding downward, respectively. Further, as shown in FIG. 1A, on the lower surface of the circuit board 2, a photodiode PD (optical element chip) formed as a chip and the above-mentioned I / V conversion circuit 52 and the like are integrated into a chip. A circuit chip IC1 is mounted in proximity. Electrodes are formed on the back surfaces of the photodiode PD and the optical element integrated circuit chip IC1 and are die-bonded to the conductor patterns 2a and 2a formed on the surface of the circuit board 2, respectively. Electrodes (not shown) are respectively formed on the upper surfaces of the photodiode PD and the optical element integrated circuit chip IC1, and a wire 80 made of a thin metal wire such as aluminum or gold is formed between the electrodes by a wire bonding method. Connected directly through. As described above, in the present embodiment, the photodiode PD and the optical element integrated circuit chip IC1 which are chipped on the same circuit board 2 are die-bonded, and the electrode of the photodiode PD and the optical element integrated with a small output current. Since the electrodes of the circuit chip IC1 are directly connected by wire bonding, the electrodes can be connected at a short distance compared to the conventional inter-chip terminal connection method, and thus the circuit board can be miniaturized, Noise is hardly applied to the bonding wire connecting the two electrodes, and noise resistance is improved.
[0026]
Here, the wire bonding method is roughly classified into two methods, that is, an ultrasonic method and a thermocompression ultrasonic combined method. Needless to say, any method may be used for wire bonding. In this case, it is constructed using a jig (capillary) having a cylindrical shape with a through-hole through which the wire passes and having a conical shape at the tip. In the case of the ultrasonic method, an aluminum wire is mainly used, and in the case of the thermocompression ultrasonic method, a gold wire is mainly used.
[0027]
For example, when bonding is performed using a gold wire 80 having a diameter of about 20 μm by the thermocompression ultrasonic method, the first connection (also referred to as “first bonding”) is performed at the tip of the wire 80 with a minute diameter of about 60 μm. After forming the ball and bonding its tip by the thermocompression ultrasonic method, the capillary is moved to the position of the electrode to be connected next (also referred to as 2nd bonding), and the tip of the capillary is pressed against the electrode Then, bonding is performed by a thermocompression ultrasonic combined method. When connecting the electrode on the bare chip and the substrate or the lead frame with a bonding wire, the first bonding is generally performed on the electrode on the bare chip, and the 2nd bonding is mainly performed on the connection destination such as the substrate or the lead frame. In the case of this embodiment, the first bonding may be performed on the electrode of the integrated circuit chip IC1 for optical elements as shown in FIG. 1A, or the photodiode as shown in FIG. 1B. The first bonding may be performed on the PD electrode.
[0028]
In addition, as shown in FIG. 1C, in the case where bonding is performed by an ultrasonic method using a wire 80 ′ made of an aluminum thin wire, the chip electrode and the substrate-side electrode are the same, and the bonding is performed in the order of the steps. The device itself is not considered as 1st bonding or 2nd bonding. Therefore, in the ultrasonic method, there is no particular regulation regarding the connection method between the electrode of the photodiode PD and the electrode of the integrated circuit chip IC1 for optical elements, and any order in the process may be first.
[0029]
When the photodiode PD and the optical element integrated circuit chip IC1 are sealed with resin, if the photodiode PD and the optical element integrated circuit chip IC1 are sealed with different resins, the sealing resin is cured. There is a problem that a tensile stress is applied to the joint portion of the wire 80 due to a difference in thermal stress, but the photodiode PD and the optical element integrated circuit chip IC1 are sealed with one kind of resin having translucency. In this way, it is possible to prevent the thermal stress from being applied to the joint portion of the wire 80 and causing a problem.
[0030]
As shown in FIGS. 12 to 14, the optical base 3 is made of a black synthetic resin and has a substantially disc-shaped bottom plate 7, a square frame-like side wall 8 projecting from the top surface of the bottom plate 7, and a bottom surface of the bottom plate 7. A labyrinth wall 9 composed of a plurality of partition walls 9a having a substantially square horizontal cross section disposed along the outer peripheral portion is integrally formed.
[0031]
The partition wall 9a constituting the labyrinth wall 9 is formed in black so that reflection does not occur, the direction in which the bent portion of the intermediate portion protrudes is the same direction as the adjacent partition wall 9a, and the partition portion where the bent portion of the intermediate portion is adjacent It is arranged at a predetermined interval so as to enter between both ends of 9a. The smoke introduction path formed between the adjacent partition walls 9a has one end communicating with the outside to become a smoke introduction port, the other end communicating with the smoke sensing chamber S, and bending the middle part of the smoke introduction path, External light is less likely to enter the smoke sensing chamber S.
[0032]
In the recess 10 surrounded by the bottom plate 7 and the side wall 8 of the optical base 3, the surface on which the light emitting diode LED, photodiode PD, optical element integrated circuit chip IC1 and thermistor 6 are mounted is the bottom plate 7 side. The circuit board 2 is delivered. The base plate 7 of the optical base 3 is provided with projecting portions 19 and 20 projecting downward at portions corresponding to the light emitting diodes LED and the photodiode PD, respectively. Through holes 11 a and 11 b penetrating through 7 are formed. Grooves 19a and 20a are formed in the respective protrusions 19 and 20 so as to be continuous with the through holes 11a and 11b and extend toward the center of the optical base 3, and light is emitted in these grooves 19a and 20a. Prism lenses 12 and 13 as optical members on the side and the light receiving side are attached. Here, the prism lenses 12 and 13 are attached to the optical base 3 with one surface facing the through holes 11a and 11b and the other surface directed toward the center of the smoke sensing chamber S. The upper side and the left and right sides of 13 are covered with the projecting parts 19 and 20. That is, the prism lenses 12 and 13 are arranged so that the optical axes L1 and L2 face the central direction of the smoke sensing chamber S and intersect at a predetermined angle as shown in FIG.
[0033]
As described above, the prism lenses 12 and 13 face the light emitting surface of the light emitting diode LED and the light receiving surface of the photodiode PD, respectively, and the light emitted from the light emitting diode LED is condensed by the prism lens 12 and irradiated to the smoke sensing chamber S. Is done. When smoke enters the smoke sensing chamber S, the light irradiated from the prism lens 12 is scattered by the smoke particles and enters the prism lens 13. Since the light incident on the prism lens 13 is condensed on the light receiving surface of the photodiode PD by the prism lens 13, the intrusion of smoke can be detected from the increase in the output of the photodiode PD. Since the prism lenses 12 and 13 are arranged so that the optical axes L1 and L2 intersect at a predetermined angle, the light of the light emitting diode LED irradiated from the prism lens 12 is directly incident on the prism lens 13. There is nothing.
[0034]
Incidentally, since the output current from the photodiode PD is very small and weak against external noise such as electrostatic noise, it is necessary to shield the photodiode PD from such external noise. Therefore, in the present embodiment, a box-shaped shield cover 14 having an opening on one surface is insert-molded at a portion of the optical base 3 facing the photodiode PD, and when the circuit board 2 is placed in the recess 10, A shield cover 14 covers the photodiode PD and the smoke detection circuit mounted on the circuit board 2 so as to electrostatically shield the photodiode PD and the smoke detection circuit. The shield cover 14 is provided with a ground pin 14a that protrudes toward the circuit board 2. The ground pin 14a is inserted into a through hole provided in the circuit board 2 and is connected to a ground line (not shown) of the circuit board 2. Soldered. The shield cover 14 is formed with a communication hole 14b that communicates with the through hole 11b, and the light collected by the prism lens 13 through the communication hole 14b is applied to the light receiving surface of the photodiode PD. .
[0035]
In addition, four terminal pins 15 are insert-molded in the optical base 3, and each terminal pin 15 is inserted into a through hole (not shown) provided in the circuit board 2 and soldered. Each terminal pin 15 is electrically connected to the wiring pattern of the circuit board 2, and the tip portion of each terminal pin 15 protruding from the circuit board 2 to the opposite side serves as an external connection terminal. Further, the circuit board 2 is held on the optical base 3 by soldering the terminal pins 15 insert-molded on the optical base 3 to the circuit board 2.
[0036]
Here, the manufacturing process of the optical base 3 will be briefly described with reference to FIGS. First, as shown in FIG. 15, the hoop material 40 formed in a strip shape from a metal material is punched, and the hatched portion in FIG. 15 is bent to the heel side of the paper, and shown in FIGS. 16 (a) and 16 (b). Thus, the shield cover 14 is formed in a box shape, and the terminal pins 15 are projected in a direction substantially orthogonal to the plane direction of the hoop material 40. After that, as shown in FIGS. 17 (a) and 17 (b), the base portion composed of the bottom plate 7 and the side wall 8 is insert-molded (primary molding) in the hoop material 40, and the labyrinth as shown in FIGS. 18 (a) and 18 (b). After the wall 9 is secondarily formed, the frame portion is cut to form a shape as shown in FIGS. 19 (a) and 19 (b). Needless to say, the base portion composed of the bottom plate 7 and the side wall 8 and the labyrinth wall 9 may be insert-molded on the hoop material 40 at a time.
[0037]
Thus, since the shield cover 14 and the terminal pins 15 and the optical base 3 are integrated by simultaneous molding (insert molding), the number of parts can be reduced and the workability of the assembly work can be improved. . In addition, the optical base 3 and the labyrinth wall 9 are integrated to improve the assembly workability by reducing the number of parts, and the positioning accuracy between the labyrinth wall 9 and the optical base 3 is increased, so that stray light can be prevented. Occurrence can be suppressed. Moreover, since the shield cover 14 and the terminal pin 15 are formed by punching one sheet metal and bending it, the process of processing the shield cover 14 and the terminal pin 15 can be easily automated. Manufacturing cost can be reduced.
[0038]
Moreover, the insect-proof cover 4 is formed in bottomed cylindrical shape with the synthetic resin which has insulation, as shown in FIGS. The bottom plate 4a of the insect-proof cover 4 communicates with an insertion hole 11c provided in the optical base 3, and is formed with a through hole 4d through which the thermistor 6 mounted on the circuit board 2 is inserted, and the peripheral wall 4b has a plurality of holes. The mesh part 4c which is opened in a lattice shape is formed. The insect cover 4 is attached to the optical base 3 with the lower end portion of the optical base 3 inserted into the cylinder, and the labyrinth wall 9 is covered with a peripheral wall 4b on which a mesh portion 4c is formed. Thus, foreign matter such as insects can be prevented from entering the smoke sensing chamber S surrounded by the labyrinth wall 9. Further, as shown in FIG. 11, the bottom plate 4 a of the insect-proof cover 4 is directed upward (on the optical base 3 side) to a portion facing the protrusions 19 and 20 provided on the bottom plate 7 of the optical base 3. Lids 21 and 22 that protrude and fit into grooves 19a and 20a provided in the protrusions 19 and 20 are integrally formed. Thus, when the insect base cover 4 is put on the optical base 3, the lid portions 21 and 22 provided on the insect base cover 4 are fitted into the grooves 19a and 20a provided on the optical base 3, respectively, and the emission of the prism lens 12 is performed. Since the surface and the incident surface of the prism lens 13 are surrounded by the projecting portions 19 and 20 and the lid portions 21 and 22, it can be optically sealed, so that extra light such as external light enters. Can be prevented from malfunctioning.
[0039]
Further, the protective cover 5 is formed of a synthetic resin in a bottomed cylindrical shape, and an engaging claw 16 that protrudes outwardly protrudes from the upper end portion of the peripheral wall 5a, and in the circumferential direction in a substantially lower half of the peripheral wall 5a. A plurality of strip-shaped openings 17 extending along the bottom surface 5b, projecting upward from the bottom plate 5b, and projecting a plurality of ribs 18 whose tips are in contact with the bottom plate 4a of the insect-proof cover 4. In the assembled state of the fire detector, the thermistor 6 protrudes downward from the through hole 4 d of the insect-proof cover 4, and the tip of the thermistor 6 is disposed between the bottom plate 4 a of the insect-proof cover 4 and the bottom plate 5 b of the protective cover 5. The The plurality of ribs 18 are arranged radially about the thermistor 6 and rectify the air flow so that the air flowing into the inside from the opening 5 c hits the heat sensitive part of the thermistor 6.
[0040]
When assembling this fire detector, circuit components such as a light emitting diode LED, a photodiode PD, an optical element integrated circuit chip IC1, a thermistor 6 and a smoke detection circuit are first mounted on the circuit board 2, and the circuit board 2 is mounted on the optical substrate. The ground pin 14 a and the terminal pin 15 of the shield cover 14 are soldered to the circuit board 2 by being inserted into the recess 10 of the base 3, and the circuit board 2 is fixed to the optical base 3. Next, after inserting the insect-proof cover 4 and the optical base 3 to which the circuit board 2 is attached into the cylinder of the protective cover 5 and holding the insect-proof cover 4 and the optical base 3 on the protective cover 5, When the upper end portion of the protective cover 5 is inserted into the round hole 1c of the body 1, the engaging claw 16 protruding from the upper end portion of the protective cover 5 and the engaging step portion 1d formed on the inner peripheral surface of the round hole 1c. Are engaged with each other, and the protective cover 5 is coupled to the body 1.
[0041]
(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIGS. In the first embodiment described above, the electrode of the photodiode PD and the electrode of the optical element integrated circuit chip IC1 are directly connected by wire bonding, whereas in the present embodiment, as shown in FIG. A metal protrusion 70 is formed on the electrode of the photodiode PD, and the metal protrusion 70 and the electrode of the optical element integrated circuit chip IC1 are electrically connected via a wire 80 by a wire bonding method. In addition, since it is the same as that of Embodiment 1 except the connection method of the electrode of photodiode PD and the electrode of integrated circuit chip IC1 for optical elements, the same code | symbol is attached | subjected to the same component and the description is abbreviate | omitted. .
[0042]
As described above, in this embodiment, since the wire 80 is connected to the metal protrusion 70 formed on the electrode of the photodiode PD, the bonding strength is stabilized and the reliability of the electrical connection between both electrodes is improved. Can be made. In this embodiment, the metal electrode 70 is formed on the electrode of the photodiode PD, and the wire 80 is connected to the metal electrode 70. As shown in FIG. Metal protrusions 70 and 70 'may be formed on both electrodes of the integrated circuit chip IC1 for optical elements, and the metal protrusions 70 and 70' may be directly connected by wires 80. A metal protrusion may be provided only on the electrode, and the protrusion 80 and the electrode of the photodiode PD may be directly connected by a wire 80.
[0043]
In this case, using the thermocompression ultrasonic combined method described in the first embodiment as the wire bonding method, immediately after forming the ball when performing the first bonding, only the ball that has been deformed into a protrusion by the capillary is pulled. The metal protrusion 70 is formed by the method of leaving. Here, the material of the metal protrusion 70 may be any material as long as it is a material capable of wire bonding (for example, gold, aluminum, silver, nickel, etc.).
[0044]
Further, when the photodiode PD and the optical element integrated circuit chip IC1 are sealed with resin, if the photodiode PD and the optical element integrated circuit chip IC1 are sealed with different resins, the sealing resin is generated when the sealing resin is cured. There is a problem that a tensile stress is applied to the joint portion of the wire 80 due to a difference in thermal stress, but the photodiode PD and the optical element integrated circuit chip IC1 are sealed with one kind of resin having translucency. In this way, it is possible to prevent the thermal stress from being applied to the joint portion of the wire 80 and causing a problem.
[0045]
(Embodiment 3)
A third embodiment of the present invention will be described with reference to FIGS. In the first embodiment described above, the electrode of the photodiode PD and the electrode of the integrated circuit chip IC1 for optical elements are directly connected by the wire bonding method, whereas in this embodiment, the electrodes shown in FIGS. As shown in FIG. 3, the electrodes of the photodiode PD and the optical element integrated circuit chip IC1 are connected to the power supply wiring 2b (wiring pattern) for electrolytic plating formed on the substrate surface of the circuit board 2 through bonding wires, respectively. ing. In addition, since it is the same as that of Embodiment 1 except the connection method of the electrode of photodiode PD and the electrode of integrated circuit chip IC1 for optical elements, the same code | symbol is attached | subjected to the same component and the description is abbreviate | omitted. .
[0046]
As shown in FIG. 3B, on the substrate surface (upper surface) of the circuit substrate 2, square-shaped conductor patterns 2a and 2a on which the photodiode PD and the back electrode of the optical element integrated circuit chip IC1 are mounted are formed. In addition, a power supply wiring 2b for electrolytic plating is formed between the two conductor patterns 2a and 2a. The power supply wiring 2b is substantially T-shaped, and is arranged so that both ends of the horizontal bar portion are positioned in the vicinity of the conductor patterns 2a and 2a. Then, the horizontal bar portion of the power supply wiring 2b is formed to a desired length by cutting the branch portion A between the horizontal bar portion and the vertical bar portion of the power supply wiring 2b. The electrodes (not shown) of the integrated circuit chip IC1 for optical elements are respectively connected by a wire bonding method, and both electrodes are electrically connected via a power supply wiring 2b. As described above, the electrodes of the photodiode PD and the power supply wiring 2b and the electrodes of the optical element integrated circuit chip IC1 and the power supply wiring 2b are connected by the wire bonding method, respectively. Compared with the connection method, both electrodes can be connected at a short distance, so that the circuit board 2 can be reduced in size and noise is less likely to be applied to the bonding wire connecting the two electrodes, thereby improving noise resistance. To do. In addition, since the branching portion A of the power supply wiring 2b is divided to form a wiring pattern that connects the two electrodes, it is possible to prevent the power supply wiring from becoming an antenna and causing noise. Further, when the photodiode PD and the optical element integrated circuit chip IC1 are sealed with resin, if the photodiode PD and the optical element integrated circuit chip IC1 are sealed with different resins, the sealing resin is generated when the sealing resin is cured. There is a problem that a tensile stress is applied to the joint portion of the wire 80 due to a difference in thermal stress, but the photodiode PD and the optical element integrated circuit chip IC1 are sealed with one kind of resin having translucency. In this way, it is possible to prevent the thermal stress from being applied to the joint portion of the wire 80 and causing a problem.
[0047]
Here, as a method of dividing the branch portion A between the horizontal bar portion and the vertical bar portion of the power supply wiring 2b, for example, the through hole is formed by punching (punching) using a die or machining using a drill or a router. It may be divided by forming, but a hole that does not penetrate may be formed. When the optical element is sealed with a transparent resin to protect the optical element from the external environment after wire bonding, the transparent resin generally flows with a low viscosity and flows out to the back side of the circuit board 2. In order to prevent this, it is preferable to divide the power supply wiring 2b by forming a hole that does not penetrate.
[0048]
(Embodiment 4)
A fourth embodiment of the present invention will be described with reference to FIGS. In the present embodiment, as shown in FIG. 4A, the optical element integrated circuit chip IC1 is made of a light-shielding substantially black sealing material (hereinafter referred to as a light-shielding sealing agent) so as not to disturb the directivity angle of the photodiode PD. After sealing at 71, together with the sealed optical circuit integrated circuit chip IC1, the light-receiving surface of the photodiode PD is a substantially transparent seal having translucency for light in the infrared band to the visible light band. It is sealed with a material (hereinafter referred to as a translucent resin) 72. In addition, since structures other than the light-shielding sealant 71 and the light-transmitting resin 72 are the same as those in the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.
[0049]
Here, as the light-shielding sealant 71, an epoxy resin usually used for sealing a semiconductor bare chip may be used. In this embodiment, a thermosetting liquid epoxy resin (model number CV5181D manufactured by Matsushita Electric Works Co., Ltd.) is used. I use it. In order to reduce the mounting area determined by the range of resin sealing, it is preferable to use a resin with high viscosity and high thixotropy, so the viscosity and thixotropy are adjusted by fillers typified by silica in the resin. doing.
[0050]
Further, as the translucent resin 72, an epoxy resin that is normally used for sealing a semiconductor bare chip may be used. In this embodiment, a thermosetting epoxy resin (model number CV5130A manufactured by Matsushita Electric Works Co., Ltd.) is used. . This epoxy resin has translucency with respect to light in the infrared band to the visible light band, and is a two-component type composed of a main agent and a curing agent.
[0051]
The procedure for resin sealing will be briefly described below. First, a substantially black light-blocking sealant 71 is applied around the integrated circuit chip IC1 for optical elements. Here, since the light-shielding sealant 71 is a resin having a high viscosity and a high thixotropy, it is possible to seal only a minimum range of a connection portion between the electrode of the integrated circuit chip IC1 for optical elements and the wire 80. it can. This is to improve productivity in a liquid resin coating method called a resin extrusion (dispensing method) by air pressure with a small coating amount per unit time. In addition, once formed into a solid, and then heated to make it temporarily liquid, then use a well-known sealing agent of a type that is cured again, and after protecting with a mask except for the part to be sealed The whole substrate is heated, and this substrate is placed in an airtight container with an open top, and a sealing resin is placed on the opening while the air is being stirred in the airtight container. A method in which the resin is melted and adhered by the heat to attach the resin only to the necessary part, or a method of sealing only the necessary part by transfer molding using a mold as shown in FIG. 4 (b) It may be sealed with.
[0052]
As described above, the substantially black light-shielding sealant 71 is applied around the integrated circuit chip IC1 for optical elements, heated and cured, and then the substantially transparent sealant 72 is used to include the optical element chip. By applying so as to cover the input / output terminals of the chip and the integrated circuit chip for the optical element, the exposed portion of the wiring pattern on the substrate corresponding thereto, and the bonding wire described in the first to third embodiments, the optical element chip The optical element chip and the bonding wire can be protected without hindering the directivity angle. The dark black light-blocking sealant 71 may be applied so as to be exposed from the substantially transparent sealant 72.
[0053]
(Embodiment 5)
A fifth embodiment of the present invention will be described with reference to FIGS. In the first embodiment described above, the photodiode PD and the optical element integrated circuit chip IC1 are mounted face-up on the circuit board 2, but in the present embodiment, the photodiode PD and the optical element integrated circuit chip IC1 are mounted. Is mounted on the circuit board 2 in a face-down state. In addition, since it is the same as that of Embodiment 1 except the mounting method of photodiode PD and integrated circuit chip | tip IC1 for optical elements, the same code | symbol is attached | subjected to the same component and the description is abbreviate | omitted.
[0054]
In the present embodiment, the circuit board 2 is provided with a through hole 2c that penetrates the circuit board 2 in the thickness direction, and the photodiode PD is arranged so that the light receiving surface of the photodiode PD faces the through hole 2c. Bump 73 provided on the electrode on the same surface as that of the surface is flip-chip bonded to a substrate-side electrode (not shown) formed on the circuit board 2, thereby electrically connecting the electrode of the photodiode PD and the circuit board 2. Connect. As shown in FIG. 5B, the photodiode PD is formed with electrodes at the four corners of the same surface as the light receiving surface, and bumps 73 are formed on each electrode. In this state, the parallelism with respect to the circuit board 2 can be ensured.
[0055]
Bumps 74 are also formed on the mounting surface of the integrated circuit chip IC1 for optical elements, and the bumps 74 are flip-chip bonded to substrate-side electrodes (not shown) formed on the circuit board 2, thereby providing an optical element. The electrode of the integrated circuit chip IC1 and the circuit board 2 are electrically connected. Here, the wiring pattern 2a for electrically connecting the photodiode PD and the optical element integrated circuit chip IC1 is the shortest distance between the electrode of the photodiode PD and the electrode of the optical element integrated circuit chip IC1. Patterned to connect.
[0056]
In addition, light is prevented from being inserted into the light receiving surface through the gap between the circuit board 2 and the photodiode PD on which flip chip mounting is performed, and the bonding strength between the bumps 73 and 74 and the substrate side electrode is maintained and reliable. In order to improve the performance, underfill resin 75 is injected into the gap between the flip-chip mounted photodiode PD and the optical element integrated circuit chip IC1 and the circuit board 2 and cured. As shown in FIG. 5C, a photodiode PD and an optical element integrated circuit in which an underfill resin 75 is applied to the upper surface of the circuit board 2 before flip chip mounting and bumps 73 and 74 are formed thereafter. The chip IC1 may be pressed against the circuit board 2 and the resin may be heat-cured in a state where the chip IC1 is in contact with the board-side electrode (a pre-coating method).
[0057]
Here, since it is necessary for light to enter the optical element, a transparent resin is used as the underfill resin for protecting the light receiving surface or light emitting surface of the optical element, and a dark black light shielding resin is applied from the outside. Then, the incidence of light from the outside may be blocked. Further, it is applied to the flip chip portion of the optical element integrated circuit chip IC1 mounted adjacent to the photodiode PD, and a photo is covered with a part of the dark black light shielding resin for sealing the optical element integrated circuit chip IC1. A sealant that seals the outside of the transparent sealant of the diode PD may also be used. The resin that covers the bump and the connection terminal on the circuit board 2 side in the above configuration may be a substantially black light shielding resin or a transparent resin.
[0058]
(Embodiment 6)
In the fifth embodiment described above, the liquid underfill resin 75 is applied to the surface of the circuit board 2, and the photodiode PD and the optical element integrated circuit chip IC 1 are pressed against the circuit board 2 to come into contact with the electrodes of the circuit board 2. In this embodiment, the resin is sealed by heat curing, but in this embodiment, the resin is sealed with a film type underfill resin 76 as shown in FIGS. In the case of a film type, by forming the underfill resin 76 in a predetermined shape in advance, the sealing band can be limited to the minimum band. In FIGS. The integrated circuit chip IC1 is formed in a shape that covers substantially the entire lower surface of the integrated circuit chip IC1 and only the bonding portion of the photodiode PD. In addition, since it is the same as that of Embodiment 5 except the underfill resin 76, the same code | symbol is attached | subjected to the same component and the description is abbreviate | omitted.
[0059]
Here, the film type underfill resin 76 is an insulating resin or an anisotropic conductive resin. As shown in FIG. 6A, the film type underfill resin 76 is placed on the wiring pattern 2a of the circuit board 2. The bumps 73, 74, 74, 74, 74, 74 are formed by aligning the photodiode PD and the optical element integrated circuit chip IC 1 on which the bumps 73, 74 are formed with the wiring pattern 2 a of the circuit board 2, and applying pressure and heating. 74 and the substrate side electrode are joined.
[0060]
When the underfill resin 76 is an insulating resin, the film-like underfill resin 76 is softened by heating, and further, the photodiode PD and the optical element integrated circuit chip IC1 are pressed against the circuit board 2 to thereby provide the photodiode. Bumps 73 and 74 provided on the PD and the optical element integrated circuit chip IC1 penetrate the underfill resin 76 to reach the wiring pattern 2a on the circuit board 2 and make electrical contact therewith. When the film-like underfill resin 76 is cured in this state, the underfill resin 76 is cured and contracted at room temperature, so that the electrical connection between the bumps 73 and 74 and the electrodes of the circuit board 2 is maintained. Can be secured.
[0061]
Further, when the underfill resin 76 is an anisotropic conductive resin, the conductive particles are dispersed in the insulating resin. Therefore, the photodiode PD and the optical element integrated circuit are formed with the underfill resin 76 softened by heating. By pressing the circuit chip IC1 against the circuit board 2, the bumps 73 and 74 formed on the photodiode PD and the optical element integrated circuit chip IC1 pass through the film-like underfill resin 76 and come into contact with the electrodes of the circuit board 2. Alternatively, it is electrically connected to the electrode of the circuit board 2 through the conductive particles, thereby conducting with the electrode of the circuit board 2. When the film-like underfill resin 76 is cured in this state, the electrical connection between the bumps 73 and 74 and the electrodes of the circuit board 2 is caused by the conduction through the conductive particles and the curing and shrinkage of the underfill resin 76. It is maintained and conduction can be secured.
[0062]
By the way, in this embodiment, as shown in FIG.6 (c), in the through-hole 2c formed in the circuit board 2, the substantially transparent sealing agent 77 which has translucency from an infrared band to a visible light band is filled. Thus, the light receiving surface of the photodiode PD may be sealed to protect the light receiving surface of the photodiode PD. In this case, it is desirable that a hole (for example, a square hole) that exposes the light receiving surface of the photodiode PD is formed in the underfill resin 76 to form a frame, and the underfill resin 76 causes the sealant 77 to flow out. Can be prevented.
[0063]
(Embodiment 7)
A seventh embodiment of the present invention will be described with reference to FIG. In the fifth embodiment described above, the photodiode PD and the optical element integrated circuit chip IC1 are flip-chip mounted on the upper surface of the circuit board 2, whereas in the present embodiment, the optical element integrated circuit is mounted on the circuit board 2. The chip IC1 is fixed in an embedded state, the photodiode PD is flip-chip mounted on the circuit board 2, and the bumps 73 of the photodiode PD are directly connected to the electrodes of the integrated circuit chip IC1 for optical elements. In addition, since it is the same as that of Embodiment 5 except the mounting method of integrated circuit chip IC1 for optical elements, the same code | symbol is attached | subjected to the same component and the description is abbreviate | omitted.
[0064]
In the present embodiment, a through hole 2c is formed through the circuit board 2, and a recess 2d for fixing the integrated circuit chip IC1 for optical elements in an embedded state is formed adjacent to the through hole 2c in advance. . Then, the integrated circuit chip IC1 for optical elements is embedded in the recess 2d, and fixed with, for example, an adhesive 78 so that the upper surface on which the connection terminal with the photodiode PD is formed is substantially flush with the surface of the circuit board 2. To do. Thereafter, the bump 73 provided on the photodiode PD is electrically connected to the wiring pattern 2a on the circuit board 2 and the electrode (not shown) of the integrated circuit chip IC1 for optical elements by flip chip bonding. Although not shown in FIG. 7, in order to protect the photodiode PD and the flip chip mounting portion of the optical element integrated circuit chip IC1 and the light receiving surface of the photodiode PD, the same method as in the fifth embodiment is used. An underfill resin 75 may be applied.
[0065]
(Embodiment 8)
An eighth embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the photodiode PD is die-bonded on the upper surface of the optical element integrated circuit chip IC1 mounted face-up on the circuit board 2 with the light receiving surface facing upward, and the upper surface of the optical element integrated circuit chip IC1. The electrode formed on the electrode PD and the electrode formed on the upper surface of the photodiode PD are connected to the wiring pattern 2a of the circuit board 2 by wire bonding. In addition, since it is the same as that of Embodiment 1 except the mounting method of photodiode PD and integrated circuit chip | tip IC1 for optical elements, the same code | symbol is attached | subjected to the same component and the description is abbreviate | omitted.
[0066]
Here, when the photodiode PD is die-bonded to the upper surface of the optical element integrated circuit chip IC1, the die-bonding is performed so as to cover a circuit portion where it is necessary to avoid the incidence of light. However, since it is necessary to connect the electrode formed on the upper surface of the integrated circuit chip IC1 for optical elements and the electrode of the circuit board 2 by wire bonding, the circuit area may be covered when the photodiode PD is die-bonded. However, it is necessary not to enter the bonding area in the vicinity.
[0067]
Then, the electrode of the integrated circuit chip IC1 for optical elements and the electrode of the photodiode PD are connected to the wiring pattern 2a of the circuit board 2 by wire bonding, and the bonding portion is sealed so as not to cover the light receiving surface of the photodiode PD. After sealing with the agent 71, a translucent sealant 72 is applied so as to cover the light receiving surface of the photodiode PD. At this time, in order to prevent the translucent sealing agent 72 applied to the light receiving surface of the photodiode PD from flowing out, a frame that protrudes above the upper surface of the photodiode and surrounds the photodiode PD is formed. A light blocking sealant 71 may be applied. In the present embodiment, the electrodes of the optical element integrated circuit chip IC1 and the photodiode PD are connected to the wiring pattern 2a of the circuit board 2 by wire bonding, and both electrodes are connected via the wiring pattern 2a. The electrode of the integrated circuit chip IC1 for optical elements and the electrode of the photodiode PD may be directly connected by a wire bonding method.
[0068]
In the present embodiment, the photodiode PD and the optical element integrated circuit chip IC1 are die-bonded to the circuit board 2 in a face-up state. However, as shown in FIG. The semiconductor integrated circuit chip IC1 is die-bonded in a face-down state, the photodiode PD is die-bonded on the upper surface of the optical element integrated circuit chip IC1, and the electrode of the photodiode PD and the wiring pattern 2a of the circuit board 2 are bonded. And the electrodes of the integrated circuit chip IC1 for optical elements and the photodiode PD may be electrically connected via the wiring pattern 2a. Here, the integrated circuit chip IC1 for optical elements is flip-chip mounted on the upper surface of the circuit board 2, and the substrate electrodes and the bumps 74 of the integrated circuit chip IC1 for optical elements are electrically connected. An underfill resin 75 is applied to the surface of the film to protect it from the external environment and light incidence. The photodiode PD is die-bonded to the back surface (upper surface) of the optical element integrated circuit chip IC1 with the light receiving surface facing upward, and the chip electrode and the wiring pattern 2a of the circuit board 2 are connected by a wire bonding method. Thereafter, the photodiode PD and the substrate-side electrode are covered with a light-transmitting sealant 72 so as to cover the photodiode PD and the substrate-side electrode.
[0069]
When sealing the integrated circuit chip IC1 for optical elements, it may be sealed with a film-type underfill resin 76 as shown in FIG. 8C, and the shape of the film-like underfill resin 76 is changed. By forming it in a predetermined shape in advance, it is possible to prevent the underfill resin 76 from protruding outside the integrated circuit chip IC1 for optical elements, and between the chip electrode and the substrate electrode of the photodiode PD. When wire bonding is performed, the underfill resin 76 for sealing the integrated circuit chip IC1 for optical elements does not get in the way, and the electrodes on the circuit board 2 side can be arranged closer to each other.
[0070]
In each of the above-described embodiments, the photodiode PD having the light receiving surface and the optical element integrated circuit chip IC1 that performs signal processing on the output of the photodiode PD are described as an example. The chip is not intended to be limited to a light receiving element such as a photodiode PD. In each embodiment, a light emitting element such as an LED chip having a light emitting surface and an integrated circuit chip for an optical element that outputs a signal to the light emitting element are provided. It may be mounted on the same circuit board and the electrodes of both chips may be directly connected by wire bonding.
[0071]
【The invention's effect】
As described above, the invention of claim 1 includes an optical element chip having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip. An inter-chip terminal connection method for mounting at least one of optical circuit integrated circuit chips for signal processing close to the same circuit board and electrically connecting electrodes of both chips, the optical element chip The electrode of the high-impedance optical element chip and the electrode of the integrated circuit chip for optical element, which have a small output current, are directly connected to each other by the wire bonding method. Direct connection by wire bonding method, so that both electrodes can be connected at a short distance compared to the conventional inter-chip terminal connection method, thus miniaturizing the circuit board Achieved with, is hard bonding wire to the noise occurs for connecting between the electrodes, there is an effect that noise resistance is improved.
[0072]
According to a second aspect of the present invention, in the first aspect of the invention, a metal protrusion is formed on at least one of the electrode of the optical element chip or the electrode of the integrated circuit chip for the optical element, and a bonding wire is formed on the metal protrusion. Since the metal protrusion is formed on the electrode and the bonding wire is connected to the metal protrusion, the bonding strength is stable and the reliability of the electrical connection between the two electrodes is improved. Can do.
[0073]
According to a third aspect of the invention, there is provided an optical element chip having at least one of a light receiving surface or a light emitting surface, and at least one of an output signal from the optical element chip or an output signal to the optical element chip. An inter-chip terminal connection method in which an integrated circuit chip for optical elements for signal processing is mounted close to the same circuit board and the electrodes of both chips are electrically connected, and the optical element chip is formed on the surface of the circuit board. A wiring pattern was formed from the vicinity of the mounting part to the vicinity of the mounting part of the integrated circuit chip for optical elements, and the electrodes of the optical element chip and the electrodes of the integrated circuit chip for optical elements were respectively connected to the wiring pattern by wire bonding. And connecting the electrode of the optical element chip and the wiring pattern, and the electrode of the integrated circuit chip for the optical element and the wiring pattern by wire bonding, respectively. Therefore, it is possible to connect both electrodes at a short distance compared to the conventional inter-chip terminal connection method, so that the circuit board can be reduced in size and noise is less likely to be applied to the bonding wire connecting the two electrodes. Thus, the noise resistance is improved.
[0074]
According to a fourth aspect of the present invention, there is provided an optical element chip including an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip. An inter-chip terminal connection method for mounting an optical element integrated circuit chip that performs signal processing on at least one of them close to the same circuit board and electrically connecting electrodes of both chips, An electrode is provided on the surface provided with either the light receiving surface or the light emitting surface of the optical element chip, and either the light receiving surface or the light emitting surface of the optical element chip is exposed through the circuit board in the thickness direction. A through-hole, an optical element electrode electrically connected to the electrode of the optical element chip, an integrated circuit electrode electrically connected to the electrode of the optical element integrated circuit chip, and an integrated optical element electrode Directly between the circuit electrodes The optical element chip is arranged on the circuit board so that either the receiving surface or the light emitting surface is exposed from the through hole, and the electrodes of the optical element chip and the integrated circuit chip for the optical element are provided. Are connected to the electrode for the optical element and the electrode for the integrated circuit by flip chip bonding, and the optical element chip is attached to the circuit board so that either the light receiving surface or the light emitting surface is exposed from the through hole of the circuit board. Since flip-chip mounting and the integrated circuit chip for optical elements are mounted on the same circuit board as the optical element chip, the area required for chip mounting can be reduced, miniaturization can be achieved, and the conventional chip Compared with the inter-terminal connection method, the electrodes of the optical element chip and the integrated circuit chip for the optical element can be connected at a short distance. Becomes between the road chip path to the noise hardly glue to connect, there is an effect that noise resistance is improved.
[0075]
The invention of claim 5 is characterized in that, in the invention of claim 4, the integrated circuit chip for optical elements is sealed with a film type underfill resin, and in addition to the effect of the invention of claim 4, The gap between the integrated circuit chip and the circuit board can be sealed with an underfill resin, and since a film type is used for the underfill resin, the shape of the underfill resin is set to a predetermined shape in advance. By forming it, the band to be sealed can be limited to the minimum band, so there is also an effect that the circuit board can be miniaturized.
[0076]
According to a sixth aspect of the present invention, there is provided an optical element chip including an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip. An inter-chip terminal connection method for mounting an optical element integrated circuit chip that performs signal processing on at least one of them close to the same circuit board and electrically connecting electrodes of both chips, An electrode is provided on the surface provided with either the light receiving surface or the light emitting surface of the optical element chip, and either the light receiving surface or the light emitting surface of the optical element chip is exposed through the circuit board in the thickness direction. The optical element integrated circuit chip is embedded so that the electrode of the optical element integrated circuit chip and the electrode of the optical element chip connected to the electrode overlap in the thickness direction of the circuit board. A concave portion is provided in the vicinity of the through hole, and after the optical circuit integrated circuit chip is embedded in the concave portion, the optical element chip is arranged so that either the light receiving surface or the light emitting surface is exposed from the through hole. An electrode of an optical element chip, an electrode of a circuit board, and an electrode of an integrated circuit chip for an optical element are directly connected to each other by flip chip bonding. After embedding the optical element integrated circuit chip in the recess, the optical element chip is flip-chip mounted on the circuit board, so that the electrode of the optical element chip and the electrode of the optical element integrated circuit chip are directly connected. Compared with the conventional interchip terminal connection method, the electrodes of the optical element chip and the integrated circuit chip for the optical element can be connected at a short distance. Integrated circuits become electrical path hardly noise occurs for connecting a chip, there is an effect that noise resistance is improved. The electrode of the optical element chip and the electrode of the integrated circuit chip for the optical element are directly connected in a state where the integrated circuit chip for the optical element is embedded in the recess of the circuit board. Since a part of the chip is arranged so as to overlap in the thickness direction of the circuit board, there is an effect that the area required for chip mounting can be reduced and the circuit board can be downsized.
[0077]
A seventh aspect of the invention is the invention according to any one of the fourth to sixth aspects, wherein the through hole has a substantially transparent sealing material having translucency for light from the infrared band to the visible light band. In addition to the effects of the inventions of claims 4 to 6, the light-receiving surface or the light-emitting surface of the optical element chip can be protected by a substantially transparent sealing material having translucency. There is.
[0078]
According to an eighth aspect of the present invention, there is provided an optical element chip including an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip. An inter-chip terminal connection method for mounting an optical element integrated circuit chip that performs signal processing on at least one of them close to the same circuit board and electrically connecting electrodes of both chips, An electrode is provided on the surface opposite to the mounting surface of the optical element integrated circuit chip, and either the light receiving surface or the light emitting surface is opposite to the optical element integrated circuit chip at a predetermined position on the surface of the optical element integrated circuit chip. The optical element chip is placed and fixed in the state of being directed, and then the electrode of the optical element chip and the electrode of the integrated circuit chip for the optical element are directly connected by a wire bonding method. Since the optical element chip is mounted and fixed on the optical element chip, the area required for chip mounting can be reduced, and the electrode of the integrated circuit chip for optical element and the electrode of the optical element chip are directly connected by the wire bonding method. Compared with the conventional inter-chip terminal connection method, the electrodes of the optical element chip and the integrated circuit chip for the optical element can be connected at a short distance, so that the connection between the optical element chip and the integrated circuit chip for the optical element is established. This makes it difficult for noise to travel on the electrical circuit to improve noise resistance.
[0079]
According to a ninth aspect of the present invention, there is provided an optical element chip including an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and an output signal from the optical element chip or an output signal to the optical element chip. An inter-chip terminal connection method for mounting an optical element integrated circuit chip that performs signal processing on at least one of them close to the same circuit board and electrically connecting electrodes of both chips, The circuit board is provided with a wiring pattern for relay around the mounting position of the optical element integrated circuit chip, and an electrode is provided on the surface opposite to the mounting surface of the optical element integrated circuit chip. After the optical element chip is placed and fixed at a predetermined position on the surface with either the light receiving surface or the light emitting surface facing away from the optical element integrated circuit chip, the optical element chip and the optical element integrated circuit chip Electric Are connected to a wiring pattern by a wire bonding method, and the optical element chip is mounted and fixed on the surface of the integrated circuit chip for optical elements, so that the area required for chip mounting can be reduced and the optical element By connecting the electrodes of the integrated circuit chip and the optical element chip to the wiring pattern by the wire bonding method, the electrodes are connected via the wiring pattern. Since the electrodes of the element chip and the integrated circuit chip for optical elements can be connected at a short distance, it becomes difficult for noise to be applied to the electric circuit connecting the optical element chip and the integrated circuit chip for optical elements, and the noise resistance. Has the effect of improving.
[0080]
According to a tenth aspect of the present invention, in the ninth aspect of the invention, the underfill resin for sealing the optical element integrated circuit chip is applied to at least a part of the outer periphery of the optical element integrated circuit chip. In addition to the effect of the ninth aspect of the invention, the circuit board can be reduced in size and the circuit board can be miniaturized.
[0081]
According to an eleventh aspect of the invention, in the invention according to any one of the first to tenth aspects, the integrated circuit chip for an optical element is sealed with a substantially black seal having a light shielding property so as not to narrow the directivity angle of the optical element chip. After sealing with a stop material, the light receiving surface or the light emitting surface of the optical element chip is transmitted with respect to light from the infrared band to the visible light band together with the integrated circuit chip for optical elements sealed with the sealing material. Sealed with a substantially transparent sealing material having a light-shielding property, and sealed with a substantially black sealing material having a light-shielding property to seal the optical element integrated circuit chip so as not to narrow the directivity angle of the optical element chip Therefore, it is possible to prevent light from being applied to the integrated circuit chip for optical elements and generating noise. In addition, the substantially black sealing material having a light shielding property is generally higher in viscosity and higher in thixotropy than the substantially transparent sealing material having a light transmitting property. As a result, the time required for applying the sealing material can be shortened and productivity can be improved.
[0082]
The invention of claim 12 is characterized in that, in the invention of claim 11, a substantially black epoxy resin is used as the substantially black sealing material having a light shielding property, and the same effect as that of the invention of claim 11 is obtained. Play.
[0083]
The invention of claim 13 is the epoxy according to claim 11 or claim 12, which is a translucent epoxy material having translucency for light from the infrared band to the visible light band as a substantially transparent sealing material having translucency. A resin is used, and the same effect as in the invention of claim 11 or claim 12 is obtained.
[0084]
The invention according to claim 14 is a circuit board manufactured by using the inter-chip terminal connection method according to any one of claims 1 to 13, and can realize a small circuit board with improved noise resistance. .
[0085]
The invention of claim 15 distributes the light from the light emitting element to the labyrinth wall formed with a partition wall that allows intrusion of smoke from outside and prevents the entrance of outside light, and the smoke sensing chamber surrounded by the labyrinth wall. A light-emitting optical member that emits light, an optical element chip that generates an electrical signal corresponding to the amount of received light, and condensing light from the light-emitting element scattered by smoke that has entered the smoke sensing chamber onto the optical element chip An optical member on the light receiving side, an optical element integrated circuit chip that performs signal processing on the output of the optical element chip, a detection circuit that detects the occurrence of a fire from the output of the optical element chip, an optical element chip, and an optical element integrated circuit chip And a circuit board manufactured by using the inter-chip terminal connection method according to any one of claims 1 to 13, wherein the circuit component of the detection circuit including the circuit board is mounted. Improve Can be realized fire detector was.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views of a circuit board for explaining an inter-chip terminal connection method according to a first embodiment.
2A and 2B are cross-sectional views of a circuit board for explaining an inter-chip terminal connection method according to a second embodiment.
3A and 3B show a circuit board manufactured by an interchip terminal connection method according to Embodiment 3, wherein FIG. 3A is a cross-sectional view, and FIG. 3B is a top view.
4A and 4B are cross-sectional views of a circuit board for explaining an inter-chip terminal connection method according to Embodiment 4. FIG.
5A is a cross-sectional view of a circuit board manufactured by the inter-chip terminal connection method according to Embodiment 5, FIG. 5B is a bottom view of an optical element chip, and FIGS. 5C and 5D are cross-sectional views explaining a manufacturing process; FIG.
6A to 6C are cross-sectional views of a circuit board for explaining an inter-chip terminal connection method according to a sixth embodiment.
FIG. 7 is a cross-sectional view of a circuit board for explaining an inter-chip terminal connecting method according to a seventh embodiment.
8A to 8C are cross-sectional views of a circuit board for explaining an inter-chip terminal connection method according to an eighth embodiment.
FIG. 9 is a cross-sectional view showing a state before assembling a fire detector including a circuit board manufactured by using the inter-chip terminal connection method.
FIG. 10 is an exploded perspective view of the above.
FIG. 11 is a cross-sectional view of the above.
12A and 12B show the optical base of the above, in which FIG. 12A is a plan view and FIG.
FIG. 13 is a rear view of the above optical base.
14 is an enlarged view of a C part in FIG. 12, showing the optical base of the above.
FIG. 15 is an explanatory diagram for explaining a manufacturing process of the optical base;
FIGS. 16A and 16B are explanatory views for explaining another manufacturing process of the optical base of the above.
FIGS. 17A and 17B are explanatory diagrams for explaining another manufacturing process of the optical base of the same.
18 (a) and 18 (b) are explanatory views illustrating still another manufacturing process of the optical base of the above.
19 (a) and 19 (b) are explanatory views for explaining still another manufacturing process of the optical base of the above.
FIG. 20 is a circuit block diagram of the above.
FIG. 21 is a cross-sectional view of a circuit board manufactured using a conventional interchip terminal connection method.
[Explanation of symbols]
2 Circuit board
PD photodiode
IC1 Integrated circuit chip for optical elements
80, 80 'wire

Claims (15)

受光面又は発光面の内の少なくとも何れか一方を有する光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子チップの電極と光素子用集積回路チップの電極とをワイヤボンディング法により直接接続することを特徴とするチップ間端子接続方法。An optical element chip having at least one of a light receiving surface and a light emitting surface, and an optical element integrated circuit that processes at least one of an output signal from the optical element chip or an output signal to the optical element chip An inter-chip terminal connection method for mounting a circuit chip close to the same circuit board and electrically connecting the electrodes of both chips, comprising: an optical element chip electrode; and an optical element integrated circuit chip electrode; Are connected directly by a wire bonding method. 前記光素子チップの電極又は前記光素子用集積回路チップの電極の内、少なくとも何れか一方に金属突起を形成して、この金属突起にボンディングワイヤを接続することを特徴とする請求項1記載のチップ間端子接続方法。The metal protrusion is formed on at least one of the electrode of the optical element chip or the electrode of the integrated circuit chip for the optical element, and a bonding wire is connected to the metal protrusion. Inter-chip terminal connection method. 受光面又は発光面の内の少なくとも何れか一方を有する光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、回路基板の表面に光素子チップの実装部位付近から光素子用集積回路チップの実装部位付近まで配線パターンを形成し、当該配線パターンに光素子チップの電極と光素子用集積回路チップの電極とをそれぞれワイヤボンディング法で接続したことを特徴とするチップ間端子接続方法。An optical element chip having at least one of a light receiving surface and a light emitting surface, and an optical element integrated circuit that processes at least one of an output signal from the optical element chip or an output signal to the optical element chip An inter-chip terminal connection method in which a circuit chip is mounted close to the same circuit board and the electrodes of both chips are electrically connected to each other. An inter-chip terminal characterized in that a wiring pattern is formed up to the vicinity of a mounting portion of an integrated circuit chip for an optical circuit, and an electrode of an optical element chip and an electrode of an integrated circuit chip for an optical element are connected to the wiring pattern by a wire bonding method, respectively Connection method. 受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子チップの受光面又は発光面の何れかが設けられた面に電極を設けるとともに、回路基板に、当該回路基板を厚み方向に貫通し光素子チップの受光面又は発光面の何れかを露出させる貫通孔と、光素子チップの電極に電気的に接続される光素子用電極と、光素子用集積回路チップの電極が電気的に接続される集積回路用電極と、光素子用電極と集積回路用電極との間を直線的に接続する配線パターンとを設け、貫通孔から受後面又は発光面の何れかが露出するようにして光素子チップを回路基板上に配置し、光素子チップ及び光素子用集積回路チップの電極をそれぞれ光素子用電極及び集積回路用電極にフリップチップボンディングによって接続したことを特徴とするチップ間端子接続方法。An optical element chip having an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and at least one of an output signal from the optical element chip or an output signal to the optical element chip An optical device integrated circuit chip for signal processing is mounted close to the same circuit board, and an inter-chip terminal connection method for electrically connecting electrodes of both chips, the light receiving surface of the optical device chip or An electrode is provided on a surface provided with any one of the light emitting surfaces, and a through hole that penetrates the circuit substrate in the thickness direction and exposes either the light receiving surface or the light emitting surface of the optical element chip, and an optical element An optical element electrode electrically connected to the chip electrode, an integrated circuit electrode to which the electrode of the optical element integrated circuit chip is electrically connected, and the optical element electrode and the integrated circuit electrode Wiring to connect in a straight line The optical element chip is arranged on the circuit board so that either the receiving surface or the light emitting surface is exposed from the through hole, and the electrodes of the optical element chip and the integrated circuit chip for the optical element are respectively used for the optical element. An inter-chip terminal connection method comprising connecting an electrode and an integrated circuit electrode by flip chip bonding. 前記光素子用集積回路チップをフィルムタイプのアンダーフィル樹脂で封止したことを特徴とする請求項4記載のチップ間端子接続方法。5. The inter-chip terminal connection method according to claim 4, wherein the integrated circuit chip for optical elements is sealed with a film type underfill resin. 受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子チップの受光面又は発光面の何れかが設けられた面に電極を設けるとともに、回路基板に、当該回路基板を厚み方向に貫通し光素子チップの受光面又は発光面の何れかを露出させる貫通孔を設けるとともに、光素子用集積回路チップの電極とこの電極に接続される光素子チップの電極とが回路基板の厚み方向において重なるようにして光素子用集積回路チップが埋め込まれる凹部を貫通孔の近傍に設け、この凹部内に光素子用集積回路チップを埋め込んだ後、貫通孔から受光面又は発光面の何れかが露出するように光素子チップを回路基板及び光素子用集積回路チップ上に配置して、光素子チップの電極と、回路基板の電極及び光素子用集積回路チップの電極とをそれぞれフリップチップボンディングによって直接接続したことを特徴とするチップ間端子接続方法。An optical element chip having an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and at least one of an output signal from the optical element chip or an output signal to the optical element chip An optical device integrated circuit chip for signal processing is mounted close to the same circuit board, and an inter-chip terminal connection method for electrically connecting electrodes of both chips, the light receiving surface of the optical device chip or While providing an electrode on the surface provided with any one of the light emitting surfaces, providing a through hole in the circuit board that penetrates the circuit board in the thickness direction and exposes either the light receiving surface or the light emitting surface of the optical element chip, Through-holes are formed in the recesses in which the integrated circuit chip for optical elements is embedded so that the electrode of the integrated circuit chip for optical element and the electrode of the optical element chip connected to this electrode overlap in the thickness direction of the circuit board. After the optical element integrated circuit chip is embedded in the recess, the optical element chip is placed on the circuit board and the optical element integrated circuit chip so that either the light receiving surface or the light emitting surface is exposed from the through hole. An inter-chip terminal connection method comprising: disposing and directly connecting an electrode of an optical element chip, an electrode of a circuit board, and an electrode of an integrated circuit chip for an optical element by flip chip bonding. 前記貫通孔を、赤外線帯域から可視光帯域までの光に対して透光性を有する略透明の封止材料で封止したことを特徴とする請求項4乃至請求項6の何れかに記載のチップ間端子接続方法。The said through-hole was sealed with the substantially transparent sealing material which has translucency with respect to the light from an infrared band to a visible light band, The Claim 4 thru | or 6 characterized by the above-mentioned. Inter-chip terminal connection method. 受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、光素子集積回路チップにおける実装面と反対側の表面に電極を設け、光素子用集積回路チップの表面の所定位置に、受光面又は発光面の何れかを光素子用集積回路チップと反対側に向けた状態で光素子チップを載置固定した後、光素子チップの電極と光素子用集積回路チップの電極とをワイヤボンディング法により直接接続したことを特徴とするチップ間端子接続方法。An optical element chip having an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and at least one of an output signal from the optical element chip or an output signal to the optical element chip An inter-chip terminal connection method for mounting an optical element integrated circuit chip for signal processing close to the same circuit board and electrically connecting the electrodes of both chips, the mounting on the optical element integrated circuit chip An electrode is provided on the surface opposite to the surface, and the optical element chip is placed at a predetermined position on the surface of the optical element integrated circuit chip with either the light receiving surface or the light emitting surface facing away from the optical element integrated circuit chip. A chip-to-chip terminal connection method characterized in that the electrode of the optical element chip and the electrode of the integrated circuit chip for optical element are directly connected by wire bonding after mounting and fixing. 受光面又は発光面の内の少なくとも何れか一方を有する光素子受発光部を具備した光素子チップと、当該光素子チップからの出力信号又は光素子チップへの出力信号の内の少なくとも何れか一方を信号処理する光素子用集積回路チップとを同一の回路基板に近接させて実装し、両チップの電極間を電気的に接続するチップ間端子接続方法であって、回路基板には光素子用集積回路チップの実装位置の周辺に中継用の配線パターンを設けるとともに、光素子集積回路チップにおける実装面と反対側の表面に電極を設け、光素子用集積回路チップの表面の所定位置に、受光面又は発光面の何れかを光素子用集積回路チップと反対側に向けた状態で光素子チップを載置固定した後、光素子チップ及び光素子用集積回路チップの電極をそれぞれ配線パターンにワイヤボンディング法により接続したことを特徴とするチップ間端子接続方法。An optical element chip having an optical element light emitting / receiving unit having at least one of a light receiving surface and a light emitting surface, and at least one of an output signal from the optical element chip or an output signal to the optical element chip Is an inter-chip terminal connection method in which an integrated circuit chip for optical elements for signal processing is mounted close to the same circuit board, and the electrodes of both chips are electrically connected to each other. A wiring pattern for relay is provided around the mounting position of the integrated circuit chip, and an electrode is provided on the surface opposite to the mounting surface of the optical element integrated circuit chip, and light is received at a predetermined position on the surface of the integrated circuit chip for optical element. After mounting and fixing the optical element chip with either the surface or the light emitting surface facing away from the optical element integrated circuit chip, the electrodes of the optical element chip and the optical element integrated circuit chip are respectively connected to the wiring pattern. Inter-chip terminal connection method being characterized in that connected by a wire bonding method over down. 前記光素子用集積回路チップを封止するアンダーフィル樹脂を、光素子用集積回路チップの外周の少なくとも一部において、光素子用集積回路チップの端面から外側にはみ出ないように設けたことを特徴とする請求項9記載のチップ間端子接続方法。The underfill resin for sealing the optical element integrated circuit chip is provided in at least a part of the outer periphery of the optical element integrated circuit chip so as not to protrude outward from the end face of the optical element integrated circuit chip. The inter-chip terminal connection method according to claim 9. 前記光素子用集積回路チップを、前記光素子チップの指向角度を狭めないように遮光性を有する略黒色の封止材料で封止した後に、封止材料で封止された光素子用集積回路チップとともに光素子チップの受光面又は発光面の何れかを赤外線帯域から可視光帯域までの光に対して透光性を有する略透明の封止材料で封止したことを特徴とする請求項1乃至請求項10の何れかに記載のチップ間端子接続方法。The integrated circuit for an optical element is sealed with a sealing material after the integrated circuit chip for the optical element is sealed with a substantially black sealing material having a light shielding property so as not to narrow the directivity angle of the optical element chip. 2. A light-receiving surface or a light-emitting surface of an optical element chip together with the chip is sealed with a substantially transparent sealing material having translucency for light from the infrared band to the visible light band. The inter-chip terminal connection method according to claim 10. 前記遮光性を有する略黒色の封止材料として略黒色のエポキシ樹脂を用いたことを特徴とする請求項11記載のチップ間端子接続方法。12. The inter-chip terminal connection method according to claim 11, wherein a substantially black epoxy resin is used as the substantially black sealing material having light shielding properties. 前記透光性を有する略透明の封止材料として赤外線帯域から可視光帯域までの光に対して透光性を有するエポキシ樹脂を用いたことを特徴とする請求項11又は請求項12に記載のチップ間端子接続方法。13. The epoxy resin having translucency with respect to light from an infrared band to a visible light band is used as the substantially transparent sealing material having translucency. Inter-chip terminal connection method. 請求項1乃至請求項13の何れかに記載のチップ間端子接続方法を用いて作製された回路基板。A circuit board manufactured using the inter-chip terminal connection method according to claim 1. 外部からの煙の侵入を許容するとともに外光の入射を防止する隔壁が形成されたラビリンス壁と、ラビリンス壁によって囲まれる煙感知室に発光素子からの光を配光する発光側の光学部材と、受光した光の光量に応じた電気信号を発生する光素子チップと、煙感知室に侵入した煙により散乱された発光素子からの光を光素子チップに集光させる受光側の光学部材と、光素子チップの出力を信号処理する光素子用集積回路チップを含み光素子チップの出力から火災の発生を検出する検出回路と、光素子チップ及び光素子用集積回路チップを含む検出回路の回路部品が実装され、請求項1乃至請求項13の何れかに記載のチップ間端子接続方法を用いて作製された回路基板とを備えて成ることを特徴とする火災感知器。A labyrinth wall formed with a partition wall that allows intrusion of smoke from outside and prevents external light from entering; and a light-emitting side optical member that distributes light from the light-emitting element to a smoke sensing chamber surrounded by the labyrinth wall; An optical element chip that generates an electrical signal according to the amount of received light, an optical member on the light receiving side that condenses the light from the light emitting element scattered by the smoke that has entered the smoke sensing chamber onto the optical element chip, A detection circuit including an integrated circuit chip for an optical element that performs signal processing on an output of the optical element chip, and detecting a fire from the output of the optical element chip, and a circuit component of the detection circuit including the optical element chip and the integrated circuit chip for the optical element And a circuit board manufactured using the interchip terminal connection method according to any one of claims 1 to 13.
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JP2019169520A (en) * 2018-03-22 2019-10-03 住友電工デバイス・イノベーション株式会社 Light receiving module and manufacturing method thereof
JP7004304B2 (en) 2018-03-22 2022-02-04 住友電工デバイス・イノベーション株式会社 Manufacturing method of light receiving module
JP2021525956A (en) * 2018-06-01 2021-09-27 ティティ エレクトロニクス ピーエルシー Semiconductor device package and how to use it

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