JP2004055824A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a driving current of a P-channel type MOS transistor while preventing a decline in driving current of an N-channel type MOS transistor. <P>SOLUTION: The arrangement concentration of dummy active regions 11 in a p-type well 3 is relatively low, making a stress to be applied on a p-type active region 5 relatively small and hence preventing a decline in driving current of the n-channel type MOS transistor. Meanwhile, the arrangement concentration of dummy active regions 12 in an n well 4 is relatively high, making a stress to be applied on an n-type active region relatively large and hence a driving current of the p-channel type MOS transistor can be increased. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having both an N-channel MOS transistor and a P-channel MOS transistor.
[0002]
[Prior art]
With the increase in the density of semiconductor devices, trench isolation technology has been widely used for element isolation.
[0003]
The trench isolation technique is a technique for electrically isolating elements by filling a trench (groove) provided between the elements with an insulating film.
[0004]
FIG. 15 is a plan view showing one mode of element isolation of a conventional CMOS (Complementary MOS) semiconductor device, and FIG. 16 is a sectional view taken along line XVI-XVI of FIG.
[0005]
In a conventional CMOS semiconductor device, a P well 203 and an N well 204 are formed on a silicon substrate 201. A P-type active region 205 for forming an N-channel MOS transistor is set in the P-well 203, and an N-type active region 206 for forming a P-channel MOS transistor is set in the N-well 204. Have been.
[0006]
Then, a trench 202a is formed between the P-type active region 205 and the N-type active region 206 in order to achieve isolation between the P-type active region 205 and the N-type active region 206. A film 202 is formed.
[0007]
Around the active regions 205 and 206 in the P well 203 and the N well 204, dummy active regions 212 where no semiconductor element is formed are provided. Trench 202a is also formed between active regions 205 and 206, and an insulator is buried in trench 202a to form trench isolation insulating film 202.
[0008]
When performing a polishing operation by CMP (Chemical Mechanical Polishing), the dummy active region 212 plays a role of preventing polishing unevenness such as local overpolishing by making the polishing rates of the respective regions equal.
[0009]
[Problems to be solved by the invention]
However, in the above-described trench isolation technique, since an insulator as a foreign substance is buried in the P well 203 and the N well 204 of the silicon substrate 201, there is a concern that stress may be generated in each of the active regions 205 and 206.
[0010]
For example, in the semiconductor device shown in FIGS. 15 and 16, a large number of dummy active regions 212 are set around a P-type active region 205 and an N-type active region 206. A trench isolation insulating film 202 is formed in each of the trenches 202a. Then, the stress generated between the insulating film 202 in each of the trenches 202a and each of the dummy active regions 212 is accumulated and applied to each of the active regions 205 and 206.
[0011]
Incidentally, the main cause of such stress is that the oxide film is generally used as the insulating film 202, so that the active regions 205 and 206 and the dummy active region 212 of the P well 203 and the N well 204 are oxidized, It is thought to be due to volume swelling.
[0012]
When stress is generated in each of the active regions 205 and 206 for forming the MOS transistor, the mobility of carriers changes, and the following effects occur.
[0013]
That is, when stress is generated in the P-type active region 205 for forming the N-channel MOS transistor, the mobility of carriers decreases, and the current (drive current) between the source and drain regions of the N-channel MOS transistor decreases. Invite. On the other hand, when a stress is generated in the N-type active region 206 for forming the P-channel MOS transistor, the mobility of carriers increases, and the driving current of the P-channel MOS transistor increases.
[0014]
Such a problem becomes particularly remarkable with recent miniaturization of semiconductor devices.
[0015]
That is, in semiconductor devices up to the 0.18 μm generation where the maximum temperature during the semiconductor manufacturing process was high, the above-mentioned generation of stress was mitigated by heat treatment at a relatively high temperature, and did not pose a major problem.
[0016]
However, the recent increase in the density of semiconductor devices requires a reduction in the maximum temperature during the manufacturing process. As described above, in recent semiconductor devices which have been changed to a process of performing heat treatment at a temperature not so high as in the past, the opportunity to release the stress has been lost, and the occurrence of the above-mentioned stress has become a problem. I have.
[0017]
In addition, with the miniaturization of the semiconductor device, the influence of the stress generated in the miniaturized active regions 205 and 206 has become relatively large.
[0018]
Accordingly, an object of the present invention is to provide a semiconductor device having high performance as a whole by preventing a decrease in drive current in an N-channel MOS transistor or increasing a drive current in a P-channel MOS transistor, and a method of manufacturing the same. To provide.
[0019]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention according to claim 1 is a semiconductor substrate having a first conductive type first semiconductor layer and a second conductive type second semiconductor layer provided on one main surface; A first conductivity type first active region provided in the semiconductor layer and formed with a second channel type MOS transistor; and a second conductivity type first active region provided in the second semiconductor layer and formed with a first channel type MOS transistor. In a semiconductor device having two active regions and a trench isolation insulating film, a stress applied to the first active region from the trench isolation insulating film acts on the second active region from the trench isolation insulating film. It is set differently from.
[0020]
3. The semiconductor device according to claim 2, wherein a semiconductor substrate provided with a P-type semiconductor layer and an N-type semiconductor layer on one main surface and a P-type MOS transistor provided on said P-type semiconductor layer are formed. Active region, at least one first dummy active region of the P-type semiconductor layer provided around the P-type active region, and a P-channel MOS transistor provided in the N-type semiconductor layer. An N-type active region, at least one second dummy active region in the N-type semiconductor layer provided around the N-type active region, the P-type active region and the first dummy An active region, an N-type active region, and a trench isolation insulating film interposed between each of the second dummy active region, wherein the first dummy active region and the trench isolation in a region of the P-type semiconductor layer are provided. Absolute The total length of the boundary line between film is smaller than the total length of the boundary line between the second dummy active region and the trench isolation insulating film in the region of the N-type semiconductor layer.
[0021]
4. A semiconductor device according to claim 3, wherein a P-type semiconductor layer provided on one main surface of the P-type semiconductor layer and the N-type semiconductor layer, and an N-channel MOS transistor provided on the P-type semiconductor layer are formed. And an N-type active region provided in the N-type semiconductor layer and forming a P-channel MOS transistor. At least one dummy active region is the N-type semiconductor layer and the N-type semiconductor region. And a trench isolation insulating film is interposed between each of the P-type active region, the dummy active region, and the N-type active region.
[0022]
5. The semiconductor device according to claim 4, wherein: a semiconductor substrate having a P-type semiconductor layer and an N-type semiconductor layer; a P-type active region provided in the P-type semiconductor layer, wherein an N-channel MOS transistor is formed; An N-type active region provided in the N-type semiconductor layer where a P-channel type MOS transistor is formed; and a trench isolation insulating film provided in each of the P-type semiconductor layer and the N-type semiconductor layer. At least a part of a boundary between the P-type semiconductor layer and the trench isolation insulating film is provided with a stress suppressing film for suppressing a stress acting on the boundary.
[0023]
As such a stress suppressing film, an oxidized species permeation preventing film that prevents the permeation of oxidized species can be used.
[0024]
Alternatively, as described in claim 6, a stress absorbing film that is easier to deform than the P-type semiconductor layer and the trench isolation insulating film can be used as the stress suppressing film.
[0025]
8. A semiconductor device according to claim 7, wherein a semiconductor substrate having a P-type semiconductor layer and an N-type semiconductor layer provided on one main surface and a P-type MOS transistor provided in said P-type semiconductor layer are formed. An active region provided in the N-type semiconductor layer and an N-type active region in which a P-channel MOS transistor is formed; a first trench isolation insulating film provided in the P-type semiconductor layer; A second trench isolation insulating film provided in a layer, wherein the first trench isolation insulating film is formed of a non-oxide insulator, and the second trench isolation insulating film is formed of an oxide insulator. .
[0026]
9. The semiconductor device according to claim 8, wherein a P-type semiconductor layer provided on one main surface of the P-type semiconductor layer and the N-type semiconductor layer, and an N-channel MOS transistor provided on the P-type semiconductor layer are formed. An active region provided in the N-type semiconductor layer and an N-type active region in which a P-channel MOS transistor is formed; a first trench isolation insulating film provided in the P-type semiconductor layer; A second trench isolation insulating film provided in a layer, wherein the thickness dimension of the second trench isolation insulating film is smaller than the thickness dimension of the first trench isolation insulating film and is 0.5 nm or less. Things.
[0027]
In this case, the position of the bottom of the first trench isolation insulating film in the thickness direction of the semiconductor substrate and the position of the bottom of the second trench isolation insulating film are substantially the same, The distance dimension between one main surface of the P-type semiconductor layer in the thickness direction of the semiconductor substrate and the bottom of the first trench isolation insulating film is equal to one main surface of the N-type semiconductor layer in the thickness direction of the semiconductor substrate. The distance may be larger than the distance from the bottom of the second trench isolation insulating film.
[0028]
11. The semiconductor device according to claim 10, wherein a semiconductor substrate provided with a P-type semiconductor layer and an N-type semiconductor layer on one main surface, and a P-type MOS transistor provided in said P-type semiconductor layer. An active region provided in the N-type semiconductor layer and an N-type active region in which a P-channel MOS transistor is formed; a first trench isolation insulating film provided in the P-type semiconductor layer; A second trench isolation insulating film provided in a layer, wherein an inclination angle of a side surface of the first trench isolation insulating film with respect to a normal direction of the surface of the P-type semiconductor layer is a normal to the surface of the N-type semiconductor layer. The inclination angle is larger than the inclination angle of the side surface of the second trench isolation insulating film with respect to the direction.
[0029]
12. The semiconductor device according to claim 11, wherein a P-type semiconductor layer provided on one principal surface thereof and a P-type semiconductor layer provided on said P-type semiconductor layer and an N-channel MOS transistor formed on said P-type semiconductor layer are formed. And an N-type active region provided in the N-type semiconductor layer and in which a P-channel MOS transistor is formed; and an N-type active region provided above at least a part of the N-type active region. A stress-generating film for generating stress in the active region.
[0030]
In this case, the stress generation film may be formed of a material having a different coefficient of thermal expansion from the semiconductor substrate.
[0031]
Further, the stress-generating film may be an insulating film provided above the N-type active region.
[0032]
Further, the stress-generating film may be a conductor film provided above a gate electrode formed in an N-type active region.
[0033]
16. The semiconductor device according to claim 15, wherein a P-type semiconductor layer having a P-type semiconductor layer and an N-type semiconductor layer provided on one main surface, and a P-type MOS transistor provided in said P-type semiconductor layer are formed. An active region provided in the N-type semiconductor layer, an N-type active region in which a P-channel MOS transistor is formed, and a strained layer provided in the N-type semiconductor layer and causing a stress in the N-type active region And with.
[0034]
In this case, the strained layer may have a lattice constant different from a lattice constant of the N-type semiconductor layer.
[0035]
Further, as set forth in claim 17, a position of one main surface of the P-type active region in a thickness direction of the semiconductor substrate is a position recessed from one main surface of the N-type active region, The strained layer may be formed at a position between one main surface of the P-type active region and one main surface of the N-type active region in a thickness direction of the semiconductor substrate.
[0036]
BEST MODE FOR CARRYING OUT THE INVENTION
This semiconductor device will be described in a comprehensive manner. In this semiconductor device, P-type semiconductor layers (first semiconductor layers) and N-type semiconductor layers (second semiconductor layers) provided on a main surface of a semiconductor substrate are respectively provided with P-type semiconductor layers. A type active region and an N type active region are formed. An N-channel MOS transistor is formed in the P-type active region, and a P-channel MOS transistor is formed in the N-type active region. Further, a trench isolation insulating film is formed on the semiconductor substrate.
[0037]
Then, the stress applied to the P-type active region by the trench isolation insulating film or the like is made larger than the stress applied to the N-type active region by the trench isolation insulating film or the like, so that the drive current of the N-channel MOS transistor is reduced. The drive current in the P-channel MOS transistor can be increased while preventing the decrease.
[0038]
More specific configurations for generating such a stress difference will be described in the following embodiments.
[0039]
Embodiment 1 FIG.
Hereinafter, a semiconductor device according to the first embodiment of the present invention will be described.
[0040]
FIG. 1 is a plan view of the semiconductor device, and FIG. 2 is a sectional view taken along line II-II of FIG.
[0041]
As shown in these figures, in the semiconductor device, a P well 3 as a P type semiconductor layer and an N well 4 as an N type semiconductor layer were formed on a silicon substrate 1 as a semiconductor substrate. It is configured. A partial region of the P well 3 is defined as a P-type active region 5, and a plurality of first dummy active regions 11 are defined around the P-type active region 5. Further, a part of the N-well 4 is defined as the N-type active region 6, and a plurality of second dummy active regions 12 are defined around the N-type active region 6.
[0042]
In addition, between the P-type active region 5 and the N-type active region 6, between the P-type active region 5 and each of the first dummy active regions 11 adjacent thereto, between each of the first dummy active regions 11, A trench isolation insulating film 22 is formed between the N-type active region 6 and each of the second dummy active regions 12 adjacent thereto and between the second dummy active regions 12.
[0043]
The total length dimension of the boundary line 22La between each first dummy active region 11 and the trench isolation insulating film 22 in the region of the P well 3 is the second dummy active region 12 and the trench isolation insulating film 22 in the region of the N well 4. Is smaller than the total length of the boundary line 22Lb.
[0044]
More specifically, the P well 3 is formed by injecting a P-type impurity into the upper surface of the silicon substrate 1, and the N well 4 is formed by injecting an N-type impurity into the upper surface of the silicon substrate 1. Is formed. FIGS. 1 and 2 show a state in which a P well 3 is formed in the left half region of the silicon substrate 1 and an N well 4 is formed in the right half region of the silicon substrate 1. The broken line in FIG. , P well 3 and N well 4 are shown.
[0045]
Note that an N-type semiconductor substrate is used as a mother substrate, and a P-type impurity is implanted into a partial region on the upper surface of the N-type semiconductor substrate, or conversely, a P-type semiconductor substrate is used as a mother substrate and the P-type semiconductor substrate is used. An N-type impurity may be implanted into a partial region of the semiconductor substrate. In short, it suffices that a P-type semiconductor layer and an N-type semiconductor layer are formed on the silicon substrate 1 in the final configuration.
[0046]
The P well 3 is provided with a P-type active region 5 where an N-channel MOS transistor is to be formed. In FIG. 1, the P-type active region 5 is formed in a substantially square shape in plan view. By forming various elements such as a gate insulating film, a gate electrode, a drain region, and a source region in the P-type active region 5, an N-channel MOS transistor is formed.
[0047]
Similarly, the N-well 4 is provided with an N-type active region 6 in which a P-channel MOS transistor is to be formed. In FIG. 1, the N-type active region 6 is formed in a substantially rectangular shape in plan view. The N-type active region 6 is formed at a position adjacent to the P-type active region 5 at a predetermined interval. Then, by forming various elements such as a gate insulating film, a gate electrode, a drain region, and a source region in the N-type active region 6, a P-channel MOS transistor is formed.
[0048]
At least one first dummy active region 11 where no semiconductor element is formed is provided around the P-type active region 5 on the side of the P well 3. In FIG. 1, a plurality of first dummy active regions 11 are provided so as to surround three sides of the four sides of the P-type active region 5 except for the side adjacent to the N-type active region 6. Each of the first dummy active regions 11 is formed in a substantially square shape in a plan view, and is provided in a form (a chessboard pattern) in which the first dummy active regions 11 are alternately provided one by one along the rows and columns of the matrix. ing.
[0049]
At least one second dummy active region 12 in which no semiconductor element is formed is provided also on the N well 4 side and around the N-type active region 6. In FIG. 1, a plurality of second dummy active regions 12 are provided so as to surround three sides of the four sides of the N-type active region 6 except for the side adjacent to the P-type active region 5. Each of the second dummy active regions 11 is formed in a substantially square shape in plan view having substantially the same shape and size as the first dummy active region, and is arranged in a matrix.
[0050]
That is, in the chessboard pattern arrangement of the first dummy active regions 11, assuming an arrangement in which dummy active regions are arranged between the first dummy active regions 11, a matrix of the second dummy active regions 12 is formed. It is almost the same as the array.
[0051]
Further, the trench isolation insulating film 22 is formed on the upper surface of the P well 3 and the N well 4, and is formed on the P type active region 5, the first dummy active region 11, the N type active region 6, and the second dummy active region 12. Is formed by forming a trench (groove) 21 in a region excluding the above, and burying an insulating film 22 in the trench 21. The trench 21 is formed by etching the P well 3 and the N well 4 using, for example, an RIE (Reactive Ion Etching) device or an ECR (Electron Cyclotron Resonance) device. As the insulating film 22, for example, an oxide insulator such as a silicon oxide film is used.
[0052]
According to the semiconductor device configured as described above, the first dummy active region 11 and the second dummy active region 12 have substantially the same shape and substantially the same size. The arrangement density of the second dummy active regions 12 on the N well 4 side is higher than the arrangement density of the N well 11. Therefore, the total length dimension of the boundary line 22La between each first dummy active region 11 and the trench isolation insulating film 22 in the region of the P well 3 is the second dummy active region 12 and the trench isolation insulating film 22 in the region of the N well 4. Is smaller than the total length of the boundary line 22Lb.
[0053]
For this reason, the total stress that the stress generated at the boundary line 22La between the first dummy active region 11 and the trench isolation insulating film 22 on the side of the P well 3 is accumulated and applied to the P-type active region 5 is based on the same principle. Is smaller than the total stress applied to the N-side active region 6.
[0054]
Therefore, the reduction in the mobility of carriers can be reduced by reducing the stress generated in the P-type active region 5, and the reduction in the drive current of the N-channel MOS transistor can be reduced. At the same time, by increasing the stress generated in the N-type active region 6, the mobility of carriers can be increased, so that the drive current of the P-channel MOS transistor can be increased.
[0055]
In this semiconductor device, the total stress acting on the P-type active region 5 depends on the total length dimension of the boundary line 22La, and the total stress acting on the N-type active region 6 is the total length of the boundary line 22Lb. Depends on dimensions. Since the stress acting on the P-type active region 5 may be smaller than the stress acting on the N-type active region 6, the total length of the boundary line 22La may be smaller than the total length of the boundary line 22Lb. .
[0056]
As a configuration of the first dummy active region 11 and the second dummy active region 12 for realizing this, in addition to the configuration disclosed in FIG. 1, various configurations can be considered by changing the shape, size, and the like. Can be.
[0057]
For example, the number of the first dummy active regions 11 and the number of the second dummy active regions 12 are the same, the shape of each first dummy active region is circular, and the second dummy active region 12 is formed in a polygonal shape such as a triangular shape. May be.
[0058]
Embodiment 2 FIG.
Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described. The same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0059]
FIG. 3 is a plan view of the semiconductor device.
[0060]
As shown in the figure, in this semiconductor device, at least one dummy active region 32 where no semiconductor element is formed is provided around the N-type active region 6 on the side of the N-well 4 which is an N-type semiconductor layer. I have. In the present embodiment, a plurality of dummy active regions 32 are provided in the same manner as in the first embodiment.
[0061]
On the side of the P well 3 which is a P type semiconductor layer, a dummy active region where no semiconductor element is formed is not provided around the P type active region 5. All around the P-type active region 5, an isolation insulating film 22 is formed.
[0062]
In this semiconductor device, since the dummy active region 32 is provided around the N-type active region 6, the N-type active region 6 is formed on the N-type active region 6 for the same reason as described in the first embodiment. By generating a large stress, the drive current of the P-channel MOS transistor can be increased. At the same time, since no dummy active region is provided around the P-type active region 5, the stress generated in the P-type active region 5 is reduced to reduce the reduction in the drive current of the N-channel MOS transistor. Can be done.
[0063]
Embodiment 3 FIG.
Third Embodiment A semiconductor device according to a third embodiment of the present invention will be described. The same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0064]
FIG. 4 is a sectional view of the semiconductor device.
[0065]
As shown in the figure, in this semiconductor device, a stress suppressing film 40 is provided on a boundary surface between the P well 3 and the trench isolation insulating film 22. On the other hand, the stress suppressing film 40 is not provided on the interface between the N well 4 and the trench isolation insulating film 22.
[0066]
In the present embodiment, on both sides of the P-well 3, stress is applied between the P-type active region 5 and the dummy active region 11 and on both side surfaces and the entire bottom surface of each trench 21 formed between the dummy active regions 11. The suppression film 40 is provided.
[0067]
The arrangement of the dummy active regions 11 and 12 may be changed between the P-well 3 and the N-well 4 in the same manner as shown in FIG. 1, or as shown in FIG. The same may be applied to the P well 3 side and the N well 4 side. In the following embodiment, the arrangement of each dummy active region is not limited to the embodiment shown in FIG.
[0068]
Also, between the P well 3 and the N well 4, of the inner peripheral surface of the trench 21 formed between the P type active region 5 and the N type active region 6, the P type active region 5 side The stress suppressing film 40 is deposited on the side surface and the bottom half of the P-type active region 5 on the bottom surface.
[0069]
The stress suppression film 40 is deposited by, for example, a CVD (Chemical Vapor deposition) method or the like, and the following two types can be used.
[0070]
First, an oxygen permeation prevention film that blocks oxygen permeation can be used as the stress suppression film 40. As such an oxygen permeation prevention film, for example, silicon nitride (SiN) or the like can be used.
[0071]
The oxygen permeation prevention film prevents the oxidizing species from transmitting from the oxide insulator used as the trench isolation insulating film 22 to the P-type active region 5 and the dummy active region 11.
[0072]
Second, as the stress suppressing film 40, silicon (silicon doped with P-type impurities) forming the P-type active region 5 and the dummy active region 11 and an oxide forming the trench isolation insulating film 22 are used. It is possible to use a stress absorbing film that is more easily deformed than the insulator (either elastically deformed or plastically deformed). As such a stress suppressing film, for example, a boron oxide film or the like can be used.
[0073]
Then, by the deformation of the stress absorbing film, the stress generated between the trench isolation insulating film 22 and each of the P-type active region 5 and the dummy active region 11 is absorbed and relaxed.
[0074]
In this semiconductor device, when the oxygen permeation prevention film is used as the stress suppressing film 40, the oxidation of the P-type active region 5 and the dummy active region 11 is prevented, and the volume swelling due to the oxidation is also prevented. In the case where a stress absorbing film is used as the stress suppressing film 40, the stress absorbing film is deformed to form between the trench isolation insulating film 22 and each of the P-type active region 5 and the dummy active region 11. The stress is absorbed and relaxed. Therefore, in any case, the stress generated in the P-type active region 5 can be reduced, and the decrease in the drive current of the N-channel MOS transistor can be reduced.
[0075]
At the same time, with respect to the N-type active region 6, a relatively large stress is generated in the P-type active region 6 by volume swelling due to oxidation, thereby increasing the drive current of the P-channel MOS transistor. it can.
[0076]
In the present embodiment, the stress suppressing film 40 is provided on the entire inner peripheral surface of the trench 21 to be formed on the P well 3 side, but it is not always necessary. For example, the stress suppressing film 40 may be provided only on the inner peripheral surface of the trench 21 provided between the P-side active region 5 and the surrounding dummy active region 11. In short, if the stress suppressing film 40 is provided on at least a part of the boundary between the P well 3 and the trench isolation insulating film 22, the stress on the P-type active region 5 can be reduced.
[0077]
Embodiment 4 FIG.
Embodiment 4 A semiconductor device according to Embodiment 4 of the present invention will be described. The same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0078]
FIG. 5 is a sectional view of the semiconductor device.
[0079]
As shown in the figure, in this semiconductor device, the first trench isolation insulating film 50 provided on the P well 3 side and the second trench isolation insulating film 51 provided on the N well 4 side are different insulating materials. Is formed.
[0080]
That is, the first trench isolation insulating film 50 is provided between the P-type active region 5 and the dummy active region 11 and between each of the dummy active regions 11 on the P-well 3 side.
[0081]
The first trench isolation insulating film 50 is formed of a non-oxidized insulator which is an insulating material containing no oxygen atoms. As such a non-oxide insulator, for example, silicon nitride (SiN) or the like can be used.
[0082]
On the N well 4 side, a second trench isolation insulating film 51 is formed between the N-type active region 6 and the dummy active region 12 and between each dummy active region 12.
[0083]
This second trench isolation insulating film 51 is formed of an oxide insulator which is an insulating material containing oxygen atoms. As such an oxide insulator, for example, silicon oxide (SiO 2) ₂ ) Etc. can be used.
[0084]
In the trench 52 formed between the P-type active region 5 and the N-type active region 6, a half of the P-type active region 5 side is filled with a non-oxidized insulator 52a, and the N-type An oxide insulator 52b is embedded in a half portion of the active region 6 side.
[0085]
These structures are formed by, for example, selectively embedding a non-oxide insulator or an oxide insulator using a mask.
[0086]
In this semiconductor device, since the first trench isolation insulating film 50 is formed of a non-oxidized insulator, the P well 3 is hardly oxidized. Therefore, volume swelling due to oxidation can be prevented, the stress generated in the P-type active region 5 can be reduced, and the decrease in the drive current of the N-channel MOS transistor can be reduced. At the same time, since the second trench isolation insulating film 51 is formed of an oxide insulator, the N well 4 is easily oxidized. Therefore, a relatively large stress is generated in the N-type active region 6 due to volume swelling due to oxidation, and the drive current of the P-channel MOS transistor can be increased.
[0087]
Embodiment 5 FIG.
A semiconductor device according to a fifth embodiment of the present invention will be described. The same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0088]
FIG. 6 is a sectional view of the semiconductor device.
[0089]
As shown in the figure, in this semiconductor device, the thickness dimension H1 of the first trench isolation insulating film 60 provided on the P well 3 side and the second trench isolation insulating film 61 provided on the N well 4 side are different. The thickness H2 differs from each other, and the thickness H2 of the second trench isolation insulating film 61 is smaller than the thickness H1 of the first trench isolation insulating film 60, and is 0.5 nm or less.
[0090]
That is, on the P-well 3 side, the first trench isolation insulating film 60 is provided between the P-type active region 5 and the dummy active region 11 and between each of the dummy active regions 11.
[0091]
On the N well 4 side, a second trench isolation insulating film 61 is provided between the N-type active region 6 and the dummy active region 12 and between each dummy active region 12.
[0092]
The first trench isolation insulating film 60 and the second trench isolation insulating film 61 are formed by burying insulators such as oxides in the trenches 60g and 61g, respectively. At this time, by making the depth dimensions of the trenches 60g and 61g different, the first trench isolation insulating film 60 and the second trench isolation insulating film 61 having different thickness dimensions are formed.
[0093]
It is to be noted that making the depth dimensions of the trenches 60g and 61g different, for example, increases the etching time when forming the trench 60g on the P well 3 side and the etching time when forming the trench 61g on the N well 4 side. This is achieved by:
[0094]
In the trench 62g formed between the P-type active region 5 and the N-type active region 6, the depth of the half of the P-type active region 5 side is set to the N-type active region 6 side. Therefore, in the trench isolation insulating film 62 formed in the trench 62a, the thickness dimension of the half portion 62a on the P-type active region 5 side is N-type. The thickness is larger than the thickness of the half 62b on the region 6 side.
[0095]
According to this semiconductor device, since the thickness H1 of the first trench isolation insulating film 60 is larger than the thickness H2 of the second trench isolation insulating film 61, the stress generated in the P-type active region 5 is reduced. The stress can be made smaller than the stress generated in the N-type active region 6.
[0096]
More specifically, the stress caused by the trench isolation insulating films 60, 61, and 62 is largest at the bottom. This is because the stress generated on the upper side of the trench isolation insulating films 60, 61, 62 is alleviated by the warpage of the silicon substrate 1, or in a later etching process, the trench isolation insulating films 60, 61, 62 are reduced. A notch (V-shaped groove) is formed at a boundary portion on the surface layer side between the trench 62 and the trenches 60a, 61a, and 62a. On the other hand, with respect to the stress generated on the bottom side of the trench isolation insulating films 60, 61, 62, such relief of the stress cannot be expected. Therefore, the stress increases as approaching the bottom of the trench isolation insulating films 60, 61, 62.
[0097]
In this semiconductor device, since the thickness of the first trench isolation insulating film 60 is relatively large, its bottom is located at a position relatively far from the surface of the P well 3. Therefore, the stress acting on the surface of P-type active region 5 where the MOS transistor is to be formed is relatively small. Therefore, it is possible to reduce the decrease in the drive current of the N-channel MOS transistor.
[0098]
On the other hand, since the thickness of the second trench isolation insulating film 61 is relatively small, its bottom is located relatively close to the surface of the N well 4. Therefore, the stress acting on the surface of N-type active region 5 where the MOS transistor is to be formed is relatively large. Therefore, the drive current of the P-channel MOS transistor can be increased. In particular, by setting the thickness dimension of the second trench isolation insulating film 61 to 0.5 nm or less, the stress generated at the bottom portion effectively acts on the surface of the N-type active region 6, and the P-channel MOS transistor An increase in drive current can be expected.
[0099]
Embodiment 6 FIG.
A semiconductor device according to Embodiment 6 of the present invention will be described. The same components as those described in the fifth embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0100]
In this semiconductor device, similarly to the fifth embodiment, the thickness H1 of the first trench isolation insulating film 70 provided on the P well 73 side and the second trench isolation insulating film 71 provided on the N well 74 side Are different from each other, and the thickness H1 of the first trench isolation insulating film 70 is larger than the thickness H2 of the second trench isolation insulating film 71.
[0101]
However, it differs from the fifth embodiment in the following points.
[0102]
That is, the position of the bottom of the first trench isolation insulating film 70 in the thickness direction of the silicon substrate 1 and the position of the bottom of the second trench isolation insulating film 71 are substantially the same.
[0103]
The main surface of the N well 74 (the upper surface in FIG. 7) is located one step below the main surface of the P well 73 (the upper surface in FIG. 7), and the main surface of the P well 73 in the thickness direction of the silicon substrate 1 is Distance H1 to the bottom of one trench isolation insulating film 70 is larger than distance H2 between the main surface of N well 74 and the bottom of second trench isolation insulating film 71 in the thickness direction of silicon substrate 1.
[0104]
In the trench isolation insulating film 72 provided between the P-type active region 5 and the N-type active region 6, the thickness H1 of the half portion 72a on the P-type active region 5 side is equal to the N-type active region. The thickness is larger than the thickness H2 of the half 72b on the region 6 side.
[0105]
Such a semiconductor device can be manufactured as follows.
[0106]
First, a silicon substrate 1 having a P well 73 and an N well 74 is prepared, and trenches 70g, 71g, 72g (see FIG. 8) having a predetermined depth are formed on both of the P wells 73 and 74 by etching. Form. Since these trenches 70g, 71g, 72g all have the same depth dimension, they can be formed collectively in the same forming step.
[0107]
Next, an insulator is buried in the trenches 70g, 71g, 72g to form trench isolation oxide films 70, 71, 72. In this state, the result is as shown in FIG.
[0108]
Thereafter, the surface layer on the N well 73 side is removed by a predetermined thickness H3. In FIG. 8, the portion above the two-dot chain line on the N well 74 side is removed. This removal is performed by, for example, an etching method.
[0109]
Thus, the semiconductor device having the configuration shown in FIG. 7 is obtained.
[0110]
In such a semiconductor device as well, for the same reason as in the fifth embodiment, it is possible to reduce the decrease in the drive current of the N-channel MOS transistor and to increase the drive current of the P-channel MOS transistor. be able to.
[0111]
In particular, in this semiconductor device, after forming trenches 70g, 71g, and 72g having the same depth dimension, the surface layer of the N well 74 is removed by a predetermined thickness, so that the trenches are formed on the P well 73 side and the N well 74 side. Since the thickness dimensions of the isolation insulating films 70, 71, 72 can be different from each other, the formation of the trenches 70g, 71g, 72g is easy.
[0112]
Embodiment 7 FIG.
A semiconductor device according to a seventh embodiment of the present invention will be described. The same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0113]
FIG. 9 is a sectional view of this semiconductor device.
[0114]
As shown in the figure, in this semiconductor device, a first trench isolation insulating film 80 is formed on the P well 83 side, and a second trench isolation insulating film 81 is formed on the N well 84 side. The inclination angle θ1 of the side surface of the first trench isolation insulating film 80 with respect to the normal direction of the surface of the P well 83 is the inclination angle of the side surface of the second trench isolation insulating film 81 with respect to the normal direction of the surface of the N well 84. It is larger than θ2.
[0115]
In the trench isolation insulating film 82 provided between the P-type active region 5 and the N-type active region 6, the inclination angle (θ1 here) of the side surface on the P-type active region 5 side is set to the N-type. The inclination angle is larger than the inclination angle (here, θ2) on the active region 6 side.
[0116]
When the inclination angle θ2 on the N-well 84 side is substantially 0 °, the inclination angle θ1 on the P-well 83 side may be, for example, greater than 0 ° and 30 ° or less.
[0117]
Such adjustment of the inclination angles θ1 and θ2 of the side surfaces can be dealt with, for example, when the trenches 80g, 81g, and 82g are formed by wet etching, by changing the manner of removing the reaction products.
[0118]
According to the semiconductor device configured as described above, since the inclination angle θ1 of the side surface of the first trench isolation insulating film 80 is relatively large, the stress generated at the boundary surface between the P well 83 and the first trench isolation insulating film 80. Are easily dispersed in the inclination direction. Therefore, the stress generated in the P-type active region 5 can be reduced, and the decrease in the drive current of the N-channel MOS transistor can be reduced. At the same time, since the inclination angle θ2 of the side surface of the second trench isolation insulating film 81 is relatively small, the stress generated at the interface between the N well 84 and the second trench isolation insulating film 81 is hardly dispersed, and the N-type active region is formed. 6, a relatively large stress is generated, and the drive current of the P-channel MOS transistor can be increased.
[0119]
Embodiment 8 FIG.
Embodiment 8 A semiconductor device according to Embodiment 8 of the present invention will be described. The same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0120]
FIG. 10 is a sectional view of the semiconductor device.
[0121]
In this semiconductor device, a stress generating film 90 for generating a stress in the N-type active region 6 is provided above at least a part of the N-type active region 6. Further, such a stress generating film 90 is not provided on the P-type active region 5 side.
[0122]
In the present embodiment, an insulator is assumed as the stress generating film 90, and the arrangement of the stress generating film 90 is as follows.
[0123]
That is, a gate insulator 95 such as a polysilicon film, a gate electrode 96, and the like are formed in the N-type active region 6 on the N-well 4 side to form a P-channel transistor. The stress generating film 90 is formed so as to cover (in FIG. 10, the stress generating film 90 is formed so as to cover the entire area of the N well 4, the trench isolation insulating film 22 formed thereon, and the gate electrode 96. Is shown). An interlayer insulating film 91 is formed on the stress generating film 90.
[0124]
The stress generating film 90 is formed by depositing a material having a different coefficient of thermal expansion from silicon at a relatively high temperature. For example, the stress generating film 90 is formed by depositing silicon nitride (SiN) by a CVD method.
[0125]
That is, when the stress generating film 90 is formed and then cooled, the stress generating film 90 contracts relatively largely due to the difference in the coefficient of thermal expansion between the silicon substrate 1 and the stress generating film 90. A relatively high stress is generated in the region.
[0126]
According to this semiconductor device, a relatively large stress is generated in the N-type active region 6 by the stress generating film 90 provided on the upper side of the N-well 4 to increase the drive current of the P-channel MOS transistor. Can be. Since such a stress generating film 90 is not provided in the P-type active region 5, it is possible to prevent the drive current of the N-channel MOS transistor from decreasing.
[0127]
In addition, the formation mode of the stress generating film 90 is not limited to the above. For example, a stress generating film may be formed between an interlayer insulating film formed on a P-channel MOS transistor formed on the silicon substrate 1 and a wiring pattern formed on the interlayer insulating film. . When forming a multilayer wiring, the stress generating film 90 may be formed on at least one of the wiring layers. In short, regardless of the position between the layers, it is sufficient that the stress generating film 90 is formed on at least a part of the corresponding region of the N well 4 and the stress generating film 90 is not formed on the P well side.
[0128]
Embodiment 9 FIG.
Embodiment 9 A semiconductor device according to Embodiment 9 of the present invention will be described. The same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0129]
FIG. 11 is a sectional view of the semiconductor device.
[0130]
This semiconductor device basically has a stress that causes a stress in the N-type active region 6 above at least a part of the N-type active region 6, similarly to the semiconductor device according to the eighth embodiment. A generator film 100 is provided.
[0131]
In the present embodiment, a conductor is assumed as the stress generating film 100, and the arrangement of the stress generating film 100 is as follows.
[0132]
That is, after a gate insulator 105 such as a polysilicon film and a gate electrode 106 are formed in the N-type active region 6 on the side of the N well 4, the stress generating film 100 is formed on the gate electrode 106.
[0133]
The stress generating film 100 is formed by depositing a material having a different coefficient of thermal expansion from silicon at a relatively high temperature. For example, the stress generating film 100 is formed by depositing tungsten or tungsten silicide by the CVD method.
[0134]
Then, when the stress generating film 100 is formed and then cooled, the stress generating film 100 contracts relatively largely due to the difference in the coefficient of thermal expansion between the silicon substrate 1 and the stress generating film 100, and the gate electrode 106 and the gate insulating film Through the object 105, relatively high stress is generated in the N-type active regions 6 thereunder.
[0135]
In order to effectively apply the stress generated by the stress generating film 100 to the N-type active region 6, the thickness of the gate insulating film 105 on the N-channel MOS transistor side (P-well 3 side) should be larger than that of the P-channel MOS transistor. It is preferable to reduce the thickness of the gate insulating film 105 on the side (N-well 4 side).
[0136]
According to this semiconductor device, a relatively large stress is generated in the N-type active region 6 by the stress generating film 100 provided on the gate electrode 106 to increase the drive current of the P-channel MOS transistor. Can be. Since such a stress generating film 100 is not provided for the gate electrode 106 on the side of the N-channel MOS transistor, it is possible to prevent a decrease in the drive current of the N-channel MOS transistor.
[0137]
Embodiment 10 FIG.
A semiconductor device according to a tenth embodiment of the present invention will be described. The same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0138]
FIG. 12 is a sectional view of the semiconductor device.
[0139]
In this semiconductor device, the strain layer 110 is provided in the N well 114 (corresponding to the N well 4). On the other hand, the P well 113 (corresponding to the P well 3) is not provided with such a strained layer 110.
[0140]
The strained layer 110 is formed in a layer at a depth within the N-well 114 at a predetermined distance from the main surface. The reason why the strained layer 110 is formed at a predetermined depth position of the N well 114 is to prevent the operation of the channel between the source and the drain in the surface layer of the active region 116 of the N well 114.
[0141]
The strained layer 110 has a lattice constant different from the lattice constant of silicon constituting the N well 114. For example, a single crystal of silicon and a single crystal of silicon germanium (SiGe) have different lattice constants. Accordingly, when silicon germanium and silicon were epitaxially grown in the region of the N well 114 on the silicon single crystal substrate serving as the mother substrate, the strained layer 110 was provided in the region of the N well 114 as shown in FIG. A silicon substrate 111 is obtained.
[0142]
On the silicon substrate 111, a P-well 113 and an N-well 114 are formed to define dummy active regions 11 and 12, and respective P-type and N-type active regions 115 and 116, and an N-channel MOS A semiconductor device is manufactured by forming a transistor and a P-channel MOS transistor.
[0143]
In this semiconductor device, the strained layer 110 having a different lattice constant from the silicon constituting the N well 114 is provided in the region on the N well 114 side (in the present embodiment, almost the entire area of the N well 114). The structural mismatch can cause stress in the N-type active region 115. Thereby, the drive current of the P-channel MOS transistor can be increased. Since such a strained layer is not provided in the P-type active region 115, it is possible to prevent the drive current of the N-channel MOS transistor from decreasing.
[0144]
Note that it is not always necessary to provide a strained layer in the entire region of the N well 114. For example, even if a strained layer is provided only in the N-type active region 116 or only in the dummy active region 11. Good.
[0145]
Embodiment 11 FIG.
Hereinafter, a semiconductor device according to an eleventh embodiment of the present invention will be described. The same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0146]
FIG. 13 is a sectional view of the semiconductor device.
[0147]
This semiconductor device has a strained layer 120 provided in an N-well 124 as in the tenth embodiment, but differs from the tenth embodiment in the following points.
[0148]
That is, in the tenth embodiment, the surfaces of the P well 113 and the N well 114 are flush (the positions in the thickness direction of the substrate are aligned), but in the present embodiment, the P well 123 is provided. Is located at a position recessed from the position of the main surface of the N-well 124.
[0149]
Further, the strained layer 120 is formed at a position between the main surface of the P well 123 and the main surface of the N well 124 in the thickness direction of the semiconductor substrate 121.
[0150]
Such a semiconductor device can be manufactured as follows.
[0151]
First, a substrate 121 having a strained layer 120 formed over substantially the entire main surface is prepared, and impurities are appropriately diffused into the substrate 121 to form a P well 123 and an N well 124.
[0152]
Thereafter, as shown in FIG. 14, a trench isolation insulating film 22 is formed between each of the P-type and N-type active regions 124 and 125 and each of the dummy active regions 11 and 12.
[0153]
Then, in the region of the P well 123, the surface layer is removed together with the strained layer 120 (the portion above the two-dot chain line of the P well 123 is removed in FIG. 14). The removal is performed by, for example, an etching method or the like.
[0154]
Thereby, the substrate 121 having the strain layer 120 only on the N well 124 side is obtained.
[0155]
Thereafter, MOS transistors are appropriately formed in the P well 123 and the N well 124.
[0156]
In the semiconductor device manufactured as described above, for the same reason as in the tenth embodiment, the decrease in the drive current of the N-channel MOS transistor can be reduced, and at the same time, the drive current of the P-channel MOS transistor can be reduced. Can be increased.
[0157]
In particular, in this semiconductor device, a semiconductor device in which the strained layer 120 is provided only in the N well 124 can be manufactured from the substrate 121 in which the strained layer 120 is formed in almost the entire main surface. Manufacturing becomes easy.
[0158]
【The invention's effect】
As described above, according to the semiconductor device according to the first aspect of the present invention, since the stress acting on the first active region is smaller than the stress occurring in the second active region, the N-channel MOS transistor is provided in the first active region. By forming the transistor, a decrease in driving current can be reduced. At the same time, the drive current can be increased by forming a P-channel MOS transistor in the second active region.
[0159]
According to the semiconductor device of the second aspect, since the total length dimension of the boundary line between the first dummy active region and the trench isolation insulating film in the region of the P-type semiconductor layer is relatively small, it occurs in the P-type active region. By reducing the stress, the decrease in the drive current of the N-channel MOS transistor can be reduced. At the same time, since the total length dimension of the boundary line between the second dummy active region and the trench isolation insulating film in the region of the N-type semiconductor layer is relatively large, a large stress is generated in the N-type active region and the P-channel type The drive current of the MOS transistor can be increased.
[0160]
According to the third aspect of the present invention, since no dummy active region is formed around the P-type active region, the stress generated in the P-type active region is reduced, and the N-channel type active region is reduced. It is possible to reduce the decrease in the drive current of the MOS transistor. At the same time, since a dummy active region is provided around the N-type active region, a large stress is generated in the N-type active region to increase the drive current of the P-channel MOS transistor. it can.
[0161]
According to the fourth aspect of the present invention, at least a part of a boundary surface between the P-type semiconductor layer and the trench isolation oxide insulating film has a boundary surface between the P-type semiconductor layer and the trench isolation insulating film. Since the stress suppressing film for suppressing the stress is provided, the stress is suppressed by the stress suppressing film. Therefore, the stress generated in the P-type active region can be reduced, and the decrease in the drive current of the N-channel MOS transistor can be reduced. At the same time, with respect to the N-type active region, a relatively large stress is generated in the P-type active region by the stress generated at the boundary with the trench isolation insulating film, thereby increasing the drive current of the P-channel MOS transistor. be able to.
[0162]
Furthermore, according to the fifth aspect of the present invention, oxidation on the P-type semiconductor layer side is prevented, and volume swelling due to oxidation is also prevented. Thereby, the stress generated in the P-type active region can be reduced, and the decrease in the drive current of the N-channel MOS transistor can be reduced. At the same time, in the N-type active region, a relatively large stress is generated in the P-type active region due to volume swelling due to oxidation, so that the drive current of the P-channel MOS transistor can be increased.
[0163]
According to the sixth aspect of the present invention, the stress generated at the interface between the P-type semiconductor layer and the trench isolation insulating film is absorbed by the stress absorbing film. Therefore, the stress generated in the P-type active region can be reduced, and the decrease in the drive current of the N-channel MOS transistor can be reduced. At the same time, with respect to the N-type active region, a relatively large stress is generated in the P-type active region by the stress generated at the boundary with the trench isolation insulating film, thereby increasing the drive current of the P-channel MOS transistor. be able to.
[0164]
According to the invention described in claim 7, since the first trench isolation insulating film is formed of a non-oxidized insulator, the P-type semiconductor layer is hardly oxidized. Therefore, volume swelling due to oxidation can be prevented, the stress generated in the P-type active region can be reduced, and the decrease in the drive current of the N-channel MOS transistor can be reduced. At the same time, since the second trench isolation insulating film is formed of an oxide insulator, the N-type semiconductor layer is easily oxidized. Therefore, a relatively large stress is generated in the N-type active region due to volume swelling due to oxidation, and the drive current of the P-channel MOS transistor can be increased.
[0165]
According to the eighth aspect of the present invention, since the thickness of the first trench isolation insulating film is relatively large, the stress generated in the P-type active region is reduced, and the decrease in the drive current of the N-channel MOS transistor is reduced. Can be done. At the same time, since the thickness of the second trench isolation insulating film is relatively small and not more than 0.5 nm, a relatively large stress is generated in the N-type active region to increase the drive current of the P-channel MOS transistor. Can be planned.
[0166]
According to the ninth aspect of the present invention, the position of the bottom of the first trench isolation insulating film and the position of the second trench isolation insulating film in the thickness direction of the semiconductor substrate are substantially the same. The trench in which the insulating film is buried and the trench in which the second trench isolation insulating film is buried can be manufactured in the same step.
[0167]
According to the tenth aspect of the present invention, since the inclination angle of the side surface of the first trench isolation insulating film is relatively large, the stress generated at the boundary surface between the P-type semiconductor layer and the first trench isolation insulating film is shifted in the inclination direction. It becomes easy to disperse. Therefore, the stress generated in the P-type active region can be reduced, and the decrease in the drive current of the N-channel MOS transistor can be reduced. At the same time, since the inclination angle of the side surface of the second trench isolation insulating film is relatively small, the stress generated at the interface between the N-type semiconductor layer and the second trench isolation insulating film is hardly dispersed, and compared with the N-type active region. By generating an excessively large stress, the drive current of the P-channel MOS transistor can be increased.
[0168]
According to the semiconductor device of the present invention, a relatively large stress is generated in the N-type active region by the stress generating film provided on the upper side of the N-type semiconductor layer, thereby increasing the drive current of the P-channel MOS transistor. Can be achieved. Since such a stress generating film is not provided in the P-type active region, a decrease in the drive current of the N-channel MOS transistor can be prevented.
[0169]
According to the twelfth aspect, stress can be generated in the N-type active region due to a difference in thermal expansion coefficient from silicon used as a semiconductor substrate.
[0170]
According to the thirteenth aspect, a relatively large stress can be generated in the N-type active region by the stress generating film provided above the N-type active region.
[0171]
According to the semiconductor device of the fourteenth aspect, stress can be generated in the N-type active region via the gate electrode.
[0172]
According to the fifteenth aspect, a relatively large stress is generated in the N-type active region by the strained layer provided in the N-type active region in the N-type semiconductor layer, so that the P-channel MOS is formed. The driving current of the transistor can be increased. Since such a strained layer is not provided in the P-type active region, it is possible to prevent the drive current of the N-channel MOS transistor from decreasing.
[0173]
According to the sixteenth aspect, stress can be generated in the N-type active region due to the mismatch of the lattice constant.
[0174]
According to the seventeenth aspect, the strained layer is formed at a position between the main surface of the P-type active region and the N-type active region in the thickness direction of the semiconductor substrate. After forming the strained layers in both the P-type active region and the N-type active region, the main surface surface portion of the P-type active region is deleted to eliminate the strained layer in the P-type active region. can do.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a sectional view taken along line II-II of FIG.
FIG. 3 is a schematic plan view showing a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a schematic sectional view showing a semiconductor device according to a third embodiment of the present invention.
FIG. 5 is a schematic sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
FIG. 6 is a schematic sectional view showing a semiconductor device according to a fifth embodiment of the present invention.
FIG. 7 is a schematic sectional view showing a semiconductor device according to a sixth embodiment of the present invention.
FIG. 8 is a schematic cross-sectional view showing a state in the middle of the manufacturing process of the semiconductor device of the above.
FIG. 9 is a schematic sectional view showing a semiconductor device according to a seventh embodiment of the present invention.
FIG. 10 is a schematic sectional view showing a semiconductor device according to an eighth embodiment of the present invention.
FIG. 11 is a schematic sectional view showing a semiconductor device according to a ninth embodiment of the present invention.
FIG. 12 is a schematic sectional view showing a semiconductor device according to a tenth embodiment of the present invention.
FIG. 13 is a schematic sectional view showing a semiconductor device according to an eleventh embodiment of the present invention.
FIG. 14 is a schematic sectional view showing a state in the course of the manufacturing process of the semiconductor device;
FIG. 15 is a schematic plan view showing a conventional semiconductor device.
FIG. 16 is a sectional view taken along line XVI-XVI in FIG. 15;
[Explanation of symbols]
1 Silicon substrate, 3P well, 4N well, 5P type active region, 6N type active region, 11, 12 dummy active region, 21 trench, 22 trench isolation insulating film, 22La, 22Lb boundary line.

Claims (17)

A semiconductor substrate having a first conductive type first semiconductor layer and a second conductive type second semiconductor layer provided on the main surface;
A first active region of a first conductivity type provided in the first semiconductor layer to form a second channel type MOS transistor;
A second conductivity type second active region provided in the second semiconductor layer and formed with a first channel type MOS transistor;
A trench isolation insulating film,
In a semiconductor device having
A semiconductor device, wherein a stress applied to the first active region from the trench isolation insulating film is set to be different from a stress applied to the second active region from the trench isolation insulating film. On the other hand, a semiconductor substrate provided with a P-type semiconductor layer and an N-type semiconductor layer on a main surface;
A P-type active region provided in the P-type semiconductor layer and formed with an N-channel MOS transistor;
At least one first dummy active region which is the P-type semiconductor layer and is provided around the P-type active region;
An N-type active region provided in the N-type semiconductor layer and forming a P-channel MOS transistor;
At least one second dummy active region that is the N-type semiconductor layer and is provided around the N-type active region;
A trench isolation insulating film interposed between each of the P-type active region, the first dummy active region, the N-type active region, and the second dummy active region;
With
The total length dimension of the boundary line between the first dummy active region and the trench isolation insulating film in the region of the P-type semiconductor layer is equal to the second dummy active region and the trench isolation insulating film in the region of the N-type semiconductor layer. A semiconductor device smaller than the total length dimension of the boundary line with the semiconductor device. On the other hand, a semiconductor substrate provided with a P-type semiconductor layer and an N-type semiconductor layer on a main surface;
A P-type active region provided in the P-type semiconductor layer and formed with an N-channel MOS transistor;
An N-type active region provided in the N-type semiconductor layer and forming a P-channel MOS transistor;
At least one dummy active region is provided only around the N-type semiconductor region and the N-type active region;
A semiconductor device, wherein a trench isolation insulating film is interposed between each of the P-type active region, the dummy active region, and the N-type active region. A semiconductor substrate having a P-type semiconductor layer and an N-type semiconductor layer;
A P-type active region provided in the P-type semiconductor layer and formed with an N-channel MOS transistor;
An N-type active region provided in the N-type semiconductor layer and forming a P-channel MOS transistor;
A trench isolation insulating film provided on each of the P-type semiconductor layer and the N-type semiconductor layer;
With
A semiconductor device, wherein a stress suppression film for suppressing stress acting on the boundary surface is provided on at least a part of a boundary surface between the P-type semiconductor layer and the trench isolation insulating film. The semiconductor device according to claim 4, wherein
The semiconductor device, wherein the stress suppression film is an oxidized species permeation preventing film that prevents transmission of oxidized species. The semiconductor device according to claim 4, wherein
The semiconductor device, wherein the stress suppressing film is a stress absorbing film that is easier to deform than the P-type semiconductor layer and the trench isolation insulating film. On the other hand, a semiconductor substrate provided with a P-type semiconductor layer and an N-type semiconductor layer on a main surface;
A P-type active region provided in the P-type semiconductor layer and formed with an N-channel MOS transistor;
An N-type active region provided in the N-type semiconductor layer and forming a P-channel MOS transistor;
A first trench isolation insulating film provided in the P-type semiconductor layer;
A second trench isolation insulating film provided in the N-type semiconductor layer;
With
The semiconductor device, wherein the first trench isolation insulating film is formed of a non-oxide insulator, and the second trench isolation insulating film is formed of an oxide insulator. On the other hand, a semiconductor substrate provided with a P-type semiconductor layer and an N-type semiconductor layer on a main surface;
A P-type active region provided in the P-type semiconductor layer and formed with an N-channel MOS transistor;
An N-type active region provided in the N-type semiconductor layer and forming a P-channel MOS transistor;
A first trench isolation insulating film provided in the P-type semiconductor layer;
A second trench isolation insulating film provided in the N-type semiconductor layer;
With
A semiconductor device, wherein a thickness dimension of the second trench isolation insulating film is smaller than a thickness dimension of the first trench isolation insulating film and is equal to or less than 0.5 nm. 9. The semiconductor device according to claim 8, wherein:
The position of the bottom of the first trench isolation insulating film in the thickness direction of the semiconductor substrate is substantially the same as the position of the bottom of the second trench isolation insulating film, and the P-type semiconductor in the thickness direction of the semiconductor substrate. The distance between one main surface of the layer and the bottom of the first trench isolation insulating film is determined by the distance between the one main surface of the N-type semiconductor layer and the bottom of the second trench isolation insulating film in the thickness direction of the semiconductor substrate. A semiconductor device that is larger than its dimensions. On the other hand, a semiconductor substrate provided with a P-type semiconductor layer and an N-type semiconductor layer on a main surface;
A P-type active region provided in the P-type semiconductor layer and formed with an N-channel MOS transistor;
An N-type active region provided in the N-type semiconductor layer and forming a P-channel MOS transistor;
A first trench isolation insulating film provided in the P-type semiconductor layer;
A second trench isolation insulating film provided in the N-type semiconductor layer;
With
The inclination angle of the side surface of the first trench isolation insulating film with respect to the normal direction of the surface of the P-type semiconductor layer is larger than the inclination angle of the side surface of the second trench isolation insulating film with respect to the normal direction of the surface of the N-type semiconductor layer. Large, semiconductor device. On the other hand, a semiconductor substrate provided with a P-type semiconductor layer and an N-type semiconductor layer on a main surface;
A P-type active region provided in the P-type semiconductor layer and formed with an N-channel MOS transistor;
An N-type active region provided in the N-type semiconductor layer and forming a P-channel MOS transistor;
A stress-generating film that is provided above at least a part of the N-type active region and generates a stress in the N-type active region;
A semiconductor device comprising: The semiconductor device according to claim 11, wherein
The semiconductor device, wherein the stress generating film is formed of a material having a different coefficient of thermal expansion from the semiconductor substrate. The semiconductor device according to claim 11 or claim 12, wherein
The semiconductor device, wherein the stress generating film is an insulating film provided above the N-type active region. The semiconductor device according to claim 11 or claim 12, wherein
The semiconductor device, wherein the stress generation film is a conductor film provided above a gate electrode formed in an N-type active region. On the other hand, a semiconductor substrate provided with a P-type semiconductor layer and an N-type semiconductor layer on a main surface;
A P-type active region provided in the P-type semiconductor layer and formed with an N-channel MOS transistor;
An N-type active region provided in the N-type semiconductor layer and forming a P-channel MOS transistor;
A strain layer provided in the N-type semiconductor layer and causing a stress in the N-type active region;
A semiconductor device comprising: The semiconductor device according to claim 15, wherein
The semiconductor device, wherein the strained layer has a lattice constant different from a lattice constant of the N-type semiconductor layer. The semiconductor device according to claim 15, wherein:
The position of one main surface of the P-type active region in the thickness direction of the semiconductor substrate is at a position recessed from one main surface of the N-type active region,
The semiconductor device, wherein the strain layer is formed at a position between one main surface of the P-type active region and one main surface of the N-type active region in a thickness direction of the semiconductor substrate.

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