JP2004055763A - Nonvolatile semiconductor memory device, and method for driving and manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately stably generate a reference electric potential, required for a differential sense amplifier to speedily read out data from a non-volatile semiconductor storage unit. <P>SOLUTION: An electric potential of a bit line B3, as the reference electric potential to the electric potential on a bit line B0 of a memory cell MC0, is generated by the steps of connecting a drain and a gate to each bit line (B0, B3), connecting a gate to a first MOSFET (TA0, TA3) having a floating gate structure and a dummy word line (DW0, DW1). As a result, a dummy cell with a second MODFET (TB0, TB3) connected to the first MOSFET in series, having a floating gate structure is constituted. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, a driving method thereof, and a manufacturing method thereof.
[0002]
[Prior art]
A conventional nonvolatile semiconductor memory device has a large capacity that requires high-speed reading as disclosed in, for example, JP-A-1-296495 (conventional example 1) and JP-A-6-267286 (conventional example 2). Used as flash memory.
[0003]
Hereinafter, the configuration and operation of Conventional Example 1 will be described with reference to FIGS. Note that the flash memory cell in the nonvolatile semiconductor memory device of Conventional Example 1 is of a split gate type, and reading is performed by applying a source bias. Differently, a case where a flash memory cell is of a stack gate type and reading is performed by applying a drain bias will be described. This structural difference does not relate to the solution of the present invention.
[0004]
FIG. 12 is a circuit diagram showing a configuration example of a nonvolatile semiconductor memory device equivalent to Conventional Example 1. 12, a nonvolatile semiconductor memory device equivalent to Conventional Example 1 includes a sense amplifier 1, a row decoder 2, a column decoder 3, precharge MOS transistors 24, 25, 26, 27, column gate MOS transistors 28, 29, and a block. It includes transistors Q0, Q1, Q2, Q3 and dummy cells DM0, DM1, DM2, DM3. MC0 is a memory cell to be read. The memory cell array is connected to four word lines W0, W1, W2, W3 and four bit lines B0, B1, B2, B3. Further, wirings BLT0, BLT1, BLT2, BLT3 are connected to the gates of the block transistors Q0 to Q3, respectively, a dummy word line DW0 is connected to the dummy cells DM0, DM1, and a dummy word line DW1 is connected to the dummy cells DM2, DM3. I have.
[0005]
According to the reading means of the nonvolatile semiconductor memory device thus configured, when the memory cell MC0 is selected, the potentials of BLT0 and BLT3 become high, Q0 and Q3 conduct, and the two bit lines B0 And B3 are connected to the sense amplifier 1. After precharging the bit lines B0 and B3 to the same potential, for example, Vbit of about 1.0 to 1.5 V, the dummy word line DW1 and the word line W0 are set to a high potential. As a result, the memory cell MC0 and the dummy cell DM3 are selected.
[0006]
At this time, the potential of the bit line B3 gradually decreases from Vbit to 0V due to the current flowing to the ground potential via the dummy cell DM3. On the other hand, when the memory cell MC0 is in the erased state, the potential of the bit line B0 rapidly drops from Vbit to 0V due to the current flowing to the ground potential via the memory cell MC0. Changes only slightly.
[0007]
FIG. 13 is a diagram showing a time change of the potentials of the bit lines B0 and B3. In FIG. 13, at the time Ts when the difference between the potential of the bit line B3 and the potential of the bit line B0 becomes an appropriate level, the potentials of BLT0 and BLT3 are lowered to a low potential almost simultaneously with raising the potential of φ1 of the sense amplifier 1. , Q0 and Q3 become non-conductive, and then φ2 of the sense amplifier 1 is further set to 0V.
[0008]
As a result, the potential difference between the bit line B3 and the bit line B0 is amplified to the amplitude of the power supply voltage by the sense amplifier 1, and the input / output lines I / O, * I / O (here, In * I / O, an inverted signal of I / O is input / output).
[0009]
Although not shown, in the nonvolatile semiconductor memory device of Conventional Example 2, a dummy cell is formed by connecting a plurality of memory cells in a series connection structure, and the current driving capability of the dummy cell is almost half that of the memory cell. Thus, the reference potential can be generated with higher precision than in the nonvolatile semiconductor memory device of the first conventional example.
[0010]
[Problems to be solved by the invention]
As shown in FIG. 13, the reference potential (potential of bit line B3) of the differential sense amplifier as in the above-described conventional example 1 is Vbit higher than the potential of bit line B0 from which data of memory cell MC0 is read. And 0V.
[0011]
However, as shown in FIG. 14A, if the current driving capability of the dummy cell DM3 is set high enough to sufficiently drive the capacitance and resistance of the bit line, the potential of the bit line B3 will pass through the dummy cell DM3 when reading is delayed from the time Ts. 0V rapidly due to the flowing current (time Tf). Therefore, there is almost no difference between the potential of bit line B0 and the potential of bit line B3 when memory cell MC0 is in the erased state, and even if there is slight noise, differential sense amplifier 1 is in the erased state. If a certain memory cell MC0 is in a write state, erroneous read may be performed.
[0012]
On the other hand, as shown in FIG. 14B, when the current driving capability of the dummy cell DM3 is set to be low, erroneous reading may occur if the memory cell MC0 is in the written state and is in the erased state, contrary to the case shown in FIG. 14A. .
[0013]
In particular, when the capacity of the bit line changes depending on the number of memory cells commonly connected to the bit line, the write state thereof, or differs between chips due to process variations, the reference potential of the dummy cell is changed. There is a problem that the current driving capability and the capacitance and resistance of the bit line vary, making it difficult to design the sense amplifier.
[0014]
In addition, when the same structure as a regular memory cell is adopted as a dummy cell, it is necessary to use means such as controlling the word line voltage of the dummy cell in order to make the current of the dummy cell smaller than that of the regular cell. Another problem is that a voltage different from the read gate voltage of the cell must be generated.
[0015]
On the other hand, the dummy cell has a different structure from the normal memory cell, for example, the dummy cell has a structure in which a plurality of memory cells are connected in series as in the above-described nonvolatile semiconductor memory device of Conventional Example 2, or the gate length of the dummy cell is reduced. If the current drive capability of the dummy cell is made half or less of that of the normal memory cell by making it longer than the normal memory cell, the capacity of the dummy word line becomes more than twice as large as the word line of the normal memory cell. There is also a problem that the read speed is delayed or the current driving capability of the peripheral circuit for driving the dummy word line must be increased in order to prevent the delay.
[0016]
Also, unlike the above conventional example, even when the dummy cell is not a nonvolatile semiconductor memory device, the current drive capability of the dummy cell is similarly designed at a fixed ratio with respect to the normal memory cell, and the capacity of the bit line and the There is a problem that the reference potential varies due to variations in resistance.
[0017]
Further, as in the nonvolatile semiconductor memory device of Conventional Example 2, the dummy bit has a structure in which a plurality of memory cells are connected in series, so that the reference bit line is special, the chip area is increased, and There is also a problem that the capacity of the reference bit line is different from that of the normal memory cell array.
[0018]
In addition, if the dummy cell is a nonvolatile semiconductor memory device as in the above-described conventional example, it is necessary to design a sense amplifier by taking into account its time-dependent variation, which causes a problem that high-speed reading is hindered.
[0019]
The present invention has been made in view of the above problems, and has as its object to accurately and stably supply a reference potential necessary for a differential sense amplifier in order to read data from a nonvolatile semiconductor memory device at high speed. An object of the present invention is to provide a nonvolatile semiconductor memory device that can be generated, a driving method thereof, and a manufacturing method thereof.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, a first nonvolatile semiconductor memory device of the present invention includes a nonvolatile memory cell coupled to a corresponding first bit line, a first source line, and a first word line. A dummy cell coupled to the second bit line, the second source line, and the second word line; and a differential sense amplifier to which the first and second bit lines are selectively connected, wherein the dummy cells are connected in series. And a source diffusion layer or a drain diffusion layer of the first MOSFET is connected to a second bit line, and a source diffusion layer or a drain diffusion layer of the second MOSFET is connected to a second source line. Connected, the gate electrode of the first MOSFET is connected to the second bit line or the second source line, and the gate electrode of the second MOSFET is connected to the second word line. And butterflies.
[0021]
Further, a second nonvolatile semiconductor memory device of the present invention includes a nonvolatile memory cell coupled to a corresponding first bit line, a first source line, and a first word line, and a corresponding second bit line, a second nonvolatile memory cell. A dummy cell coupled to the source line and the second word line; and a differential sense amplifier to which the first and second bit lines are selectively connected, wherein the dummy cell is connected in series with the first and second MOS type. A source diffusion layer or a drain diffusion layer of the first MOSFET is connected to a second bit line; a source diffusion layer or a drain diffusion layer of the second MOSFET is connected to a second source line; Is connected to the second bit line or the second source line, and the gate electrode of the first MOSFET is connected to the second word line.
[0022]
Further, a third nonvolatile semiconductor memory device of the present invention includes a nonvolatile memory cell coupled to a corresponding first bit line, a first source line, and a first word line, and a corresponding second bit line, a second nonvolatile memory cell. A dummy cell coupled to the source line and the second word line; and a differential sense amplifier to which the first and second bit lines are selectively connected, wherein the dummy cell is connected in series with the first and second MOS type. A source diffusion layer or a drain diffusion layer of the first MOSFET is connected to the second bit line; a source diffusion layer or a drain diffusion layer of the second MOSFET is connected to the second source line; Is connected to a diffusion layer connecting the first MOS-type FET and the second MOS-type FET, and the gate electrode of the second MOS-type FET is connected to the second word line. The features.
[0023]
Further, a fourth nonvolatile semiconductor memory device of the present invention includes a nonvolatile memory cell coupled to a corresponding first bit line, a first source line, and a first word line, and a corresponding second bit line, a second nonvolatile memory cell. A dummy cell coupled to the source line and the second word line; and a differential sense amplifier to which the first and second bit lines are selectively connected, wherein the dummy cell is connected in series with the first and second MOS type. A source diffusion layer or a drain diffusion layer of the first MOSFET is connected to a second bit line; a source diffusion layer or a drain diffusion layer of the second MOSFET is connected to a second source line; Is connected to the diffusion layer connecting the first MOS-type FET and the second MOS-type FET, and the gate electrode of the first MOS-type FET is connected to the second word line. The features.
[0024]
Further, in the first to fourth nonvolatile semiconductor memory devices of the present invention, the nonvolatile memory cell includes a gate insulating film, a floating gate electrode, a capacitor insulating film, which are sequentially formed on the semiconductor substrate from the semiconductor substrate side. It is preferable that the stacked gate electrode is formed of a control gate electrode, and a source diffusion layer and a drain diffusion layer formed on the surface of the semiconductor substrate on both sides of the stacked gate electrode.
[0025]
Further, in the first to fourth nonvolatile semiconductor memory devices of the present invention, the nonvolatile memory cell includes a first gate insulating film, a floating gate electrode, a capacitor insulating layer, which are sequentially formed on the semiconductor substrate from the semiconductor substrate side. A first semiconductor element formed from a stacked gate electrode composed of a film and a control gate electrode; a source diffusion layer and a drain diffusion layer formed on the surface of the semiconductor substrate on both sides of the stacked gate electrode; A second semiconductor element formed from a second gate insulating film and a gate electrode formed sequentially from the side and a source diffusion layer and a drain diffusion layer formed on the surface of the semiconductor substrate on both sides of the gate electrode were connected in series. Preferably, it has a configuration.
[0026]
The first method for driving a nonvolatile semiconductor memory device according to the present invention is a method for driving the first to fourth nonvolatile semiconductor memory devices according to the present invention, wherein the first and second source lines are connected to a predetermined source line. After the potentials of the first and second bit lines are precharged to the first potential in the voltage state, a predetermined voltage is applied to the first word line to vary the potential of the first bit line from the first potential. A predetermined voltage is applied to the second word line to change the potential of the second bit line from the first potential, and the potential of the first bit line and the potential of the second bit line after fluctuating from the first potential. Is amplified by a differential sense amplifier to read information stored in a nonvolatile memory cell.
[0027]
Further, a second method for driving a nonvolatile semiconductor memory device according to the present invention is a method for driving the first to fourth nonvolatile semiconductor memory devices according to the present invention, wherein the nonvolatile memory cell includes a first semiconductor element. In the case where the second semiconductor element has a series connection structure, the first voltage is applied to the control gate electrode of the first semiconductor element, and the second voltage is applied to the semiconductor substrate or the well region where the first semiconductor element is formed. A third voltage is applied to the gate electrode of the second semiconductor element when the charge stored in the floating gate electrode of the first semiconductor element is extracted to erase information stored in the first semiconductor element. At the same time, a fourth voltage that is the same as the second voltage or a voltage between the first voltage and the second voltage is applied to the gate electrode of the first or second MOS-type FET connected to the second word line. That And butterflies.
[0028]
Further, a third method for driving a nonvolatile semiconductor memory device according to the present invention is a method for driving the first to fourth nonvolatile semiconductor memory devices according to the present invention, wherein the nonvolatile memory cell includes a first semiconductor element. In the case where the second semiconductor element has a series connection structure, a first voltage is applied to a control gate electrode of the first semiconductor element, and a second voltage is applied to a semiconductor substrate or a well region where the first semiconductor element is formed. At the same time, a third voltage is applied to the source line of the first semiconductor element to inject charge into the floating gate electrode of the first semiconductor element and to connect to the second word line when writing information to the first semiconductor element. A fourth voltage, which is the same voltage as the second voltage or a voltage between the first voltage and the second voltage, is applied to the gate electrode of the first or second MOSFET.
[0029]
Further, in the third method for driving a nonvolatile semiconductor memory device according to the present invention, a fourth voltage is applied to a control gate electrode of the first semiconductor element in the non-selected nonvolatile memory cell, and the fourth voltage is applied to the non-selected nonvolatile memory cell. It is preferable to apply a fifth voltage to the source line so that charge is not injected into the floating gate of the non-selected nonvolatile memory cell.
[0030]
Further, the method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming an element isolation region in a predetermined region in a nonvolatile memory cell region and a MOSFET region on a semiconductor substrate; Forming a film, growing a first conductive film on the gate insulating film, and forming the first conductive film in a part of the element isolation region in the nonvolatile memory cell region and the element isolation region in the MOS FET region Etching, removing a capacitive insulating film on the first conductive film, growing a second conductive film on the capacitive insulating film, and removing the second conductive film in a predetermined region in the nonvolatile memory cell region. Forming a gate electrode and a word line of the nonvolatile memory cell by removing the film, the capacitor insulating film and the first conductive film by etching, and laminating the first and second conductive films in the MOS FET region. Etching the second conductive film in the predetermined region to expose the first conductive film, forming source and drain diffusion layers of the nonvolatile memory cell, and forming the source and drain diffusion layers of the MOS FET. Forming, forming an interlayer insulating film on the semiconductor substrate, forming in the interlayer insulating film a first contact hole connected to a drain diffusion layer of a nonvolatile memory cell, and a source or drain diffusion layer of a MOS FET Forming a second contact hole connected to the first conductive film and a third contact hole connected to the first conductive film exposed in the MOS type FET region; and electrically connecting the first, second and third contact holes. Forming a wiring to be connected.
[0031]
According to the nonvolatile semiconductor memory device, the driving method, and the manufacturing method thereof of the present invention as described above, two MOSFETs are connected to the bit lines, respectively. After connecting to the sense amplifier and precharging the two bit lines, one of the two bit lines turns on one of the two MOSFETs while saturating at the other threshold voltage of the two MOSFETs. Is generated, the other of the two bit lines turns off one of the two MOSFETs, and the potential of the bit line fluctuates from the precharge level depending on the magnitude of the current of the desired memory cell.
[0032]
Therefore, the sense amplifier is activated at the timing when the bit line potential has sufficiently changed, and the sense amplifier differentially amplifies and detects the potential difference between the bit line potential and the reference potential. Since the reference potential is lower than the precharge level and hardly drops below the threshold voltage of one of the two MOSFETs, it is easy to set the timing for activating the sense amplifier. Also, unlike the nonvolatile semiconductor memory device, the two MOSFETs have almost no fluctuation in the threshold value with time, and the variation is smaller than that of the memory cell.
[0033]
The two MOSFETs forming the dummy cell have the same structure as that of the memory cell, and have a structure in which electrical connection can be made to the first polycrystalline silicon corresponding to the floating gate. According to this structure, since the dummy cell can be formed in the same region as the memory cell array, the wiring capacity of the bit line hardly increases. Further, it is possible to make the gate length and width of one of the two MOSFETs constituting the dummy cell the same as those of the normal memory cell, and it is possible to suppress a shift in the generation timing of the reference potential for the normal memory cell. In particular, by processing the first polycrystalline silicon, the two MOSFETs forming the dummy cell can have the same shape as the memory cell.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Throughout the drawings, parts having the same configuration and function are denoted by the same reference numerals and symbols.
[0035]
(1st Embodiment)
FIG. 1 is a circuit diagram showing a configuration example of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
[0036]
In FIG. 1, TA0, TA1, TA, and TA3 are first MOSFETs constituting a dummy cell which enable electrical connection to a first polycrystalline silicon corresponding to a floating gate, and TB0, TB1, TB2, and TB3 are floating gates. Is a second MOSFET constituting a dummy cell, which is capable of electrically connecting to the first polycrystalline silicon corresponding to. The first MOSFET (TA0 to TA3) and the second MOSFET (TB0 to TB3) are connected in series to each bit line B0 to B3. Other configurations are the same as those of the conventional example shown in FIG.
[0037]
Next, a method of driving the nonvolatile semiconductor memory device thus configured will be described with reference to FIGS. 2A and 2B in addition to FIG.
[0038]
2A and 2B are a circuit diagram showing a partial configuration of a dummy cell and a diagram showing a time change of a bit line potential, respectively, for explaining a read driving method of the nonvolatile semiconductor memory device shown in FIG.
[0039]
At the time of reading, when the memory cell MC0 is selected as in the conventional example, the potentials of BLT0 and BLT3 become high, Q0 and Q3 conduct, and the two bit lines B0 and B3 are connected to the sense amplifier 1. . After precharging the bit lines B0 and B3 to the same potential, for example, Vbit of about 1.0 to 1.5 V, the potentials of the dummy word line DW1 and the word line W0 are set to a high potential (FIG. 2A).
[0040]
At this time, as shown in FIG. 2B, the potential of the bit line B3 gradually decreases from Vbit due to a channel current flowing to the ground potential via the first MOSFET (TA3) and the second MOSFET (TB3) constituting the dummy cell. When the potential of the bit line B3 reaches the threshold voltage Vtfg of the first MOSFET (TA3), the channel current flowing through the first MOSFET (TA3) is significantly reduced. For this reason, the rate of decrease of the potential of the bit line B3 becomes extremely slow, and the potential of the bit line B3 decreases extremely gradually due to the minute leak current.
[0041]
On the other hand, the potential of the bit line B0 is the same as in the conventional example, and as shown in FIG. 2B, when the memory cell MC0 is in the erased state, the current flowing to the ground potential via the memory cell MC0 causes The potential rapidly drops from Vbit to 0 V, and when the memory cell MC0 is in a write state, the potential of the bit line B0 changes only slightly from Vbit.
[0042]
At a time point Ts (FIG. 2B) at which the difference between the potential of the bit line B3 and the potential of the bit line B0 becomes an appropriate value, the potentials of BLT0 and BLT3 are lowered almost simultaneously with raising the potential of φ1 of the sense amplifier 1. Then, Q0 and Q3 are turned off, and φ2 of the sense amplifier 1 is further set to 0V.
[0043]
As a result, the potential difference between the bit line B3 and the bit line B0 is amplified to the power supply voltage by the sense amplifier 1, and the input / output lines I / O, * I / O (here, * I / O inputs / outputs an inverted signal of I / O).
[0044]
Here, the difference from the conventional example is that, after the potential of the bit line B3 reaches the threshold voltage Vtfg of the first MOSFET (TA3), the decrease becomes extremely small, so that the saturation state becomes close to a constant value, The read timing is delayed, and even if the sense amplifier 1 is operated later than the time Ts, erroneous read hardly occurs.
[0045]
Next, the structure of the nonvolatile semiconductor memory device shown in FIG. 1 will be described with reference to FIGS. 3 and 4 are a cross-sectional view and a plan view, respectively, showing a structure of a main part in the nonvolatile semiconductor memory device of FIG.
[0046]
In FIG. 3, 4 is a P well, 5 is an element isolation region, 6 is a gate oxide film, 7 is first polycrystalline silicon, 8 is a capacitive insulating film, 9 is second polycrystalline silicon, 10 is an N-type diffusion layer, Reference numeral 11 denotes a side wall, 13 denotes a bit line, 17 denotes a contact made of tungsten or aluminum, 18 denotes a floating gate, and 19 denotes a control gate.
[0047]
In FIG. 4, reference numeral 14 denotes a diffusion region, 15 denotes an opening region of the first polycrystalline silicon 7, and 16a and 16b denote opening regions of the second polycrystalline silicon 9. In FIG. 3, two MOSFETs (TA0, TB0) connected in series to each bit line 13 have a structure that enables electrical connection to the first polycrystalline silicon 7 forming the floating gate 18.
[0048]
As shown in FIG. 4, it is necessary to form a contact 17 for each bit line 13 on the first polycrystalline silicon 7 which is a gate electrode of the first MOSFET (TA0 to TA3 is collectively referred to as TA). By providing the opening region 15 of the polycrystalline silicon 7 not only in the element isolation region 5 of the memory cell but also in the element isolation region 5 of the first MOSFET, a gate electrode can be formed for each bit line 13.
[0049]
After the opening region 15 of the first polycrystalline silicon 7 is also provided in the element isolation region 5 of the first MOSFET (TA), the capacitor insulating film 8 and the second polycrystalline silicon 9 are formed, and simultaneously when forming the word lines. For the first MOSFET (TA) and the second MOSFET (TB0 to TB3 are collectively referred to as TB), the first polycrystalline silicon 7, the capacitor insulating film 8, and the second polycrystalline silicon 9 are etched. Thereafter, after forming an N-type diffusion layer serving as a source and a drain, opening regions 16a and 16b are formed in the second polycrystalline silicon.
[0050]
Thereafter, as shown in FIG. 4, by forming a contact 17, the first MOSFET (TA) and the second MOSFET (TB) can be electrically connected to the first polycrystalline silicon 7. Functions as gate electrodes of the first MOSFET (TA) and the second MOSFET (TB).
[0051]
Since the gate electrode of the second MOSFET (TB) may be common to all the bit lines, the opening region 15 of the first polysilicon 7 may not be provided, but may be commonly used as the opening region 16b of the second polysilicon. It may be formed.
[0052]
As described above, according to the present embodiment, in the memory cell array region, for each bit line, two series-connected MOSFETs that can be electrically connected to the floating gate and constitute a dummy cell are provided. The reference potential can be brought into a saturated state close to a constant value. Thus, high-speed reading can be realized by generating a reference potential for a differential sense amplifier that is resistant to noise on each bit line.
[0053]
In the present embodiment, two MOSFETs are used for each bit line so that they can be electrically connected to the floating gate. However, ordinary MOSFETs may be used.
[0054]
In this embodiment, the MOSFET electrically connectable to the two floating gates in each bit line has the structure shown in FIG. 2A. However, the MOSFET shown in FIG. 5 may be used, or the structure shown in FIG. 7. A source bias reading structure as shown in FIG. In the case of the structure shown in FIG. 6A, as shown in FIG. 6B, the reference potential (potential of the bit line B3) is in a saturation state close to Vbit-Vftg.
[0055]
Further, in the structure shown in FIG. 6A, the gate of the one of the two MOSFETs connected to the bit line is connected to the diffusion layer connecting the two MOSFETs. Of these, the gate of the MOSFET connected to the source line may be connected to the diffusion layer connecting these two MOSFETs.
[0056]
(Second embodiment)
FIG. 9 is a circuit diagram showing a configuration example of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.
[0057]
In FIG. 9, MC 20 is a nonvolatile memory cell, 21 is a control gate driver, 22 is a source driver, and CG0, CG1, CG2, and CG3 are control gate lines.
[0058]
Non-volatile memory cell MC20 is a memory cell having a structure of two transistors per bit, and one of the two transistors is electrically connected to first polycrystalline silicon corresponding to a floating gate. The other MOSFET has a floating gate and a control gate, and operates under the control of the potential of the control gate line CG0 from the control gate driver 21. Information is stored according to the magnitude of the charge stored in the floating gate or whether the charge is positive or negative. This is a second MOSFET (MC202) having a structure for storing.
[0059]
Next, an erasing operation and a writing operation of the nonvolatile semiconductor memory device thus configured will be described with reference to FIGS. FIGS. 10 and 11 are cross-sectional views schematically showing states of an erasing operation and a writing operation in the nonvolatile semiconductor memory device of FIG. 9, respectively.
[0060]
First, in the erase operation shown in FIG. 10, -7 V is applied to the control gate 19 of the second MOSFET (MC 202) from the control gate driver 21 via the control gate line CG0, and +8 V is applied to the P well 4. The electrons stored in the floating gate 182 by the FN (Fowler-Nordheim) current are extracted to the P well 4 through the gate oxide film 62 (indicated by arrows in the drawing).
[0061]
At this time, although the bit line 13 is in the open state, the positive voltage of +8 V is applied to the P-well 4, so that the bit line 13 is also near +8 V, and is applied to the gate oxide film 61 of the first MOSFET (MC201). The applied electric field is almost zero. On the other hand, since +8 V is applied to the P well, the electric field applied to the gate oxide film 62 of the second MOSFET (MC202) increases. However, by applying about +3 V to the gate electrode 181 of the second MOSFET (MC202), the electric field applied to the gate oxide film 62 of the second MOSFET (MC202) can be made about 5 MV / cm. Thereby, the setting can be made so that the gate oxide film 62 of the second MOSFET (MC202) is not broken or significantly deteriorated. During the erasing operation, +3 V is applied to the floating gate of the second MOSFET (TB0) constituting the dummy cell.
[0062]
Next, in the write operation shown in FIG. 11, while applying -7 V to the P well 4, +9 V is applied to the selected control gate of the second MOSFET constituting the memory cell from the control gate driver 21 via the control gate line. On the other hand, by applying -3 V to the non-selected control gate, applying -7 V to the selected source line by the source driver 22 and applying 0 V to the non-selected source line, the P well 4 Then, electrons are injected into the floating gate 182 through the gate oxide film 62.
[0063]
At this time, although the bit line 13 is in the open state, the bit line 13 is near -7 V, so that the electric field applied to the gate oxide film 61 of the first MOSFET constituting the memory cell is low. On the other hand, 0 V is applied to the floating gate 181 of the second MOSFET constituting the memory cell so that the gate oxide film 61 is set so as not to be broken or significantly deteriorated. During the write operation, 0 V is applied to the floating gate of the second MOSFET (TB0) forming the dummy cell.
[0064]
As described above, according to the present embodiment, unlike the first embodiment, even when the memory cell has a structure having two MOSFETs per bit, two MOSFETs connected to each bit line are used. Can be used without any problem in an erasing operation or a writing operation of a nonvolatile semiconductor memory device.
[0065]
(Third embodiment)
FIGS. 15A, 15B, 15C, 15D, and 15E are cross-sectional views showing a semiconductor structure in respective manufacturing steps for describing a method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the present invention. 16A, FIG. 16B, FIG. 16C, FIG. 16D, and FIG. 16E correspond to the positions where the first MOSFET forming the dummy cell is formed in FIG. 15A, FIG. 15B, FIG. 15C, FIG. It is sectional drawing along the AA line. 17A, FIG. 17B, FIG. 17C, FIG. 17D, and FIG. 17E correspond to the positions where the second MOSFET forming the dummy cell is formed in FIG. 15A, FIG. 15B, FIG. 15C, FIG. It is sectional drawing which followed the BB line.
[0066]
In the present embodiment, a method for manufacturing the nonvolatile semiconductor memory device described with reference to FIGS. 3 and 4 as the first embodiment will be described.
[0067]
First, a P well 4 and an element isolation region 5 are formed on a semiconductor substrate, a gate oxide film 6 is formed thereon, and then a first polysilicon 7 is grown. Thereafter, as described with reference to FIG. 4, the opening region 15 of the first polycrystalline silicon 7 is provided not only in the memory cell MC0 but also in the element isolation region 5 of the first MOSFET (TA0) constituting the dummy cell. For this purpose, the resist 31 shown in FIGS. 15A, 16B, and 17A is formed, and the first polysilicon 7 in the opening region 15 is etched (see FIG. 16A). After removing the resist 31, the capacitance insulating film 8 and the second polysilicon 9 are grown as shown in FIGS. 15B, 16B and 17B.
[0068]
Next, as shown in FIGS. 15C, 16C and 17C, a resist 32 is formed to form a word line, and as shown in FIG. 15C, the second polycrystalline silicon 9, the capacitor insulating film 8 and the first The polycrystalline silicon 7 is etched to form an N-type diffusion layer serving as a source and a drain. At this time, also in the first MOSFET (TA0) and the second MOSFET (TB0) constituting the dummy cell, the first polycrystalline silicon 7, the capacitor insulating film 8 and the second polycrystalline silicon 9 are etched, and the N-type serving as the source and the drain is formed. A diffusion layer is formed.
[0069]
After removing the resist 32, a resist 33 is formed and the second polycrystalline silicon 9 is etched as shown in FIGS. 15D and 17D. The resist 33 has opening regions 16a (FIG. 15D) and 16b (FIG. 17d) as shown in FIG. Next, after forming the sidewalls 11 shown in FIGS. 15E and 17E and depositing an interlayer film, the contacts 17 shown in FIGS. 15E, 16E and 17E are formed, and wirings are formed with tungsten and aluminum.
[0070]
In the steps shown in FIGS. 15A to 15C, 16A to 16C, and 17A to 17C, the first MOSFET (TA0) constituting the memory cell and the dummy cell has the same structure, but the first MOSFET (TA0) As shown in FIGS. 15D and 16D, only the step of etching second polycrystalline silicon 9 is different. On the other hand, the second MOSFET (TB0) constituting the memory cell and the dummy cell includes a step of etching the first polycrystalline silicon 7 as shown in FIGS. 15A and 17A, and a second step as shown in FIGS. 15D and 17D. The step of etching the polycrystalline silicon 9 is different.
[0071]
As described above, the first MOSFET (TA0) and the second MOSFET (TB0) constituting the dummy cell can be formed by the same process as the nonvolatile memory cell.
[0072]
Although not shown, the etching process of the second polycrystalline silicon 9 shown in FIGS. 15D and 16D is a process of etching a gate electrode of a MOS semiconductor element for a peripheral circuit operating a nonvolatile semiconductor device. May also be used.
[0073]
【The invention's effect】
As described above, according to the present invention, a reference potential required for a differential sense amplifier can be generated with high accuracy and stability in order to read data from a nonvolatile semiconductor memory device at high speed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration example of a nonvolatile semiconductor memory device according to a first embodiment of the present invention;
FIG. 2A is a circuit diagram showing a partial configuration of a dummy cell during a read operation of the nonvolatile semiconductor memory device shown in FIG. 1;
FIG. 2B is a diagram showing a time change of a bit line potential in the configuration of FIG. 2A;
FIG. 3 is a sectional view showing a structure of a main part in the nonvolatile semiconductor memory device of FIG. 1;
FIG. 4 is a plan view showing a structure of a main part in the nonvolatile semiconductor memory device of FIG. 1;
FIG. 5 is a circuit diagram showing a second example of a partial configuration of a dummy cell during a read operation of the nonvolatile semiconductor memory device according to the first embodiment;
FIG. 6A is a circuit diagram showing a third partial configuration example of a dummy cell during a read operation of the nonvolatile semiconductor memory device according to the first embodiment;
FIG. 6B is a diagram showing a time change of a bit line potential in the configuration of FIG. 6A;
FIG. 7 is a circuit diagram illustrating a fourth partial configuration example of a dummy cell during a read operation of the nonvolatile semiconductor memory device according to the first embodiment;
FIG. 8 is a circuit diagram showing a fifth partial configuration example of a dummy cell during a read operation of the nonvolatile semiconductor memory device according to the first embodiment;
FIG. 9 is a circuit diagram showing a configuration example of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.
10 is a cross-sectional view schematically showing a state during an erasing operation in the nonvolatile semiconductor memory device of FIG. 9;
11 is a cross-sectional view schematically showing a state during a write operation in the nonvolatile semiconductor memory device in FIG. 9;
FIG. 12 is a circuit diagram showing a configuration example of a conventional nonvolatile semiconductor memory device.
FIG. 13 is a diagram showing a time change of a bit line potential during a read operation of the nonvolatile semiconductor memory device of FIG. 12;
14A is a diagram showing a time change of a bit line potential at the time of a read operation when the current drive capability of the dummy cell DM3 in the nonvolatile semiconductor memory device of FIG. 12 is set high;
14B is a diagram showing a time change of a bit line potential at the time of a read operation when the current driving capability of the dummy cell DM3 in the nonvolatile semiconductor memory device of FIG. 12 is set low;
FIG. 15A is a sectional view showing a semiconductor structure in one manufacturing step of the nonvolatile semiconductor memory device according to the third embodiment of the present invention;
FIG. 15B is a sectional view showing a semiconductor structure in one manufacturing step of the nonvolatile semiconductor memory device according to the third embodiment of the present invention;
FIG. 15C is a sectional view showing a semiconductor structure in one manufacturing step of the nonvolatile semiconductor memory device according to the third embodiment of the present invention;
FIG. 15D is a sectional view showing the semiconductor structure in one manufacturing step of the nonvolatile semiconductor memory device according to the third embodiment of the present invention;
FIG. 15E is a sectional view showing the semiconductor structure in one manufacturing step of the nonvolatile semiconductor memory device according to the third embodiment of the present invention;
FIG. 16A is a cross-sectional view of the nonvolatile semiconductor memory device of FIG. 15A, taken along line AA.
16B is a cross-sectional view of the nonvolatile semiconductor memory device of FIG. 15B, taken along line AA.
16C is a cross-sectional view of the nonvolatile semiconductor memory device of FIG. 15C, taken along line AA.
16D is a sectional view of the nonvolatile semiconductor memory device of FIG. 15D taken along line AA.
16E is a cross-sectional view of the nonvolatile semiconductor memory device of FIG. 15E, taken along line AA.
FIG. 17A is a cross-sectional view of the nonvolatile semiconductor memory device of FIG. 15A, taken along line BB.
FIG. 17B is a cross-sectional view of the nonvolatile semiconductor memory device of FIG. 15B, taken along line BB.
17C is a sectional view of the nonvolatile semiconductor memory device of FIG. 15C, taken along line BB.
17D is a sectional view of the nonvolatile semiconductor memory device of FIG. 15D taken along line BB.
FIG. 17E is a cross-sectional view of the nonvolatile semiconductor memory device of FIG. 15E, taken along line BB.
[Explanation of symbols]
1 sense amplifier
2 Row decoder
3 column decoder
4 P well
5 Device isolation area
6 Gate oxide film
7 First polycrystalline silicon
8 Capacitive insulation film
9 Second polycrystalline silicon
10 N-type diffusion layer
11 Sidewall
13 bit line
14 Diffusion area
15 Opening region of first polycrystalline silicon 7
16a, 16b Opening regions of second polycrystalline silicon 9
17 contacts
18 Floating gate
19 Control Gate
21 Control gate driver
22 Source Driver
24, 25, 26, 27 Precharge MOS transistors
28, 29 Column gate MOS transistor
31, 32, 33 resist
B0, B1, B2, B3 bit lines
W0, W1, W2, W3 Word line
DM0, DM1, DM2, DM3 Dummy cell
DW0, DW1 Dummy word line
MC0, MC20 Memory cell to be read
MC201 First MOSFET constituting memory cell 20
MC202 Second MOSFET configuring memory cell 20
Q0, Q1, Q2, Q3 block transistors
TA0, TA1, TA2, TA3 First MOSFETs constituting dummy cells
TB0, TB1, TB2, TB3 Second MOSFET constituting dummy cell

Claims (12)

A nonvolatile memory cell coupled to a corresponding first bit line, a first source line, and a first word line; a dummy cell coupled to a corresponding second bit line, a second source line, and a second word line; A differential sense amplifier to which the first and second bit lines are selectively connected, respectively.
The dummy cell includes first and second MOS FETs connected in series,
A source diffusion layer or a drain diffusion layer of the first MOSFET is connected to the second bit line; a source diffusion layer or a drain diffusion layer of the second MOSFET is connected to the second source line;
A nonvolatile semiconductor memory, wherein a gate electrode of the first MOSFET is connected to the second bit line or the second source line, and a gate electrode of the second MOSFET is connected to the second word line. apparatus. A nonvolatile memory cell coupled to a corresponding first bit line, a first source line, and a first word line; a dummy cell coupled to a corresponding second bit line, a second source line, and a second word line; A differential sense amplifier to which the first and second bit lines are selectively connected, respectively.
The dummy cell includes first and second MOS FETs connected in series,
A source diffusion layer or a drain diffusion layer of the first MOSFET is connected to the second bit line; a source diffusion layer or a drain diffusion layer of the second MOSFET is connected to the second source line;
A nonvolatile semiconductor memory, wherein a gate electrode of the second MOSFET is connected to the second bit line or the second source line, and a gate electrode of the first MOSFET is connected to the second word line. apparatus. A nonvolatile memory cell coupled to a corresponding first bit line, a first source line, and a first word line; a dummy cell coupled to a corresponding second bit line, a second source line, and a second word line; A differential sense amplifier to which the first and second bit lines are selectively connected, respectively.
The dummy cell includes first and second MOS FETs connected in series,
A source diffusion layer or a drain diffusion layer of the first MOSFET is connected to the second bit line; a source diffusion layer or a drain diffusion layer of the second MOSFET is connected to the second source line;
A gate electrode of the first MOSFET is connected to a diffusion layer connecting the first MOSFET and the second MOSFET, and a gate electrode of the second MOSFET is connected to the second word line. Nonvolatile semiconductor memory device. A nonvolatile memory cell coupled to a corresponding first bit line, a first source line, and a first word line; a dummy cell coupled to a corresponding second bit line, a second source line, and a second word line; A differential sense amplifier to which the first and second bit lines are selectively connected, respectively.
The dummy cell includes first and second MOS FETs connected in series,
A source diffusion layer or a drain diffusion layer of the first MOSFET is connected to the second bit line; a source diffusion layer or a drain diffusion layer of the second MOSFET is connected to the second source line;
A gate electrode of the second MOSFET is connected to a diffusion layer connecting the first MOSFET and the second MOSFET, and a gate electrode of the first MOSFET is connected to the second word line. Nonvolatile semiconductor memory device. The nonvolatile memory cell includes:
A gate insulating film, a floating gate electrode, a stacked gate electrode including a capacitor insulating film and a control gate electrode, which are sequentially formed on the semiconductor substrate from the semiconductor substrate side;
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is formed from a source diffusion layer and a drain diffusion layer formed on the surface of the semiconductor substrate on both sides of the stacked gate electrode. The nonvolatile memory cell includes:
A first gate insulating film, a floating gate electrode, a stacked gate electrode including a capacitor insulating film and a control gate electrode, which are sequentially formed on the semiconductor substrate from the semiconductor substrate side, and a surface of the semiconductor substrate on both sides of the stacked gate electrode. A first semiconductor element formed from the formed source diffusion layer and the drain diffusion layer;
A second gate insulating film and a gate electrode formed in this order on the semiconductor substrate from the semiconductor substrate side, and a source diffusion layer and a drain diffusion layer formed on the semiconductor substrate surface on both sides of the gate electrode. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device has a configuration in which two semiconductor elements are connected in series. 7. The nonvolatile semiconductor memory device according to claim 5, wherein the gate electrodes of the first and second MOSFETs are formed of the same film as the floating gate electrode. A method for driving the nonvolatile semiconductor memory device according to claim 1, wherein:
After pre-charging the potentials of the first and second bit lines to a first potential while keeping the first and second source lines at a predetermined voltage, applying a predetermined voltage to the first word line, Changing the potential of the first bit line from the first potential and applying a predetermined voltage to the second word line to change the potential of the second bit line from the first potential;
The potential difference between the potential of the first bit line and the potential of the second bit line after fluctuating from the first potential is amplified by the differential sense amplifier to store information stored in the nonvolatile memory cell. A method for driving a non-volatile semiconductor storage device, comprising: A method for driving a nonvolatile semiconductor memory device according to claim 6, wherein
A first voltage is applied to a control gate electrode of the first semiconductor device, and a second voltage is applied to the semiconductor substrate or the well region on which the first semiconductor device is formed, so that a floating gate of the first semiconductor device is applied. When erasing the information stored in the first semiconductor element by extracting the charge stored in the electrode, a third voltage is applied to the gate electrode of the second semiconductor element, and the third electrode is connected to the second word line. Applying a fourth voltage that is the same voltage as the second voltage or a voltage between the first voltage and the second voltage to the gate electrode of the first or second MOS FET. For driving a nonvolatile semiconductor memory device. A method for driving a nonvolatile semiconductor memory device according to claim 6, wherein
A first voltage is applied to a control gate electrode of the first semiconductor element, a second voltage is applied to the semiconductor substrate or the well region on which the first semiconductor element is formed, and a second voltage is applied to a source line of the first semiconductor element. When applying a third voltage to inject charges into the floating gate electrode of the first semiconductor element and write information to the first semiconductor element, the first or second MOS transistor connected to the second word line Driving the nonvolatile semiconductor memory device, wherein a fourth voltage which is the same voltage as the second voltage or a voltage between the first voltage and the second voltage is applied to a gate electrode of the type FET. Method. Applying the fourth voltage to the control gate electrode of the first semiconductor element in the non-selected nonvolatile memory cell, and applying the fifth voltage to the source line in the non-selected nonvolatile memory cell, 11. The method according to claim 10, wherein the charge is prevented from being injected into the floating gate of the volatile memory cell. Forming an element isolation region in a predetermined region in a nonvolatile memory cell region and a MOS type FET region on a semiconductor substrate;
Forming a gate insulating film on the semiconductor substrate;
Growing a first conductive film on the gate insulating film;
Etching the first conductive film in a part of the element isolation region in the nonvolatile memory cell region and in the element isolation region in the MOS type FET region;
Forming a capacitive insulating film on the first conductive film;
Growing a second conductive film on the capacitive insulating film;
Forming a gate electrode and a word line of the nonvolatile memory cell by etching and removing the second conductive film, the capacitor insulating film, and the first conductive film in a predetermined region in the nonvolatile memory cell region;
Etching the second conductive film in a predetermined region in which the first and second conductive films are stacked in the MOS type FET region to expose the first conductive film;
Forming source and drain diffusion layers of the nonvolatile memory cell;
Forming source and drain diffusion layers of the MOS FET;
Forming an interlayer insulating film on the semiconductor substrate;
A first contact hole connected to a drain diffusion layer of the non-volatile memory cell, a second contact hole connected to a source or drain diffusion layer of the MOS FET, Forming a third contact hole connected to the first conductive film exposed in
Forming a wiring for electrically connecting the first, second and third contact holes.

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