JP2004047050A - Nonvolatile semiconductor storage device and method for determining data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of correctly detecting data regardless of the existence of a leakage current in a virtual ground memory array. <P>SOLUTION: This nonvolatile semiconductor storage device comprises: the virtual ground memory array including a plurality of word lines and a plurality of bit lines; a row decoder for selectively activating one word line out of the plurality of word lines; a column decoder for applying sense voltage to one bit line out of the plurality of bit lines and setting all of the other bit lines in a ground potential; and a sense amplifier for judging the data state of two memory cells connected to one word line and sharing one bit line as one of a first state in which both data are 0, a second state in which both data are 1, and a third state in which one of the data is 1 and the other is 0 by comparing the current flowing the one bit line with a first reference current and a second reference current. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device using a virtual ground memory array.
[Prior art]
In the virtual ground memory array, the bit line is formed of a diffusion layer, and the side of the diffusion layer corresponding to the two bit lines set to the ground potential is the source and the side set to the power supply potential is the drain. In such a virtual ground memory array, a diffusion layer of each memory cell serving as a bit line is formed in common with a diffusion layer serving as a bit line of a memory cell adjacent in the word line direction. Therefore, a drain contact for each memory cell in a general NOR type memory cell array is unnecessary, and the memory cell size can be reduced.
[0002]
FIG. 1 is a diagram showing a part of a virtual ground memory array.
[0003]
The virtual ground memory array of FIG. 1 includes memory cells M00 to M23, bit lines BL0 to BL4, and word lines WL0 to WL2. In order to read data from the memory cell M02, the word line WL0 is set to a predetermined potential to select all the memory cells connected to the word line WL, and the bit lines BL0 to BL2 are set to a drain side potential of, for example, 1 V. And the bit lines BL3 and BL4 are set to the ground potential. Thus, the bit line BL2 becomes a drain and the bit line BL3 becomes a source for the memory cell M02. At this time, as shown in FIG. 1, the current Im02 flowing in the memory cell M02 is equal to the current Ibl2 flowing in the bit line BL2, and the data value of the memory cell M02 is read by detecting the current Ibl2 by a sense amplifier (not shown). .
[0004]
In this read operation, applying 1 V to the bit line BL1 to make the bit line BL1 the same potential as the bit line BL2 prevents a leak current from flowing from the bit line BL2 to the bit line BL1 via the memory cell M01. That's why. If such a leak current flows, the current Im02 flowing in the memory cell M02 will be different from the current Ibl2 flowing in the bit line BL2, and even if the current Ibl2 is detected, a correct data value of the memory cell cannot be read. There may be cases.
[0005]
In the configuration for preventing the leakage current as described above, the voltage applied to the adjacent bit line BL1 is called a precharge voltage, and the voltage applied to the read target bit line BL2 is called a sense voltage.
[Patent Document 1]
JP-A-10-69794
[Problems to be solved by the invention]
Since the virtual ground memory array has a bit line formed of an impurity diffusion layer, the bit line resistance value is larger than that of a general NOR type nonvolatile memory in which the bit line is connected with a low-resistance metal. Voltage drop along the line is apt to occur. Therefore, the sense voltage and the precharge voltage may not be at the same potential.
[0006]
In addition, the sense voltage and the precharge voltage are usually supplied from different circuits, respectively, and the voltage application timing tends to shift between them. In such a case, the sense voltage and the precharge voltage are not at the same potential.
[0007]
When detecting the data of the memory cell M02 in FIG. 1, if the data state of the adjacent memory cell M01 is "0" and the threshold voltage is high, even if there is a slight potential difference between the precharge voltage and the sense voltage, the memory cell M01 Almost no leak current flows through. However, when the data state of the memory cell M01 is "1" and the threshold voltage is low, the influence of the potential difference between the precharge voltage and the sense voltage cannot be ignored.
[0008]
In addition, when a program verify operation or an erase verify operation is performed, if the threshold voltage of a memory cell is detected differently from the actual one due to the influence of a leak current, the reliability of the verify operation itself is significantly reduced. As a result, the variation in the threshold voltage of the data “0” and “1” between the memory cells increases, and the margin for the threshold variation due to thermal stress or the like decreases, so that the reliability of the nonvolatile memory deteriorates.
[0009]
In view of the above, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of accurately detecting data regardless of the presence of a leak current in a virtual ground memory array.
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to the present invention includes a virtual ground memory array including a plurality of word lines and a plurality of bit lines, a row decoder for selectively activating one word line of the plurality of word lines, A column decoder for applying a sense voltage to one of the bit lines and setting all other bit lines to a ground potential; and a current flowing through the one bit line as a first reference current and a second reference current. By comparing with the current, the data state of two memory cells connected to the one word line and sharing the one bit line is a first state where both are 0, and both are 1 It is characterized in that it includes a sense amplifier that determines one of the second state and the third state in which one is 1 and the other is 0.
[0010]
In the above invention, both of the two memory cells sharing the bit line to be sensed are subjected to data determination by including, as the data determination target, a memory cell that is not a data determination target that has conventionally been a current leak path, By comparing two different reference currents and the current of the bit line, the data states of the two memory cells are determined together. In this configuration, all bit lines other than the bit line to be sensed at the time of data determination have the ground potential, so that the bit line precharge operation that has been conventionally required is unnecessary. The ground potential is extremely stable as compared with the precharge voltage, and is not affected by a voltage drop due to bit line resistance. Therefore, in the present invention, it is possible to completely prevent the read failure caused by the unstable potential difference between the bit line to be sensed and the bit line to be precharged.
[0011]
According to another aspect of the present invention, a nonvolatile semiconductor memory device includes: a virtual ground memory array including a plurality of word lines and a plurality of bit lines; and a memory connected to any one of the plurality of word lines. Data is set by making at least one of the threshold voltage of data “0” and the threshold voltage of data “1” different between two memory cells sharing an arbitrary one of a plurality of bit lines. And a control circuit for performing the control.
[0012]
The nonvolatile semiconductor memory device includes a row decoder for selectively activating one word line of the plurality of word lines, a sense voltage applied to one of the plurality of bit lines, and And a column decoder for setting the bit line to the ground potential, and comparing the current flowing through the one bit line with a first reference current, a second reference current, and a third reference current to form the one word line. And a sense amplifier for determining a data state of each of two memory cells sharing the one bit line.
[0013]
In the above nonvolatile semiconductor memory device, two types of memory cells having different threshold voltages for data "0" or different threshold voltages for data "1" are alternately arranged in the word line direction, and the adjacent even-numbered memory cells are read at the time of data reading. And the odd-numbered memory cells are paired, and the total current flowing through the pair of memory cells is compared with three different reference currents. This makes it possible to perform data determination on each of the paired memory cells.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0014]
FIG. 2 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the present invention.
[0015]
2 includes a control circuit 11, a chip enable & output enable circuit 12, an input / output buffer 13, a cell array 14, a row decoder 15, a column decoder 16, an address latch 17, a data latch 18, and a read circuit. 19, a writing circuit 20, an erasing circuit 21, and a reference current generating circuit 22.
[0016]
The control circuit 11 receives control signals such as a write enable / WE and a chip enable / CE, an address signal, and a data signal from the outside, and operates as a state machine based on these signals to operate each part of the nonvolatile semiconductor memory device 10. Control the operation of. The input / output buffer 13 receives data from the outside and supplies the data to the control circuit 11 and the data latch 18. The chip enable & output enable circuit 12 receives a chip enable signal / CE and an output enable signal / OE as control signals from outside the device, and controls the operation / non-operation of the input / output buffer 13 and the cell array 14.
[0017]
The read circuit 19 operates under the control of the control circuit 11, and controls the cell array 14, the row decoder 15, the column decoder 16 and the like via the address latch 17 to read data from the read address of the cell array 14. The write circuit 20 operates under the control of the control circuit 11, and controls the cell array 14, the row decoder 15, the column decoder 16, and the like via the address latch 17 to write data to a write address of the cell array 14. The erasing circuit 21 operates under the control of the control circuit 11, and erases a specified area of the cell array 14 at a predetermined unit at a time via the address latch 17, the cell array 14, the row decoder 15, the column decoder 16 and the like. Control.
[0018]
The cell array 16 is a virtual ground memory array, including an array of memory cell transistors, word lines, bit lines, and the like, and stores data in each memory cell transistor. At the time of data reading, data from a memory cell specified by the activation word line is read to a bit line. At the time of programming or erasing, by setting the word line and the bit line to appropriate potentials according to the respective operations, the operation of injecting or extracting the charge to the memory cell is executed.
[0019]
The data latch 18 operates under the control of the control circuit 11, and compares the current of the data supplied from the cell array 14 with the reference current according to the designation by the row decoder 15 and the column decoder 16, so that the data is 0. Or 1 is determined. This determination is performed by the sense amplifier circuit in the data latch 18, and the determination result is supplied to the input / output buffer 13 as read data. The verify operation accompanying the program operation and the erase operation is performed by comparing the current of the data supplied from the cell array 14 according to the designation by the row decoder 15 and the column decoder 16 with the reference currents for the program verify and the erase verify. Done. The reference current generation circuit 22 is a circuit that generates a reference current used for these data determination operations. The data latch 18 further latches data input from the outside via the input / output buffer 13 during a data write operation, and is used for a data write operation to the cell array 14.
[0020]
As one feature of the present invention, the reference current generating circuit 22 generates a first reference current and a second reference current (second reference current> first reference current) as described below, Reference numeral 18 compares the two reference currents with the data current, thereby realizing accurate data determination regardless of the presence of a leak current.
[0021]
FIG. 3 is a diagram for explaining the data determination operation according to the first embodiment.
[0022]
The cell array 14 is a virtual ground memory array and includes memory cells M00 to M23, bit lines BL0 to BL4, and word lines WL0 to WL2. The bit lines BL0 to BL4 are connected to a column decoder 16, and the word lines WL0 to WL2 are connected to a row decoder 15. The column decoder 16 controls the potential of the bit lines BL0 to BL4, and the row decoder 15 controls the potential of the word lines WL0 to WL2. The sense amplifier 18a is a circuit provided in the data latch 18 shown in FIG. 2, and applies a data current supplied from the cell array 14 in accordance with the designation of the row decoder 15 and the column decoder 16 to a reference current supplied from the reference current generation circuit 22. The data determination is performed by comparing with the current.
[0023]
In FIG. 3, in order to read data from the memory cell M02, the word line WL0 is set to a predetermined potential (for example, 2 V), all the memory cells connected to the word line WL are selected, and the bit line BL2 is set to, for example, The drain side potential is set to 1 V, and the other bit lines BL0, BL1, BL3, BL4 are set to the ground potential. In this case, as shown in FIG. 3, a current Im02 and a current Im01 flow through the memory cell M02 and the adjacent memory cell M01, respectively. The current Ibl2 flowing through the bit line BL2 is the sum of the current Im02 and the current Im01.
[0024]
The sense amplifier 18a compares the current Ibl2 with the first reference current IREF1. If the current Ibl2 is smaller than the first reference current IREF1, the data held in the memory cell pair M01 / M02 is determined to be in the "0/0" state. That is, both the memory cells M01 and M02 are determined to be in the “0” state (program state).
[0025]
When the current Ibl2 is larger than the first reference current IREF1, the sense amplifier 18a compares the current Ibl2 with the second reference current IREF2. When the current Ibl2 is larger than the second reference current IREF2, the data of the memory cell pair M01 / M02 is determined to be in the "1/1" state. That is, both the memory cells M01 and M02 are determined to be in the “1” state (erase state). When the current Ibl2 is smaller than the second reference current IREF2, the data of the memory cell pair M01 / M02 is determined to be "1/0" or "0/1". That is, it is determined that one of the memory cells M01 and M02 is in the “1” state and the other is in the “0” state.
[0026]
As described above, by comparing the current of the bit line to be sensed with the two types of reference currents, the data of a pair of memory cells adjacent to each other in the word line direction while sharing this bit line is simultaneously detected. It is determined whether the data state of the pair is the “0/0” state, the “1/1” state, the “1/0 or 0/1” state.
[0027]
FIG. 4 is a flowchart illustrating the data determination operation according to the first embodiment.
[0028]
In step ST1, it is determined whether the current Ibl2 is smaller than the first reference current IREF1. If smaller, it is determined that the memory cell pair M01 / M02 is in the “0/0” state. If not, the process proceeds to step ST2.
[0029]
In step ST2, it is determined whether the current Ibl2 is larger than the second reference current IREF2. If it is larger, it is determined that the memory cell pair M01 / M02 is in the “1/1” state. If not, the process proceeds to step ST3.
[0030]
In step ST3, the memory cell pair M01 / M02 is determined to be in the “1/0” state or the “0/1” state.
[0031]
In the data determination method according to the present embodiment, when the data state is the “0/0” state or the “1/1” state, the state of each memory cell can be determined, but the data state is “1/0 or 0”. When in the "/ 1" state, it cannot be determined which memory cell is "1" and which memory cell is "0". However, by using this data determination method, it can be efficiently determined whether all the bits of the cell array are in the written state or all the bits are in the erased state.
[0032]
At this time, by applying a sense voltage every other line, for example, BL0, BL2, BL4,. Can be determined. When data is determined in this manner, all bit lines other than the bit line to be sensed are set to the ground potential, so that the bit line precharge operation, which was conventionally required, becomes unnecessary. The ground potential is extremely stable as compared with the precharge voltage, and is not affected by a voltage drop due to bit line resistance. Therefore, in the present invention, it is possible to completely prevent the read failure which has conventionally occurred due to the potential difference between the bit line to be sensed and the bit line to be precharged.
[0033]
Being able to efficiently and reliably determine whether all bits are “0” state or all bit “1” state is particularly effective when executing batch data erasure on a memory cell array in chip or block units. It is.
[0034]
In the flash memory batch erasing operation, if memory cells are over-erased and become depleted, a column leak phenomenon occurs in which current flows even if there is no potential difference between adjacent bit lines, and the data in the memory cells becomes normal. Detection cannot be performed. In order to prevent such excessive erasure, it is usually necessary to set all memory cells to be erased to a write state before executing the erase operation. That is, in order to reduce the threshold variation for each memory cell after erasure and prevent excessive erasure, it is necessary to set all the memory cells to a write state before erasing to reduce the threshold variation. Therefore, in the flash memory, when a command for batch erasing of all bits is input, first, all bits are set to "0" state, and then all bits are set to "1" state.
[0035]
By using the above-described embodiment, for example, it is possible to detect the state of all bits “0” and the state of all bits “1” required at the time of inputting a batch erasure command more reliably and faster than in the past.
[0036]
There is a virtual ground cell array structure in which a nitride film is used as a charge trapping layer so that one memory cell transistor can physically store two bits of information. In such a nonvolatile semiconductor memory device, both ends of a single nitride film existing between bit lines are treated as two independent memory cells, and a total of two are determined according to whether hot electrons are injected into each memory cell. Bit data can be stored. This is made possible by the characteristic that charges do not move in the nitride film serving as the charge trapping layer in this case.
[0037]
In this type of flash memory, a film composed of an oxide film, a nitride film, and an oxide film is provided between a control gate and a substrate, and charges are trapped in the nitride film to change a threshold value. A distinction is made between "0" and "1". In this case, charges do not move because the trap layer such as a nitride film is an insulating film. Therefore, it is possible to store two bits of information per cell by storing charges independently at both ends of the trap layer. The 2-bit information can be read separately by exchanging the drain and source in the read operation.
[0038]
Writing to a memory cell is performed by electron injection using channel hot electrons. For example, about 12 V is applied to the gate electrode, about 8 V to the drain, and 0 V to the source and the substrate, and hot electrons generated in the channel are trapped in the nitride film. At this time, hot electrons are injected into the nitride film on the side near the drain. The erasing operation is performed by hole injection by hot hole injection. That is, by applying, for example, about -6 V to the gate electrode and about 5 V to the drain, holes generated by an interband tunnel current flowing from the drain to the substrate are injected into the nitride film to neutralize the charge and erase the charge. When two bits of electric charge are injected per cell, the erase operation can be performed by applying the same voltage to the source as that of the drain. The read operation is performed by a reverse read in which the drain is reversed at the time of writing. That is, data is read using the diffusion layer on the side opposite to the diffusion layer that was the drain at the time of writing as the drain.
[0039]
The embodiment described below is directed to a type of flash memory capable of storing two bits of information per memory cell by storing charges in a trap layer made of a nitride film or the like.
[0040]
FIG. 5 is a diagram for explaining a data determination operation according to a modification of the first embodiment. 5, the same elements as those of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.
[0041]
The cell array 14A is a virtual ground memory array of a type capable of storing 2-bit information, and includes memory cells M00 to M23, bit lines BL0 to BL4, and word lines WL0 to WL2. In order to show that 2-bit information can be stored in each memory cell, the positions of two bits are represented by two white boxes.
[0042]
To read the data of the right bit (represented by “x” in the box) of the memory cell M02 and the data of the left bit (represented by “x” in the box) of the memory cell M01, the word line WL0 must be connected to the word line WL0. The potential is set to a predetermined potential (for example, 2 V), the bit line BL2 is set to a drain side potential of, for example, 1 V, and the other bit lines BL0, BL1, BL3, and BL4 are set to the ground potential. In this case, as shown in FIG. 5, a current Im02 and a current Im01 flow through the memory cell M02 and the adjacent memory cell M01, respectively. The current Ibl2 flowing through the bit line BL2 is the sum of the current Im02 and the current Im01.
[0043]
The sense amplifier 18a compares the current Ibl2 with the first reference current IREF1. When the current Ibl2 is smaller than the first reference current IREF1, the data held in the M01 left bit / M02 right bit is determined to be in the "0/0" state. When the current Ibl2 is larger than the first reference current IREF1, the sense amplifier 18a compares the current Ibl2 with the second reference current IREF2. When the current Ibl2 is larger than the second reference current IREF2, the data of the M01 left bit / M02 right bit is determined to be in the "1/1" state. When the current Ibl2 is larger than the first reference current IREF1 and smaller than the second reference current IREF2, the data of the M01 left bit / M02 right bit is determined to be "1/0" or "0/1".
[0044]
The above-described determination operation is the same as that of the first embodiment, but differs from the first embodiment in the method of applying a sense voltage when performing data determination for each memory cell. That is, since 2-bit information can be stored in each memory cell, a sense voltage is applied to each bit line in order instead of applying a sense voltage to every other bit line as in the first embodiment. By doing so, data can be determined for the left and right bits of each memory cell.
[0045]
Hereinafter, a data determination method according to the second embodiment of the present invention will be described.
[0046]
The data determination method according to the second embodiment is a method of storing data of "0" state and data of "1" state in a floating gate type nonvolatile memory (FIG. 3) capable of storing 1-bit information in each memory cell. The present invention relates to a method for judging data of each memory cell in a case where are mixed.
[0047]
FIGS. 6A to 6C are diagrams for explaining a data determination method according to the second embodiment of the present invention. FIGS. 6A to 6C show only the memory cell portion connected to the word line WL0 from the cell array 14 of FIG. 3 for convenience of explanation.
[0048]
First, as shown in FIG. 6A, the word line WL0 is set to a predetermined potential (for example, 2 V), the bit line BL0 at the end of the memory cell block is set to a sense potential (for example, 1 V), and another bit line is set. All bit lines are set to the ground potential. At this time, the current Ibl0 flowing through the bit line BL0 is compared with the first reference current IREF1. The memory cell M00 is determined to be in the “0” state when the current Ibl0 is smaller than the first reference current IREF1, and is determined to be in the “1” state when the current Ibl0 is larger than the first reference current IREF1.
[0049]
The data determination result of the memory cell M00 is stored in, for example, the internal data register by the control circuit 11 of FIG. 2 and used for data determination of the next memory cell M01.
[0050]
Next, as shown in FIG. 6B, the word line WL0 is set to a predetermined potential (for example, 2 V), and the bit line BL1 next to the bit line sensed last time is set to the sense potential (for example, 1 V). All other bit lines are set to the ground potential. A current Im00 and a current Im01 flow through the memory cells M00 and M01, respectively. At this time, the current Ibl1 flowing through the bit line BL1 is the sum of the current Im00 and the current Im01.
[0051]
When the data of the memory cell M00 determined last time is in the “0” state, the current Ibl1 is compared with the first reference current IREF1. When current Ibl1 is smaller than first reference current IREF1, memory cell M01 is determined to be in the "0" state. When current Ibl1 is larger than first reference current IREF1, memory cell M01 is determined to be in the "1" state.
[0052]
When the data of the memory cell M00 determined last time is in the “1” state, the current Ibl1 is compared with the second reference current IREF2. When current Ibl1 is smaller than second reference current IREF2, memory cell M01 is determined to be in the "0" state. When current Ibl1 is larger than second reference current IREF2, memory cell M01 is determined to be in the "1" state.
[0053]
The data determination result of the memory cell M01 is stored in, for example, the internal data register by the control circuit 11 of FIG. 2 and used for data determination of the next memory cell M02.
[0054]
Next, as shown in FIG. 6C, the word line WL0 is set to a predetermined potential (for example, 2 V), and the bit line BL2 next to the bit line sensed last time is set to the sense potential (for example, 1 V). All other bit lines are set to the ground potential. A current Im01 and a current Im02 flow through the memory cells M01 and M02, respectively. At this time, the current Ibl2 flowing through the bit line BL2 is the sum of the current Im01 and the current Im02.
[0055]
Thereafter, the data determination of the memory cell M02 can be performed based on the data of the memory cell M01 by the same operation as the data determination of the memory cell M01 based on the data of the memory cell M00.
[0056]
FIG. 7 is a flowchart illustrating a data determination operation of a memory cell according to the second embodiment. This flowchart shows a procedure for determining the data of the current memory cell M0n based on the data state of the memory cell M0 (n-1) for which the data has been previously determined.
[0057]
First, in step ST1, it is determined whether the previous memory cell M0 (n-1) was "0" or "1". If it is “0”, the current Ibln is compared with the first reference current IREF1 in step ST2. When the current Ibln is smaller than the first reference current IREF1, the memory cell M0n is determined to be in the “0” state in step ST3. When the current Ibln is larger than the first reference current IREF1, the memory cell M0n is determined to be in the “1” state in step ST4.
[0058]
If the data of the memory cell M0 (n-1) determined last time is "1", the current Ibln is compared with the second reference current IREF2 in step ST5. When the current Ibln is smaller than the second reference current IREF2, the memory cell M0n is determined to be in the “0” state in step ST6. If the current Ibln is larger than the second reference current IREF2, the memory cell M0n is determined to be in the "1" state in step ST7.
[0059]
In this way, the data state of each memory cell can be determined in order from the end of the memory block. Thus, when the “0” state data and the “1” state data are mixed, it is possible to reliably determine the data of each memory cell.
[0060]
A case where the present invention is applied to data determination in write verify and erase verify will be described below.
[0061]
If the memory cell pair M01 / M02 is "1/1" and the user wants to change it to "0/1", the following procedure is executed.
[0062]
First, for example, 12 V is applied to the word line WL0. In this state, the bit lines BL0 and BL1 are set to the ground potential, and the bit lines BL2, BL3, BL4. . . 8V is applied, and electrons are injected into the floating gate of M01 by hot electron injection to write data.
[0063]
Next, the current Ibl2 (= IM01 + IM02) flowing through the bit line BL2 is detected with the word line WL0 at 1V, the bit line BL2 at 1V, and the other bit lines at the ground potential. In this case, since it is known that the data of the other memory cell M02 forming the pair is already "1", it is sufficient to verify whether or not Ibl2 <IREF2 is satisfied. That is, if Ibl2 <IREF2, it is determined that M01 / M02 = "0/1", and the write and write verify operations are terminated. If Ibl2 <IREF2 is not satisfied, the above-described write and write-verify operations are repeated until the condition of Ibl2 <IREF2 is satisfied.
[0064]
If it is desired to further change the memory cell pair M01 / M02 from "0/1" to "0/0", the following procedure is executed.
[0065]
First, for example, 10 V is applied to the word line WL0. In this state, the bit lines BL0, BL1, and BL2 are set to the ground potential, and the bit lines BL3, BL4,. . . 5V is applied, and electrons are injected into the floating gate of M02 by hot electron injection to write data.
[0066]
Next, the current Ibl2 (= IM01 + IM02) flowing through the bit line BL2 is detected with the word line WL0 at 1V, the bit line BL2 at 1V, and the other bit lines at the ground potential. In this case, since it is known that the data of the other memory cell M02 forming the pair is “0”, it is sufficient to verify whether or not Ibl2 <IREF1 is satisfied. That is, if Ibl2 <IREF1, it is determined that M01 / M02 = "0/0", and the write and write verify operations are terminated. If Ibl2 <IREF1 is not satisfied, the above-described write and write verify operations are repeated until the condition of Ibl2 <IREF1 is satisfied.
[0067]
When the memory cell pair M01 / M02 is "0/0" and the user wants to change it to "1/1", the following procedure is executed.
[0068]
With the word line WL0 set to -5 V, the bit line BL2 set to 5 V, and the other bit lines set to the floating potential (floating) or ground potential, electrons injected into the floating gates of M01 and M02 by the FN tunneling method are used as BL2 impurity diffusion layers. To erase the data.
[0069]
Next, the current Ibl2 (= IM01 + IM02) flowing through the bit line BL2 is detected with the word line WL0 at 1V, the bit line BL2 at 1V, and the other bit lines at the ground potential. In this case, since both memory cells of the pair are erased at the same time, it is sufficient to verify whether Ibl2> IREF2 is satisfied. That is, if Ibl2> IREF2, it is determined that M01 / M02 = "1/1", and the erase and erase verify operations are terminated. If Ibl2> IREF2 is not satisfied, the above-described erase and erase verify operation are repeated until the condition of Ibl2> IREF2 is satisfied.
[0070]
When the memory cell pair M01 / M02 is "0/1" and the user wants to change to "1/1", the following procedure is executed.
[0071]
Since a pre-program operation is necessary to prevent excessive erasing, first, writing and write verify are performed on M02 to change M01 / M02 from the “0/1” state to the “0/0” state. Thereafter, the erase and erase verify operations are executed to change the “0/0” state to the “1/1” state.
In the above-described embodiment, the first and second reference currents used for the read operation, the write verify, and the erase verify have been described as being the same. However, these need not necessarily be the same. A dedicated reference current may be prepared.
[0072]
Hereinafter, a data determination method according to the third embodiment of the present invention will be described.
[0073]
The data judging method according to the third embodiment is a method of storing data of "0" state and data of "1" state in a floating gate type nonvolatile memory (FIG. 3) capable of storing 1-bit information in each memory cell. The present invention relates to a method for judging data of each memory cell in a case where are mixed. In the above-described second embodiment, it was necessary to determine the data state of each memory cell in order from the end of the memory block. In the third embodiment, however, data determination was performed independently for a desired memory cell. It is possible to do.
[0074]
In order to realize this, in the third embodiment, in the memory cell array, two types of memory cells having different "0" levels are arranged alternately in the word line direction. More specifically, in the configuration of FIG. 3, even-numbered memory cells M0 (2n), M1 (2n), M2 (2n),... (N is an integer of 0 or more) are odd-numbered memory cells M0. (2n + 1), M1 (2n + 1), and M2 (2n + 1) are set to have different “0” levels.
[0075]
FIG. 8 is a diagram showing a relationship between memory cell currents for even-numbered memory cells and odd-numbered memory cells. As shown in FIG. 8, even-numbered memory cells and odd-numbered memory cells have the same amount of memory cell current in the data state of “1”. On the other hand, when the data state is "0", the amount of memory cell current flowing in the even-numbered memory cells is set to the first amount of current, and the amount of memory cell current flowing in the odd-numbered memory cells is The second current amount is set to be a substantially intermediate value between the first current amount and the memory cell current amount in the case of the data state of “1”.
[0076]
In the present embodiment, each of the paired memory cells is compared by comparing the total current flowing through the pair of memory cells with three different reference currents by taking the adjacent even-numbered memory cells and odd-numbered memory cells as a pair. Data determination is performed on the cell.
[0077]
FIG. 9 is a diagram showing a relationship between a memory cell current level flowing through a pair of memory cells and three types of reference currents for data determination. Here, the pair of memory cells is, for example, the memory cell M01 and the memory cell M02 illustrated in FIG. In order to read the data of the pair of memory cells, in FIG. 3, the word line WL0 is set to a predetermined potential, all the memory cells connected to the word line WL are selected, and the bit line BL2 is set to 1V, for example. The drain side potential is set, and the other bit lines BL0, BL1, BL3, BL4 are set to the ground potential. As a result, the currents Im02 and Im01 flow through the pair of memory cells, and the current Ibl2, which is the sum of the currents Im02 and Im01, is the total current of the pair of memory cells.
[0078]
As shown in FIG. 9, three different reference currents IREF1, IREF2, and IREF3 are prepared. The total current Ibl2 is “0” when both the even-numbered memory cell and the odd-numbered memory cell are “0”, “1” and “1”, respectively. And both are "1", and change stepwise as shown in FIG. The three reference currents IREF1, IREF2, and IREF3 are set to lie between four different levels of the total current.
[0079]
FIG. 10 is a diagram illustrating a flow of a process of determining data in the third embodiment. In this determination process, the operation of comparing the total current and the reference current to determine data is performed by the sense amplifier 18a in FIG. 3, and the operation of the sense amplifier is controlled by the control circuit 11 in FIG. Note that the configuration of the nonvolatile semiconductor memory device may be similar to that shown in FIG. However, since it is necessary to compare three different reference currents and the data current at the time of data determination, the control circuit 11 is configured to be able to control the determination operation for the reference currents IREF1, IREF2, and IREF3.
[0080]
In step ST1 of FIG. 10, it is determined whether or not the total current Ibl2 is smaller than the reference current IREF1. If the total current Ibl2 is smaller than the reference current IREF1, both the even-numbered memory cells and the odd-numbered memory cells are "0". Otherwise, the process proceeds to step ST2.
[0081]
In step ST2, it is determined whether or not the total current Ibl2 is larger than the reference current IREF3. If the total current Ibl2 is larger than the reference current IREF3, both the even-numbered memory cells and the odd-numbered memory cells are "1". Otherwise, the process proceeds to step ST3.
[0082]
In step ST3, it is determined whether or not the total current Ibl2 is larger than the reference current IREF2. If the total current Ibl2 is larger than the reference current IREF2, the even-numbered memory cells and the odd-numbered memory cells are "1" and "0", respectively. If the total current Ibl2 is equal to or smaller than the reference current IREF2, the even-numbered memory cells and the odd-numbered memory cells are "0" and "1", respectively.
[0083]
Thus, the data determination processing ends.
[0084]
FIG. 11 is a flowchart of a process of erasing even-numbered memory cells and odd-numbered memory cells and setting the data state to “1”. The batch erasing operation is simply performed by applying an erasing voltage pulse of -8 V to all the word lines while applying, for example, 8 V to all the bit lines, thereby causing electrons in the floating gate to be emitted to the bit lines by a tunnel current. Run by doing. However, in the flow of FIG. 11, a pre-program procedure is executed to prevent excessive erasure.
[0085]
In step ST1, erase verify is executed for all even-numbered and odd-numbered cells.
[0086]
In step ST2, it is determined whether or not the threshold voltage Vt_cell of all the memory cells is higher than the verify voltage Ve1. If there is no memory cell having the threshold voltage Vt_cell higher than the verify voltage Ve1, the process proceeds to the correction verify in step ST9.
[0087]
In step ST9, correction verify is executed. Further, in step ST10, it is determined whether or not the threshold voltage Vt_cell is higher than the verify voltage Ve2 (<Ve1) for all the memory cells. If "No", the correction program is executed in step ST11, and the process returns to step ST9 and repeats the subsequent processing. As a result, all the memory cells are set to the data state of "1" so that Ve2 <Vt_cell. By this correction verify and program operation, the threshold voltage Vt_cell is set so as to be distributed between the verify voltages Ve2 and Ve1. That is, the threshold distribution of the data state of “1” can be set in a desired range.
[0088]
If it is determined in step ST2 that there is a memory cell having a threshold voltage Vt_cell higher than Ve1, preprogram verify is executed in step ST3.
[0089]
Next, in step ST4, it is determined whether or not the threshold voltage Vt_cell of all the memory cells is higher than the verify voltage Vp2. If there is a memory cell having a threshold voltage Vt_cell that is not higher than the verify voltage Vp2, pre-program is executed in step ST5. Thereafter, returning to step ST3, the subsequent operations are repeated, and the threshold voltages Vt_cell of all the memory cells are set to be higher than the verify voltage Vp2. Such a step of programming all cells as pre-processing for erasing is called pre-programming, and is performed to prevent excessive erasing in a flash memory in which erasing is performed collectively in chip or block units.
[0090]
After setting all the memory cells to the data state of "0" by the above processing, all the even-numbered and odd-numbered memory cells are erased in step ST6, and erase verification is executed in step ST7. In step ST7, it is determined whether or not the threshold voltage Vt_cell of all the memory cells is lower than the verify voltage Ve1. If there is a memory cell having a threshold voltage Vt_cell that is not lower than the verify voltage Ve1, the process returns to step ST6 and repeats the subsequent processing. As a result, data is set so that Ve1> Vt_cell for all the even-numbered and odd-numbered cells. After that, the correction verification and the correction program consisting of steps ST9 to ST11 described above are repeated, and the data of all the memory cells are set so that Ve2 <Vt_cell.
[0091]
FIG. 12 is a flowchart of a process for programming even-numbered memory cells and setting the data state to “0” in the third embodiment. FIG. 13 is a flowchart of a process for programming the odd-numbered memory cells and setting the data state to “0” in the third embodiment. FIG. 14A is a diagram showing a change in a memory cell threshold voltage when programming an even-numbered memory cell, and FIG. 14B is a diagram showing a change in a memory cell threshold voltage when programming an odd-numbered memory cell. FIG.
[0092]
The processing in FIG. 12 is executed for the even-numbered memory cells. First, in step ST1, the even-numbered cells are programmed. Next, in step ST2, a program verify operation is performed on the even-numbered cells. In step ST3, it is determined whether or not the threshold voltage Vt_cell of the memory cell to be programmed is higher than the verify voltage Vp1. In the case of "No", the process returns to step ST1 and the subsequent processes are repeated. Thereby, data is set so that Vp1 <Vt_cell for the memory cell to be programmed. As a result, as shown in FIG. 14A, the threshold voltage of the memory cell in the data state of “1” between the erase verify voltage Ve1 and the correction verify voltage Ve2 changes the program verify for the even-numbered memory cell. The voltage is raised to the level of the voltage Vp1 or higher, and the memory cell becomes a data state of “0”.
[0093]
The processing of FIG. 13 is executed for the odd-numbered memory cells. First, in step ST1, odd-numbered cells are programmed. Next, in step ST2, a program verify operation is performed on the odd-numbered cells. In step ST3, it is determined whether or not the threshold voltage Vt_cell of the memory cell to be programmed is higher than the verify voltage Vp2. In the case of "No", the process returns to step ST1 and the subsequent processes are repeated. Thereby, data is set so that Vp2 <Vt_cell for the memory cell to be programmed. As a result, as shown in FIG. 14B, the threshold voltage of the memory cell in the data state of “1” between the erase verify voltage Ve1 and the correction verify voltage Ve2 is changed to the program verify for the odd-numbered memory cell. The memory cell is raised to the level of the voltage Vp2 or higher, and has a data state of "0".
[0094]
As shown in FIGS. 14A and 14B, the program verify voltage Vp2 for the odd-numbered memory cells is set lower than the program verify voltage Vp1 for the even-numbered memory cells.
[0095]
In the third embodiment, the memory cell threshold voltage in the data state of “1” is the same between the even-numbered memory cell and the odd-numbered memory cell, but the memory in the data state of “0” is the same. The cell threshold voltages were set differently. Conversely, the memory cell threshold voltage in the data state “0” may be the same, but the memory cell threshold voltage in the data state “1” may be set to be different.
[0096]
Hereinafter, as a fourth embodiment, a case will be described in which the even-numbered memory cell and the odd-numbered memory cell have different memory cell threshold voltages in the data state of “1”.
[0097]
FIG. 15 is a diagram showing a relationship between memory cell currents for even-numbered memory cells and odd-numbered memory cells. As shown in FIG. 15, the memory cell current amount is the same between the even-numbered memory cells and the odd-numbered memory cells when the data state is “0”. On the other hand, in the case of the data state of "1", the amount of memory cell current flowing in the even-numbered memory cells is set to the first current amount, and the amount of memory cell current flowing in the odd-numbered memory cells is The second current amount is set to be a substantially intermediate value between the first current amount and the memory cell current amount in the case of the data state of “0”.
[0098]
FIG. 16 is a diagram showing a relationship between a memory cell current level flowing through a pair of memory cells and three types of reference currents for data determination. As shown in FIG. 16, three different reference currents IREF1, IREF2, and IREF3 are prepared. The total current of the pair of memory cells is “1” and “0” when both the even-numbered memory cell and the odd-numbered memory cell are “0”, “0” and “1”, respectively. , And when both are “1”, they change stepwise as shown in FIG. The three reference currents IREF1, IREF2, and IREF3 are set to lie between four different levels of the total current.
[0099]
In the above-described fourth embodiment, the process of determining data is the same as the process of the flow in FIG.
[0100]
FIG. 17 is a flowchart of a process for erasing even-numbered memory cells and odd-numbered memory cells and setting the data state to “1”.
[0101]
In step ST1, erase verify is executed for all even-numbered and odd-numbered cells.
[0102]
In step ST2, it is determined whether or not the threshold voltage Vt_cell of all the memory cells is higher than the verify voltage Vp2. If there is no memory cell having the threshold voltage Vt_cell higher than the verify voltage Vp2, the process proceeds to step ST7.
[0103]
If it is determined in step ST2 that a memory cell having a threshold voltage Vt_cell higher than Vp2 exists, in step ST3, pre-program verify is executed. Next, in step ST4, it is determined whether the threshold voltage Vt_cell of all the memory cells is higher than the verify voltage Vp1 (> Vp2). If there is a memory cell having a threshold voltage Vt_cell that is not higher than the verify voltage Vp1, a pre-program is executed in step ST5. Thereafter, returning to step ST3, the subsequent operations are repeated, and the threshold voltages Vt_cell of all the memory cells are set to be higher than the verify voltage Vp1. After setting all the memory cells to the data state of "0" by the above processing, all the even-numbered and odd-numbered memory cells are erased in step ST6.
[0104]
Next, erase verify is executed in step ST7. In step ST7, it is determined whether or not the threshold voltage Vt_cell of all the memory cells is lower than the verify voltage Ve1. If there is a memory cell having a threshold voltage Vt_cell that is not lower than the verify voltage Ve1, the process returns to step ST6 and repeats the subsequent processing. As a result, data is set so that Ve1> Vt_cell for all the even-numbered and odd-numbered cells.
[0105]
In step ST9, correction verification is executed. In step ST10, it is determined whether or not the threshold voltage Vt_cell is higher than the verify voltage Ve2 (<Ve1) for all the memory cells. If "No", the correction program is executed in step ST11, and the process returns to step ST9 and repeats the subsequent processing. As a result, all the memory cells are set to the data state of "1" so that Ve2 <Vt_cell. By this correction verify and program operation, the threshold voltage Vt_cell is set so as to be distributed between the verify voltages Ve2 and Ve1. That is, the threshold distribution of the data state of “1” can be set in a desired range.
[0106]
As shown in step ST12, the setting of "1" data in the even-numbered memory cells is completed at this point.
[0107]
Next, in step ST13, the odd-numbered memory cells are programmed. In step ST14, a program verify operation is performed on the odd-numbered cells. In step ST15, it is determined whether or not the threshold voltage Vt_cell of the odd-numbered memory cell is higher than the verify voltage Vp2. In the case of “No”, the process returns to step ST13 and the subsequent processes are repeated. Thus, data is set so that Vp2 <Vt_cell for all odd-numbered memory cells.
[0108]
FIG. 18 is a flowchart of a process for programming even-numbered or odd-numbered memory cells and setting the data state to “0” in the fourth embodiment. FIG. 19A is a diagram illustrating a change in a memory cell threshold voltage for an even-numbered memory cell, and FIG. 19B is a diagram illustrating a change in a memory cell threshold voltage for an odd-numbered memory cell.
[0109]
In step ST1 of FIG. 18, the even-numbered or odd-numbered cells are programmed. Next, in step ST2, a program verify operation is performed on the even-numbered or odd-numbered cells. In step ST3, it is determined whether or not the threshold voltage Vt_cell of the memory cell to be programmed is higher than the verify voltage Vp1. In the case of "No", the process returns to step ST1 and the subsequent processes are repeated. Thereby, data is set so that Vp1 <Vt_cell for the memory cell to be programmed.
[0110]
As a result of the above-described program operation, as shown in FIG. 14A, the threshold voltage of the even-numbered memory cells in the data state of “1” between the erase verify voltage Ve1 and the correction verify voltage Ve2 becomes the program verify. The voltage is raised to the level of the voltage Vp1 or higher, and the memory cell becomes a data state of “0”. Further, as shown in FIG. 14B, in the case of the odd-numbered memory cells, the threshold voltage is changed from the state between the erase verify voltage Ve1 and the correction verify voltage Ve2 to a level higher than the program verify voltage Vp2. The data is “1” when pulled up. As a result of the program operation of FIG. 18 from this state, the threshold voltage of the odd-numbered memory cell is raised to a level equal to or higher than the program verify voltage Vp1, and the memory cell becomes a data state of “0”.
[0111]
In the third and fourth embodiments, the floating gate type nonvolatile memory has been described as an example. However, a trap gate type nonvolatile memory as shown in FIG. 5 may be applied. As described above, the trap gate nonvolatile memory is a flash memory capable of storing two bits of information per memory cell by storing charges in a trap layer made of a nitride film or the like.
[0112]
Even when the trap gate type nonvolatile memory is used, two types of memory cells having different "0" levels or different "1" levels are connected in the word line direction as in the third and fourth embodiments. Can be set to be alternately arranged. At the time of data reading, adjacent even-numbered memory cells and odd-numbered memory cells are paired, and the total current flowing through the pair of memory cells is compared with three different types of reference currents. Data determination is performed on the cell. This data determination operation can be performed in the same manner as in the case of the floating gate nonvolatile memory, as described below.
[0113]
In FIG. 5, in order to read the data of the right bit (represented by “x” in the box) of the memory cell M02 and the data of the left bit (represented by “x” in the box) of the memory cell M01, The word line WL0 is set to a predetermined potential (for example, 2 V), the bit line BL2 is set to a drain side potential of, for example, 1 V, and the other bit lines BL0, BL1, BL3, and BL4 are set to the ground potential. In this case, the total current Ibl2 of the pair of memory cells is the sum of the current Im02 and the current Im01.
[0114]
FIG. 20 is a diagram illustrating a flow of a process of determining data when a trap gate nonvolatile memory is used.
[0115]
In step ST1, it is determined whether or not the total current Ibl2 is smaller than the reference current IREF1. If the total current Ibl2 is smaller than the reference current IREF1, the right bit (M02R) of the even-numbered memory cell and the left bit (M01L) of the odd-numbered memory cell are both "0". Otherwise, the process proceeds to step ST2.
[0116]
In step ST2, it is determined whether or not the total current Ibl2 is larger than the reference current IREF3. If the total current Ibl2 is larger than the reference current IREF3, both the right bit (M02R) of the even-numbered memory cell and the left bit (M01L) of the odd-numbered memory cell are "1". Otherwise, the process proceeds to step ST3.
[0117]
In step ST3, it is determined whether or not the total current Ibl2 is larger than the reference current IREF2. If the total current Ibl2 is larger than the reference current IREF2, the right bit (M02R) of the even-numbered memory cell and the left bit (M01L) of the odd-numbered memory cell are "1" and "0", respectively. If the total current Ibl2 is equal to or smaller than the reference current IREF2, the right bit (M02R) of the even-numbered memory cell and the left bit (M01L) of the odd-numbered memory cell are "0" and "1", respectively.
[0118]
Thus, the data determination processing ends.
[0119]
In order to set data so as to have different “0” levels or different “1” levels between the even-numbered and odd-numbered numbers, FIGS. 11 to 13 or FIGS. Using the same procedure as described above, data erasing and programming can be performed on the trap gate nonvolatile memory.
[0120]
As described above, in the third and fourth embodiments according to the present invention, two types of memory cells having different threshold voltages are alternately arranged in the word line direction, and the adjacent even-numbered memory cells are used at the time of data reading. And the odd-numbered memory cells are paired, and the total current flowing through the pair of memory cells is compared with three different reference currents. This makes it possible to perform data determination on each of the paired memory cells. Therefore, data read from each memory cell can be reliably executed without being affected by the leak current.
[0121]
In the above embodiment, it has been described that the even-numbered memory cells and the odd-numbered memory cells have the same memory cell current amount for either one of “0” and “1”. There is no problem without it. The set value of the memory cell current amount of each memory cell (that is, the set value of the memory cell threshold voltage) is set to 4 according to the data state for a pair of memory cells including even-numbered memory cells and odd-numbered memory cells. It is only necessary to be able to determine three different total current amounts. Further, in order to realize different memory cell current amounts, for example, the gate width is made different between the even-numbered cells and the odd-numbered cells, instead of adjusting the charge amount in the gates by the program or erase data setting operation. It can also be realized as a difference in the structure of the nonvolatile semiconductor memory device.
[0122]
As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.
【The invention's effect】
In the present invention, by including, as a data determination target, a memory cell that is not a data determination target that has conventionally been a current leak path, two memory cells sharing a bit line to be sensed are both data determination targets, By comparing two different reference currents and the current of the bit line, the data states of the two memory cells are determined together. In this configuration, all bit lines other than the bit line to be sensed at the time of data determination have the ground potential, so that the bit line precharge operation that has been conventionally required is unnecessary. The ground potential is extremely stable as compared with the precharge voltage, and is not affected by a voltage drop due to bit line resistance. Therefore, in the present invention, it is possible to completely prevent the read failure caused by the unstable potential difference between the bit line to be sensed and the bit line to be precharged.
[Brief description of the drawings]
FIG. 1 is a diagram showing a part of a virtual ground memory array.
FIG. 2 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the present invention.
FIG. 3 is a diagram for explaining a data determination operation according to the first embodiment.
FIG. 4 is a flowchart illustrating a data determination operation according to the first embodiment.
FIG. 5 is a diagram for explaining a data determination operation according to a modification of the first embodiment.
FIGS. 6A to 6C are diagrams illustrating a data determination method according to a second embodiment of the present invention.
FIG. 7 is a flowchart illustrating a data determination operation of a memory cell according to a second embodiment.
FIG. 8 is a diagram showing a relationship between memory cell currents of even-numbered memory cells and odd-numbered memory cells of the third embodiment.
FIG. 9 is a diagram showing a relationship between a memory cell current level flowing through a pair of memory cells of the third embodiment and three types of reference currents for data determination.
FIG. 10 is a diagram illustrating a flow of a process of determining data in the third embodiment.
FIG. 11 is a flowchart of a process for erasing even-numbered memory cells and odd-numbered memory cells and setting the data state to “1”;
FIG. 12 is a flowchart of a process for programming even-numbered memory cells and setting the data state to “0” in the third embodiment;
FIG. 13 is a flowchart of a process for programming an odd-numbered memory cell and setting it to a data state of “0” in the third embodiment.
14A is a diagram showing a change in a memory cell threshold voltage when an even-numbered memory cell is programmed, and FIG. 14B is a diagram showing a change in a memory cell threshold voltage when an odd-numbered memory cell is programmed; FIG.
FIG. 15 is a diagram showing a relationship between memory cell currents of even-numbered memory cells and odd-numbered memory cells of the fourth embodiment.
FIG. 16 is a diagram illustrating a relationship between a memory cell current level flowing through a pair of memory cells and three types of reference currents for data determination according to the fourth embodiment.
FIG. 17 is a flowchart of a process of erasing even-numbered memory cells and odd-numbered memory cells and setting the data state to “1”;
FIG. 18 is a flowchart of a process for programming even-numbered or odd-numbered memory cells and setting the data state to “0” in the fourth embodiment;
19A is a diagram showing a change in a memory cell threshold voltage for an even-numbered memory cell, and FIG. 19B is a diagram showing a change in a memory cell threshold voltage for an odd-numbered memory cell; is there.
FIG. 20 is a diagram showing a flow of processing for determining data when using a trap gate nonvolatile memory.
[Explanation of symbols]
11 Control circuit
12 Chip enable & output enable circuit
13 I / O buffer
14 cell array
15 Row decoder
16 column decoder
17 Address Latch
18 Data latch
19 Readout circuit
20 Write circuit
21 Erasing circuit
22 Reference current generation circuit

Claims (10)

A virtual ground memory array including a plurality of word lines and a plurality of bit lines;
A row decoder for selectively activating one word line of the plurality of word lines;
A column decoder for applying a sense voltage to one of the plurality of bit lines and setting all other bit lines to a ground potential;
By comparing a current flowing through the one bit line with a first reference current and a second reference current, data of two memory cells connected to the one word line and sharing the one bit line can be obtained. Including a sense amplifier that determines the state as a first state in which both are 0, a second state in which both are 1, and a third state in which one is 1 and the other is 0 A nonvolatile semiconductor memory device characterized by the above-mentioned. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a control circuit for controlling said row decoder, said column decoder, and said sense amplifier. When the data state of one of the two memory cells is known, the control circuit determines whether the data state of the two memory cells is the third state based on the one known data state. 3. The nonvolatile semiconductor memory device according to claim 2, wherein a data state of the other memory cell is determined. Selectively activating one word line of the plurality of word lines in a virtual ground memory array including a plurality of word lines and a plurality of bit lines;
Applying a sense voltage to one of the plurality of bit lines and setting all other bit lines to ground potential;
By comparing a current flowing through the one bit line with a first reference current and a second reference current, data of two memory cells connected to the one word line and sharing the one bit line can be obtained. Determining that the state is one of a first state in which both are 0, a second state in which both are 1, and a third state in which one is 1 and the other is 0. A data determination method in a nonvolatile semiconductor memory device characterized by the above-mentioned. Selectively activating one word line of the plurality of word lines in a virtual ground memory array including a plurality of word lines and a plurality of bit lines;
A sense voltage is applied to the first bit line in the arrangement of the plurality of bit lines, and all other bit lines are set to the ground potential,
Comparing the current flowing through the first bit line with a reference current,
Determining the data state of the first memory cell connected to the first bit line among the plurality of memory cells connected to the one word line based on the result of the comparison;
Applying a sense voltage to the n-th bit line in the row of the plurality of bit lines and setting all other bit lines to ground potential;
Of the plurality of memory cells connected to the one word line, the (n-1) th memory cell and the (n-1) th memory cell that share the nth bit line A step of determining a data state of the nth memory cell by comparing a reference current selected according to the data state of the nth bit line with a current flowing through the nth bit line. A data determination method in a storage device. The reference current to be compared with the current flowing through the head bit line is the first reference current, and the reference current to be compared with the current flowing through the n-th bit line is the (n-1) th memory cell. Is the first reference current when the data state is 0, and the second reference current is larger than the first reference current when the data state of the (n-1) th memory cell is 1. The data determination method according to claim 5. A virtual ground memory array including a plurality of word lines and a plurality of bit lines;
The threshold voltage of data “0” and the threshold voltage of data “1” are connected between two memory cells connected to any one of the plurality of word lines and sharing any one of the plurality of bit lines. A nonvolatile semiconductor memory device including a control circuit for setting data by changing at least one of the threshold voltages. A row decoder for selectively activating one word line of the plurality of word lines;
A column decoder for applying a sense voltage to one of the plurality of bit lines and setting all other bit lines to a ground potential;
By comparing the current flowing through the one bit line with a first reference current, a second reference current, and a third reference current, the currents are connected to the one word line and share the one bit line. 8. The nonvolatile semiconductor memory device according to claim 7, further comprising a sense amplifier for determining a data state of each of the two memory cells. Selectively activating one word line of the plurality of word lines in a virtual ground memory array including a plurality of word lines and a plurality of bit lines;
Applying a sense voltage to one of the plurality of bit lines and setting all other bit lines to ground potential;
By comparing the current flowing through the one bit line with a first reference current, a second reference current, and a third reference current, the currents are connected to the one word line and share the one bit line. A method of determining data in a nonvolatile semiconductor memory device, comprising the steps of determining the data state of each of two memory cells. The threshold voltage of data “0” and the threshold voltage of data “1” are connected between two memory cells connected to any one of the plurality of word lines and sharing any one of the plurality of bit lines. The method according to claim 9, further comprising the step of setting data by changing at least one of the threshold voltages.

Images