JP2004046392A - Usb host control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a USB host control circuit which can improve transfer efficiency while suppressing the load of a CPU. <P>SOLUTION: A USB control circuit is provided with a pipe control buffer 31, a pipe information buffer 32, a transfer information buffer 33, a pipe selection circuit 34 and a protocol engine 36. The pipe selection circuit 34 selects a pipe for transferring data between CPU 10 and a USB device 40 in accordance with information stored in the pipe control buffer 31 and the pipe information buffer 33. A response result to data transfer is acquired from the protocol engine 36 and the pipe for transferring data is switched while rewriting the content of the transfer information buffer 33 in accordance with the response result. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to data communication technology. More specifically, the present invention relates to a technology for controlling communication via USB.
[0002]
[Prior art]
In communication via USB, communication (data transfer) is performed between a single USB host and one or more USB devices. When performing data transfer between a plurality of USB devices, the USB host and the USB device perform data transfer by time-division processing using communication channels (logical channels) called pipes.
[0003]
The USB host performs transfer scheduling (routing of a communication channel) in advance in order to communicate with a plurality of USB devices. The transfer scheduling refers to determining which USB device performs communication with which pipe during a transfer effective period within a unit time called a frame, and determining the communication order (priority) of each pipe.
[0004]
Thereby, the data in the data transfer using the USB is divided into frames and transferred, and by allocating the data transfer time for each USB device in the frame, the USB host can impartially transmit the data to each USB device. It will operate to give a transfer opportunity.
[0005]
Conventionally, transfer scheduling by a USB host is performed in units of transfer for each frame, and when communication is performed using a plurality of pipes, data transfer of each pipe is averaged within a frame.
[0006]
[Problems to be solved by the invention]
However, in the conventional USB host as described above, even if a pipe assigned to transmit data in a certain frame is busy, transfer scheduling is performed for each frame. No update of transfer scheduling is performed. Therefore, if the busy state of the pipe continues in the frame, no data transfer is performed in the frame during that time, so that the transfer efficiency of the entire communication is reduced.
[0007]
In order to solve this problem, for example, when monitoring the state of each pipe and updating the transfer scheduling according to the communication status, the load on the CPU increases because transfer scheduling requires CPU processing. There was a problem of doing it.
[0008]
Particularly, when the number of transactions included in one transfer is small, the number of pipes defined in one frame increases, and the number of pipes to be scheduled increases. was there.
[0009]
The present invention has been made to solve the above problems, and has as its object to obtain a USB host control circuit that improves the transfer efficiency in USB while suppressing the load on the CPU.
[0010]
[Means for Solving the Problems]
In order to solve the above problem, the invention of claim 1 is a USB host control circuit that controls data transfer between a CPU and a plurality of USB devices, wherein each of the USB devices performs data transfer with the CPU. A plurality of communication channels for performing the communication, a channel selection unit for selecting a communication channel for performing the data transfer from the plurality of communication channels, and a data transfer performed by the communication channel selected by the channel selection unit. Acquiring means for acquiring a response result, wherein the channel selecting means switches the selection of the communication channel according to the response result acquired by the acquiring means.
[0011]
A second aspect of the present invention is the USB host control circuit according to the first aspect of the present invention, wherein the obtaining means obtains a response result for each transaction transferred by the communication channel.
[0012]
A third aspect of the present invention is the USB host control circuit according to the first or second aspect of the present invention, wherein the channel selection unit switches the communication channel selection when the response result is an error or NAK.
[0013]
A fourth aspect of the present invention is the USB host control circuit according to any one of the first to third aspects, further comprising storage means for storing the priority of each communication channel, and wherein the channel selection means comprises The selection of the communication channel is switched according to the priority stored in the means.
[0014]
A fifth aspect of the present invention is the USB host control circuit according to any one of the first to fourth aspects, wherein the channel selecting means determines whether or not the current time is a transfer valid period in the frame. The communication channel whose selection has been switched in accordance with the response result has data retransfer within the time determined by the propriety determination device to be a transfer valid period.
[0015]
A sixth aspect of the present invention is the USB host control circuit according to the fifth aspect of the present invention, wherein the channel selecting means further includes a transfer type determining means for determining a transfer type of data to be transferred for each communication channel. And retransmitting the data only to a communication channel determined to be of a predetermined transfer type by the transfer type determining means.
[0016]
The invention of claim 7 is the USB host control circuit according to the invention of claim 6, wherein the predetermined transfer type is control transfer or bulk transfer.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing a configuration of a USB host 1 according to an embodiment of the present invention, together with other configurations. The USB host 1 performs data transfer with each of the USB devices 41, 42, and 43 (hereinafter, collectively referred to as “USB device 40”) via the bus 38.
[0018]
The USB host 1 includes a CPU 10 for calculating various data and generating control signals, a memory 20 for storing various data, and a host control circuit 30 for controlling data transfer between the CPU 10 and the USB device 40 via USB. Prepare.
[0019]
The host control circuit 30 includes a pipe control buffer 31, a pipe information buffer 32, a transfer information buffer 33, a pipe selection circuit 34, a data buffer 35, a protocol engine 36, a frame timer 37, and a bus 38, and executes processing described later. It is configured as dedicated hardware.
[0020]
Further, in data transfer via USB, as described above, each of the USB devices 41, 42, and 43 defines a plurality of pipes for performing data transfer with the CPU 10, thereby performing time-division processing. .
[0021]
The pipe control buffer 31 is a storage buffer for holding information (pipe control PC) for controlling each pipe, and specifically, a transfer type in each pipe, valid / invalid of pipe information, and stored in the data buffer 35. The information includes validity / invalidity of data transmitted to the USB device 40, and presence / absence of an area in the data buffer 35 for storing data received from the USB device 40. These pieces of information exist for each pipe, and as shown in FIG. 1, each pipe number can be identified as a key, such as pipe control PC0, pipe control PC1,..., Pipe control PCn. (N is an arbitrary integer of 126 or less).
[0022]
The pipe information buffer 32 is a storage buffer for holding information about each pipe (pipe information PI), and specifically, addresses, end points, maximum addresses of the USB devices 41, 42, and 43 using each pipe. Includes packet size, transfer direction, and number of transactions. These pieces of information also exist for each pipe, similarly to the pipe control PC, and are held in an identifiable state like pipe information PI0, pipe information PI1,..., Pipe information PIn, respectively.
[0023]
Although details will be described later, in the host control circuit 30 according to the present embodiment, the priority in pipe selection is determined based on the transfer type and the pipe number. That is, the pipe control buffer 31 and the pipe information buffer 32 correspond to storage means for storing the priority of the communication channel.
[0024]
The transfer information buffer 33 is a storage buffer that holds information (transfer information TI) related to the communication result of each pipe, and includes a transfer completion, a transfer error, a transfer data number, and the like. These pieces of information also exist for each pipe, and are held in an identifiable state like transfer information TI0, transfer information TI1,..., Transfer information TIn.
[0025]
The pipe selection circuit 34 performs frame management based on the output of the frame timer 37 having a timing function, such as start / end of the frame and determination as to whether or not the time is a transfer valid period.
[0026]
The pipe selection circuit 34 is capable of accessing the pipe control buffer 31, the pipe information buffer 32, and the transfer information buffer 33, and based on the information held therein, during the frame transfer valid period. , Select a pipe for data transfer.
[0027]
Further, the pipe selection circuit 34 transmits the pipe information PI about the selected pipe to the data buffer 35 and the protocol engine 36, and information about the number of transferred transactions from the data buffer 35, and from the protocol engine 36, The information on the response result of each of the USB devices 41, 42, and 43 is received, the transfer information buffer 33 is accessed, and the transfer information TI is rewritten as necessary.
[0028]
The data buffer 35 is a storage buffer for holding data (data transmitted by the CPU 10 and data transmitted by the USB device 40) transferred by the pipe selected by the pipe selection circuit 34, and includes a protocol engine 36 and a memory 20. Arbitrates the exchange of data with the
[0029]
In addition, the data buffer 35 accesses the pipe control buffer 31 to change the state of the data buffer 35 such as validity / invalidity of data transmitted to the USB device 40 and presence / absence of an area for storing data received from the USB device 40. Write as pipe control PC.
[0030]
Further, a transaction counter 350 for counting the number of transferred transactions is provided based on the number of transferred data, and notifies the pipe selection circuit 34 of the number of transferred transactions.
[0031]
The data buffer 35 determines whether or not the data has actually been transferred based on information on a response result to the transferred data, which is notified from the protocol engine 36. Further, in the present embodiment, the data counter 35 includes the transaction counter 350, but the function of the transaction counter 350 may be included in the pipe selection circuit 34. In that case, the data buffer 35 simply transmits the number of transferred data to the pipe selection circuit 34, and counts the number of transactions transferred by the pipe selection circuit 34 based on the number of data.
[0032]
The protocol engine 36 performs a response operation in transaction units according to any one of the USB devices 41, 42, and 43 connected on the bus 38 and the pipe information PI supplied from the pipe selection circuit 34, and pipes the obtained response result to the pipe. The selection circuit 34 and the data buffer 35 are notified.
[0033]
When data is transmitted from the USB host 1, transmission data is obtained from the data buffer 35, and when data is received from the USB device 40, the received data is transmitted to the data buffer 35.
[0034]
The above is the description of the configuration of the host control circuit 30 in the embodiment.
[0035]
FIG. 2 is a flowchart showing the operation of the host control circuit 30. Hereinafter, the operation of the host control circuit 30 will be described with reference to FIG. First, prior to transfer by frame, the CPU 10 performs transfer scheduling, creates a pipe control PC and pipe information PI, and stores them in the pipe control buffer 31 and the pipe information buffer 32, respectively.
[0036]
Next, based on the input signal from the frame timer 37, the pipe selection circuit 34 determines whether or not the current time is within the data transfer valid period, and when the transfer valid period is reached, starts the processing of FIG. Initialization of the middle transfer type (step S11) and initialization of the pipe number (step S12) are performed.
[0037]
In USB data transfer,
(1) Isochronous (Isochronous) transfer: a transfer mode that does not perform error processing or retransmission processing and has the highest priority in transfer in a transfer mode that emphasizes real-time performance;
(2) Interrupt (Interrupt) transfer: A transfer mode used for transfer with a human interface device such as a keyboard, in which the amount of data is small but the data must be transferred preferentially at a constant period.
(3) Control transfer: a transfer mode used for transferring control commands and the like between the USB host 1 and the USB device 40;
(4) Bulk (Bulk) transfer: A transfer mode in which real-time performance is not so important but a transfer with a large amount of data is performed.
In the host control circuit 30, the isochronous transfer is a transfer type "0", the interrupt transfer is a transfer type "1", the control transfer is a transfer type "2", and the bulk transfer is a transfer type. Identify as "3". That is, in step S11, the currently selected transfer type is initialized to "0", so that the isochronous transfer with the highest priority is selected first.
[0038]
When the initialization is completed, the pipe selection circuit 34 accesses the pipe control buffer 31 to refer to the pipe control PC, and for the pipe indicated by the pipe number, the pipe information is valid (in the pipe in which data to be transferred exists). Is determined and the transfer type matches the selected transfer type (step S13), and the pipe information is valid and the transfer type matches the selected transfer type. Only in this case, the transaction transfer processing (step S14) is performed.
[0039]
FIG. 3 is a flowchart showing details of the transaction transfer process in step S14. In the transaction transfer process, first, the transaction counter 350 is cleared to "0" (step S31), and based on the input from the frame timer 37, whether or not the frame has ended, that is, the present time is the transfer valid period in the frame Is determined (step S32).
[0040]
If the frame has ended, the transfer information buffer 33 is accessed to update the portion of the transfer information TI relating to the pipe (step S40), and the process returns to step S21 in FIG. Is a bulk transfer (transfer type "3"), the pipe information stores a valid pipe number (steps S21 and S22), and the process ends.
[0041]
Specifically, the transfer information TI is updated by calculating the number of data transferred by the pipe selection circuit 34 based on the number of transferred transactions input from the transaction counter 350, This is performed by rewriting the number of data transfers.
[0042]
On the other hand, if the frame has not been completed, an instruction is given to the protocol engine 36 to transfer one transaction by the selected pipe, and a response result to the transfer of the transaction is obtained from the protocol engine 36 (step S33).
[0043]
The process of transferring a transaction in step S33 will be specifically described. First, the pipe selection circuit 34 sends information on a portion of the pipe information PI relating to the selected pipe number to the data buffer 35 and the protocol engine 36. introduce.
[0044]
The data buffer 35 determines whether the data transfer between the USB host 1 and the USB device 40 is transmission or reception based on the transfer direction indicated by the received pipe information PI.
[0045]
When the data transfer is transmission, necessary transmission data is read from the memory 20 and held, and the pipe control buffer 31 is accessed to transmit information indicating that transmission data to the USB device 40 is valid. Write to the pipe control PC. Further, in response to a request from the protocol engine 36, the transmission data held in the buffer is transmitted for each transaction.
[0046]
The protocol engine 36 transfers the transaction (transfer data) transmitted from the data buffer 35 to the USB device 40 according to the address and the transfer type of the USB device 40 indicated in the pipe information PI, and the response result of the data transfer. Is acquired and transmitted to the pipe selection circuit 34 and the data buffer 35.
[0047]
On the other hand, if the data transfer is reception, the data buffer 35 secures a necessary storage area on the buffer, accesses the pipe control buffer 31, and secures an area for storing the reception data from the USB device 40. Write information indicating that the operation has been performed.
[0048]
The protocol engine 36 makes a transmission request to the USB device 40 according to the address and the transfer type of the USB device 40 indicated in the pipe information PI, receives a transaction, and transmits the transaction to the data buffer 35. Further, a response result of the data transfer is obtained and transmitted to the pipe selection circuit 34 and the data buffer 35.
[0049]
When a transaction (transfer data) can be normally received, the data buffer 35 writes the data in a predetermined area of the memory 20 while temporarily holding the received transaction. The above is the specific description of step S33.
[0050]
Next, the data buffer 35 executes step S34. If the response result obtained from the protocol engine 36 in step S33 is ACK (Acknowledgement: acknowledgment), it indicates that the transferred transaction has been normally transferred. Therefore, the transaction counter 350 is counted up (step S35), and is notified to the pipe selection circuit 34.
[0051]
The pipe selection circuit 34 determines whether or not the transfer of the transaction to be transferred has been completed based on the input signal from the transaction counter 350 of the data buffer 35 and the pipe information PI (step S36), and the processing is still completed. If not, the process returns to step S32 to repeat the process to transfer the transaction by the pipe.
[0052]
As a result, when the transfer is performed normally (when the response result is ACK), the transfer of the transaction to be transferred ends (Yes in step S36), or the valid transfer period of the frame ends ( Until “Yes” in step S32), the processing in steps S32 to S36 is repeated, and the transfer of the transaction by the selected pipe (the pipe having the transfer right) (step S33) is repeatedly performed.
[0053]
When the transfer of the transaction is completed (Yes in step S36), the fact is notified to the CPU 10 (step S37), and the portion related to the pipe in the transfer information TI is updated (step S39), and the transaction by the selected pipe is performed. The transfer process ends, and the process returns to step S15 in FIG.
[0054]
Thereby, the CPU 10 can detect that the transfer of the transaction by the pipe has been normally completed, and can obtain necessary information by accessing the transfer information TI.
[0055]
If the response result acquired from the protocol engine 36 is not ACK (No in step S34) and is an error (Yes in step S38), some transfer error has occurred between the USB host 1 and the USB device 40. This is notified to the CPU 10 (step S37), the portion of the transfer information TI relating to the pipe is updated (step S39), the transaction transfer process by the selected pipe is completed, and the process returns to step S15 in FIG. . In this case, the pipe selection circuit 34 includes not only the number of transfer data that can be transferred until then, but also data indicating a transfer error in a portion of the transfer information TI related to the pipe.
[0056]
Thereby, the CPU 10 can detect that a transfer error has occurred in the data transfer by the pipe, and confirm the number of data transfers that can be transferred by accessing the transfer information TI. be able to.
[0057]
If the response result obtained from the protocol engine 36 is neither ACK nor error (No in step S38), it can be determined that the response result obtained from the protocol engine 36 is NAK (Not Acknowledgement: negative response). Therefore, in this case, the pipe selection circuit 34 does not notify the CPU 10 but updates only the transfer information TI (step S39), ends the transaction transfer processing by the selected pipe, and returns to step S15 in FIG. Return to
[0058]
When the transfer of the transaction to be transferred is completed or the response result to the transfer data is an error or NAK, and the transaction transfer processing (step S14) of the selected pipe is completed, the pipe selection circuit 34 It is determined whether or not the frame is completed based on the input (step S15). If the frame has ended, steps S21 and S22 are executed and the process ends.
[0059]
On the other hand, if the frame has not ended, the processing of steps S13 to S17 is repeated while incrementing the pipe number and switching the pipe (step S16) until the determination of step S13 is completed for all the pipes (step S17). . That is, step S16 corresponds to a process of transferring the right to transfer data to a pipe having a pipe number corresponding to the next priority and switching the pipe selection.
[0060]
As described above, the host control circuit 30 according to the present embodiment can switch the pipe for performing the data transfer in accordance with the response result obtained for each transaction. When the USB device 41 is busy, that is, when it is in a state where data transfer cannot be performed, the selection of the pipe used by the USB device 41 is switched to another USB device (42 or 43). ) Can start the data transfer by the pipe used, and it is possible to improve the transfer efficiency without waiting for another USB device until the busy state of the USB device 41 is eliminated.
[0061]
Further, the switching process of the pipe selection can be performed in the host control circuit 30 without the process by the CPU 10, so that the transfer efficiency can be improved while suppressing the load on the CPU 10.
[0062]
Furthermore, since the response result is obtained for each transaction, the pipe for performing data transfer can be switched for each transaction which is the minimum unit in data transfer, and the transfer efficiency can be further improved.
[0063]
If the reference has been completed for all the pipes that perform data transfer according to the selected transfer type (Yes in step S17), the transfer type is incremented (step S18) until the processing is completed for all the transfer types. The processing from S12 is repeated (step S19). That is, step S18 corresponds to a process of switching pipe selection by transferring the right to transfer data to a pipe that performs data transfer according to the next priority transfer type.
[0064]
By performing such processing by the pipe selection circuit 34, the transfer type is selected in the order of isochronous transfer, interrupt transfer, control transfer, and bulk transfer, and the pipe is selected in the order of the pipe number for each transfer type to transfer data. Is executed.
[0065]
Note that, when the bulk transfer (transfer type “3”) with the lowest priority is selected and reference to all the pipes is completed, the transfer type is incremented to “4” (step S18). Therefore, after the opportunity of data transfer is given to all the pipes for which the pipe information is valid (Yes in step S19), the pipe selection circuit 34 changes the selected transfer type to the transfer type “2” (control (Step S20), and the processing from Step S12 is repeated.
[0066]
Thus, a pipe that performs data transfer by control transfer or bulk transfer and that is switched according to a response result (error or NAK) can be selected as a pipe that performs data transfer again, and is transferred. For a pipe in which a transaction to be left (a pipe for which pipe information in the pipe control PC is valid), data is re-transferred as long as the frame is valid for transfer, and an opportunity to transfer the remaining transaction is provided. Thereby, the transfer efficiency can be further improved.
[0067]
The above processing will be described based on a specific example. FIG. 4 is a schematic diagram of data transfer in a frame by the host control circuit 30. FIG. 4 shows an example in which transfer 0 (transfer composed of transactions T00 to T03) and transfer 1 (transfer composed of transactions T10 to T13) are respectively bulk-transferred by pipes 0 and 1. ing. In the section (time) shown in FIG. 4, the frame is not ended.
[0068]
First, when the pipe selection circuit 34 selects the pipe number “0” while selecting the transfer type “3” (bulk transfer), the pipe 0 is referred to in step S13, and the transaction transfer processing (step S14) is performed. Be executed.
[0069]
As a result, first, the transaction T00 is transferred. As long as the response result to the transfer is ACK, the transactions T01 and T02 are further sequentially transferred, and the transaction counter 350 is counted up for the normally transferred transaction in step S35. That is, the bulk transfer by the pipe 0 is performed during the section TM1 shown in FIG.
[0070]
In the example illustrated in FIG. 4, the response result to the transaction T02 is NAK (Steps S34 and S38 are both determined to be No.). Accordingly, the pipe selection circuit 34 calculates the number of transferred data from the number of transactions (T00 and T01) transferred so far and accesses the transfer information buffer 33 to update the transfer information TI0. Then, the transaction transfer processing by the pipe 0 ends. Further, the selected pipe 0 is switched by incrementing the pipe number, and the pipe 1 is selected.
[0071]
Thereby, the pipe 1 is referred to in step S13, and the transaction transfer process (step S14) is executed again.
[0072]
In the section TM2, similarly to the section TM1, first, the transaction T10 is transferred, and since the response result to the transfer is ACK, the transactions T11 to T13 are sequentially transferred, and each time the transaction is transferred normally. Next, the transaction counter 350 is counted up.
[0073]
In the example shown in FIG. 4, the response result to the transaction T13 is NAK even in the transfer in the section TM2. Therefore, the pipe selection circuit 34 calculates the number of transferred data from the number of transactions transferred so far (T10 to T12), updates the transfer information TI1, and ends the transaction transfer processing by the pipe 1. I do. Further, the pipe number is incremented, and switching of pipe selection is performed.
[0074]
At this point, since all the pipes in the bulk transfer have been referred to, the pipe selection circuit 34 executes step S20 to provide an opportunity to transfer the remaining transactions to the remaining pipes to be transferred. give.
[0075]
In the example shown in FIG. 4, when the pipe is switched after the section TM2, the transfer type is selected in the order of control transfer and bulk transfer. When the pipe 0 is referred to while the bulk transfer is selected, the transaction to be transferred remains in the pipe 0, and the transaction transfer process (step S14) by the pipe 0 is restarted.
[0076]
At this time, the pipe selection circuit 34 starts the transfer from the untransferred transaction T02 in the pipe 0 by referring to the transfer information TI0 and the pipe information PI0.
[0077]
As a result, in the section TM3, the transactions T02 and T03 are sequentially transferred, and since the response results to the transfer of the transactions T02 and T03 are both ACK, the transfer of the transaction by the pipe 0 ends normally (the transfer ends). ). Therefore, the pipe selection circuit 34 notifies the CPU 10 (step S37), updates the transfer information TI0 (step S39), and ends the transaction transfer processing by the pipe 0.
[0078]
Further, the pipe is switched by incrementing the pipe number, and the transaction transfer processing by the pipe 1 is started. Also in this case, the transfer is restarted from the untransferred transaction T13 by referring to the transfer information TI1 and the pipe information PI1.
[0079]
Since the response result to the transfer of the transaction T13 is ACK, the transfer of the transaction by the pipe 1 ends normally, and the pipe selection circuit 34 notifies the CPU 10 (step S37) and updates the transfer information TI1 (step S37). Step S39), the transaction transfer processing by the pipe 1 ends.
[0080]
Thereafter, since there is no valid pipe information, the transaction transfer process is not executed, and after the transfer valid period in the frame ends (not shown), after steps S21 and S22 are executed, The process ends.
[0081]
As described above, in the host control circuit 30, not only when the pipe transfer circuit 34 has successfully completed the data transfer (Yes in step S36), but also when an error has occurred in the data transfer, a NAK response (busy response, etc.) ), The data transfer by the pipe can be terminated and the data transfer by another pipe can be started without waiting for an instruction from the CPU 10, and the transfer on the CPU 10 can be suppressed while suppressing the load on the CPU 10. Efficiency can be improved.
[0082]
In addition, for a pipe that performs data transfer by control transfer and bulk transfer, the transfer valid period in the frame remains even if the data transfer is terminated by receiving an error or NAK as a response result once. As long as the re-transfer can be performed, the transfer efficiency can be further improved.
[0083]
【The invention's effect】
As described above, according to the first to seventh aspects of the present invention, it is possible to improve the transfer efficiency while suppressing the load on the CPU by switching the selection of the communication channel according to the obtained response result. it can.
[0084]
According to the second aspect of the present invention, by acquiring the response result for each transaction transferred by the communication channel, it is possible to acquire the response result for each minimum unit of data transfer and switch the communication channel selection. Therefore, the transfer efficiency can be further improved.
[0085]
According to the third aspect of the present invention, by switching the communication channel selection when the response result is an error or NAK, it is possible to switch to another communication channel when the communication channel cannot perform data transfer. Therefore, the transfer efficiency can be improved.
[0086]
According to the fourth aspect of the present invention, the communication channel can be switched efficiently by switching the selection of the communication channel in accordance with the priority stored in the storage means.
[0087]
According to the invention described in claim 5, for the communication channel switched according to the response result, the data is re-transferred within the time determined to be the transfer valid period, so that the transfer validity within the frame is at present. In the case of the period, the transfer efficiency can be further improved by retrying the interrupted communication channel once.
[Brief description of the drawings]
FIG. 1 is a diagram showing a host control circuit according to an embodiment of the present invention together with another configuration.
FIG. 2 is a flowchart showing an operation of the host control circuit.
FIG. 3 is a flowchart showing details of a transaction transfer process in the host control circuit.
FIG. 4 is a schematic diagram of data transfer in a frame by a host control circuit.
[Explanation of symbols]
1 USB host, 10 CPU, 20 memory, 30 host control circuit, 31 pipe control buffer, 32 pipe information buffer, 33 transfer information buffer, 34 pipe selection circuit, 35 data buffer, 350 transaction counter, 36 protocol engine, 37 frame timer , 38 bus, 40, 41, 42, 43 USB devices.

Claims (7)

A USB host control circuit for controlling data transfer between a CPU and a plurality of USB (Universal Serial Bus) devices,
A plurality of communication channels for each of the USB devices to perform data transfer with the CPU;
Channel selection means for selecting a communication channel for performing the data transfer from the plurality of communication channels,
Acquisition means for acquiring a response result to data transfer performed by the communication channel selected by the channel selection means,
With
The channel selecting means,
A USB host control circuit, wherein selection of the communication channel is switched according to the response result obtained by the obtaining unit. The USB host control circuit according to claim 1, wherein
Acquisition means,
A USB host control circuit for acquiring a response result for each transaction transferred by a communication channel. The USB host control circuit according to claim 1 or 2,
The channel selection means is
A USB host control circuit for switching a communication channel selection when a response result is an error or NAK. The USB host control circuit according to claim 1, wherein:
Storage means for storing the priority of each communication channel,
The channel selection means is
A USB host control circuit, wherein the selection of the communication channel is switched according to the priority stored in the storage unit. The USB host control circuit according to claim 1, wherein:
The channel selection means is
The present time has a feasibility determination means for determining whether or not the transfer validity period in the frame,
A USB host control circuit characterized in that data is re-transferred for a communication channel whose selection has been switched according to a response result, within a time period determined by the availability determination unit to be a transfer valid period. The USB host control circuit according to claim 5, wherein
The channel selection means is
Further comprising transfer type determining means for determining the transfer type of the transferred data for each communication channel,
A USB host control circuit, wherein the data is retransmitted only to a communication channel determined to be a predetermined transfer type by the transfer type determining means. The USB host control circuit according to claim 6, wherein
A USB host control circuit, wherein the predetermined transfer type is control transfer or bulk transfer.

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