JP2004041321A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine taken all possible measures against noise to practically exclude effects such as noise. <P>SOLUTION: This game machine is provided with a main routine ST5-ST14 being endlessly executed into a loop, a voice output interruption routine STOUT1-STOUT12 interrupting other processing under execution and started, a watchdog timer WDT forcedly returning a game operation to an initial state according to the result in an own clocking operation, and when a flag value WDFLG to be turned on by the interruption routine is turned on, a processing outputting a clear signal to the watchdog timer WDT is provided in the main routine. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gaming machine such as a pachinko machine, an arrangement ball machine, a sparrow ball game machine, and a revolving game machine, and more particularly, to a gaming machine with a complete noise countermeasure.
[0002]
[Prior art]
A gaming machine is generally composed of a plurality of circuit boards separated by function, and the plurality of circuit boards operate synchronously based on control commands, thereby realizing a complex gaming operation as a whole. Such a gaming machine is generally composed of a main control board that outputs a control command and a plurality of sub-control boards that operate based on the control command from the main control board.
[0003]
Sub-control boards include, for example, a symbol control board that controls a liquid crystal display, a payout control board that controls the payout operation of a game ball by driving a payout motor, a lamp control board that blinks an LED lamp, and a voice control that drives a speaker. There are substrates and the like.
[0004]
[Problems to be solved by the invention]
By the way, a large number of gaming machines are installed in the gaming hall in close proximity, and these gaming machines with built-in solenoids, motors, and the like are operating at the same time, so there is a considerable noise environment. Therefore, the control command may be garbled due to noise, or the data in the RAM work area may be garbled.
[0005]
In such a case, for example, an unexpectedly meaningless sound may be generated from the speaker, which may give a great distrust to the player. In particular, when a loudspeaker is used to produce powerful sound effects, an unacceptably loud noise may occur over a long period of time. It is necessary to take all possible measures to prevent this situation from occurring.
[0006]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine in which noise countermeasures are thoroughly taken.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problem, the invention according to claim 1 includes a main processing unit that is executed in an infinite loop, and one or more interrupt processing units that are started by interrupting other processes being executed. A reset unit that forcibly returns the control operation to the initial state according to the result of its own timing operation, and the timing operation of the reset unit is initialized on the condition that the operation of the interrupt processing unit is executed. A reset prohibiting means for returning to the state is provided.
[0008]
The reset prohibiting unit may be provided in either the main processing unit or the interrupt processing unit, but is preferably provided in the main processing unit. In this case, whether or not the operation of the interrupt processing unit has been executed is determined by a flag value set at the final stage of the interrupt processing unit.
[0009]
Preferably, the present invention preferably includes two or more types of interrupt processing units, and the reset prohibiting unit returns the timing operation of the reset unit to the initial state on condition that the operations of the plurality of interrupt processing units are executed. ing. A determination means for repeatedly determining the validity of the inspection data stored in the predetermined area in advance, and an avoidance means for avoiding the operation of the reset prohibition means when the determination means determines that the validity is not valid. It is also preferable that the main processing unit is provided. The inspection data is not particularly limited, but a checksum sum value or data obtained by copying data at a plurality of addresses in the ROM to the RAM area is preferably used. Prior to avoiding the operation of the reset prohibiting means, it is preferable to set the CPU in an interrupt acceptance prohibited state.
[0010]
In addition, the present invention preferably includes a main control unit that mainly controls gaming operations and a sub-control unit that realizes individual operations based on control commands from the main control unit. It is an example, and is composed of a main control unit that mainly controls gaming operations, and a plurality of sub-control units that realize individual operations based on control commands from the main control unit, the main processing unit, More preferably, the interrupt processing unit and the reset unit are provided in all or part of the main control unit and the sub-control unit.
[0011]
On the other hand, the invention according to claim 6 is a gaming machine comprising: a main control unit that mainly controls gaming operations; and a voice control unit that realizes voice production based on a control command from the main control unit. The audio control unit is configured to include a main process executed in an infinite loop and an interrupt process that interrupts other processes being executed and outputs an audio signal. The interrupt process is an audio signal to be output. Regardless of the presence or absence of, it is started regularly. In the present invention, since the audio circuit is always driven, there is virtually no possibility of abnormal sounds occurring for a long time. Here, it is preferable that the interrupt process functions to output a sound signal corresponding to the received control command and to continue outputting a silence signal to the sound circuit after the output of the sound signal. It is.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the gaming machine of the present invention will be described in more detail based on examples. FIG. 17 is a block diagram illustrating the overall configuration of the pachinko machine according to the embodiment. The illustrated pachinko machine has a main control board 1 for centrally controlling gaming operations, a symbol control board 2 for changing the characters and symbols displayed on the liquid crystal display 8, and a voice for driving a speaker to realize a sound effect. A control board 3, a lamp control board 4 that realizes a lamp effect by blinking lamps, a payout control board 5 that pays out game balls, and a launch control board that is controlled by the payout control board 5 and fires game balls 7 and a power supply substrate 6 that receives AC 24V and supplies a DC voltage to each part of the apparatus.
[0013]
The main control board 1, the design control board 2, the voice control board 3, the lamp control board 4, and the payout control board 5 are each composed of a computer circuit having a one-chip microcomputer. Based on the control command from the main control board 1, the individual control operations described above are realized. In this embodiment, the control command has a 2-byte length and is transmitted by a one-way parallel communication method, but is not particularly limited to this configuration.
[0014]
FIG. 18 is a block diagram showing a circuit configuration of the audio control board 3. As illustrated, the audio control board 3 includes a one-chip microcomputer 10, an amplifier 11 that amplifies an analog audio signal (mixed sound of the sound effect BGM and the background sound SE) output from the one-chip microcomputer 10, and a watchdog timer ( WDT) 12.
[0015]
The one-chip microcomputer 10 includes an input port 13 that receives a control command from the main control board 1, an output port 14 that outputs a clear pulse to the watchdog timer 12, a CPU core 15 that controls the operation of the audio control board 3, A TPU (Timer Pulse Unit) 16 that outputs various signals based on the system clock; an interrupt controller 17 that receives internal interrupt signals CH0 and CH1 from the TPU 16 and a strobe signal STB (external interrupt signal) from the main control board 1; D / A converter 18 that receives PCM audio data restored in software and outputs an audio analog signal, and stores a control program and ADPCM data (adaptive differential pulse code modulation) in a fixed manner A ROM (Read Only Memory) 19, and is structured around a RAM (Random Access Memory) 20 used as a work area of the control program (work area).
[0016]
When the clear pulse to be output from the output port 14 is interrupted for a predetermined time or more, a reset signal is output from the watchdog timer 12 to the CPU core 15, and the CPU core 15 is reset and the control program is started from the beginning. Will be re-executed.
[0017]
As shown in FIG. 18, the interrupt controller 17 is supplied with internal interrupt signals CH0 and CH1 from the TPU 16 and a strobe signal STB from the main control board 1, both of which can be prohibited (masked). It is a signal. Here, the strobe signal STB is a signal output from the main control board 1 together with a control command, and is supplied to the interrupt controller 17 as an IRQ (Interrupt Request) signal. Is supplied with an interrupt signal INT and outputs an interrupt vector for specifying an interrupt processing routine.
[0018]
The internal interrupt signal is set to be output from the channel 0 and the channel 1 of the TPU 16 respectively, but the interrupt signal CH1 from the channel 1 is set to be emitted every 4 mS, and the interrupt signal CH0 from the channel 0 is Are set to be emitted at each sampling period (τ) individually set by the control program. Here, the sampling period means the output interval (τ) of the audio analog signal output from the D / A converter 18.
[0019]
The sampling period (τ) is individually set by the control program so that the sampling period can be appropriately changed according to each voice message output from the D / A converter 18. For example, when reproducing audio data (ADPCM data) acquired at sampling frequencies of 8 KHz, 16 KHz, and 32 KHz and stored in the ROM 19, the time intervals (τ) of 125 μS, 62.5 μS, and 31.25 μS, respectively. When the interrupt signal CH0 is issued, the ADPCM data is converted into PCM data and output from the D / A converter 18 at a timing corresponding to the sampling frequency.
[0020]
In connection with these points, the operation of the TPU 16 will be described in more detail. TPU16 (Hitachi) has TCNT (timer counter), TGR (timer general register), TSR (timer status register), TIER (timer interrupt register) and others for each channel. It is provided for each. In this embodiment, a timer upper limit value is set in the TGR (timer general register), the TCNT (timer counter) count-up operation is started, and the TCNT counted up in synchronization with the system clock is started. When the value matches the upper limit value of TGR, the TGF flag of TSR (timer status register) of TPU 16 is turned on. In accordance with this operation, TCNT (timer counter) is cleared to zero.
[0021]
Here, when TIER (timer interrupt register) is set to the interrupt enabled state, an internal interrupt of channel 0 or channel 1 is generated and transmitted to the interrupt controller 17. The interrupt controller 17 generates an interrupt signal INT to the CPU core 15 according to the interrupt priority. If the CPU core 15 is in an interrupt acceptance state EI (Enable Interrupt), the interrupt controller 17 is specified by an interrupt vector. The interrupt processing program stored at the address is executed.
[0022]
Therefore, for example, when reproducing audio data with sampling frequencies of 8 KHz, 16 KHz, and 32 KHz, in the embodiment in which the frequency of the system clock is 20 MHz, the timer is set in the TGR (timer general register) of channel 0, respectively. As the upper limit value, 20000/8, 20000/16, 20000/328 may be set. Then, after the TCNT is cleared to zero, when the start of the count-up operation is instructed by software, the value of the TCNT is updated at a speed of 20 MHz, and the TSR of the TPU 16 is updated after the predetermined number of count-up operations. The TGF flag of the (timer status register) is turned on.
[0023]
As described above, when the TGF flag is turned on, the interrupt signal INT is output to the CPU core 15 on condition that the TIER (timer interrupt register) is turned on. The TGF flag of the (timer status register) is returned from the on state to the off state in the interrupt processing program. In addition, the TIER (timer interrupt register) of the TPU 16 and the IER (IRQ enable register) of the interrupt controller 17 are also turned on or off by software, and the interrupt operation is appropriately managed. Yes.
[0024]
In this embodiment, an audio effect is realized by using such an internal interrupt from the channel 0 (CH0) of the TPU 16. FIG. 19 is a flowchart in which a portion related to the interrupt of channel 0 is extracted from the main routine (details will be described later) shown in FIG. As shown in the figure, after the CPU is reset, such as when the power is turned on, the CPU is disabled from accepting interrupts (DI state disable interrupt), and (1) the counter upper limit value (a value corresponding to 8 KHz) is set in TGR At the same time, (2) the count-up operation is started after TCNT is cleared to zero, and (3) the TIER (timer interrupt enable register) of channel 0 is set to the on state (ST4).
[0025]
As a result, after the CPU is set to the interrupt permission state (EI state enable interrupt) (ST5), an internal interrupt of channel 0 is generated every 125 μS (= 1/8 KHz). However, since silence data is stored in the SNDDATA address of the work area in the first stage (ST3) and the SNDFLG address for BGM sound and SE sound is set to 00H (ST3), D / An audio circuit such as an A converter is driven in a silent state. Although the significance of the SNDDATA address and the SNDFLG address will be described later, this embodiment always drives the audio circuit in a silent state even when no audio production is performed, and such characteristic configuration generates abnormal sound due to noise or the like. Is effectively prevented.
[0026]
That is, when the audio circuit is maintained in a non-driven state (for example, a state in which an interrupt of channel 0 is not generated), the input value of the D / A converter is maintained at an abnormal level due to the influence of noise and the like. However, in this embodiment, since the interruption of channel 0 is constantly generated, the SNDDATA address is repeatedly rewritten to silence data when unnecessary (see FIG. 14 STOUT11 ′, etc.), such a trouble cannot occur.
[0027]
1 to 5 exemplify a reference table for explaining the relationship between the control command received from the main control board 1 and the voice information issued from the voice control board 3. In this embodiment, in response to a 2-byte length control command transmitted from the main control board 1, sound information obtained by mixing sound effects (SE) and background sounds (BGM) is output from the speaker SP. First, this series of processes will be schematically described.
[0028]
As shown in FIG. 1 (a), a 1-byte Fi command (complete information Full Intelligence Command) is specified in response to the received 2-byte control command. Here, the Fi command is to completely specify a series of audio information. For example, when the symbol change operation is started in the liquid crystal display 8 in accordance with a winning at the symbol start opening, the symbol change is performed. (1) “I can expect this time!” → (2) ... (silent state) → (3) "Hore reach!" → (4) ... ( Silence state) → (5) A series of sound effects SE such as “Yeah! Big hit !!!!” are specified together with the background sound BGM (usually music).
[0029]
The Fi command is configured by combining the classification information (1) to (5) as described above, and the classification information is specified by the Si command (Semi Intelligence Command). That is, the Fi command is composed of a combination of Si commands, and by combining a plurality of Si commands, (1) “I can expect this time!”, (2)... (Silent state), (3 ) "Hello reach!", (4) ... (silence state), (5) "Yeah! Big hit!"
[0030]
FIG. 2 schematically shows the relationship between the Fi command, the Si command, and the sound NO. As shown in FIGS. 2A and 2B, for one Fi command, an Si command for background sound (BGM) and an Si command for sound effect (SE) are specified. For example, in the case of the Fi command with the command number 01H, the combination of a series of 10 Si command numbers (50H, 23H, 50H, 24H, 41H, 50H, 4BH, 4CH, 5CH, 50H) is specified as the sound effect. As a background sound, a combination of a series of seven Si command numbers (01H, 51H, 02H, 51H, 10H, 0FH, 51H) is specified. H means a hexadecimal number.
[0031]
Each Si command is defined along with its playback time. In the case of the sound effect (SE) illustrated in FIG.
(1) Si command 50H (silence) that requires 9.4 seconds of playback time
(2) Si command 23H which requires a playback time of 0.7 seconds
(3) Si command 50H (silence) requiring a playback time of 12.7 seconds
(4) Si command 24H requiring a reproduction time of 1.0 second
(5) Si command 41H requiring a playback time of 0.8 seconds
(6) Si command 50H (silence) requiring a playback time of 3.6 seconds
(7) Si command 4BH requiring a playback time of 2.0 seconds
(8) Si command 4CH requiring a playback time of 0.8 seconds
(9) Si command 5CH, which requires a playback time of 11.27 seconds
(10) Si command 50H (silence) requiring a playback time of 0.004 seconds
Means that the Fi command 1 is activated. The Si command to be executed among the series of Si commands is determined by the progress counter CNT for SE.　Directed by SE.
[0032]
These points are the same for the background sound. In the case of the background sound (BGM) illustrated in FIG.
(1) Si command 01H which requires a reproduction time of 9.4 seconds
(2) Si command 51H (silence) requiring a playback time of 0.7 seconds
(3) Si command 02H requiring a playback time of 12.7 seconds
(4) Si command 51H (silence) requiring a playback time of 3.6 seconds
(5) Si command 10H requiring a reproduction time of 4.8 seconds
(6) Si command 0FH that requires a playback time of 9.1 seconds
(7) Si command 51H (silence) requiring a playback time of 0.004 seconds
Means that the Fi command 01H is activated. The BGM progress counter CNT determines which Si command is currently to be executed in the series of Si commands.　Directed by BG.
[0033]
Each Si command is further configured to specify a combination of a sound NO that is an audio part and its playback time. For example, in the example of FIG. 2 (a), the Si command 5CH is a sound NO47H requiring a reproduction time of 0.6 seconds → a sound NO47H requiring a reproduction time of 0.6 seconds → ... → reproduction of 1.1 seconds. Sound NO47H requiring time →... → Equipped with sound NO56H requiring reproduction time of 2 seconds. As described above, the sound NO and the reproduction time thereof are not necessarily fixed, and the reproduction time is appropriately changed. The sound NO to be executed among the series of sound NOs is determined by the progress counter PT.　Directed by CNT. In FIG. 2, ENDCD is a code indicating the end of data, and the playback time is in units of mS (milliseconds) and is specified in the format ** / 4. This is because interrupt processing occurs every 4 ms.
[0034]
As described above, in this embodiment, the Fi command is specified from the control command, the Si command combination is specified by the Fi command, and each Si command is configured to specify the sound NO combination. 3 to 5 illustrate in more detail the relationship from the identification of the Fi command number to the reproduction of the audio signal, and FIG. 3 illustrates the relationship between the Fi command number and a series of Si commands for realizing this. Is shown. FIG. 4 shows the relationship between the Si command and a series of sound NOs for effecting this, and FIG. 5 shows the relationship between the sound NO and the storage location of the corresponding audio data (ADPCM data). Is shown.
[0035]
Hereinafter, the control program of the voice control board 3 will be described based on these points. In the present embodiment, the control program for the voice control board 3 includes a main routine (FIG. 6) that starts executing after power-on, a timer interrupt processing routine (FIG. 7) that is started every predetermined time (4 mS), A sound output interrupt routine (FIG. 14) for supplying PCM data to the D / A converter at each sampling period (τ), and a reception interrupt routine (FIG. 15) started upon receiving a strobe signal STB from the main control board 1; It is composed of an abnormal interrupt routine (not shown) that is started due to a program runaway or the like.
[0036]
When a timer interrupt (FIG. 7), a sound output interrupt (FIG. 14), and a reception interrupt (FIG. 15) are started, the CPU is disabled. In this embodiment, the CPU is interrupted in the interrupt processing routine. Since one of the interrupt processing is started during the execution of the main routine, the other interrupt signals are suspended unless the EI instruction is executed in the main routine (ST5). Become.
[0037]
Further, at the end of the timer interrupt (FIG. 7) and the sound output interrupt (FIG. 14), the main routine (FIG. 7) is executed by setting the flag WDFLG1 and the flag WDFLG2 to the ON state and executing each interrupt process at least once. 6).
[0038]
Furthermore, at the end of the timer interrupt (FIG. 7) and the sound output interrupt (FIG. 14), the TGF flag of the TPU 16 TSR (timer status register) is changed from the on state to the off state. Therefore, the count-up operation of TCNT (timer counter) of TPU 16 which is cleared to zero at this stage is started by the internal module resetting process (ST5 in FIG. 19), and again the TGR (timer general register) Until the value is reached, the CH0 interrupt will not occur.
[0039]
First, the main routine will be described with reference to FIG. When the power is turned on or a reset signal is received from the watchdog timer 12, the CPU enters a reset state, and after the CPU puts itself into an interrupt acceptance disabled state (DI), whether or not all the inspection data Di match. Is checked (ST1). Here, the inspection data Di is obtained by copying stored data of a specific plurality of ROMs (addresses AD1, AD2,..., ADn) to n addresses in the RAM area.
[0040]
Then, as the check process, it is determined whether or not all the n pieces of inspection data stored in the RAM area match the stored data in the ROM (addresses AD1, AD2,..., ADn). Here, if even one of the inspection data Di does not match, the RAM 20 of the one-chip microcomputer 10 constituting the voice control board 3 is cleared to zero (ST2). On the other hand, if all the inspection data Di match, The process of step ST2 is skipped.
[0041]
Next, 80H (silent data) is stored at the SNDDATA address where the output data to the D / A converter 18 is stored, and the flag value (the value of the SNDFLG address) is set to 00H to prohibit the output of the sound effect SE and the background sound BGM. Set to. Further, the built-in module is initialized and the inspection data Di is set (ST3). This setting process corresponds to the inspection data Di described above. For example, as shown in FIG. 16 (a), ROMs (AD1, AD2,. , ADn address) is copied to n addresses in RAM not used as a work area (work area).
[0042]
When the setting of the inspection data Di is completed in this way, next, after the audio output process is executed (ST4), the CPU is set to an interrupt enabled state (EI: enable interrupt) and the built-in one-chip microcomputer 10 The module is reset to the initial state (ST5).
[0043]
After the CPU executes the EI instruction, a maskable interrupt signal including an internal interrupt of CH0 is accepted thereafter. However, since silence data is stored in the SNDDATA address after the power is turned on (ST3), silence is output from the AD converter 18 in the voice output interrupt process (FIG. 14) that occurs after 125 μS has elapsed (1 / 8K). Is output (see STOUT1 in FIG. 14). Since the SE sound and BGM sound flag values (the value of the SNDFGLG address) are set to 00H (ST3), after the silence is output from the AD converter 18, the silence data is again input to the SNDDATA address. Is stored (see STOUT11 ′ in FIG. 14).
[0044]
Subsequent to the process in step ST5, a process related to the sound control work table (see FIG. 13) that manages the activation of the sound NO is performed (ST6). Specifically, as shown in FIG. 12, the processes of steps ST92 to ST97 are performed on the control work tables SNDCTBL (for BGM) and SNDCTBL (for SE) shown in FIG. First, the data of the SNDNO address storing the sound NO in the work table SNDCTBL and the inverted data of the data of the SNDNOCS address are compared, and if they match, the data of the SNDNO address is used as the sound NO in the subsequent processing (ST92). ).
[0045]
On the other hand, if the two do not match, the data in the backup area SNOBUP is used as the sound NO on condition that the data in the SNOBUP address and the inverted data of the data in the SNOBUPC address match (ST92). If neither data can be used, silence processing is performed so that no sound is output from the speaker.
[0046]
As described above, the first information and the second information obtained by inverting the first information are stored in the work area, and the data stored in the work area by the first and second information is stored. The validity is checked. In this way, the validity of the data (sound NO) is strictly checked in the case of the present embodiment in addition to the occurrence of a data reception interrupt (FIG. 15) during the execution of the main routine, as well as a timer for every 4 ms. Since the interrupt (FIG. 7) and the audio output interrupt (FIG. 14) are executed in parallel and control processing for the sound NO is performed at a complicated timing in each, data mismatch may occur due to the influence of noise or the like. Because there is sex. The validity check is not limited to the above method, but may be a checksum method using a predetermined number of bits.
[0047]
Subsequently, the sound NO and its inverted data are stored in the SNOBUP address, SNDNOCS address, and SNOBUPC address of the work table SNDCTBL (ST93). Further, the data of the ADFLG address, SNDADR address, SNDFLG address, SNDNO address, DELTA address, XN address, ADFLG address, and SNDADR address of the work table SNDCTBL are acquired in this order (ST94). Here, the reason why the data at the ADFLG address and the SNDADR address is acquired twice is that the stored data may change due to a timer interrupt (FIG. 7) or an audio output interrupt (FIG. 14) during the process of step ST94. Because there is. Therefore, as long as the first and last data do not match, all the data is acquired again.
[0048]
Next, (SNDFLG + SNDNO + DELTA + AFDLG + XN + SNDADR　H + SNDADR　L), the checksum is calculated by 16-bit addition operation, and the inverted data is converted to B　Store in the CS address (ST95). SNDADR　H is the upper 2 bytes of the 4-byte length address value (4 bytes from SNDADR address), SNDADR　L means the lower 2 bytes. In addition, B of work table SNDCTBL　DELTA address, B　Address XN, B　ADFLG address, B　SNDADR address, B　SNDNO address, B　Backup data is stored in the address SNDFLG. This also takes into consideration that the stored data may change due to the occurrence of a timer interrupt (FIG. 7) or an audio output interrupt (FIG. 14) during the processing of step ST94.
[0049]
Subsequently, address information and other information corresponding to the sound NO are acquired based on the reference table SNDBL of FIG. 5A and stored in the SNDSTR address, SNDEND address, SNDLOOP address, and SMPFRQ address of the work table SNDCTBL (ST96). ).
[0050]
The processes in steps ST92 to ST96 are performed for the control work tables SNDCTBL (for BGM) and SNDCTBL (for SE). The contents of the control work table SNDCTBL are updated during the execution of the main routine (mainly ST4). This is because the audio information output process (FIG. 14) is also progressing at every sampling period (τ).
[0051]
When the process of step ST6 is completed as described above, the inspection data set in the process of step ST3 is checked (ST7). Specifically, as shown in FIG. 16B, the n pieces of inspection data stored in the RAM area are stored in the ROM (AD1, AD2,..., ADn address as in the case of step ST1. First, it is determined whether or not all the stored data match.
[0052]
Here, when there is even one non-matching data, an infinite loop process is entered. In this case, it is preferable to enter the infinite loop process after setting the CPU to the interrupt acceptance disabled state (DI). This is because an abnormal sound may be emitted when the voice output interrupt process (FIG. 14) is started in this state as long as an abnormality is found in the inspection data.
[0053]
In any case, since the infinite loop process is entered, the clear pulse for the watchdog timer 12 is not supplied, and the CPU is eventually reset. After that, it is determined that the inspection data does not match, and the process proceeds to the RAM clear process (ST2).
[0054]
On the other hand, when the inspection data check process (ST7) is normally completed, a watchdog timer process is executed (ST8). The specific contents are as shown in FIG. 16 (c), and it is determined whether or not both the watchdog flags WDFLG1 and WDFLG2 are in the on state (S100, S101). If there is, after the flags WDFLG1 and WDFLG2 are returned to the off state (S102), a clear pulse is output to the watchdog timer 12 (S103).
[0055]
As shown in step ST27 of FIG. 7 and step STOUT12 of FIG. 14, the watchdog flags WDFLG1 and WDFLG2 are set to the ON state at the end of the interrupt processing. The process proceeds from step S102 to S103, and the watchdog timer 12 is cleared. However, if at least one of the interrupt processes is not executed, the watchdog process of step ST8 is finished without doing anything. Therefore, if any one of the interrupt processes is not executed for a predetermined time or longer, a CPU reset signal is output from the watchdog timer 12 to the CPU core 15.
[0056]
As described above, in this embodiment, since the main routine (FIG. 6) always checks whether or not the interrupt processing of FIGS. 7 and 14 is normally executed, the program runs away due to the influence of noise or the like. Even in such a case, the operation state of the sound control board can be quickly returned to the initial state, and abnormal sound is prevented from being generated from the speaker.
[0057]
When the watchdog process (ST5) is completed as described above, the command conversion process and the random number distribution process are performed on the condition that a new control command is received (ST9). If a new control command has been received, 5AH is stored in the COM WRT address (ST9). Here, the command conversion process is a RING that cyclically stores control commands from the main control board 1.　The BUFFER area (see the reception buffer in FIG. 15B) is checked, and if a new control command is detected, the control command is referred to the Fi command by referring to the conversion table as shown in FIG. It is processing to convert to. The random number distribution process is a process for changing the Fi command with reference to a lottery table as shown in FIG.
[0058]
In the random number distribution process, specifically, the Fi command is changed by the Fi command determined by the command conversion process and the random value RND. Here, the random value RND is, for example, 0 to 255 (= RND).　It is a numerical value up to MAX). Therefore, in the example of FIG. 1B, when the Fi command determined by the command conversion process is 11H, if 0 ≦ random number value RND ≦ 68 or 79 ≦ random number value RND ≦ 255, Fi command = 11H. However, if 69 ≦ random number value RND ≦ 78, the Fi command is changed to 83H.
[0059]
Next, the random value RND is updated (ST10). In this embodiment, the random number value RND is 0 to 255 (= RND).　MAX), it is updated by incrementing (+1) the random number value RND within the numerical range. Subsequently, the value of the sound NO write completion flag RCMDFLG is checked. If this flag RCMDFLG is not set, it is determined that there is no audio information to be newly output, and the process returns to step ST5 (ST11). The sound NO write completion flag RCMDFLG is set when the sound NO corresponding to the new control command is determined in the timer interrupt process (FIG. 7) (see ST58 in FIG. 9 (a)).
[0060]
Therefore, if it is confirmed in step ST11 that the sound NO write completion flag RCMDFLG is set, sound NO analysis processing is executed (ST12). Specifically, the sound NO written in the timer interrupt process (FIG. 7) is copied to the work area RCMD, and various information corresponding to the sound NO is stored in the corresponding column of the sound control work table SNDCTRL. Store (ST12).
[0061]
Further, in the sound NO analysis process (ST12), the validity of the sound NO is also determined. If it is determined that the sound is not valid, the process returns to step ST5. The process proceeds to the output activation process (ST14). Note that sound NO is not valid because multiple interrupt processes may be executed in multiple layers. In such a case, since the audio output activation process is skipped, abnormal audio information Is prevented from being output.
[0062]
If it is determined in step ST13 that the sound NO is valid, a series of sound data sampling periods (τ) corresponding to the extracted sound NO is specified as the sound output activation process, The internal interrupt signal CH0 is set to be output from the TPU 16 at every sampling period (τ) (ST14). Specifically, a predetermined value is set as an upper limit value in TGR (timer general register), TCNT is cleared to zero, then a count-up operation is started, and TIER (timer The interrupt enable register is turned on (see FIG. 19).
[0063]
Thereafter, the processing returns to step ST5. However, since the internal interrupt signal CH0 is set to be output from the TPU 16, thereafter, an internal interrupt is generated every sampling period (τ), corresponding to the specified sound NO. Audio data is output every sampling period (τ) (see FIG. 14). When a series of audio data output is completed by a plurality of CH0 interrupt processes (FIG. 14), silence processing is performed in the interrupt process of FIG. 14 (see the broken line portion in FIG. 14), and thereafter The silence is continuously output from the D / A converter 18. In the silence process, since the sampling frequency is set to 16 KHz, silence is output with a time period of 62.5 μS (= 1/16 KHz).
[0064]
These audio output processes will be confirmed with reference to FIG. When TCNT (timer counter), which has been cleared to zero in the process of step ST14, reaches the counter upper limit value and is cleared to zero, voice output CH0 interrupt processing (FIG. 14) is executed. After this interrupt processing is completed, TIER (timer interrupt enable register) is turned on again (ST5 in FIG. 19), and the count-up operation of TCNT (timer counter) is resumed (FIG. 19). 19 ST5). Therefore, the interruption of CH0 is repeatedly executed every sampling period (τ) specified by the sound NO.
[0065]
After a series of audio data is output in this manner, the sampling frequency is set to 16 KHz in the silence process of FIG. 14, and thereafter, 16 KHz until an audio effect corresponding to a new control command is started. The silence data of the sampling frequency is repeatedly output from the D / A converter 18.
[0066]
As described above, after the power is turned on, the processing from steps ST5 to ST14 is repeated in an infinite loop, but the timer interrupt processing shown in FIG. 7 is performed in parallel with such main routine processing. In timer interrupt processing, the BGM variable TIME that manages the playback time of the Si command　Variable TIME for BG and SE　It is decremented (-1) until SE becomes zero (ST20). Further, the BGM variable PT1 and SE variable PT2 which manage the reproduction time of the sound NO are decremented until they become zero (ST20). As described above with reference to FIG. 2, the playback time of the Si command and the sound NO is specified and extracted, but each variable TIME is used to realize the specified playback time.　BG, TIME　SE, PT1, and PT2 are decremented. Since the interrupt period of the timer interrupt is 4 mS, for example, 9400/4 = 2350 interrupt processes are required to realize a reproduction time of 9.4 seconds.
[0067]
Subsequently, work area COM　It is determined whether or not the value of WRT is 05H (ST21). As described in step ST6 of FIG. 6, when a new control command is acquired, the work area COM　05H is written in WRT. So work area COM　If WRT = 05H, after initializing the work area for the Fi command and the work area for the Si command (ST22), COM that is the command buffer area　The Fi command stored in the SND (not shown) is changed to the COM command storage area COM.　Store in NUM (ST23).
[0068]
The work areas for Fi command and Si command have the data structures shown in FIGS. 7B and 7C, and the work area for Fi command has a storage area COM.　A NUM is provided. In addition, the time variable TIME for the Si command which becomes a problem in step ST20.　BG, TIME　SE is provided in the work area for Fi command, and time variables PT1 and PT2 for sound NO are provided in the work area for Si command.
[0069]
When the process of step ST23 is completed, the Fi command storage area COM　Buffer area BUP by bit-inverting the contents of NUM　COM to indicate that the initial processing for the new control command has been completed while storing in NUM　Zero is stored in the WRT address (ST24). COM　WRT address = 0 (COM　If WRT ≠ 05H), the processing of steps ST22 to ST24 is skipped.
[0070]
Subsequently, Fi command expansion processing is performed (ST25). The details of the Fi command expansion process are as shown in FIG. 8.　Based on the Fi command stored in the NUM and the Si progress counter, the Si command to be executed is identified. The Si progress counter is the CNT in the Fi command work area.　BG and CNT　This is the value of SE, and for one Fi command, a BGM (background sound) Si command and an SE (notification sound) Si command are specified. The specified BGM (background sound) Si command and SE (notification sound) Si command are respectively the BGM area and the PT of the SE area in FIG.　Stored in NUM.
[0071]
As a result of the above processing, the Si command to be executed is specified, and then data expansion processing is performed for the Si command (ST26). The details of the Si command data development process are as shown in FIG. 9, but in a simplified manner, the Si command and the sound NO progress counter PT　Based on the CNT, the sound NO to be activated is identified. Here, the progress counter is the PT of the BGM area.　PT of CNT and SE area 2　This is the value of CNT, and the sound NO for BGM and SE is specified for one Fi command. Then, the two specified types of sound NO are stored in RCMDBF1 and RCMDBF2 shown in FIG.
[0072]
FIG. 8 is a flowchart showing specific contents of the Fi command expansion process (ST25 in FIG. 7). First, an error confirmation process (ST30) for the Fi command work area (see FIG. 7B) is executed. Specifically, (1) COM　NUM value and BUP　Comparison with NUM inverted value, (2) COM　Validity check of whether Fi command stored in NUM is within a predetermined numerical range, (3) CNT　BG value and BUP　Comparison with the inverted value of BG, (4) CNT　SE value and BUP　The comparison with the inverted value of SE is performed, and if any abnormality is detected, the work area for Fi command (FIG. 7B) is initialized and the process is terminated. As described above, in this embodiment, since abnormality determination is performed prior to the expansion process of the Fi command, abnormal voice information is not output.
[0073]
Next, the variable TIME　It is determined whether or not the value of BG has become zero (ST31). Variable TIME　BG manages the playback time of the BGM Si command, and is a variable that is decremented every 4 mS in step ST20 of FIG. Therefore, TIME　If BG = 0, the process proceeds to step ST32 in order to specify the Si command to be executed next. Specifically, COM　Of the group of Si commands corresponding to the storage data (Fi command) at the NUM address, the BGM progress counter CNT　Data Dx (Si command) corresponding to BG is acquired (ST32).
[0074]
Then, it is determined whether or not the Si command is the end code ENDCD (see FIG. 3) (ST33). If the Si command is not the end code ENDCD, the reproduction time of the Si command is set to the time variable TIME.　Set as the initial value of BG. Next, it is determined whether or not the data Dx acquired in step ST32 is a continuation code (ST35). If it is not a continuation code, the BGM work in the Si command work area (FIG. 7C) is determined. Area 1 is initialized (ST36). Specifically, the 4th address (PT) from the SEMIDT address shown in FIG.　TIME, PT　NUM, PT　CTH is stored with 00H, and the next 2 addresses (PT　NUM　BP, PT　CNT　0FFH is stored in (BP).
[0075]
Thereafter, the Si command (Dx) acquired in the process of step ST32 is used as the PT of the work area 1 for BGM.　In addition to storing in the NUM address, the inverted data of the Si command (Dx) is stored in the PT of the BGM work area 1　NUM　Store in the BP (ST37). And BGM progress counter CNT　BG value is incremented (+1) and BGM progress counter CNT　BUP the inverted data of BG　Store at address BG (ST38). The inversion data is stored so that the validity of the Si command to be executed from now on and the validity of the value of the BGM progress counter for specifying the sound NO can be checked when necessary.
[0076]
With the above processing, the processing for the BGM area in the Si command work area (FIG. 7C) is completed. The specific processing contents of steps ST39 to ST46 are substantially the same as the processing contents of steps ST31 to ST38 described above, and necessary data is stored in the SE area (6 addresses starting from SEMIDT + 6). SE progress counter CNT　The value of SE is also incremented (+1) (ST46).
[0077]
Next, the Si command data expansion process (ST26) of FIG. 7 will be described based on the flowchart shown in FIG. First, Si command error check processing is performed (ST50). Specifically, (1) PT in the BGM area shown in FIG.　NUM address data and PT　NUM　Contrast with inverted data of BP address, (2) PT　CNT address data and PT　CNT　Contrast with inverted data at address BP, and (3) PT in SE area　NUM address data and PT　NUM　Contrast with inverted data at address BP, (4) PT　CNT address data and PT　CNT　Processing such as comparison with the inverted data at the BP address is performed, and when an abnormality is detected, the BGM area and the SE area are initialized and the processing ends.
[0078]
Next, the register R3 is cleared to zero, and initial processing is performed for the BGM area in the Si command work area (FIG. 7B) (ST51). As a result, work for the BGM area is initially performed, and it is first determined whether or not the value of the time variable PT1 for managing the reproduction time of the BGM sound NO is zero (ST52). The time variable PT1 is set to an initial value in the process of step ST56 of FIG. 9A, and is decremented (−1) by the process of step ST20 of FIG. The case where PT1 = 0 is when it is time to finish executing the current sound NO and shift to the execution of the next sound NO.
[0079]
First, an instruction table PARTS as shown in FIG.　From the COM address list, the PT of the BGM area (FIG. 7C)　PARTS corresponding to Si command stored at NUM address　COMi address information is extracted (ST53). Next, the extracted PARTS　From the group of sound NO data stored in the COMi area (see FIG. 4B), the sound NO progress counter PT in FIG.　Sound NO data Dz corresponding to CNT is extracted (ST54).
[0080]
If the extracted data Dz is not the end code ENDCD, the reproduction time of the sound NO specified by the processing in step 54 is set as the PT of the BGM area in FIG.　Initial setting is made to the TIME address (ST56). If the data Dz is not a continuation code, the extracted sound NO (Dz) is stored in the work area RCMDBF1 shown in FIG. 7D, and the corresponding bit of the write completion flag RCMDFLG is set to 1. (ST58).
[0081]
Also, the sound NO progress counter PT in the BGM area 1 in FIG.　While incrementing the value of CNT, the inverted data is changed to PT　CNT　Store in the BP address (ST59). With the above processing, the processing for the BGM area 1 in FIG. 7C is completed. Next, the value of the register R3 that has been reset to zero in the processing of step ST51 is checked (ST70). After writing, initial processing is performed for the SE area (ST71), and the process returns to step ST52.
[0082]
As a result, the same work as the work for the BGM area described above is subsequently performed for the SR area 2. That is, if PT2 = 0, PARTS　From the group of sound NO data stored in the COMi area (see FIG. 4B), the sound NO progress counter PT in the SE area 1 in FIG.　Sound NO data Dz corresponding to CNT is extracted (ST54). Then, the reproduction time of the sound NO specified by the processing in step 54 is set as the PT of the SE area in FIG.　Initially set to the TIME address (ST56), the sound NO (Dz) is stored in the work area RCMDBF2 shown in FIG. 7D, and the corresponding bit of the write completion flag RCMDFLG is set to 1 (ST58). The process of step ST58 is as shown in detail in FIG. 9B, and FIG. 9C is a transcription of FIG. 7D.
[0083]
Next, the flowchart of FIG. 10 will be described. FIG. 10 shows the details of the sound NO analysis process (ST9) of FIG. In the sound NO analysis process, first, the corresponding bit of the sound NO write completion flag RCMDFLG shown in FIG. 9C is checked, and the sound NO is stored in the sound NO first buffer RCMDBF1 (see FIG. 9C). It is determined whether or not (ST70). If the determination result is Yes, the data of RCMDBF1, which is the reception buffer 1, is copied to the work area RCMD, and the corresponding bit of the sound NO write completion flag RCMDFLG is reset to indicate the work end (ST71).
[0084]
On the other hand, if the reception buffer 1 is determined to be empty by checking the sound NO write completion flag RCMDFLG, the corresponding bit of the sound NO write completion flag RCMDFLG is checked and the sound NO is stored in the sound NO second buffer RCMDBF2. It is determined whether it has been performed (ST72). If the determination result is Yes, the data of RCMDBF2, which is the reception buffer 2, is copied to the work area RCMD address, and the corresponding bit of the sound NO write completion flag RCMDFLG is reset to indicate the work end (ST72).
[0085]
The reason why the reception buffer 1 and the reception buffer 2 are checked in this way is that only one piece of audio information can be processed at a time. That is, the sound NO stored in the reception buffer 1 is stored in the RCMD address, and after the subsequent sound output activation (ST11), the processing of steps ST4 to ST8 is performed (the internal interrupt processing of CH0 is executed only once during this time). The sound corresponding to the reception buffer 1 may be output), and the sound NO stored in the reception buffer 2 is stored again at the RCMD address. If it is determined in step ST8 in FIG. 6 that “sound NO writing has been completed” but the determinations in steps ST70 and ST72 in FIG. 10 are both NO, the carry flag CY is set to 1. Set and finish the process (ST80).
[0086]
However, in a normal case, the sound NO stored in the reception buffer 1 or the reception buffer 2 is copied to the RCMD address (ST71, ST73). Next, the value of the sound NO is within a predetermined numerical range. It is determined whether or not it is (ST74). For example, if the sound NO is assigned to a numerical value range of 0 ≦ sound NO ≦ SNDmax, it is determined that a sound NO greater than SNDmax is an error, and the process proceeds to step ST80. Since such a determination process is provided, it is possible to prevent an abnormal sound from being output or a program from running away.
[0087]
If it is determined that the sound NO does not exceed the predetermined numerical range, the value of the sound NO is further checked, and if it is normal, the carry flag CY = 0 is set, and if it is abnormal, the carry flag CY = 1 is set (ST75). ). The sound NO check includes a process of referring to the reference table SNDTBL shown in FIG. 5, and if the content of the corresponding address in the reference table SNDTBL corresponding to the sound NO is zero, there is no ADPCM data. The carry flag CY = 1 is set as an abnormality.
[0088]
When the processing of step ST75 is completed, it is next determined whether or not the value of the sound NO is abnormal based on the value of the carry flag CY (ST76). If normal, the sampling frequency for reproducing the sound NO is acquired. (ST77). Specifically, as shown in FIG. 11A, a sound control work table SNDCTBL reserved for the background sound (BGM) and the sound effect (SE) (FIG. 11B, FIG. 13). Of which is used (ST80), and the sound NO is stored in the corresponding column of one of the work tables SNDCTBL (ST81). Of the sound control work tables SNDCTBL for background sound (BGM) and sound effect (SE), which should be used can be specified from the sound NO. That is, as shown in FIGS. 5B and 5C, it is possible to specify from sound NO whether it is related to BGM sound or SE sound (see BGM1 + 2 and SE1 + 2). ) Including the subsequent processing, one of the specified sound control work tables SNDCTBL is used.
[0089]
When the processing of step ST81 is completed, the position where the sound data (ADPCM data) corresponding to the sound NO is stored is specified, and information such as the start address and end address of the sound data is used for sound control from the header information. Store in the corresponding column of the work table SNDCTBL (ST82). Further, the sound flag (BGM / SE), the information on the presence / absence of repeated playback LOOP, and the sampling frequency are acquired from the header information of the audio data, and stored in the corresponding column of the sound control work table SNDCTBL (ST83). Finally, a data check process is performed (ST84). The process content is as described in the flowchart of FIG. 12, and is the same as the process related to step ST5 of FIG.
[0090]
FIG. 14 is a flow chart for explaining interrupt processing for audio output (CH0 internal interrupt of TPU 16). For example, when it is instructed to reproduce the audio data with the sampling frequency of 8 KHz by the process of step ST14 in FIG. 6, this CH0 interrupt process is executed every 125 μS, and the audio data with the sampling frequency of 16 KHz should be reproduced. In this case, the CH0 interrupt process is executed every 62.5 μS. Since this internal interrupt is an interruptable (maskable) interrupt, it is accepted on condition that the CPU is in the EI state (see ST5). In short, infinite loop processing (mainly ST5 to ST11) is performed. A cycle is a condition for execution.
[0091]
Based on the above, FIG. 14 will be described. Audio output interrupt (SND　In (INT), first, the contents of the SNDDATA address are output to the D / A converter 18 (STOUT1). In the SNDDATA address, the previous interrupt processing (SND　Since the PCM data (8-bit length) in which the SE sound and the BGM sound are mixed is stored by the process of step STOUT12 in (INT), the PCM data is output to the D / A converter 18. The D / A converter 18 converts the received PCM data into an analog signal and outputs it.
[0092]
Next, the content of the SNDFLG address (FIG. 13) for the background sound BGM is referred to (STOUT2). If the stored value of the address SNDFLG is 00H, the processing of steps STOUT3 to STOUT5 is skipped. On the other hand, if the value is other than 00H, the address value stored in the SNDADR address of the sound control (BGM) work table SNDCTBL is acquired to acquire the compressed audio data (ADPCM data) (STOUT3). The address value (data address during sound data conversion) stored in the SNDADR address is updated to the next address value (STOUT4). When the updated address value exceeds the final address value, silence processing including processing for storing 00H at the SNDFLG address is executed as indicated by the broken line portion.
[0093]
Next, the ADPCM data acquired in the process of step STOUT3 is converted into PCM data (background sound BGM) and temporarily stored (STOUT5). In this embodiment, since 8-bit PCM data is compressed into 4-bit ADPCM data, it is restored and temporarily stored.
[0094]
Since the background sound (BGM) has been restored by the above processing, next, the contents of the SNDFLG address (FIG. 13) for the sound effect SE are referred to (STOUT 6). If the stored value of the address SNDFLG is 00H, the background sound BGM and / or the sound effect SE is set as silence data and stored in the address SNDDATA, and then the process proceeds to step STOUT12 (STOUT11 '). That is, if the SNGMLG for BGM is 00H, the background sound BGM is silence data, and if the SNDFLG for SE is 00H, the sound effect SE is silence data. Therefore, in the next audio output interruption, only the background sound BGM, only the sound effect SE, or complete silence is output (see STOUT1).
[0095]
On the other hand, if the stored value of the SNDFLG address for the sound effect SE (FIG. 13) is a value other than 00H, the restoration process for the sound effect (SE) is performed. Specifically, the address value stored in the SNDADR of the work table SNDCTBL for sound control (SE) is acquired to acquire the compressed audio data (ADPCM data) (STOUT7), and the address stored in the SNDADR address. The value (data address during sound data conversion) is updated to the next address value (STOUT8).
[0096]
Then, when the updated address value exceeds the final address value, as shown by the broken line portion, a silence process including a process of storing 00H at the SNDFLG address is executed. After that, the ADPCM data acquired in the process of step STOUT7 is converted to PCM data (sound effect SE) (STOUT9), and then mixed with the temporarily stored background sound BGM (STOUT10). (STOUT11). This mixing sound is output to the D / A converter at the next audio interruption (see STOUT1).
[0097]
Finally, the flag value WDFLG2 of the work area is turned on to indicate that the voice output interrupt process is normally completed. Also, the TGF flag of the TPU 16 TSR (timer status register) is returned from the on state to the off state, and the interrupt process is completed (STOUT 12).
[0098]
Next, a reception interrupt for receiving a control command from the main control board 1 will be described with reference to FIG. As described above, the main control board 1 outputs the strobe signal STB together with the output of the control command, and the processing of FIG. 15 is started due to the reception of the strobe signal. Since this interrupt is also an interruptable (maskable) interrupt, it is accepted on the condition of one round of the main routine (mainly ST5 to ST11).
[0099]
In the reception interrupt, data is continuously received twice from the command input port 13, and it is first determined whether or not the two data match (identical check). This is because control command data that is garbled due to the influence of noise or the like is not received, and the process proceeds to the next reception process on condition that this identity check is OK for seven consecutive times. (STIN1, STIN2).
[0100]
If the determination in step STIN2 is Yes, then the control command received this time is compared with the control command received immediately before, and if they match, the process is terminated as it is (STIN3). This is because the same control command cannot be continuously output from the main control board 1, so that it is determined that there is some malfunction and the received control command is discarded.
[0101]
On the other hand, if the newly received control command is different from the control command received immediately before, the write pointer WR　A control command is stored at the address indicated by POINT (STIN4). The write pointer WR　The value of POINT is updated (STIN5). As shown in FIG. 15B, the reception buffer for storing the control command has a ring buffer structure, and has a write pointer WR.　The value of POINT is updated cyclically. The control command stored in the reception buffer is read out in the process of step ST6 in FIG. Read pointer RD when reading　POINT is used, and this read pointer RD　POINT is also used by being updated cyclically.
[0102]
Finally, a bullet ball game machine to which the present invention is preferably applied will be described for confirmation. FIG. 20 is a perspective view showing the pachinko machine 22 of the present embodiment, and FIG. 21 is a side view of the pachinko machine 22. A plurality of pachinko machines 21 are arranged in the length direction of the island structure of the pachinko hall while being electrically connected to the card-type ball lending machine 22.
[0103]
The illustrated pachinko machine 21 includes a rectangular frame-shaped wooden outer frame 23 that is detachably mounted on an island structure, and a front frame 24 that is pivotably mounted via a hinge H fixed to the outer frame 23. It consists of A game board 25 is detachably attached to the front frame 24 from the back side, and a glass door 26 and a front plate 27 are pivotally attached to the front side so as to be freely opened and closed.
[0104]
The front plate 27 is provided with an upper plate 28 for storing game balls for launch. A lower plate 29 for storing game balls overflowing from or extracted from the upper plate 28 and a launch handle 30 are disposed below the front frame 24. And are provided. The launch handle 30 is interlocked with the launch motor, and a game ball is launched by a striking rod 31 (see FIG. 23) that operates according to the rotation angle of the launch handle.
[0105]
On the right side of the upper plate 28, an operation panel 32 for lending the ball to the card-type ball lending machine 22 is provided. On the operation panel 32, a card remaining amount display unit 32a for displaying the remaining amount of the card with a three-digit number. A ball lending switch 32b for instructing lending of game balls for a predetermined amount, and a return switch 32c for instructing to return the card at the end of the game. On the upper part of the glass door 26, a big hit LED lamp P1 indicating a big hit state is arranged. In addition, in the vicinity of the big hit LED lamp P1, abnormality notification LED lamps P2 and P3 are provided to indicate a replenishment state or a full state of the lower plate.
[0106]
As shown in FIG. 22, the game board 25 is provided with a guide rail 33 formed of a metal outer rail and an inner rail in an annular shape, and the liquid crystal color display 8 is provided at the approximate center of the game area 25a inside. Has been placed. In addition, at a suitable place in the game area 25a, a symbol start opening 35, a big winning opening 36, a plurality of normal winning openings 37 (four on the right and left of the big winning opening 36), and a gate 38 which is two passage openings are arranged. Has been. Each of these winning openings 35 to 38 has a detection switch inside, and can detect the passage of a game ball.
[0107]
The liquid crystal display 8 is a device that variably displays a specific symbol related to the big hit state, and displays a background image, various characters, and the like in an animated manner. This liquid crystal display 8 has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 39 in the upper right portion. The normal symbol display unit 39 displays a normal symbol. When a game ball that has passed through the gate 38 is detected, the displayed normal symbol fluctuates for a predetermined time, and a lottery is drawn when the game ball passes through the gate 38. The stop symbol determined by the random number for lottery is displayed and stopped.
[0108]
The symbol start opening 35 is opened and closed by an electric tulip having a pair of left and right opening and closing claws 35a, and when the stop symbol after the fluctuation of the normal symbol display unit 39 hits and the symbol is displayed, the opening and closing claw 35a is kept at a predetermined time. Only to be released. When a game ball wins the symbol start opening 35, the display symbols of the special symbol display portions Da to Dc change for a predetermined time, and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start opening 35. Stop at the stop symbol pattern.
[0109]
The special winning opening 36 is controlled to be opened and closed by an opening / closing plate 36a that can be opened forward. When the stop symbol after the symbol variation of the special symbol display portions Da to Dc is a winning symbol such as “777”, “big hit” is obtained. A special game is started and the opening / closing plate 36a is opened. There is a specific area 36b inside the big winning opening 36, and when the winning ball passes through the specific area 36b, a special game advantageous to the player is continued.
[0110]
After the opening / closing plate 36a of the big winning opening 36 is opened, the opening / closing plate 36a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. At this time, if the game ball does not pass through the specific area 36b, the special game ends. However, if the game ball passes through the specific area 36b, the special game is continued up to, for example, 15 times, which is advantageous to the player. To be controlled. Furthermore, when the stop symbol after the change is a certain symbol of the special symbols (hereinafter referred to as a specific symbol), a privilege of shifting to a high probability state is given after the special game ends.
[0111]
As shown in FIG. 23, on the back side of the front frame 24, a back mechanism plate 40 for holding the game board 25 from the back side is detachably mounted. An opening 40a is formed in the back mechanism plate 40, and a prize ball tank 41 and a tank rail 42 extending therefrom are provided on the upper side thereof. A payout device 43 connected to the tank rail 42 is provided on the side of the back mechanism plate 40, and a passage unit 44 connected to the payout device 43 is provided below the back mechanism plate 40. The game balls paid out from the payout device 43 are paid out to the upper plate 28 from the upper plate discharge port 28a (FIG. 20) via the passage unit 44.
[0112]
The opening 40a of the back mechanism plate 40 is fitted with a back cover 45 mounted on the back side of the game board 25 and a winning ball discharge basket (not shown) for discharging the game balls won in the winning holes 35 to 37. Has been. The main control board 1 is disposed inside the case CA1 attached to the back cover 45, and the symbol control board 2 is disposed on the front side thereof (see FIG. 21). Below the main control board 1, the lamp control board 4 is provided in the case CA2 attached to the back cover 45, and the sound control board 3 is provided in the adjacent case CA3.
[0113]
Below these cases CA2 and CA3, a power supply board 6 and a payout control board 5 are provided in a case CA4 mounted on the back mechanism plate 40. A power switch 53 and an initialization switch 54 are disposed on the power board 6. The parts corresponding to both the switches 53 and 54 are notched, and both switches can be operated simultaneously with a finger. A launch control board 7 is provided inside the case CA5 attached to the rear side of the launch handle 30. And these circuit boards 1-7 are each comprised independently, The computer circuit provided with the one-chip microcomputer is mounted in the control boards 2-6 except the power supply board 6 and the launch control board 7. FIG.
[0114]
As mentioned above, although one Example of this invention was described concretely, the game machine of this invention can be suitably changed not only in the structure of each above-mentioned Example. For example, in the above embodiment, the main control board and the plurality of sub-control boards are configured as different board configurations, and the control command from the main control board is transmitted by one-way communication. For example, the configuration of FIG. Any combination configuration is possible. In FIG. 24, an arrow indicates a transmission direction of a signal such as a control command. For example, an acknowledgment signal (ACK) may be returned as shown in FIG. Further, it is not necessary to configure the voice control board as an independent circuit board, and it may be a composite board with another control unit as shown in FIGS.
[0115]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a gaming machine with a complete noise countermeasure that virtually eliminates the influence of noise and the like.
[Brief description of the drawings]
FIG. 1 is a conversion table (a) for obtaining Fi commands and a lottery table (b) for Fi commands.
FIG. 2 is a diagram for explaining a relationship between a Fi command, a Si command, and a sound NO.
FIG. 3 illustrates a method for specifying a Si command from a Fi command.
FIG. 4 illustrates a method for identifying a sound NO from an Si command.
FIG. 5 illustrates a method (a) for specifying sound data from a sound NO and a data structure (b) of the sound data.
FIG. 6 is a flowchart illustrating a main routine.
FIG. 7 is a flowchart (a) illustrating a timer interrupt routine and a work area thereof.
FIG. 8 is a flowchart illustrating a part of a timer interrupt routine in detail.
FIG. 9 is a flowchart illustrating a part of a timer interrupt routine in detail.
FIG. 10 is a flowchart illustrating a part of the main routine in detail.
FIG. 11 is a flowchart illustrating a part of FIG. 10 in detail.
FIG. 12 is a flowchart illustrating a part of the main routine in detail.
FIG. 13 illustrates a work table SNDCTBL for sound control.
FIG. 14 is a flowchart illustrating an interrupt process for audio output.
FIG. 15 is a flowchart illustrating interrupt processing for receiving a control command.
FIG. 16 is a flowchart illustrating a part of FIG. 6 in detail.
FIG. 17 is a block diagram illustrating an overall configuration of a pachinko machine according to an embodiment.
FIG. 18 is a block diagram illustrating a configuration of an audio control board.
FIG. 19 is a schematic flowchart illustrating an internal interrupt of CH0.
FIG. 20 is a perspective view of a pachinko machine according to an embodiment.
21 is a side view of the pachinko machine shown in FIG.
22 is a front view of the pachinko machine shown in FIG.
FIG. 23 is a rear view of the pachinko machine shown in FIG. 20;
FIG. 24 illustrates a modified example of the substrate configuration.
[Explanation of symbols]
ST1-14 Main processing part
ST20-27 Interrupt processing unit (timer interrupt)
STOUT1-12 Interrupt processing unit (audio output interrupt)
WDT reset section (watchdog timer)
S102-103 Reset prohibition means
1. Main control unit (main control board)
3. Voice control unit (voice control board)
21 game machines (pachinko machines)

Claims (8)

A main processing unit that is executed in an infinite loop, one or more interrupt processing units that are started by interrupting other processes being executed, and a control operation that is forced according to the results of its own timing operation A gaming machine comprising a reset unit for returning to an initial state, and provided with a reset prohibiting means for returning the timing operation of the reset unit to an initial state on condition that the operation of the interrupt processing unit is executed . The two or more types of the interrupt processing units are provided, and the reset prohibiting unit returns the timing operation of the reset unit to the initial state on condition that the operations of a plurality of interrupt processing units are executed. Game machines. A determination means for repeatedly determining the validity of the inspection data stored in the predetermined area in advance,
3. The gaming machine according to claim 1, wherein an avoidance unit that avoids the operation of the reset prohibiting unit is provided in the main processing unit when it is determined that the determination unit is not valid. The main control part which mainly controls game operation | movement and the sub control part which implement | achieves individual operation | movement based on the control command from the said main control part are comprised in any one of Claims 1-3. Game machines. A main control unit that mainly controls game operations and a plurality of sub-control units that realize individual operations based on control commands from the main control unit, the main processing unit, the interrupt processing unit The game machine according to any one of claims 1 to 4, wherein the reset unit is provided in all or a part of the main control unit and the sub control unit. In a gaming machine including a main control unit that mainly controls gaming operations and a voice control unit that realizes voice production based on a control command from the main control unit, the voice control unit is executed in an infinite loop shape Main processing, and interrupt processing for outputting an audio signal by interrupting other processing being executed,
The gaming machine according to claim 1, wherein the interruption process is constantly started regardless of the presence or absence of an audio signal to be output. The function of claim 6, wherein the interrupt processing functions to output a sound signal corresponding to the received control command, and to continue outputting a silence signal to the sound circuit after finishing outputting the sound signal. Gaming machine. A main processing unit that is executed in an infinite loop, and an interrupt processing unit that interrupts the other processing being executed and executes an audio output process for one unit,
The gaming machine according to claim 6 or 7, wherein when the clock timer reaches a predetermined upper limit value, the clock timer is reset to an initial value and the interrupt process is started.

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