JP2004040270A - High speed pixel correction processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high speed pixel correction processing apparatus meticulously performing pixel correction processing depending on the number of pixels in following to high speed tendency of a recording speed of an image. <P>SOLUTION: A pattern detection circuit 1 receives an image signal a and outputs a plurality of image signals detected in response to the number of pixels and an image signal b. A minimum pixel ensuring circuit 2 outputs an image signal e wherein only a pixel of image data comprising one pixel is corrected. A selection circuit 3 selects the image signal b or the image signal e. A white pixel correction circuit 4 composes an image signal whose pixels are corrected in response to two pixels or more with an output image signal g of the selection circuit 3 and outputs an image signal h whose pixels of only white pixel data are corrected. A selection circuit 5 selects the output image signal g or the image signal h. A black pixel correction circuit 6 composes an image signal whose pixels are corrected in response to two pixels or more with an output image signal j of the selection circuit 5 and outputs an image signal k whose pixels of only black pixel data are corrected. A selection circuit 7 selects the output image signal j or the image signal k. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a high-speed pixel correction processing device, and more particularly to a high-speed pixel correction processing device that individually performs pixel correction for each pixel number.
[0002]
[Prior art]
2. Description of the Related Art Recently, binarized white and black image signals are not only displayed on a screen, but also recorded on a printing paper such as a film or a newspaper or a magazine.
[0003]
In general, a pixel correction process is performed to improve the recording quality of such an image.
[0004]
FIG. 12 is a block diagram showing an image recording apparatus using a conventional high-speed pixel correction processing apparatus.
[0005]
The operation of the image recording apparatus in FIG. 12 will be described. The communication control unit 101 performs interface control with an external device (not shown) and mainly receives image data. The image memory control unit 102 performs control for transferring and storing the image data received by the communication control unit 101 to the image memory 103. The image memory 103 stores image data.
[0006]
The margin character generation unit 104 generates image data of a date, a title, and other information. The image selection unit 105 selects the image data of the margin character generation unit 104 and the image data of the image memory control unit 102.
[0007]
The speed conversion control unit 106 has a built-in memory for two lines, reads and writes the image data selected by the image selection unit 105 line by line, and reverses the read address to the write address. It can be read out as image data of an inverted image.
[0008]
The parallel / serial conversion unit 107 converts the image data processed in parallel by the speed conversion control unit 106 into serial image data.
[0009]
A pixel correction processing unit 108 performs a pixel correction process on the serial image data and outputs the data for recording on a film.
[0010]
The CPU control unit 109 performs management control of the entire image recording apparatus.
[0011]
Now, in an image recording apparatus such as a plotter, image signal processing is performed by the configuration shown in FIG. 12 to record on a film. In the course of image processing, there is a case where an image cannot be logically reproduced due to the influence of film characteristics, LED switching characteristics, and the like. In order to reproduce this, the pixel correction processing unit 108 performs pixel correction.
[0012]
Generally, in an image recording apparatus, even if pixel correction of an image is uniformly performed with the same correction amount, recording can be performed on a film without any problem. However, as the recording processing speed of the recording apparatus increases, the influence of the LED switching characteristics and the film characteristics appears remarkably, and there is a problem that the expected recording cannot be performed with uniform pixel correction. In particular, the reproducibility of an image becomes worse as the number of pixels is smaller.
[0013]
FIG. 13 is a waveform diagram showing the effects of film characteristics and LED switching characteristics on a conventional image signal.
[0014]
FIG. 13A is a diagram showing a waveform of an image signal, FIG. 13B is a diagram showing a waveform after influence of film characteristics, and FIG. 13C is a diagram showing a waveform after influence of LED switching characteristics.
[0015]
Next, description will be made with reference to FIG.
[0016]
Generally, unless the power value of the image signal level is equal to or more than a certain value (here, α), it is impossible to record on a film. The waveform in FIG. 13B has a peak due to the film characteristics, and the range of the waveform width required for recording that is equal to or more than the power value α is narrower than the waveform width in FIG. In the waveform of FIG. 13C, the range of the peak of the waveform changes depending on the speed of the recording motor of the recording apparatus. As the speed of the recording motor increases, the range of the waveform width equal to or more than the power value α required for recording becomes narrower. .
[0017]
FIG. 13 illustrates the case where the image signal waveform is one pixel and two pixels. As is clear from the figure, the waveform of one pixel having a smaller number of pixels as compared with the waveform of two pixels has a film or LED switching characteristic. It can be understood that the effect of the above appears more remarkably, and the waveform width becomes narrower. For these reasons, uniform pixel correction degrades the reproducibility of an image, so it is necessary to perform finer pixel correction in units of pixels.
[0018]
As an example of such a pixel correction technique, an "image processing circuit" described in JP-A-3-22754 and a "pixel ratio measuring device" described in Utility Model Registration No. 2530947 are known.
[0019]
JP-A-3-22754 describes a technique for correcting a pixel by changing the data length of a white pixel or a black pixel of image data within a range of one dot in the image data using a basic clock as a minimum unit. .
[0020]
Further, in Utility Model Registration No. 2530947, the pulse width of a pixel signal is extended and corrected by a minimum of 10 [mm] units using a mono-multi or a logic gate with respect to an input image signal. And a circuit technique for correcting pixels.
[0021]
[Problems to be solved by the invention]
The conventional high-speed pixel correction processing apparatus described above has a drawback in that as the recording processing speed of the image recording apparatus increases, the effects of the LED switching characteristics and the film characteristics become remarkable, and the expected image cannot be recorded with uniform pixel correction. are doing.
[0022]
In addition, since the influence of the LED switching characteristics and the film characteristics becomes more conspicuous as the number of pixels to be corrected is smaller, uniform pixel correction has a disadvantage that image reproducibility is deteriorated.
[0023]
An object of the present invention is to set an arbitrary pixel according to the number of pixels of one pixel, two pixels, three pixels,..., N pixels (n: an arbitrary integer) so that pixel correction can be performed following an increase in image recording speed. The amount of delay can be set individually within the range, and fine pixel correction processing is performed, and even if the recording density is increased and the effects of film characteristics and LED switching characteristics are increased, the effects of these characteristics are sufficiently corrected, An object of the present invention is to provide a high-speed pixel correction processing device capable of obtaining a theoretical pixel width.
[0024]
[Means for Solving the Problems]
A first high-speed pixel correction processing device of the present invention is a pixel correction processing device used for image recording,
A white image signal and a black image signal of one pixel, a white image signal corresponding to each pixel number of two pixels, three pixels,... N (n: an arbitrary integer) pixels, and two pixels, three pixels. It includes three-stage processing means for a black image signal corresponding to each pixel number, and delays the white image signal and the black image signal pixel signal by individually selecting an arbitrary integer delay amount for each pixel. And performing pixel correction by means for increasing the waveform pulse width of the pixel signal.
[0025]
A second high-speed pixel correction processing device according to the present invention includes:
One pixel isolated white image signal, one pixel isolated black image signal, two pixel isolated white image signal, two pixel isolated black image signal, three pixel isolated white image signal, three pixel isolated with respect to the input image signal A pattern generation circuit for detecting an n-pixel isolated white image signal and an n-pixel isolated black image signal and outputting these image signals for each pixel;
A minimum pixel securing circuit that performs pixel correction on the one-pixel-isolated white image signal and the one-pixel-isolated black image signal in a range of one pixel;
A first selection circuit for selecting the input image signal and the output image signal of the minimum pixel securing circuit;
A white pixel correction circuit that performs pixel correction on a pixel-by-pixel basis for the two-pixel isolated white image signal to the n-pixel isolated white image signal, and combines the white image signal with the output image signal of the first selection circuit;
A second selection circuit for selecting an output image signal of the first selection circuit and an output image signal of the white pixel correction circuit;
A black pixel correction circuit that performs pixel correction for the two-pixel isolated black image signal to the n-pixel isolated black image signal on a pixel-by-pixel basis and combines the pixel image with the output image signal of the second selection circuit;
A third selection circuit for selecting an output image signal of the second selection circuit and an output image signal of the black pixel correction circuit;
It is characterized by having.
[0026]
A third high-speed pixel correction processing device according to the present invention includes:
A pattern detection circuit that receives the image signal a and outputs a plurality of white image signals, a plurality of black image signals, and an image signal b detected according to the number of pixels 1 to n;
A minimum pixel securing circuit for outputting an image signal e in which only one pixel of image data is pixel corrected;
A first selection circuit for selecting the image signal b and the image signal e;
An image signal corrected by white pixel correction according to each of 2 pixels to n pixels and an image signal g output by the first selection circuit are combined to form an image signal h in which only white pixel data is pixel corrected. An output white pixel correction circuit;
A second selection circuit for selecting the image signal g output from the first selection circuit and the image signal h output from the white pixel correction circuit;
By combining the image signal that has been subjected to black pixel correction in accordance with each of the two to n pixels with the image signal j that is output from the second selection circuit, an image signal k that has been subjected to pixel correction for only black pixel data is obtained. A black pixel correction circuit to output;
A third selection circuit that selects the image signal j output by the second selection circuit and the image signal k output by the black pixel correction circuit, and outputs the selected signal as an image signal m;
It is characterized by having.
[0027]
A fourth high-speed pixel correction processing device according to the present invention is the third high-speed pixel correction processing device,
The pattern detection circuit,
From the image signal a input to the input terminal, the image signal b, the one-pixel isolated white image signal c1, the one-pixel isolated black image signal d1, the two-pixel isolated white image signal c2, and the two-pixel isolated black image signal d2, three-pixel isolated white image signal c3, three-pixel isolated black image signal d3,..., n-pixel isolated white image signal cn, and n-pixel isolated black image signal dn. And output.
[0028]
The fifth high-speed pixel correction processing device of the present invention is the third or fifth high-speed pixel correction processing device,
The minimum pixel securing circuit,
Pixel correction processing is individually performed on the one-pixel-isolated white image signal c1 and the one-pixel-isolated black image signal d1, and the image signal subjected to these two correction processing and the image signal b are combined. In this case, the image signal e obtained by correcting only one pixel is output.
[0029]
A sixth high-speed pixel correction processing apparatus according to the present invention is the high-speed pixel correction processing apparatus according to any of the third to fifth aspects,
The first selection circuit includes:
One of the image signal b and the image signal e is selected by a first selection signal, and the image signal g is output.
[0030]
A seventh high-speed pixel correction processing apparatus according to the present invention is the high-speed pixel correction processing apparatus according to any of the third to sixth high-speed pixel correction processing apparatuses,
The white pixel correction circuit includes:
Pixel correction processing is individually performed on the two-pixel isolated white image signal c2, the three-pixel isolated white image signal c3,..., And the n-pixel isolated white image signal cn, which are output image signals of the pattern detection circuit. And outputting the image signal h pixel-corrected with respect to white image data by combining the image signal g corrected by the white pixel and the image signal g output by the first selection circuit. It is characterized by.
[0031]
An eighth high-speed pixel correction processing device according to the present invention, in any one of the third to seventh high-speed pixel correction processing devices,
The second selection circuit includes:
One of the image signal g and the image signal h output from the white pixel correction circuit is selected by a second selection signal, and the image signal j is output.
[0032]
According to a ninth high-speed pixel correction processing device of the present invention, in any one of the third to eighth high-speed pixel correction processing devices,
The black pixel correction circuit,
Pixel correction processing is individually performed on the two-pixel isolated black image signal d2, the three-pixel isolated black image signal d3,..., And the n-pixel isolated black image signal dn, which are output image signals of the pattern detection circuit. And synthesizing these black pixel corrected image signals and the image signal j output by the second selection circuit to output the image signal k pixel corrected for black image data. Features.
[0033]
According to a tenth high-speed pixel correction processing device of the present invention, in any of the third to ninth high-speed pixel correction processing devices,
The third selection circuit includes:
One of the image signal j and the image signal k output from the black pixel correction circuit is selected by a third selection signal, and the selected signal is output to an output terminal as the image signal m.
[0034]
According to an eleventh high-speed pixel correction processing device of the present invention, in the fourth high-speed pixel correction processing device,
The pattern detection circuit,
It has a single shift register, a plurality of AND gates, a plurality of OR gates, and a plurality of pixel generation counters. The detection signals p1 to pn and q1 to qn are generated for each pixel by these circuit elements. By outputting to the plurality of corresponding pixel generation counters and processing the same, the one-pixel isolated white image signal c1, the one-pixel isolated black image signal d1, the two-pixel isolated white image signal c2, The two-pixel isolated black image signal d2, the three-pixel isolated white image signal c3, the three-pixel isolated black image signal d3,..., The n-pixel isolated white image signal cn, and the n-pixel isolated black image signal dn is generated.
[0035]
According to a twelfth high-speed pixel correction processing device of the present invention, in the fifth high-speed pixel correction processing device,
The minimum pixel securing circuit,
A first delay line and a second delay line, an AND gate, an OR gate,
The first delay line sets an amount of pixel correction in the input one-pixel-isolated white image signal c1 with a delay amount in an arbitrary range according to a setting signal r1, and outputs a pixel-corrected image signal t1. And, by taking the logical product of the image signal b and the image signal t1 by the logical product gate, an image signal v which is pixel-corrected only for the data of one pixel of white is generated,
The second delay line sets an amount of pixel correction in the input one-pixel-isolated black image signal d1 with a delay amount in an arbitrary range by a setting signal s1, and outputs a pixel-corrected image signal u1. The image signal v and the image signal u1 are ORed by the OR gate to generate an image signal e in which pixel correction is performed only for one white pixel and one black pixel. .
[0036]
According to a thirteenth high-speed pixel correction processing device of the present invention, in the seventh high-speed pixel correction processing device,
The white pixel correction circuit includes:
A plurality of (2-n) delay lines and a logical product gate;
The image signals c2, c3,... Cn of the two white isolated pixels, the three white isolated pixels,..., The n isolated white pixels are respectively input to each of the plurality of delay lines, and a plurality of settings are made. By setting the amount of pixel correction by the signals r2, r3,... Rn individually for each pixel with an arbitrary range of delay amount, the pixel-corrected image signals t2, t3,. .., Tn and the image signal g are ANDed by the AND gate, whereby the image signal h, which has been subjected to pixel correction according to the number of pixels of white image data, is obtained. It is characterized by generating.
[0037]
According to a fourteenth high-speed pixel correction processing device of the present invention, in the ninth high-speed pixel correction processing device,
The black pixel correction circuit,
A plurality of (2 to n) delay lines and an OR gate;
The image signals d2, d3,..., Dn of the black isolated two pixels, the black isolated three pixels,. By individually setting the amount of pixel correction based on the signals s2, s3,..., Sn with an arbitrary range of delay amount, pixel-corrected image signals u2, u3,. .., Un and the image signal j are ORed by the OR gate, whereby the image signal k corrected for pixels in accordance with the number of pixels of the black image data is obtained. Is generated.
[0038]
According to a fifteenth high-speed pixel correction processing device of the present invention, in any one of the first to fourteenth high-speed pixel correction processing devices,
A high-speed pixel correction processing device is applied to an image recording system.
[0039]
According to a sixteenth high-speed pixel correction processing device of the present invention, in any one of the first to fourteenth high-speed pixel correction processing devices,
It is characterized by a pixel correction processing method in which the high-speed pixel correction processing method is applied to image recording.
[0040]
According to a seventeenth high-speed pixel correction processing device of the present invention, in any one of the second to fourteenth high-speed pixel correction processing devices,
It is characterized in that each circuit included in the high-speed pixel correction processing device is formed into a gate array.
[0041]
According to an eighteenth high-speed pixel correction processing device of the present invention, in the second or third high-speed pixel correction processing device,
The minimum pixel securing circuit and the first selection circuit are removed, the one-pixel isolated white image signal is directly input to the white pixel correction circuit, and the one-pixel isolated black image signal is input to the black pixel correction circuit. It is characterized by direct input.
[0042]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0043]
FIG. 1 is a block diagram showing one embodiment of the high-speed pixel correction processing device of the present invention.
[0044]
In the present embodiment shown in FIG. 1, a pattern detection circuit 1 that inputs an image signal a and outputs a plurality of image signals and image signals b detected according to the number of pixels, and performs pixel correction for only one pixel of image data A minimum pixel securing circuit 2 for outputting the image signal e, a selecting circuit 3 for selecting the image signal b and the image signal e, and an image signal corrected for white pixels corresponding to two or more pixels, and a selecting circuit 3 A white pixel correction circuit 4 that synthesizes the image signal g output by the pixel signal and outputs an image signal h in which only the white pixel data is pixel-corrected, and the image signal g output by the selection circuit 3 and the white pixel correction circuit 4 output A selection circuit 5 for selecting an image signal h, an image signal corrected for black pixels according to each of two or more pixels, and an image signal j output from the selection circuit 5 are combined to correct only the black pixel data. Output image signal k A black pixel correcting circuit 6, selects an image signal k output by the image signal j and the black pixel correction circuit 6 outputs the selection circuit 5, and a selection circuit 7 for outputting an image signal m.
[0045]
Next, the operation of the present embodiment will be described in more detail with reference to FIG.
[0046]
The pattern detection circuit 1 converts an image signal a input to the input terminal {circle around (1)} from an image signal b, a white image signal c1, an isolated black image signal d1, a two-pixel isolated white image signal c2, A black image signal d2 of two pixels isolated, a white image signal c3 of three pixels isolated, a black image signal d3 of three pixels isolated,..., A white image signal cn of n pixels isolated (n is an arbitrary integer) and n pixels isolated An isolated image signal is detected and output for each pixel of the black image signal dn.
[0047]
The minimum pixel securing circuit 2 individually performs a pixel correction process on the one-pixel isolated white image signal c1 and the one-pixel isolated black image signal d1, and outputs the image signal and the image signal b that have been subjected to these two correction processes. To output an image signal e in which only one pixel is pixel-corrected.
[0048]
The selection circuit 3 selects one of the image signal b and the image signal e by the selection signal 8 and outputs the image signal g. The selection circuit 3 increases the options of the user and increases the variations.
[0049]
The white pixel correction circuit 4 separates the two-pixel isolated white image signal c2 which is the output image signal of the pattern detection circuit 1, the three-pixel isolated white image signal c3,. The pixel signal is subjected to a pixel correction process, and the image signal h subjected to the pixel correction with respect to the white image data is output by synthesizing the image signal subjected to the white pixel correction and the image signal g output from the selection circuit 3.
[0050]
The selection circuit 5 selects one of the image signal g and the image signal h output from the white pixel correction circuit 4 by the selection signal 9 and outputs the image signal j.
[0051]
The black pixel correction circuit 6 separates the two-pixel isolated black image signal d2, the three-pixel isolated black image signal d3,... The n-pixel isolated black image signal dn, which is the output image signal of the pattern detection circuit 1. A pixel correction process is performed on the black image data, and the image signal corrected by the black pixel and the image signal j output by the selection circuit 5 are combined to output an image signal k obtained by performing a pixel correction on the black image data.
[0052]
The selection circuit 7 selects either the image signal j or the image signal k output from the black pixel correction circuit 6 by the selection signal 10 and outputs the selected signal as the image signal m to the output terminal (2).
[0053]
FIG. 2 is a time chart showing the operation of the high-speed pixel correction processing device of FIG.
[0054]
In FIG. 2, the time chart of each code corresponds to each image signal in FIG.
[0055]
Referring to FIG. 2, the image signal a input to the pattern detection circuit 1 and the one-pixel isolated white image signal c1 output from the pattern detection circuit 1, the one-pixel isolated black image signal d1, and the two-pixel isolated white Image signal c2, 2-pixel isolated black image signal d2, 3-pixel isolated white image signal c3, 3-pixel isolated black image signal d3,..., N-pixel isolated white image signal cn, n-pixel isolated black image An isolated image signal is shown for each pixel of the signal dn.
[0056]
White image signals c1, c2, c3, and cn are H (High) level → L (Low) level → H (High) level pulse signals, and black image signals d1, d2, d3, and dn are L (Low) level → H This is a pulse signal of (High) level → L (Low) level.
[0057]
The image signal e is subjected to pixel correction separately for the one-pixel-isolated white image signal c1 and the one-pixel-isolated black image signal d1 by the minimum pixel securing circuit 2 in FIG. As shown in FIG. 2, the white pixel correction of Δc1 is performed on the white image signal c1 of one pixel isolation, and the black pixel correction of Δp1 is performed on the black image signal d1 of one pixel isolation, as shown in FIG. ing.
[0058]
The image signal g is the same as the image signal e selected by the selection circuit 3.
[0059]
The image signal h is an image signal obtained by individually correcting the pixels of the white image signals c2, c3,..., Cn by the white image correction circuit 4 and synthesizing them with the image signal g, as shown in FIG. The white pixel correction of Δc2, Δc3, and Δcn is performed for the pixel isolated white image signal c2, the three-pixel isolated white image signal c3, and the n-pixel isolated white image signal cn.
[0060]
The image signal j is the same as the image signal h selected by the selection circuit 5.
[0061]
The image signal k is an image signal obtained by individually correcting the image signals d2, d3,... Dn by the black pixel correction circuit 6 and synthesizing with the image signal j. As shown in FIG. Black pixel correction of Δp2, Δp3, and Δpn is performed on the black image signal d2, the black image signal d3 of 3 pixels isolated, and the black image signal dn of n pixels isolated.
[0062]
As the image signal m, the image signal k selected by the selection circuit 7 is output to the output terminal (2).
[0063]
3 and 4 for the pattern detection circuit 1, FIGS. 5 and 6 for the minimum pixel securing circuit 2, FIGS. 7 and 8 for the white pixel correction circuit 4 and FIGS. The details of each operation will be described with reference to FIG.
[0064]
FIG. 3 is a detailed block diagram showing the configuration of the pattern detection circuit of FIG.
[0065]
The operation of the pattern detection circuit 1 will be described with reference to FIG.
[0066]
The shift register circuit 11 shifts the image signal a input from the input terminal {circle around (1)} shown in FIG. 1 by the internally generated image signal clock 28, thereby shifting the shifted image signals b, n1, n2, n3,. , Nn, n + 1, nn + 2 are output.
[0067]
Here, the reason why the image signal b is output from the shift register circuit 11 is to synchronize the timing of the image signals c1 to cn and d1 to dn for each pixel.
[0068]
Also, the image signals n2, n3,..., Nn, and nn + 1 are inverted by the inverter elements to obtain the image signals o2, o3,.
[0069]
These image signals n1, n2, n3,..., Nn, nn + 1, nn + 2, o2, o3,..., On, on + 1 can be obtained for each pixel by using NAND gates 12, 14, 16, 18 as logic gates. , Pn corresponding to the detection signals p1, p2, p3,.
[0070]
Further, by using the OR gates 13, 15, 17, 19, detection signals q1, q2, q3,..., Qn corresponding to each pixel are generated.
[0071]
The output of each of the detection signals p1, p2, p3,..., Pn is a white isolated one pixel generation counter 20, a white isolated two pixel generation counter 22, a white isolated three pixel generation counter 24, and a white isolated n pixel generation counter 26. These output signals are generated as a one-pixel-isolated white image signal c1, a two-pixel isolated white image signal c2, a three-pixel isolated white image signal c3, and an n-pixel isolated white image signal cn.
[0072]
Similarly, the outputs of the detection signals q1, q2, q3,..., Qn are output from a black isolated one pixel generation counter 21, a black isolated two pixel generation counter 23, a black isolated three pixel generation counter 25, and a black isolated n pixel The output signals are output to the generation counter 27, and these output signals are generated as a one-pixel-isolated black image signal d1, a two-pixel isolated black image signal d2, a three-pixel isolated black image signal d3, and an n-pixel isolated black image signal dn. .
[0073]
That is, by outputting the detection signals p1 to pn and q1 to qn to the pixel generation counters 20 to 27 corresponding to each pixel and processing them, the pixel signals c1, c2, c3,. .., dn are generated.
[0074]
FIG. 4 is a time chart showing the operation of the pattern detection circuit.
[0075]
The time chart of each code in FIG. 4 corresponds to each image signal in FIG.
[0076]
The pattern detection circuit 1 detects and outputs an image signal for each arbitrary pixel. Here, as an example, a case where an image signal of three white isolated pixels and an image signal of two black isolated pixels are detected and generated is shown in FIGS. This will be described with reference to FIG.
[0077]
The image signal b is a final stage output obtained by inputting the image signal a to the shift register circuit 11 and processing the same. The image signals n1, n2, n3, n4, and n5 are obtained by shifting the image signal a by the shift register circuit 11. This is the output signal. The image signals o2, o3, and o4 are signals obtained by inverting the image signals n2, n3, and n4, and have opposite polarities as shown in FIG.
[0078]
The detection signal p3 is a signal for processing the image signals n1, n5, o2, o3, and o4 by the NAND gate 16 and detecting image data of three white isolated pixels in the image signal b. After the detection signal p3 is clearly input to the white-isolated three-pixel generation counter 24, the image signal clock 28 is input as a counter clock to obtain the white-isolated three-pixel generation counter output of FIG.
[0079]
Here, by stopping the function of the counter after the counter output has counted 0, 1, 2, 3 using a logic gate, a signal for three counts, that is, three pixels, is obtained, and this signal is inverted. Thus, an image signal c3 of three white isolated pixels is generated.
[0080]
On the other hand, the detection signal q2 is a signal obtained by processing the image signals n1, n4, o2, and o3 by the OR gate 15, and is a signal for detecting image data of two black isolated pixels in the image signal b. After the detection signal q2 is clearly input to the black isolated two-pixel generation counter 23, the image signal clock 28 is input as a counter clock to obtain the black isolated two-pixel generation counter output of FIG.
[0081]
Here, by stopping the function of the counter after the counter output has counted 0, 1, 2 using the logic gate, a signal for 2 counts, that is, 2 pixels, is obtained, and the image signal d2 of the black isolated 2 pixels Has been generated.
[0082]
Note that, other than the described example, it is possible to detect and generate image data for an arbitrary pixel depending on the combination of circuits.
[0083]
FIG. 5 is a detailed block diagram showing the configuration of the minimum pixel securing circuit of FIG.
[0084]
The operation of the minimum pixel securing circuit will be described with reference to FIG.
[0085]
The image signal b is an image signal output from the pattern detection circuit 1 in FIG. The C1 delay line 31 receives a white image signal c1 of one pixel isolated, sets the amount of pixel correction with an arbitrary range of delay amount by the setting signal r1, and outputs the pixel-corrected image signal t1. Here, the image signal b and the image signal t1 are logically ANDed by the AND gate 33, thereby generating an image signal v in which only white pixel data is corrected.
[0086]
On the other hand, the D1 delay line 32 receives a black image signal d1 of one pixel isolated, sets an amount of pixel correction with an arbitrary range of delay amount by the setting signal s1, and outputs a pixel-corrected image signal u1. Here, the image signal v and the image signal u1 are ORed by the OR gate 34, thereby generating an image signal e in which only one pixel of white and one pixel of black are corrected.
[0087]
FIG. 6 is a time chart showing the operation of the minimum pixel securing circuit.
[0088]
Note that the time chart of each code in FIG. 6 corresponds to each image signal in FIG.
[0089]
The image signal c1 in FIG. 6 is a one-pixel isolated white image signal, and the image signal t1 is subjected to pixel correction by setting a delay amount Δt1 with respect to the image signal c1 by the setting signal r1 by the C1 delay line 31. This is an image signal. Here, by performing pixel correction processing of Δt1 (t1: any integer), white pixel correction of Δc1 is performed as shown in FIG. 6, and the pulse width of the image signal t1 is increased by Δc1.
[0090]
The image signal v is an image signal obtained by ANDing the image signal b and the image signal t1 with the AND gate 33, and the pixel correction of Δt1 = Δc1 is performed only on the image data of one white pixel.
[0091]
On the other hand, the image signal d1 is an isolated black image signal of one pixel, and the image signal u1 is an image obtained by performing pixel correction by setting a delay amount Δu1 with respect to the image signal d1 by the setting signal s1 using the D1 delay line 32. Signal. Here, black pixel correction of Δp1 is performed by performing pixel correction processing of Δu1 (u1: any integer), and the pulse width of the image signal u1 is increased by Δp1.
[0092]
The image signal e is an image signal obtained by calculating the logical sum of the image signal v and the image signal u1 by the OR gate 34, and the pixel correction processing of Δt1 = Δc1 for the data of one white pixel and Δu1 = Δp1 for the data of one black pixel is performed. The image signal is output to the selection circuit 3 in FIG.
[0093]
FIG. 7 is a detailed block diagram showing the configuration of the white pixel correction circuit of FIG.
[0094]
The operation of the white pixel correction circuit will be described with reference to FIG.
[0095]
The image signal g is an image signal output from the selection circuit 3 in FIG. The image signals c2, c3,..., Cn are image signals of two white isolated pixels, three white isolated..., And n isolated white pixels, respectively, and are output from the pattern detection circuit 1 in FIG.
[0096]
, Cn are input to the C2 delay line 41, the C3 delay line 42,..., The CN delay line 43, respectively, and the amount of pixel correction by the setting signals r2, r3,. By individually setting each pixel with a delay amount in an arbitrary range, pixel-corrected image signals t2, t3,..., Tn are output. By ANDing these image signals t2, t3,..., And tn with the image signal g by the AND gate 44, an image signal h whose pixel has been corrected according to the number of pixels of the white image data is generated.
[0097]
FIG. 8 is a time chart showing the operation of the white pixel correction circuit.
[0098]
The time chart of each code in FIG. 8 corresponds to each image signal in FIG.
[0099]
, Cn of the image signals c2, c3,..., Cn are the amounts of pixel correction by the C2 delay lines 41, C3 delay lines 42,. .., Δtn (Δt3, Δt3,..., Δtn: arbitrary integers) are set individually for each pixel, so that each pixel correction is performed and the image signal t2, .., tn.
[0100]
As shown in FIG. 8, the image signal t2 is subjected to white pixel correction of Δc2, the image signal t3 is subjected to white pixel correction of Δc3, and the image signal tn is subjected to white pixel correction of Δcn.
[0101]
The image signal h is a signal obtained by taking the logical product of the image signal g and the image signals t2, t3,..., Tn by the AND gate 44, and the pixel correction processing is performed on the white image data of the image signal according to the number of pixels. Are output to the selection circuit 5 of FIG.
[0102]
FIG. 9 is a detailed block diagram showing the configuration of the black pixel correction circuit of FIG.
[0103]
The operation of the black pixel correction circuit will be described with reference to FIG.
[0104]
The image signal j is an image signal output from the selection circuit 5 in FIG. The image signals d2, d3,..., Dn are image signals of two black isolated pixels, three black isolated pixels, and n isolated black pixels, respectively, and are output from the pattern detection circuit 1 in FIG.
[0105]
, Dn are input to the D2 delay line 61, D3 delay line 62,..., DN delay line 63, respectively, and the amount of pixel correction by the setting signals s2, s3,. Image signals u2, u3,..., Un which are individually set for each pixel with a delay amount in an arbitrary range and pixel corrected are output.
[0106]
The image signal j is logically ORed with the image signal j by the OR circuit 64 to generate an image signal k that has been subjected to pixel correction according to the number of pixels of the black image data.
[0107]
FIG. 10 is a time chart showing the operation of the black pixel correction circuit.
[0108]
The time chart of each code in FIG. 10 corresponds to each image signal in FIG.
[0109]
, Dn in the D2 delay line 61, D3 delay line 62,..., DN delay line 63 are subjected to pixel correction by setting signals s2, s3,. .., Δun (Δu2, Δu3,..., Δun: arbitrary integer) are set individually for each pixel, whereby each pixel correction is performed. , Un are output as image signals u2, u3,.
[0110]
As shown in FIG. 10, the image signal u2 is subjected to black pixel correction of Δp2, the image signal u3 is subjected to black pixel correction of Δp3, and the image signal un is subjected to Δpn black pixel correction.
[0111]
The image signal k is a signal obtained by ORing the image signal j with the image signals u2, u3,..., Un by the OR gate 64, and the pixel correction processing according to the number of pixels is performed on the black image data of the image signal. Then, it is output to the selection circuit 7 of FIG.
[0112]
Note that in the white pixel correction circuit of FIG. 7, the image signal h subjected to the pixel correction according to the number of pixels of the white image data is ANDed by the AND gate 44, while the black pixel correction circuit of FIG. The image signal k subjected to pixel correction according to the number of pixels of data is ORed by the OR gate 64. Since the logic is changed in design, the white pixel correction circuit and the black pixel correction circuit may be configured by AND gates or OR gates, for example. A gate configuration is also possible.
[0113]
FIG. 11 is a block diagram showing a second embodiment of the high-speed pixel correction processing device of the present invention.
[0114]
The configuration of FIG. 11 is different from the configuration of FIG. 1 in that the minimum pixel securing circuit 2 and the selecting circuit 3 are removed, and a one-pixel isolated white image signal c1 input to the minimum pixel securing circuit 2 and an image signal output by the selecting circuit 3 g (image signal b) is directly input to the white pixel correction circuit 4 and the one-pixel isolated black image signal d1 input to the minimum pixel securing circuit 2 is directly input to the black pixel correction circuit 6 to obtain the same signal. The function and performance are obtained.
[0115]
The high-speed pixel correction processing device shown in FIG. 11 includes a pattern detection circuit 1 that inputs an image signal a and outputs a plurality of image signals and image signals b detected according to the number of pixels, and a pattern detection circuit 1 that outputs one or more pixels. A white pixel correction circuit 4 that combines the image signal b and the image signal b, and outputs an image signal h in which only the white pixel data is pixel corrected, and outputs the image signal b and the white pixel correction circuit 4. A selection circuit 5 for selecting an image signal h, an image signal corrected for black pixels according to one or more pixels, and an image signal j output from the selection circuit 5 are combined to correct only the black pixel data. A black pixel correction circuit 6 that outputs the image signal k, and a selection circuit 7 that selects the image signal j output by the selection circuit 5 and the image signal k output by the black pixel correction circuit 6 and outputs the selected signal as an image signal m. It is configured.
[0116]
Note that the detailed operation in FIG. 11 is the same as that in FIG. 1 except for the difference in the above-described configuration, and thus the description is omitted here.
[0117]
The principle of the pixel correction according to the present invention is to recover the pulse width or increase the pulse width by shaping the waveform of the image signal by delaying the pixel signal. This delay means that pixel correction is performed on an arbitrary integer in units of one pixel, that is, one pixel, two pixels, three pixels,...
[0118]
As described above, in general, in a recording apparatus that records an image, when the recording processing speed increases, the influence of the LED switching characteristics and the film characteristics becomes remarkable. Correction cannot be performed completely.
[0119]
Therefore, correction processing is performed in accordance with the number of pixels of two pixels, three pixels,..., N pixels (n: an arbitrary integer), and fine pixel correction processing is performed in pixel units, so that the recording density can be reduced by the printing apparatus. Even if the influence of the film characteristics and the LED switching characteristics is increased due to the increase in the density, the pixel width sufficiently corrected for the effects can be obtained.
[0120]
By applying the high-speed pixel correction processing device according to the present invention to an image recording system, high-speed, high-quality image recording can be performed.
[0121]
Further, since each circuit of the high-speed pixel correction processing device according to the present invention is mainly constituted by a logic circuit, it is possible to reduce the size and weight by forming these circuits into a gate array.
[0122]
Furthermore, the method of the high-speed pixel correction processing according to the present invention can be applied to image recording.
[0123]
【The invention's effect】
As described above, the high-speed pixel correction processing device according to the present invention performs high-speed pixel correction of an image signal, so that an arbitrary range is set according to the number of pixels such as one pixel, two pixels, three pixels,. The pixel correction process can be performed finely by setting the delay amount individually in, and even if the recording density is increased by the recording device and the influence of the film characteristics and LED switching characteristics increases, This has an effect that the influence is sufficiently corrected and a theoretical pixel width is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing one embodiment of a high-speed pixel correction processing device according to the present invention.
FIG. 2 is a time chart illustrating an operation of the high-speed pixel correction processing device of FIG. 1;
FIG. 3 is a detailed block diagram illustrating a configuration of a pattern detection circuit in FIG. 1;
FIG. 4 is a time chart illustrating an operation of the pattern detection circuit.
FIG. 5 is a detailed block diagram showing a configuration of a minimum pixel securing circuit of FIG. 1;
FIG. 6 is a time chart illustrating an operation of the minimum pixel securing circuit.
FIG. 7 is a detailed block diagram illustrating a configuration of a white pixel correction circuit in FIG. 1;
FIG. 8 is a time chart illustrating an operation of the white pixel correction circuit.
FIG. 9 is a detailed block diagram illustrating a configuration of a black pixel correction circuit in FIG. 1;
FIG. 10 is a time chart illustrating an operation of the black pixel correction circuit.
FIG. 11 is a block diagram illustrating a high-speed pixel correction processing device according to a second embodiment of the present invention.
FIG. 12 is a block diagram showing an image recording device using a conventional high-speed pixel correction processing device.
FIG. 13 is a waveform diagram showing the influence of film characteristics and LED switching characteristics on a conventional image signal.
[Explanation of symbols]
1 Pattern detection circuit
2 Minimum pixel securing circuit
3 Selection circuit
4 White pixel correction circuit
5 Selection circuit
6. Black pixel correction circuit
7 Selection circuit
8, 9, 10 selection signal
11 Shift register circuit
12 NAND gate
13 OR gate
14 NAND gate
15 OR gate
16 NAND gate
17 OR gate
18 NAND gate
19 OR gate
20 White isolated 1 pixel generation counter
21 Black isolated 1 pixel generation counter
22 White isolated 2-pixel generation counter
23 Black isolated 2-pixel generation counter
24 White isolated 3-pixel generation counter
25 Black isolated 3 pixel generation counter
26 White isolated n-pixel generation counter
27 Black Isolated n Pixel Generation Counter
28 Image signal clock
31 C1 delay line
32 D1 delay line
33 AND gate
34 OR gate
41 C2 delay line
42 C3 delay line
43 CN delay line
44 AND gate
61 D2 delay line
62 D3 delay line
63 DN delay line
64 OR gate
101 Communication control unit
102 Image memory control unit
103 Image memory
104 Margin character generator
105 Image Selector
106 Speed conversion control unit
107 Parallel / Serial Converter
108 pixel correction processing unit
109 CPU control unit

Claims (18)

A pixel correction processing device used in image recording,
A white image signal and a black image signal of one pixel, a white image signal corresponding to each pixel number of two pixels, three pixels,... N (n: an arbitrary integer) pixels, and two pixels, three pixels. It includes three-stage processing means for a black image signal corresponding to each pixel number, and delays the pixel signals of the white image signal and the black image signal by individually selecting an arbitrary integer delay amount for each pixel. A high-speed pixel correction processing device for performing pixel correction by means for increasing the pulse width of the waveform of the pixel signal. One pixel isolated white image signal, one pixel isolated black image signal, two pixel isolated white image signal, two pixel isolated black image signal, three pixel isolated white image signal, three pixel isolated with respect to the input image signal A pattern generation circuit for detecting an n-pixel isolated white image signal and an n-pixel isolated black image signal and outputting these image signals for each pixel;
A minimum pixel securing circuit that performs pixel correction on the one-pixel-isolated white image signal and the one-pixel-isolated black image signal in a range of one pixel;
A first selection circuit for selecting the input image signal and the output image signal of the minimum pixel securing circuit;
A white pixel correction circuit that performs pixel correction on a pixel-by-pixel basis for the two-pixel isolated white image signal to the n-pixel isolated white image signal, and combines the white image signal with the output image signal of the first selection circuit;
A second selection circuit for selecting an output image signal of the first selection circuit and an output image signal of the white pixel correction circuit;
A black pixel correction circuit that performs pixel correction for the two-pixel isolated black image signal to the n-pixel isolated black image signal on a pixel-by-pixel basis and combines the pixel image with the output image signal of the second selection circuit;
A third selection circuit for selecting an output image signal of the second selection circuit and an output image signal of the black pixel correction circuit;
A high-speed pixel correction processing device comprising: A pattern detection circuit that receives the image signal a and outputs a plurality of white image signals, a plurality of black image signals, and an image signal b detected according to the number of pixels 1 to n;
A minimum pixel securing circuit for outputting an image signal e in which only one pixel of image data is pixel corrected;
A first selection circuit for selecting the image signal b and the image signal e;
An image signal corrected by white pixel correction according to each of 2 pixels to n pixels and an image signal g output by the first selection circuit are combined to form an image signal h in which only white pixel data is pixel corrected. An output white pixel correction circuit;
A second selection circuit for selecting the image signal g output from the first selection circuit and the image signal h output from the white pixel correction circuit;
By combining the image signal that has been subjected to black pixel correction in accordance with each of the two to n pixels with the image signal j that is output from the second selection circuit, an image signal k that has been subjected to pixel correction for only black pixel data is obtained. A black pixel correction circuit to output;
A third selection circuit that selects the image signal j output by the second selection circuit and the image signal k output by the black pixel correction circuit, and outputs the selected signal as an image signal m;
A high-speed pixel correction processing device comprising: The pattern detection circuit,
From the image signal a input to the input terminal, the image signal b, the one-pixel isolated white image signal c1, the one-pixel isolated black image signal d1, the two-pixel isolated white image signal c2, and the two-pixel isolated black image signal d2, three-pixel isolated white image signal c3, three-pixel isolated black image signal d3,..., n-pixel isolated white image signal cn, and n-pixel isolated black image signal dn. 4. The high-speed pixel correction processing device according to claim 3, wherein the high-speed pixel correction processing device outputs the result. The minimum pixel securing circuit,
Pixel correction processing is individually performed on the one-pixel-isolated white image signal c1 and the one-pixel-isolated black image signal d1, and the image signal subjected to these two correction processing and the image signal b are combined. 5. The high-speed pixel correction processing device according to claim 3, wherein the image signal e is output after pixel correction of only one pixel. The first selection circuit includes:
6. The high-speed pixel correction processing apparatus according to claim 3, wherein one of the image signal b and the image signal e is selected by a first selection signal and the image signal g is output. The white pixel correction circuit includes:
Pixel correction processing is individually performed on the two-pixel isolated white image signal c2, the three-pixel isolated white image signal c3,..., And the n-pixel isolated white image signal cn, which are output image signals of the pattern detection circuit. And outputting the image signal h pixel-corrected with respect to white image data by combining the image signal g corrected by the white pixel and the image signal g output by the first selection circuit. 7. The high-speed pixel correction processing device according to claim 3, wherein: The second selection circuit includes:
6. The image signal j according to claim 3, wherein one of the image signal g and the image signal h output from the white pixel correction circuit is selected by a second selection signal. 8. The high-speed pixel correction processing device according to 6 or 7. The black pixel correction circuit,
Pixel correction processing is individually performed on the two-pixel isolated black image signal d2, the three-pixel isolated black image signal d3,..., And the n-pixel isolated black image signal dn, which are output image signals of the pattern detection circuit. And synthesizing these black pixel corrected image signals and the image signal j output by the second selection circuit to output the image signal k pixel corrected for black image data. 9. The high-speed pixel correction processing device according to claim 3, wherein: The third selection circuit includes:
4. The image processing apparatus according to claim 3, wherein one of the image signal j and the image signal k output from the black pixel correction circuit is selected by a third selection signal and output to an output terminal as the image signal m. The high-speed pixel correction processing device according to 4, 5, 6, 7, 8, or 9. The pattern detection circuit,
It has a single shift register, a plurality of AND gates, a plurality of OR gates, and a plurality of pixel generation counters. The detection signals p1 to pn and q1 to qn are generated for each pixel by these circuit elements. By outputting to the plurality of corresponding pixel generation counters and processing the same, the one-pixel isolated white image signal c1, the one-pixel isolated black image signal d1, the two-pixel isolated white image signal c2, The two-pixel isolated black image signal d2, the three-pixel isolated white image signal c3, the three-pixel isolated black image signal d3,..., The n-pixel isolated white image signal cn, and the n-pixel isolated black image signal The high-speed pixel correction processing device according to claim 4, wherein dn is generated. The minimum pixel securing circuit,
A first delay line and a second delay line, an AND gate, an OR gate,
The first delay line sets an amount of pixel correction in the input one-pixel-isolated white image signal c1 with a delay amount in an arbitrary range according to a setting signal r1, and outputs a pixel-corrected image signal t1. And, by taking the logical product of the image signal b and the image signal t1 by the logical product gate, an image signal v which is pixel-corrected only for the data of one pixel of white is generated,
The second delay line sets an amount of pixel correction in the input one-pixel-isolated black image signal d1 with a delay amount in an arbitrary range by a setting signal s1, and outputs a pixel-corrected image signal u1. The image signal v and the image signal u1 are ORed by the OR gate to generate an image signal e in which only one pixel of white and one pixel of black are corrected. The high-speed pixel correction processing device according to claim 5. The white pixel correction circuit includes:
A plurality of (2-n) delay lines and a logical product gate;
The image signals c2, c3,... Cn of the two white isolated pixels, the three white isolated pixels,..., The n isolated white pixels are respectively input to each of the plurality of delay lines, and a plurality of settings are made. By setting the amount of pixel correction by the signals r2, r3,... Rn individually for each pixel with an arbitrary range of delay amount, the pixel-corrected image signals t2, t3,. .., Tn and the image signal g are ANDed by the AND gate, whereby the image signal h, which has been subjected to pixel correction according to the number of pixels of white image data, is obtained. The high-speed pixel correction processing device according to claim 7, wherein the high-speed pixel correction processing is performed. The black pixel correction circuit,
A plurality of (2 to n) delay lines and an OR gate;
The image signals d2, d3,..., Dn of the black isolated two pixels, the black isolated three pixels,..., The black isolated n pixels are respectively input to each of the plurality of delay lines, and a plurality of settings are performed. By individually setting the amount of pixel correction by the signals s2, s3,..., Sn for each pixel with an arbitrary range of delay amount, the pixel-corrected image signals u2, u3,. .., Un and the image signal j are ORed by the OR gate, whereby the image signal k corrected for pixels in accordance with the number of pixels of the black image data is obtained. 10. The high-speed pixel correction processing device according to claim 9, wherein An image recording system to which the high-speed pixel correction processing device according to claim 1 is applied. A high-speed pixel correction processing method, wherein the high-speed pixel correction processing method according to any one of claims 1 to 14 is applied to image recording. 15. A high-speed pixel correction processing device, wherein each circuit of the high-speed pixel correction processing device according to claim 2 is formed into a gate array. The high-speed pixel correction processing device according to claim 2 or 3,
The minimum pixel securing circuit and the first selection circuit are removed, the one-pixel isolated white image signal is directly input to the white pixel correction circuit, and the one-pixel isolated black image signal is input to the black pixel correction circuit. A high-speed pixel correction processing device characterized by being directly input.

Images