JP2004032495A - Image processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing device, in which data inside each frame can be completely and continuously processed at prescribed timing in the image processing device, in which the data regarding images of a plurality of frames are processed at prescribed timing by units of frames. <P>SOLUTION: The image processing device is so constituted that the data regarding the images of a plurality of the frames received from the inside or the outside are processed at prescribed timing, at a processing part by the units of the frames. The image processing device has a data storage means to successively store the data regarding the images received from the inside or the outside to a plurality of buffer memories by the units of the frames and a data outputting means to output the data, regarding the images of the units of the frames to the processing part at prescribed timing in turn from the buffer memory storing the data regarding the image equivalent to one frame by the data storage means. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing apparatus that processes data related to images for a plurality of frames in frame units.
[0002]
[Prior art]
FIG. 4 is a diagram showing a configuration of a conventional image processing apparatus 200. The memory 3 stores code data of a plurality of frames of video obtained by photographing a certain subject. The code data is obtained by dividing an image of each frame into a plurality of blocks each having a predetermined pixel matrix and coding the divided blocks. The memory 3 stores code data in block units.
[0003]
When reproducing a video, the CPU 1 sends a reproduction signal of the code data of the first block of the first frame to the DMA 2. The DMA 2 separates the data bus 7 from the CPU 1 in response to the reproduced signal, and outputs the encoded first block code data of the first frame stored in the memory 3 to the decoder 4 via the data bus 7. I do. After the output of the code data of the first block is completed, the DMA 2 temporarily releases the data bus 7.
[0004]
Subsequently, the CPU 1 sends a reproduction signal of the code data of the second block of the first frame to the DMA 2. The DMA 2 disconnects the data bus 7 from the CPU 1 again, and outputs the code data of the second block of the first frame stored in the memory 3 to the decoder 4 via the data bus 7. After outputting the code data of the second block, the DMA 2 releases the data bus 7.
[0005]
In the same manner, the CPU 1 sends the third block, fourth block,..., First block, second block,..., First block, second block,. And the reproduced signals of the coded data of all the blocks of all the expected frames are sequentially output.
[0006]
The decoder 4 decodes the input code data of each block into original image data and outputs the original image data to the buffer 5 at the subsequent stage. The buffer 5 sequentially stores the image data in block units input from the decoder 4 and outputs the image data to the display 6 in synchronization with the frame synchronization signal Sync input in 1/30 second units. The display 6 continuously displays an image based on the input image data and reproduces a video.
[0007]
[Problems to be solved by the invention]
FIG. 5 shows the code data of each block stored in the memory 3, the block data input to the decoder 4 via the data bus 7, the respective block data output from the decoder 4, the frame synchronization signal Sync, 6 is a diagram illustrating data output from the buffer 5 in response to the frame synchronization signal Sync. FIG.
[0008]
As described above, the DMA 2 disconnects the CPU 1 from the data bus 7 each time the block 2 outputs the image data of the block to the decoder 4 in response to a request from the CPU 1. If the data bus 7 is occupied by the CPU 1 when the disconnection is performed, the DMA 2 waits for the CPU 1 to release the data bus 7. In FIG. 5, the standby time is represented by an interval between each block data input to the decoder 4 and an interval between decoded data (image data) output from the decoder 4 in block units. As shown in the figure, if the waiting times are accumulated, reading of the code data of all the blocks for one frame may not be completed within 1/30 seconds, which is the output interval of the frame synchronization signal Sync. In this case, incomplete image data in which two blocks of image data are missing is output from the buffer 5, and so-called missing frames occur, deteriorating the reproduction image quality.
[0009]
The present invention provides an image processing apparatus that processes data relating to images of a plurality of frames in a frame unit at a predetermined timing, wherein the image processing apparatus can continuously process at the predetermined timing without missing data in a frame. The purpose is to do.
[0010]
[Means for Solving the Problems]
According to a first image processing apparatus of the present invention, an image processing apparatus that processes data on a plurality of frames of images received from the inside or the outside on a frame basis at a predetermined timing in a processing unit. Storage means for sequentially storing data on a frame basis in a plurality of buffer memories, and the buffer memory in which data on one frame of image has been completely stored by the data storage means at predetermined timing in order from the buffer memory. And data output means for outputting data relating to the data to the processing unit.
[0011]
A second image processing apparatus according to the present invention is characterized in that, in the first image processing apparatus, a plurality of buffer memories each capable of storing data relating to an image for one frame are provided.
[0012]
A third image processing apparatus according to the present invention is the first or second image processing apparatus, wherein a plurality of frames of encoded data received from inside or outside is decoded by a decoder, and the decoded image data is used. A plurality of buffer memories, each of which can store image data of one frame, wherein the plurality of buffer memories each store image data of one frame. The storage means sequentially stores the image data decoded by the decoder in the plurality of buffer memories in units of one frame, and the data output means completes the storage of the image data for one frame by the data storage means. The image data of one frame unit is sequentially output to the output unit at a predetermined timing from the buffer memory.
[0013]
The fourth image processing device of the present invention is the first or second image processing device, and sequentially decodes code data for a plurality of frames received from inside or outside by a decoder as the processing unit, An image processing apparatus for continuously outputting an image of each frame to an output unit based on decoded image data, wherein the plurality of buffer memories are each capable of storing code data for one frame. The data storage means sequentially stores a plurality of frames of code data received from the inside or the outside in the plurality of buffer memories in units of one frame, and the data output means stores the code data of one frame by the data storage means. Are sequentially output to the decoder at predetermined timing in order from the buffer memory in which the storage of the data has been completed.
[0014]
A first image processing method according to the present invention is an image processing method in which data relating to a plurality of frames of images received from inside or outside is processed in a frame unit at a predetermined timing in a processing unit. A data storage step of sequentially storing data relating to one frame in a plurality of buffer memories in a plurality of buffer memories, and storing data relating to an image for one frame in the data storage step is completed at a predetermined timing in order from the buffer memory in relation to the image in the frame unit. And a data output step of outputting data to the processing unit.
[0015]
In a second image processing method according to the present invention, the first image processing method decodes, using a decoder, code data for a plurality of frames received internally or externally, and decodes an image of each frame based on the decoded image data. An image processing method for continuously outputting the image data to an output unit serving as the processing unit, wherein the data storing step sequentially stores the image data decoded by the decoder in a plurality of buffer memories in units of one frame. The data output step is to output the image data in units of one frame to the output unit at a predetermined timing in order from the buffer memory in which the storage of the image data for one frame is completed in the data storage step.
[0016]
According to a third image processing method of the present invention, the first image processing method sequentially decodes code data for a plurality of frames received internally or externally by a decoder as the processing unit, and performs decoding based on the decoded image data. An image processing method of continuously outputting an image of each frame to an output unit, wherein the data storing step stores code data of a plurality of frames received from inside or outside in the plurality of buffer memories in units of one frame. In the data output step, the code data of one frame unit is output to the decoder at a predetermined timing sequentially from the buffer memory in which the storage of the code data for one frame is completed by the data storage means. Things.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of an image processing apparatus according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a configuration of an image processing apparatus 100 according to an embodiment. The same components as those of the conventional image processing apparatus 200 (FIG. 4) described above in the section of the prior art are denoted by the same reference numerals.
[0018]
The data bus 7 is connected to the CPU 1, which controls the operation of the entire apparatus, the memory 3, and the decoder 4. The memory 3 stores data obtained by encoding video data for a plurality of frames obtained by photographing a certain subject. The code data is obtained by dividing an image of each frame into a plurality of blocks each having a predetermined pixel matrix and coding the divided blocks. The memory 3 stores code data in block units.
[0019]
When reproducing a video, the CPU 1 sends a reproduction signal of the code data of the first block of the first frame to the DMA 2. The DMA 2 separates the data bus 7 from the CPU 1 in response to the reproduced signal, and outputs the encoded first block code data of the first frame stored in the memory 3 to the decoder 4 via the data bus 7. I do. After the output of the code data of the first block is completed, the DMA 2 temporarily releases the data bus 7.
[0020]
Subsequently, the CPU 1 sends a reproduction signal of the code data of the second block of the first frame to the DMA 2. The DMA 2 again disconnects the CPU 1 from the data bus 7 and outputs the code data of the second block to the decoder 4 via the data bus 7. After outputting the code data of the second block, the DMA 2 releases the data bus 7.
[0021]
Hereinafter, similarly, the CPU 1 performs the third block of the first frame, the fourth block,..., The first block of the second frame, the second block,. .., And outputs reproduced signals of the code data of all the blocks of all the planned frames.
[0022]
The decoder 4 decodes the code data input in block units into image data in the above-described procedure, and sequentially outputs the decoded image data to the buffer circuit 8. As will be described later in detail, the buffer circuit 8 includes a buffer memory for two frames. The buffer circuit 8 first stores the decoded image data for each block in one buffer memory, and switches the buffer memory as soon as the image data for one frame is stored, and stores the image data for the other block. To start. The image data for one frame is output to the display 6 in synchronization with the frame synchronization signal Sync input after the buffer memory is switched.
[0023]
FIG. 2 is a diagram illustrating a configuration of the buffer circuit 8. The decoded data (image data) is input to the selector 10 and the bit counter 13. The selector 10 selects the first buffer memory 12 according to the input of the low-level (initial value) selector signal B, and stores the input image data in the first buffer memory 12.
[0024]
As described below, the selector 10, the bit counter 13, the comparator 14, the block counter 15, the comparator 16, and the 1-bit counter 17 sequentially store one frame of data in the first buffer memory 12 and the second buffer memory 11. It functions as data storage means for storing image data.
[0025]
The bit counter 13 counts the number of bits of the input image data and outputs it to the comparator 14 at the next stage. The comparator 14 determines that the input bit count value is equal to a preset number of bits for one block (for example, 128 × 128 bits), that is, the input of the image data for one block is completed. In this case, a high-level signal is output to the next-stage block counter 15 and the signal is output to the reset terminal of the bit counter 13 to reset the counter value. The signal output from the comparator 14 in response to the reset of the bit counter 13 returns from the high level to the low level.
[0026]
The block counter 15 counts up according to the input of the High level signal from the comparator 14 and outputs the count value to the comparator 16 at the next stage. The comparator 16 sets the High level when the input count value becomes equal to the preset number of blocks for one frame, that is, when the input of the code data for one frame to the buffer memory is completed. Is output to the next-stage 1-bit counter 17 as a data input completion signal A. At the same time, the high-level signal is output to the reset terminal of the bit counter 15 to reset the counter value. The signal output from the comparator 16 in response to the reset of the block counter 15 returns from the high level to the low level.
[0027]
The 1-bit counter 17 counts up according to a High-level signal input from the comparator 16 and inputs the count value as a selector signal B to the selector signal input terminal of the selector 10. That is, the 1-bit counter 17 changes the level of the output signal from the High level to the Low level every time the storage of one frame of image data in one of the first and second buffer memories 11 and 12 is completed, or Switching from the low level to the high level starts storage of the code data in the other buffer memory.
[0028]
As will be described below, the 1-bit counter 17, the AND gate 18, the AND gate 19, and the delay circuit 20 perform the image processing for one frame at a predetermined timing in order from the buffer memory in which the input of the image data for one frame is completed. It functions as data output means for outputting data to the display 6 at the subsequent stage.
[0029]
The 1-bit counter 17 also inverts the count value to one signal input terminal of a two-input AND gate 18 and inputs the inverted value, and outputs the same to one signal input terminal of a two-input AND gate 19. To the remaining signal input terminals of the AND gates 18 and 19, a signal C obtained by delaying the frame synchronization signal Sync by a predetermined time (for example, a half cycle) by the delay circuit 20 is inverted and input. The frame synchronization signal Sync is a trigger signal output at 1/30 second intervals.
[0030]
When the signal from the 1-bit counter 17 switches from the low level to the high level, that is, when the storage of one frame of image data in the first buffer memory 12 is completed, The first buffer memory data read request signal D at a high level is input from the AND gate 19 to the input terminal of the data read request signal of the first buffer memory 12. In response to the high-level signal D, the first buffer memory 12 continuously outputs the stored image data for one frame to the display 6.
[0031]
On the other hand, when the signal from the 1-bit counter 17 switches from the High level to the Low level, that is, when the storage of one frame of image data in the second buffer memory 11 is completed, the input of the signal C is performed. Accordingly, the high-level second buffer memory data read request signal E is input from the AND gate 18 to the input terminal of the data read request signal of the second buffer memory 11. Upon receiving the high-level signal E, the second buffer memory 11 continuously outputs the stored image data for one frame to the display 6.
[0032]
FIG. 3 shows code data of each frame stored in the memory 3 in block units, block data input to the decoder via the data bus 7 by the operation of the DMA 2, and decoded data output from the decoder 4 (image data). 4 is a time chart showing states of data, a data input completion signal A, a selector signal B, a signal C, a first buffer memory data read request signal D, a second buffer memory data read request signal E, and output data.
[0033]
FIG. 3 shows a case where the data bus 7 is congested and the storage of the image data of all the blocks for one frame in the first buffer memory 12 cannot be completed within 1/30 second. is there. The buffer circuit 8 stores the image data of each frame in the two buffer memories 11 and 12 alternately, so that the image data of all the blocks for one frame is completely stored in the buffer memory, The stored image data may be output in response to the input of the signal C obtained by delaying the frame synchronization signal Sync until the image data of the data bus 7 is input. Can be output without skipping frames even when the data transfer process by the DMA 2 takes time due to congestion.
[0034]
As described above, the image processing apparatus 100 including the buffer circuit 8 between the decoder 4 and the display 6 has been described. However, the two buffer memories 11 and 12 included in the buffer circuit 8 are provided in the buffer circuit 8 as in the present embodiment. It may be built in or may be prepared outside. Further, the buffer circuit 8 itself may be provided between the data bus 7 and the decoder 4. In this case, the buffer circuit 8 alternately stores the code data for one frame transmitted in block units in the first buffer memory 12 and the second buffer memory 11 and converts the frame synchronization signal Sync into a delayed signal C. Synchronously, it outputs the code data in units of one frame to the decoder 4 in order.
[0035]
Note that the code data is not limited to data read in units of blocks from the memory 3 via the data bus 7, and may be data input in blocks from an external recording device via the data bus 7.
[0036]
Furthermore, the code data sent via the data bus 7 is not necessarily divided into blocks, and all the code data for one frame may be sent at a time. The image processing device 100 is a device that displays images in frame units at 1/30 second intervals in synchronization with the frame synchronization signal Sync, and the buffer circuit 8 includes a data bus 7 that is congested. This is because it is provided in order to eliminate the trouble that the image data of the next one frame is not prepared in the above 1/30 second before the display 6 which performs the processing in units of frames.
[0037]
Further, the buffer circuit 8 sequentially encodes image data transmitted in frame units from the photographing camera in synchronization with the frame synchronization signal Sync by the encoder, and stores the encoded data in real time in a recording medium such as a memory or a hard disk. It may be used for an image processing apparatus (not shown) for recording in. In this case, the buffer circuit 8 is provided before the recording medium and after a portion where data sent from the photographing camera can be delayed during data transfer, for example, after the data bus. For example, when an encoder that receives image data from a photographing camera divides an image for one frame into blocks of a predetermined size, and records data that has been encoded for each block on a recording medium via a data bus, A buffer circuit 8 is provided between the data bus and the recording medium. By employing this configuration, it is possible to accurately record, in real time, the code data of the video captured by the capturing camera.
[0038]
【The invention's effect】
The first image processing apparatus according to the present invention sequentially stores received data relating to an image in a plurality of buffer memories and outputs the data at a predetermined timing in order from the stored data. Even when data on one frame of image is not obtained within the predetermined timing interval, data on one frame of image can be output to the processing unit without causing data loss.
[0039]
The second image processing apparatus according to the present invention sequentially stores the received data relating to the image in a plurality of buffer memories, which are one of the constituent elements, and outputs the data at a predetermined timing in order from the stored one. Even if data for one frame of image is not obtained within the above-mentioned predetermined timing at the time of data transfer for some reason, the data relating to the image of frame is transmitted to the processing unit without causing data loss. Can be output.
[0040]
A third image processing apparatus according to the present invention is the image processing apparatus according to the first or second image processing apparatus, wherein the image data decoded by the decoder is sequentially stored in a plurality of buffer memories, and a predetermined number of the image data are stored in order from the stored one. By outputting at the timing of, even if one frame of image data cannot be obtained within the above-mentioned predetermined timing at the time of data transfer for some reason, data loss does not occur and the processing unit Image data for a frame can be output.
[0041]
A fourth image processing apparatus according to the present invention is the image processing apparatus according to the first or second image processing apparatus, wherein code data for a plurality of frames received from inside or outside is sequentially stored in a plurality of buffer memories for each frame, and stored. Is output to the decoder at a predetermined timing in order from the one completed, so that even if image data for one frame cannot be obtained within the predetermined timing interval during data transfer for some reason, Image data for a frame can be output to the processing unit without causing loss of the image.
[0042]
According to the first image processing method of the present invention, the data relating to the received image is sequentially stored in a plurality of buffer memories, and is output at a predetermined timing in order from the stored data, so that the data can be transferred at any time during data transfer. Even when data on one frame of image is not obtained within the predetermined timing interval, data on one frame of image can be output to the processing unit without causing data loss.
[0043]
In the second image processing method of the present invention, the image data after decoding by the decoder is sequentially stored in a plurality of buffer memories, and output at a predetermined timing in order from the stored image data. Even if one frame of image data is not obtained within the predetermined timing interval at the time of transfer, the image data of one frame can be output to the processing unit without causing data loss.
[0044]
According to a third image processing method of the present invention, code data for a plurality of frames received from the inside or the outside is sequentially stored in a plurality of buffer memories in a unit of one frame, and a decoder is sequentially stored at a predetermined timing from a stored one. Even if the image data for one frame cannot be obtained within the predetermined timing interval during data transfer for some reason, the data is not lost in the processing unit. Can be output.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an image processing apparatus according to an embodiment.
FIG. 2 is a configuration diagram of a buffer circuit.
FIG. 3 is a time chart of signals in the image processing apparatus.
FIG. 4 is a configuration diagram of a conventional image processing apparatus.
FIG. 5 is a time chart of signals in a conventional image processing apparatus.
[Explanation of symbols]
1 CPU, 2 DMAs, 3 memories, 4 decoders, 5 buffers, 6 displays, 7 data buses, 8 buffer circuits.

Claims (7)

In an image processing apparatus that processes data related to a plurality of frames of images received from the inside or the outside at a predetermined timing in a processing unit in frames.
Data storage means for sequentially storing data on an image received from the inside or the outside in a plurality of buffer memories in frame units;
Data output means for outputting data relating to the image in frame units to the processing unit at a predetermined timing in order from the buffer memory in which data relating to the image for one frame has been completely stored by the data storage means. Image processing device. The image processing apparatus according to claim 1,
Further, the image processing apparatus includes a plurality of buffer memories each capable of storing data relating to one frame of image. The image processing device according to claim 1 or 2, wherein the decoder decodes code data for a plurality of frames received from the inside or the outside by a decoder, and continuously executes the image of each frame based on the decoded image data. An image processing device that outputs to an output unit that is a processing unit,
The plurality of buffer memories are each capable of storing image data for one frame,
The data storage means sequentially stores the image data decoded by the decoder in the plurality of buffer memories in units of one frame,
The image processing device, wherein the data output means outputs the image data in units of one frame to the output unit at a predetermined timing in order from the buffer memory in which the storage of the image data for one frame is completed by the data storage means. The image processing apparatus according to claim 1 or 2 sequentially decodes code data of a plurality of frames received from the inside or the outside by a decoder as the processing unit, and decodes each frame based on the decoded image data. An image processing device that continuously outputs images to an output unit,
Each of the plurality of buffer memories can store one frame of code data.
The data storage means sequentially stores, in the plurality of buffer memories, code data of a plurality of frames received internally or externally in units of one frame,
The image processing device, wherein the data output unit outputs the code data in units of one frame to the decoder at a predetermined timing in order from the buffer memory in which the storage of the code data for one frame is completed by the data storage unit. In an image processing method for processing data on a plurality of frames of images received from the inside or the outside in a processing unit on a frame basis at predetermined timing,
A data storage step of sequentially storing data relating to an image received from the inside or the outside in a plurality of buffer memories in frame units;
Storing the data relating to the image for one frame in the data storing step, and outputting the data relating to the image in the frame unit to the processing unit at a predetermined timing in order from the completion buffer memory; Processing method. The image processing method according to claim 5, wherein the decoding unit decodes code data for a plurality of frames received from the inside or the outside by a decoder, and continuously processes the image of each frame based on the decoded image data. An image processing method to output to the output unit,
In the data storing step, the image data decoded by the decoder is sequentially stored in a plurality of buffer memories in units of one frame.
The data output step is an image processing method for outputting image data in units of one frame to the output unit at a predetermined timing in order from a buffer memory in which image data for one frame is completely stored in the data storage step. In the image processing method according to the fifth aspect, code data for a plurality of frames received from inside or outside is sequentially decoded by a decoder as the processing unit, and an image of each frame is continuously generated based on the decoded image data. Is an image processing method for outputting to the output unit
The data storing step includes sequentially storing code data for a plurality of frames received from the inside or the outside in the plurality of buffer memories in units of one frame.
The data output step is to output the code data in units of one frame to the decoder at a predetermined timing in order from the buffer memory in which the storage of the code data for one frame is completed by the data storage means.

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