JP2004032310A - Automatic gain control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an automatic gain control circuit, in which the output signal from a variable gain amplifier can be pulled in quickly to a target level, and gain control is not performed when a defective signal is inputted to the variable gain amplifier. <P>SOLUTION: The automatic gain control circuit comprises a gain control section 32 generating a gain control signal Sg performing gain control of the variable gain amplifier 11, based on an integrated signal Si from an equalizer filter 31, and a clock-generating section 33 generating a clock CLK2 for driving the gain control section 32 based on a differentiated signal Sd from the equalizer filter 31 and the integration signal Si. The gain control section 32 comprises a buffer circuit 13A, a filter circuit 14, an amplitude-detecting circuit 35, an adder circuit 36, and a latch circuit 37. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an automatic gain control circuit that variably controls the gain of a variable gain amplifier so that the level of an output signal becomes constant even when the level of an input signal changes.
[0002]
[Prior art]
For example, in a data recording / reproducing apparatus that records / reproduces data on a recording medium such as an MO (magneto-optical disk) or a DVD-RAM, a pre-processing for binarizing (digitalizing) an analog signal detected by an optical system An automatic gain control circuit is provided for adjusting the amplitude of the analog signal to a target value.
[0003]
FIG. 5 shows an example of such a conventional automatic gain control circuit.
This automatic gain control circuit controls the gain of the variable gain amplifier 1 so that the amplitude of the output signal of the equalizer filter 2 becomes constant even if the amplitude of the input signal of the variable gain amplifier (VGA) 1 changes. Things.
Here, the variable gain amplifier 1 amplifies an input signal and can vary the gain. Further, the equalizer filter 2 performs the waveform equalization of the output signal of the variable gain amplifier 1.
[0004]
To this end, as shown in FIG. 5, the automatic gain control circuit includes a smoothing circuit 3, a peak hold circuit 4, a Gm amplifier (transconductance amplifier) 5, and an output capacitor C2.
The smoothing circuit 3 includes a capacitor C1 and a resistor R1, and smoothes an output signal of the equalizer filter 2. The peak hold circuit 4 holds the peak value of the output signal of the smoothing circuit 3.
[0005]
The Gm amplifier 5 compares the output signal of the peak hold circuit 4 with a reference signal (target value), and charges or discharges the capacitor C2 according to the difference, thereby generating a gain control voltage Vc across the capacitor C2. The gain control voltage Vc is supplied to the variable gain amplifier 1 to be controlled.
Therefore, the gain of the variable gain amplifier 1 is continuously varied by the gain control voltage Vc. Therefore, regardless of the magnitude of the amplitude of the input signal of the variable gain amplifier 1, the amplitude of the output signal from the equalizer filter 2 is increased. Is the target value.
[0006]
However, in the conventional automatic gain control circuit shown in FIG. 5, it is generally difficult to operate the peak hold circuit 4 at high speed. For example, when the input signal of the peak hold circuit 4 is large, it is possible to catch the peak of the input signal in a relatively short time, but after that, it takes time for the input signal to become small and reach the target value. It will be long. For this reason, there is an inconvenience that it is difficult to quickly pull the output signal to the target value.
[0007]
In order to cope with the case where the input signal of the variable gain amplifier 1 is a defective signal, if the period until the output signal is pulled to the target value is made longer, some tolerance can be obtained, but the period of the defective signal is reduced. If the length is long, there is a disadvantage that the gain of the variable gain amplifier 1 becomes much larger than a target.
Next, an example of a conventional automatic gain control circuit is shown in FIG.
[0008]
This automatic gain control circuit controls the gain of the variable gain amplifier 11 so that the amplitude of the output signal of the equalizer filter 12 becomes constant even if the amplitude of the input signal of the variable gain amplifier (VGA) 11 changes. Things.
Here, the variable gain amplifier 11 amplifies an input signal and can vary its gain discretely. Therefore, the variable gain amplifier 11 can change the gain in steps of 0.8 [dB] in the range of, for example, -9.5 to 14.5 [dB]. , A 5-bit digital signal can be input. Further, the equalizer filter 12 performs waveform equalization of the output signal of the variable gain amplifier 11.
[0009]
To this end, the automatic gain control circuit includes a buffer circuit 13, a smoothing circuit 14, an output signal detection circuit 15, an addition circuit 16, and a latch circuit 17, as shown in FIG.
The buffer circuit 13 is composed of, for example, a circuit having a gain of five times, and amplifies the output signal of the equalizer filter 12.
[0010]
The smoothing circuit 14 includes a capacitor C3 and a resistor R3, and smoothes an output signal of the buffer circuit 13.
The output signal detecting circuit 15 compares the output signal of the smoothing circuit 14 with each reference value and outputs a signal corresponding to the comparison, and the latch circuits 25 to store the respective outputs of the comparators 21 to 24. 28.
[0011]
The comparator 21 compares the output signal of the smoothing circuit 14 with the reference voltage V1, and if the output signal exceeds the reference voltage V1, outputs an output signal “1” indicating that. At this time, the output signal "1" is stored in the latch circuit 25. Here, the reference voltage V1 is, for example, +0.75 [V].
[0012]
Similarly, each of the comparators 22 to 24 compares the output signal of the smoothing circuit 14 with its own reference voltage V2 to V4, and when the output signal exceeds each of the reference voltages V2 to V4, the output signal “ 1 "is output. At this time, the respective output signals "1" are stored in the corresponding latch circuits 26 to 28, respectively. Here, the reference voltages V2, V3, and V4 are, for example, +0.55 [V], +0.45 [V], and +0.25 [V].
[0013]
Each of the latch circuits 25 to 28 has a reset terminal. By supplying the system clock CLK1 to the reset terminal, initialization can be performed at the cycle of the system clock CLK1.
The addition circuit 16 is a circuit that adds the output signals A to D of the latch circuits 25 to 28 and the output of the latch circuit 17.
[0014]
The latch circuit 17 is a storage circuit that captures the output signal of the addition circuit 17 at the rise of the system clock CLK1 and temporarily stores the captured signal. The output signal of the latch circuit 17 is supplied to the variable gain amplifier 11.
For this reason, the gain of the variable gain amplifier 11 is discretely varied by the output signal, so that the amplitude of the output signal from the equalizer filter 2 becomes the target regardless of the amplitude of the input signal of the variable gain amplifier 11. Value.
[0015]
Here, the relationship between the output signals A, B, C, and D of the latch circuits 25 to 28 and the corresponding gain of the variable gain amplifier 11 is as shown in FIG. 7, for example. For example, when the output signals A, B, C, and D of the latch circuits 25 to 28 are “0011”, the gain of the variable gain amplifier 11 is not controlled because the output signal matches the target value. When the output signals A, B, C, and D are “0001”, the gain increases by one step, and when the output signals A, B, C, and D are “0111”, the gain increases. It is controlled to decrease by one step.
[0016]
[Problems to be solved by the invention]
By the way, in the conventional automatic gain control circuit shown in FIG. 6, the latch circuits 25 to 28 and the latch circuit 17 operate based on the system clock CLK1 as described above.
The system clock CLK1 has a constant frequency, for example, and is supplied from the outside. When the automatic gain control circuit is applied to the data recording / reproducing apparatus as described above, the input of the variable gain amplifier 11 is It is not synchronized with the signal.
[0017]
For this reason, the comparators 21 to 24 and the subsequent latch circuits 25 to 28 cannot determine that the peak value of the output signal of the equalizer filter 12 has been captured, so that the timing for changing the gain of the variable gain amplifier 11 is not sufficient. It is necessary to wait for a time (time corresponding to a predetermined number of system clocks CLK1). As a result, there is a disadvantage that the operation of the automatic gain control circuit for pulling the output signal of the variable gain amplifier 11 to the target value tends to be slow.
[0018]
Further, in the conventional automatic gain control circuit, since there is no correlation between the input signal of the variable gain amplifier 11 and the system clock, it is better not to perform the gain control of the variable gain amplifier 11 when the input signal is a defective signal. However, there is a disadvantage that the gain control is performed.
In view of the above, it is an object of the present invention to quickly pull an output signal of a variable gain amplifier to a target value and perform gain control when the input signal of the variable gain amplifier is a defective signal. It is an object of the present invention to provide an automatic gain control circuit which is not required.
[0019]
[Means for Solving the Problems]
In order to solve the above problems and achieve the object of the present invention, the inventions according to claims 1 to 3 are configured as follows.
That is, according to the present invention, the automatic gain control circuit controls the gain of the variable gain amplifier so that the amplitude of the output signal becomes a target value even if the amplitude of the input signal of the variable gain amplifier changes. A gain control unit that detects an amplitude of an output signal of the variable gain amplifier, and performs gain control of the variable gain amplifier according to the detection result; and a timing at which the gain control unit performs gain control of the variable gain amplifier. A clock generation unit for generating a clock according to the above, wherein the clock generation unit generates the clock based on a differential signal obtained by differentiating an output signal of the variable gain amplifier. It is.
[0020]
According to a second aspect of the present invention, in the automatic gain control circuit according to the first aspect, the clock generation unit is configured to perform, based on an integrated signal obtained by integrating an output signal of the variable gain amplifier, in addition to the differential signal. It is characterized in that a clock is generated.
According to a third aspect of the present invention, in the automatic gain control circuit according to the first or second aspect, the variable gain amplifier differentiates an integrated signal obtained by integrating an output signal of the variable gain amplifier and the output signal. And a filter for outputting the differential signal.
[0021]
According to the present invention having such a configuration, the output signal of the variable gain amplifier can be pulled into the target value at high speed, and the gain control is not performed when the input signal of the variable gain amplifier is a defective signal. It becomes possible to.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a configuration of an automatic gain control circuit according to an embodiment of the present invention will be described with reference to FIG.
In the embodiment of the automatic gain control circuit of the present invention, as shown in FIG. 1, even if the amplitude of the input signal In of the variable gain amplifier (VGA) 11 changes, the amplitude of the output signal of the equalizer filter 31 is kept constant. Thus, the gain of the variable gain amplifier 11 is controlled.
[0023]
The variable gain amplifier 11 is the same as the variable gain amplifier 11 shown in FIG. 6, and amplifies an input signal In, and the gain of the variable gain amplifier 11 can be discretely varied by a gain control signal Sg.
The equalizer filter 31 is, for example, a filter configured by a sixth-order biquad system. Therefore, the equalizer filter 31 can generate an integrated signal Si obtained by integrating the output signal of the variable gain amplifier 11, generate a differentiated signal Sd obtained by differentiating the output signal, and output both signals simultaneously. I can do it.
[0024]
As shown in FIG. 1, the automatic gain control circuit includes a gain control unit 33 that generates a gain control signal Sg for controlling the gain of the variable gain amplifier 11 based on the integrated signal Si from the equalizer filter 31; And a clock generator 32 for generating a clock CLK2 for driving the gain controller 33 based on the differential signal Sd from S31 and the integration signal Si.
[0025]
The clock generator 32 captures the differential signal Sd and the integrated signal Si from the equalizer filter 31 via the buffer circuits 13A and 13B, and generates a clock CLK2 as shown in FIG. It has become.
The gain control unit 33 includes a buffer circuit 13A, a smoothing circuit 14, an output signal detection circuit 35, an addition circuit 36, and a latch circuit 37, as shown in FIG.
[0026]
The buffer circuit 13A and the smoothing circuit 14 have the same configuration as the buffer circuit 13 and the smoothing circuit 14 shown in FIG.
The output signal detection circuit 35 compares the output signal of the smoothing circuit 14 with each reference value and outputs a signal corresponding to the comparison, and the latch circuits 25A to 25 which store the respective outputs of the comparators 21 to 24. 28A.
[0027]
The comparators 21 to 24 have the same configuration as the comparators 21 to 24 shown in FIG.
The latch circuits 25A to 28A have basically the same configuration as the latch circuits 25 to 28 shown in FIG. However, the latch circuits 25A to 28A are different in that the clock CLK2 generated by the clock generation unit 32 is supplied to the reset terminal (R) and is initialized at the cycle of the clock CLK2.
[0028]
The addition circuit 36 is a circuit that adds the output signals A to D of the latch circuits 25A to 28A and the output of the latch circuit 37.
The latch circuit 37 is a storage circuit that captures the output signal of the addition circuit 36 at the rising edge of the clock CLK2 from the clock generation unit 33 and temporarily stores the captured signal. The output signal of the latch circuit 37 is supplied to the variable gain amplifier 11 as a gain control signal Sg. Therefore, since this latch circuit 37 is driven by the clock CLK2, this point is different from the latch circuit 17 shown in FIG.
[0029]
The relationship between the output signals A, B, C, and D of the latch circuits 25A to 28A and the corresponding gain of the variable gain amplifier 11 is as shown in FIG.
Next, a specific configuration of the clock generation unit 32 shown in FIG. 1 will be described with reference to FIG.
As shown in FIG. 3, the clock generator 32 includes comparators 321 and 322, latch circuits 323 and 324, a delay circuit 325, an AND circuit 326, and a pulse width stretching circuit 327.
[0030]
The comparator 321 compares the integrated signal Si output from the equalizer filter 31 with a reference value (analog ground potential), and outputs an output signal S1 according to the comparison result.
The comparator 322 compares the differential signal Sd output from the equalizer filter 31 with a reference value (analog ground potential), and outputs an output signal S2 according to the comparison result.
[0031]
The latch circuit 323 inputs an output signal S1 from the comparator 321 to an input terminal (D) and inputs an output signal S2 from the comparator 322 to a clock terminal (C). That is, when the output signal S1 from the comparator 321 is at “H” level, the latch circuit 323 stores the “H” level state by the output signal S2 of the comparator 322.
[0032]
Further, the output signal S3 from the output terminal (Q) of the latch circuit 323 is directly supplied to one input terminal of the AND circuit 326, and is also delayed by the delay circuit 325 so that each reset terminal of the latch circuit 323, 324 ( R).
The latch circuit 324 receives the output signal S1 from the comparator 321 at a clock terminal (C) and applies a power supply voltage to an input terminal (D). The output signal S5 from the output terminal (Q) of the latch circuit 324 is supplied to the other input terminal of the AND circuit 326.
[0033]
The AND circuit 326 receives the output signal S3 from the output terminal (Q) of the latch circuit 323 and the output signal S5 from the output terminal (Q) of the latch circuit 324, and performs an AND operation on the two signals. This is a circuit that outputs a signal corresponding to the AND operation as an output signal S6.
The pulse width stretching circuit is a circuit that widens the pulse width of the output signal S6 from the AND circuit 326 and outputs the signal having the widened pulse width as the clock signal CLK2.
[0034]
Next, an example of the operation of the first embodiment having such a configuration will be described with reference to FIGS.
Now, it is assumed that the input signal In as shown in FIG. This input signal In is amplified by the variable gain amplifier 11 and supplied to the equalizer filter 31.
[0035]
As shown in FIGS. 2B and 2C, the equalizer filter 31 outputs an integrated signal Si obtained by integrating the input signal In and a differentiated signal Sd obtained by differentiating the input signal In.
The differential signal Sd and the integral signal Si are input to the clock generator 32 via the buffer circuits 13B and 13A. The clock generation unit 32 generates a clock CLK2 as shown in FIG. 2D based on the differential signal Sd and the integration signal Si as described later. The generated clock CLK2 is supplied as a reset signal to each reset terminal (R) of the latch circuits 25A to 28A, and is also supplied as a clock to the clock terminal (C) of the latch circuit 37.
[0036]
On the other hand, the integration signal Si from the equalizer filter 31 is supplied to the comparators 21 to 24 via the buffer circuit 13A and the smoothing circuit 14. The comparators 21 to 24 compare the integrated signal Si with each of the reference voltages V1 to V4, and output a signal corresponding to the comparison.
The output signals of the comparators 21 to 24 are stored in the corresponding latch circuits 25A to 28A. The signals stored in this manner become output signals A to D of the output terminals (Q) of the latch circuits 25A to 28A, and the output signals A to D are supplied to the addition circuit 36.
[0037]
The addition circuit 36 adds the output signals A to D and the output signal of the latch circuit 37, and outputs the addition result to the latch circuit 37. The latch circuit 37 captures the addition output from the addition circuit 36 at the timing when the clock CLK2 rises (see FIG. 2D), and outputs the captured data to the variable gain amplifier 11 as a gain control signal Sg.
[0038]
The variable gain amplifier 11 performs its own gain control according to the gain control signal Vg. As a result, regardless of the magnitude of the amplitude of the input signal In of the variable gain amplifier 11, the amplitude of the output signal that is the integrated signal Si of the equalizer filter 31 can be set to the target value.
Next, an operation in which the clock generation unit 32 generates the clock CLK2 will be described with reference to FIGS.
[0039]
Now, it is assumed that the integrated signal Si as shown in FIG. 4A is input to the comparator 321 in FIG. 3 and the differential signal Sd as shown in FIG. 4B is input to the comparator 322 in FIG.
The comparator 321 compares the integrated signal Si with the analog ground potential, and outputs an output signal S1 as shown in FIG. 4C according to the comparison result. Further, the comparator 322 compares the differential signal Sd with an analog ground potential, and outputs an output signal S2 as shown in FIG. 4D according to the comparison result.
[0040]
As shown in FIG. 4 (C), when the output signal S1 of the comparator 321 becomes “H” level, this is taken into the latch circuit 324, and the output signal S5 of the latch circuit 324 becomes “H” as shown in FIG. H ”level.
Further, as shown in FIG. 4D, when the output signal S2 of the comparator 322 becomes “H” level, the “H” level state of the output signal S2 of the comparator 321 is captured. Therefore, the output signal S3 of the latch circuit 323 becomes “H” level as shown in FIG.
[0041]
The output signal S3 of the latch circuit 323 is delayed by the delay circuit 325, and the output signal S4 of the delay circuit 325 becomes as shown in FIG. The output signal S4 of the delay circuit 325 is supplied as a reset signal to the reset terminals (R) of the latch circuits 323 and 324. Therefore, at the rise of the output signal S4, each of the output signals S3 and S5 of the latch circuits 323 and 324 becomes “L” level (see FIGS. 4E and 4G).
[0042]
On the other hand, since the output signals S3 and S5 of the latch circuits 323 and 324 are supplied to the AND circuit 326, the output signal S6 of the AND circuit 326 becomes as shown in FIG. Since the pulse width of the output signal S6 is expanded by the pulse width stretching circuit 326, the clock CLK2 output from the pulse width stretching circuit 326 becomes as shown in FIG.
[0043]
As described above, the clock generation unit 32 shown in FIG. 3 creates a window with the integrated signal Si and generates the clock CLK2 using this and the differential signal Sd. (See FIG. 4).
According to the clock generation unit 32 shown in FIG. 3, two or more clocks CLK2 are not generated in one window.
[0044]
Further, in the clock generation unit 32 shown in FIG. 3, the output signal of the AND circuit 326 has a short pulse width, but the pulse width is widened by the pulse width stretching circuit 327. The clock CLK2 can be obtained.
As described above, in this embodiment, in addition to the gain control unit 33, the clock generation unit 32 that generates a clock for operating the gain control unit 33 is provided. The signal is generated based on a differentiated signal obtained by differentiating the signal and an integrated signal obtained by integrating the output signal.
[0045]
Therefore, according to this embodiment, the output signal of the variable gain amplifier 11 can be quickly pulled to the target value, and the gain control is not performed when the input signal of the variable gain amplifier 11 is a defective signal. Can be
Further, in this embodiment, as the equalizer filter 31, a filter in which the integrated signal and the differential signal are simultaneously output from the input signal is used, so that the differential filter for obtaining the differential signal to be input to the clock generator 32 is used. There is an advantage that no circuit is required.
[0046]
【The invention's effect】
As described above, according to the present invention, the output signal of the variable gain amplifier can be quickly pulled to the target value, and the gain control is not performed when the input signal of the variable gain amplifier is a defective signal. It becomes possible to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of an automatic gain control circuit of the present invention.
FIG. 2 is a waveform chart showing an example of a signal waveform of a main part of the embodiment.
FIG. 3 is a circuit diagram illustrating a specific configuration example of a clock generation unit in FIG. 1;
FIG. 4 is a waveform diagram showing a waveform example of each unit of the clock generation unit.
FIG. 5 is a block diagram showing a configuration of a conventional automatic gain control circuit.
FIG. 6 is a block diagram showing a configuration of another conventional automatic gain control circuit.
FIG. 7 is an explanatory diagram illustrating a relationship between an output of a latch circuit and a gain of a variable gain amplifier corresponding thereto.
[Brief description of reference numerals]
11 Variable gain amplifiers 13A, 13B Buffer circuit 14 Smoothing circuit 21-24 Comparator 25A-28A Latch circuit 31 Equalizer filter 32 Clock generation unit 33 Gain control unit 35 Amplitude detection circuit 36 Addition circuit 37 Latch circuit

Claims (3)

Even if the amplitude of the input signal of the variable gain amplifier changes, an automatic gain control circuit that controls the gain of the variable gain amplifier so that the amplitude of the output signal becomes a target value,
A gain control unit that detects the amplitude of the output signal of the variable gain amplifier, and performs gain control of the variable gain amplifier according to the detection result;
The gain control unit includes a clock generation unit that generates a clock related to the timing of performing the gain control of the variable gain amplifier,
The automatic gain control circuit, wherein the clock generation section generates the clock based on a differential signal obtained by differentiating an output signal of the variable gain amplifier. 2. The automatic clock generator according to claim 1, wherein the clock generator generates the clock based on an integrated signal obtained by integrating an output signal of the variable gain amplifier, in addition to the differential signal. Gain control circuit. 3. The variable gain amplifier according to claim 1, wherein the variable gain amplifier includes a filter that outputs an integrated signal obtained by integrating an output signal of the variable gain amplifier and a differential signal obtained by differentiating the output signal. Automatic gain control circuit.

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