JP2004222251A - Digital amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a digital amplifier for suppressing a pop noise without using a mute circuit. <P>SOLUTION: A timing control circuit 131 generates select signals SEL1, SEL2 for outputting any one of music data, a center output and a least-significant output to a P output and an N output on the basis of a power supply on/off signal and a start/stop signal, and a select signal SEL4 for determining whether a signal of the same phase as the P output or a signal inverting the P output is outputted to the N output. On the basis of the select signals SEL1, SEL2, a data selector circuit 132 determines data to be outputted to the P output and the N output. An output data register circuit 133 converts parallel data which are determined by the data selector circuit 132, into serial data and outputs the data to the P output. On the basis of the select signal SEL4, an output selector circuit 134 determines the N output. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a digital amplifier for audio, and more particularly to a digital amplifier of a pulse width modulation (PWM) system.

  Devices that operate on batteries and include speakers, such as notebook computers, portable CD (Compact Disk) players, DVD (Digital Versatile Disc) players, and car audio, have become widespread. These devices are required to have not only high sound quality but also small size and low power. Against this background, digital amplifiers have attracted attention. Among them, a PWM (Pulse Width Modulation) type digital amplifier used for an audio preamplifier is configured by a digital circuit from input to output, and is capable of digitally processing all audio signals. In the PWM method, it is possible to convert the voltage amplitude of sound information into a digital pulse width and directly drive a speaker, and there is no need for analog processing. Therefore, it is possible to realize a small-sized amplifier with low power and small heat generation.

  However, when a PWM-type digital amplifier and a speaker are connected to a BTL (Bridge-Tied Load) that drives a load with two outputs of a positive polarity and a negative polarity, a pop sound is generated when the output of the digital amplifier changes rapidly. There was a problem.

  In order to improve such a problem, in the related art, a sawtooth wave having a frequency higher than the frequency of the carrier signal supplied to the pulse width modulation circuit and having a converted oscillation output synchronized with the carrier signal and a power supply voltage are applied. By comparing the level with the output of the time constant circuit and supplying the level comparison output and the output of the pulse width modulation circuit to the exclusive OR circuit, the two outputs are in phase at power-on and power-down. Thus, the generation of pop noise is suppressed (for example, see Patent Document 1).

JP 06-196940 A

  However, in the related art, when the phase of the output of the exclusive OR is in the transition state, the audio signal output to the load is distorted. In order to suppress the distortion, there is a problem that the mute must be applied for a certain period during which the phase of the output of the exclusive OR is transitioning.

  In addition, since an integrating circuit and a time constant circuit are used, there is also a problem that processing cannot be performed using only digital signals.

  The present invention has been made in view of the above, and has as its object to obtain a digital amplifier that suppresses pop noise without using a mute circuit.

  In order to solve the above-described problems and achieve the object, a digital amplifier according to the present invention uses pulse width modulation of n (n> 1, where n is an integer) bit sound data from which quantization noise has been removed by a noise shaper. In a digital amplifier that outputs two systems of a P output and an N output with the polarity of the P output inverted, when a power-on is detected, a sound data stop is detected, or a power-down is detected. Comprises a data selection circuit for increasing or decreasing the P output and the N output by one step every period of a data setting clock obtained by dividing the basic clock of pulse width modulation by n and fixing the output to a center output. I do.

  According to the present invention, the data selection circuit switches the P output and the N output to the pulse width modulation basic clock when detecting the power-on, when detecting the sound data stop, or when detecting the power-down. Each time the frequency of the data setting clock divided by n is increased or decreased by one step, the output is fixed to the center output.

  According to the digital amplifier of the present invention, the data selection circuit performs pulse width modulation on the P output and the N output when detecting the power-on, when detecting the sound data stop, or when detecting the power-down. Is increased or decreased by one step for each cycle of the data setting clock obtained by dividing the basic clock by n and fixed to the center output. This makes it possible to suppress a sudden change in the P output and the N output at the start of the sound data, and to suppress the occurrence of pop noise without using a mute circuit.

  Hereinafter, embodiments of a digital amplifier according to the present invention will be described in detail with reference to the drawings. It should be noted that the present invention is not limited by the embodiment.

  An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a digital amplifier 1 according to an embodiment of the present invention and a configuration of an audio system to which the digital amplifier 1 is applied. In the audio system using the digital amplifier 1 according to this embodiment, the bridge pre-driver 20 in the BTL circuit 2 is based on the P output and the N output generated by the digital amplifier 1, and the switching element 21 includes two transistors. And the output of the switching element 21 from which the high-frequency component has been removed by the low-pass filter 3 composed of a coil and a capacitor drives the speaker 4.

  The digital amplifier 1 outputs a value of (n + 1) with respect to the number n of basic clocks (n> 1, where n is an integer) determined by the number of bits of sound data output from the noise shaper 12. Since the BTL circuit 2 operates with a differential input, the pulse width modulation circuit 13 has two outputs, a P output and an N output with the polarity of the P output inverted. A case where the P output is half of the number n of the basic clocks, ie, “1” for n / 2 basic clocks, is defined as the center output of the digital amplifier 1.

  FIG. 2 shows the P output and the N output of the digital amplifier 1 when the number n of the basic clocks is eight. If the number of basic clocks is 8, the P output that has a period of "1" for four basic clocks is defined as a center output "0". If the period is "1" for five basic clocks, "+1". In the case of a period of “1” for six clocks, it becomes “+2”. Further, when the P output has a period of “1” for three basic clocks, it is “−1”, and when the P output has a period of “1” for two basic clocks, it is “−2”. The digital amplifier 1 outputs nine stages from the lowest output of “−4” to the highest output of “+4” by changing the pulse widths of the P output and the N output, and outputs the speaker 4 via the BTL circuit 2. To generate sound.

  The digital amplifier 1 includes a sampling rate converter 10, a volume circuit 11, a noise shaper 12, and a pulse width modulation circuit 13. The sampling rate converter 10 converts a digital signal recorded on a CD (Compact Disk), MD (Mini Disk), DVD (Digital Versatile Disc) or the like at a specific sampling rate to a sampling frequency different from the sampling rate at the time of recording. Convert. The volume circuit 11 adjusts the volume of the digital signal based on the external designation. The noise shaper 12 removes quantization noise. The pulse width modulation circuit 13 performs a pulse width modulation process based on the sound data from which the quantization noise has been removed by the noise shaper 12.

  FIG. 3 is a diagram showing the P output and the N output of the pulse width modulation circuit 13 and the output of the BTL circuit 2 when the power is turned on. When the power is turned on, the pulse width modulation circuit 13 outputs the P output and the N output as in-phase signals. That is, current is prevented from flowing through the BTL circuit 2 that operates with differential input, and no sound is generated from the speaker 4. Further, the pulse width modulation circuit 13 changes the P output and the N output in the order of -4, -3, -2, -1, and 0 from the time of power-on, and changes the P output and the N output one step at a time, and fixes the output to the center output. I do. Thus, the output of the BTL circuit 2 changes gradually and is fixed at the center.

  When the P output and the N output are fixed to the center output, the pulse width modulation circuit 13 switches the N output from a signal having the same phase as the P output to a signal obtained by inverting the P output.

  When the sound data starts, the pulse width modulation circuit 13 performs a pulse width modulation process based on the sound data input from the noise shaper 12, and outputs a P output and an N output to the BTL circuit 2. The BTL circuit 2 drives the speaker 4 based on the P output and the N output to generate a sound.

  FIG. 4 is a diagram showing the P output and the N output of the pulse width modulation circuit 13 and the output of the BTL circuit 2 when the sound data stops and starts. The pulse width modulation circuit 13 performs pulse width modulation processing based on the sound data input from the noise shaper 12 until the sound data stops, and outputs a P output and an N output to the BTL circuit 2. The BTL circuit 2 drives the speaker 4 based on the P output and the N output to generate a sound.

  When the sound data is stopped by the stop function or the temporary stop function of the digital amplifier 1, the pulse width modulation circuit 13 changes the P output to the center output by changing the sound data one step at a time from the value at the time of the stop. That is, when the P output and the N output are +1 to +4 shown in FIG. 2, the output is decreased by one step to the center output, and when the P output and the N output are -1 to -4, the step is one step. Increase to center output. As a result, the output of the BTL circuit 2 changes gradually and is fixed at the center.

  When sound data is started by the reproduction function of the digital amplifier 1, the pulse width modulation circuit 13 performs pulse width modulation processing based on the sound data input from the noise shaper 12, and outputs a P output and an N output to the BTL circuit 2. I do. The BTL circuit 2 drives the speaker 4 based on the P output and the N output to generate a sound.

  FIG. 5 is a diagram showing the P output and the N output of the pulse width modulation circuit 13 and the output of the BTL circuit 2 when the power is turned off. The pulse width modulation circuit 13 performs pulse width modulation processing based on the sound data input from the noise shaper 12 until the sound data stops, and outputs a P output and an N output to the BTL circuit 2. The BTL circuit 2 drives the speaker 4 based on the P output and the N output to generate a sound.

  Upon detecting the power-down, the pulse width modulation circuit 13 changes the P output to the center output by sequentially changing the sound data one step at a time from the value at the time of the stop. That is, when the P output and the N output are +1 to +4 shown in FIG. 2, the output is decreased by one step to the center output, and when the P output and the N output are -1 to -4, the step is one step. Increase to center output. As a result, the output of the BTL circuit 2 changes gradually and is fixed at the center.

  When the P output and the N output are fixed to the center output, the pulse width modulation circuit 13 switches the N output from an inverted signal of the P output to a signal having the same phase as the P output. Then, the pulse width modulation circuit 13 decreases the P output from the center output one step at a time to “-4”.

  FIG. 6 is a block diagram showing a configuration of the pulse width modulation circuit 13. The pulse width modulation circuit 13 includes a timing control circuit 131, a data selection circuit 132, an output data register circuit 133, and an output selection circuit 134.

  The timing control circuit 131 generates the data setting clock CLK8 and the selection signals SEL0 to SEL4 based on the clock CLK, the power ON / OFF signal, and the start / stop signal. Then, the selection signals SEL0 to SEL2 and the data setting clock CLK8 are output to the data selection circuit 132, the selection signal SEL3 is output to the output data register circuit 133, and the selection signal SEL4 is output to the output selection circuit 134, respectively.

  The data selection circuit 132 selects either 8-bit sound data DATA0 to 7 input from the noise shaper 12 or predetermined data for removing a pop sound based on the selection signals SEL0 to SEL2, and selects the selected output. PWM0 to PWM7 are output to the output data register circuit 133.

  FIG. 7 is a diagram showing an example of a circuit of the data selection circuit 132 shown in FIG. The data selection circuit 132 includes an IV 41 as an inversion circuit, ANDs 50 to 65 as AND gates, selectors 70 to 73 as selection circuits, and flip-flops with a set function 80 to 87. When the selection signal SEL0 is "1" and the selection signal SEL1 is "1", the output of the AND 65 becomes "1", and the ANDs 50 to 57 select the sound data DATA0 to 7 and supply the sound data DATA0 to 7 to the flip-flops 80 to 87 with the set function. Set DATA0-7. Thereby, the data selection circuit 132 outputs the sound data DATA0 to 7 to the output PWMs 0 to 7.

  The selection signal SEL2 is valid when the selection signal SEL1 is "0". When the selection signal SEL1 is “0” and the selection signal SEL2 is “1”, the flip-flops with a set function 80 to 87 are connected in the order of the flip-flops with a set function 80, 81, 82,. 8 shift registers that shift data at the rising edge of. Since the fixed value “0” is input to the terminal D of the flip-flop 80 with the set function, if the outputs PWM7 to 0 are “111110000” by the shift operation, for example, “1111100000”, “11100000”, .., "00000000". That is, the values of the output PWMs 7 to 0 are changed one step at a time to “00000000”.

  When the selection signal SEL1 is “0” and the selection signal SEL2 is “0”, the flip-flops with a set function 80 to 83 are connected in the order of the flip-flops with a set function 80, 81, 82, 83, and A four-stage shift register that shifts data at the rising edge is configured. The flip-flops with a set function 84 to 87 are connected in the order of the flip-flops with a set function 87, 86, 85, 84, and constitute a four-stage shift register that shifts data at the rise of the data setting clock CLK 8. Since “1” is input to the terminal D of the flip-flop 87 with the set function, the outputs PWM 7 to 4 change to “1000”, “1100”, “1110”, “1111”. Also, since “0” is input to the terminal D of the flip-flop 80 with the set function, the outputs PWM3 to 0 become “0000”. That is, when the selection signal SEL1 is "0" and the selection signal SEL2 is "0", the outputs PWM7-0 are changed one step at a time to have the value of the center output.

  The output data register circuit 133 latches the outputs PWM0 to 7 of the data selection circuit 132 based on the selection signal SEL3, and synchronizes the latched outputs PWM0 to 7 with the outputs PWM0, PWM1,. It is output as a P output signal bit by bit. That is, the parallel outputs PWM0 to PWM7 latched based on the selection signal SEL3 are converted into serial data.

  FIG. 8 is a diagram showing an example of the output data register circuit 133 shown in FIG. The output data register circuit 133 includes flip-flops 90 to 97 with a selector function. The flip-flops with selector function 90 to 97 select the data input to the terminal D2 when the terminal SEL is “1” and select the data input to the terminal D1 when the terminal SEL is “0”. , And output in synchronization with the rise of the terminal CK.

  The flip-flops with a selector function 90 to 97 are connected in order of the flip-flops with a selector function 97, 96, 95,... 90, and constitute an eight-stage shift register that shifts data in synchronization with the rise of the clock CLK.

  The output selection circuit 134 selects, based on the selection signal SEL4, whether to output the P output signal as it is as the N output signal or to use a signal obtained by inverting the P output signal as the N output signal. That is, it selects whether the N output should be a signal having the same phase as the P output or a signal obtained by inverting the P output.

  Next, the operation of the pulse width modulation circuit 13 will be described with reference to the time charts of FIGS. First, a normal operation will be described with reference to a time chart of FIG.

  The timing control circuit 131 sets the selection signal SEL1 to “1”, the selection signal SEL2 to “0”, and the selection signal SEL4 to the normal operation of outputting the sound data DATA7 to 0 input from the noise shaper 12. Set to “1”. In addition, it outputs a data setting clock CLK8 obtained by dividing the clock CLK by 8 in synchronization with the falling of the clock CLK. The sound data DATA7 to DATA0 are input in synchronization with the falling edge of the clock CLK every eight cycles of the clock CLK. The timing control circuit 131 outputs the data setting clock CLK8 such that the data setting clock CLK8 rises seven cycles of the clock CLK from the transition point of the sound data DATA7 to DATA0. The timing control circuit 131 sets the selection signal SEL0 to “1” for one cycle of the clock CLK in synchronization with the rising of the clock CLK 1.5 cycles after the rising of the data setting clock CLK8 from the rising of the data setting clock CLK8 every cycle of the data setting clock CLK8. 1 ”. That is, the selection signal SEL0 becomes “1” for one cycle of the clock CLK after a half cycle of the clock CLK from the change point of the sound data DATA7 to DATA0. Further, the timing control circuit 131 outputs the selection signal SEL3 for one cycle of the clock CLK in synchronization with the fall of the clock CLK one cycle after the clock CLK from the rise of the data set clock CLK8 every cycle of the data set clock CLK8. Set to “0”. That is, the selection signal SEL3 becomes "0" for one cycle of the clock CLK from the change point of the sound data DATA7-0. The timings of the data setting clock CLK8, the selection signals SEL0 to SEL2, and the data setting clock CLK8 are based on the timing constraints (recovery time, removal time, setup time, hold time, pulse It is assumed that the selection signal SEL3 is generated so as to satisfy the timing constraint conditions of the flip-flops with selector function 90 to 97.

  At time t1, the sound data DATA7-0 changes to "11100000". At time t2, the selection signal SEL0 becomes “1”. Since the selection signal SEL0 is “1” and the selection signal SEL1 is “1”, the output of the AND 65 becomes “1”, and the ANDs 50 to 57 set the sound data DATA7 to 0 to the flip-flops 87 to 80 with a set function. Is output to the terminal S. As a result, "1" is input to the terminals S of the flip-flops with a set function 87 to 85, "0" is input to the terminals S of the flip-flops 84 to 80 with a set function, and the PWMs 7 to 0 become "11100000". . That is, sound data DATA7-0 are output to PWM7-0.

  Further, since the selection signal SEL3 is “0”, the flip-flops with selector function 97 to 90 latch the outputs PWM7 to 0. Then, the value of the output PWM0 (in this case, “0”) is output to the P output. At time t3, which is the next rising of the clock CLK, the selection signal SEL3 is "1", so that the grip flops 97 to 90 with the selector function operate as shift registers. That is, the P output is set to “0”, “0”, “0”, “0”, “0”, “1”, “1”, “1” in synchronization with the rise of the clock until time t4b.

  Since the selection signal SEL4 is “1”, the output selection circuit 134 outputs a signal obtained by inverting the P output to the N output.

  At time t4a, the data setting clock CLK8 changes from “0” to “1”. At this time, since the selection signal SEL0 is “0”, the output of the AND 65 is “0”. Therefore, the ANDs 50 to 57 output “0” to the terminals S of the flip-flops 87 to 80 with the set function. Further, since the selection signal SEL1 is “1”, “0” is input to the ANDs 58 to 64 via the IV 41, and “0” is input to the terminals D of the flip-flops 81 to 87 with the set function. The terminal D of the flip-flop with a set function 80 is fixed to “0”. The flip-flops with a set function 80 to 87 latch “0” input to the terminal D at the rising edge when the data setting clock CLK8 changes from “0” to “1” because the terminal S is “0”. And output. As a result, the outputs of the flip-flops with a set function 80 to 87 all become "0", which means that the sound data DATA7 to 0 set at the time t2 have been reset.

  The data selection circuit 132 and the output data register circuit 133 repeat such operations, and output the sound data DATA7 to 0 input from the noise shaper 12 to the P output and the N output.

  Next, the operation of the pulse width modulation circuit 13 when the power is turned on will be described with reference to the time chart of FIG. The timing control circuit 131 sets the selection signals SEL1, SEL2, SEL4 to "0" when detecting that the power is turned on by the power ON / OFF signal. In addition, it outputs a data setting clock CLK8 obtained by dividing the clock CLK by 8 in synchronization with the falling of the clock CLK. The timing control circuit 131 sets the selection signal SEL0 to “1” for one cycle of the clock CLK in synchronization with the rise of the clock CLK every cycle of the data setting clock CLK8. In addition, the selection signal SEL3 is set to “0” for one cycle of the clock CLK in synchronization with the fall of the clock CLK every cycle of the data setting clock CLK8.

  Since the selection signal SEL1 is "0", the output of the AND 65 becomes "0", and the ANDs 50 to 57 output "0" to the terminals S of the flip-flops 80 to 87 with the set function. Thus, the flip-flops with a set function 80 to 87 latch the data input to the terminal D at the rising edge of the clock input to the terminal CK and output the latched data. Since the selection signal SEL2 is “0”, the flip-flops with a set function 87 to 84 operate as four-stage shift registers.

  At time t5, when the data setting clock CLK8 rises, the flip-flops with a set function 80 to 83 shift data. The flip-flops with a set function 87 to 84 also shift data. Since the flip-flop 80 with the set function latches “0” and the flip-flop 87 with the set function latches “1”, the output PWMs 7 to 0 become “10000000”.

  At time t6, since the selection signal SEL3 is “0”, the flip-flops with selector function 97 to 90 latch the outputs PWM7 to 0. Then, the value of the output PWM0 (in this case, “0”) is output to the P output. At time t7, which is the next rising of the clock CLK, the selection signal SEL3 is “1”, so that the flip-flops 97 to 90 with the selector function operate as shift registers. That is, the P output is set to “0”, “0”, “0”, “0”, “0”, “0”, “0”, “1” in synchronization with the rise of the clock until time t9.

  At time t8, since the selection signals SEL1 and SEL2 have not changed from time t5, the data selection circuit 132 performs the same operation as at time t5. That is, when the data setting clock CLK8 rises, the flip-flops with a set function 80 to 83 shift data. The flip-flops with a set function 87 to 84 also shift data. Since the flip-flop 80 with the set function latches “0” and the flip-flop 87 with the set function latches “1”, the output PWMs 7 to 0 become “11000000”.

  At time t9, the flip-flops with selector function 97 to 90 perform the same operation as at time t6 to latch the outputs PWM7 to PWM0. .., 7 in synchronization with the rise of the clock CLK. That is, the P output is set to “0”, “0”, “0”, “0”, “0”, “0”, “1”, “1” in synchronization with the rise of the clock.

  The data selection circuit 132 and the output data register circuit 133 repeat such an operation until time t11 when the selection signal SEL1 becomes "1", and changes the P output one step at a time to fix it at the center output.

  Until time t10, since the selection signal SEL4 is "0", the output selection circuit 134 outputs a signal having the same phase as the P output to the N output.

  At time t10, the timing control circuit 131 sets the selection signal SEL4 to “1”. That is, the timing control circuit 131 sets the selection signal SEL4 to “1” after the P output is fixed to the center output (in this case, four cycles or more from the first rising of the data setting clock CLK8).

  When the selection signal SEL4 becomes “1”, the output selection circuit 134 outputs a signal obtained by inverting the P output to the N output.

  After setting the selection signal SEL4 to "1", the timing control circuit 131 sets the selection signal SEL1 to "1" at a predetermined timing. In the case of the timing chart of FIG. 10, the timing control circuit 131 sets the selection signal SEL1 to "1" at time t11. That is, after the P output is fixed to the center output, the timing control circuit 131 sets the selection signal SEL4 to "1", changes the N output to a signal obtained by inverting the P output, sets the selection signal SEL1 to "1", and sets the selection signal SEL1 to "1". To As a result, the P output and the N output are outputs based on the sound data DATA7 to DATA0.

  Next, the operation of the pulse width modulation circuit 13 when the sound data is temporarily stopped and the reproduction is started will be described with reference to FIG. Until time t12, the pulse width modulation circuit 13 operates normally. That is, the pulse width modulation circuit 13 outputs a P output and an N output based on the sound data DATA7 to DATA0.

  At time t12, when detecting the stop of the sound data by the start / stop signal, the timing control circuit 131 sets the selection signal SEL1 to “0”.

  While the selection signal SEL1 is “0”, the output of the AND 65 is “0” without being affected by the selection signal SEL0, and the ANDs 50 to 57 are connected to the terminals S of the flip-flops 80 to 87 with the set function by “0”. Is output. Thus, the flip-flops with a set function 80 to 87 latch the data input to the terminal D at the rising edge of the clock input to the terminal CK and output the latched data. Since the selection signal SEL2 is “0”, the flip-flops with a set function 87 to 84 operate as four-stage shift registers.

  At time t13, when the data setting clock CLK8 rises, the flip-flops with a set function 80 to 83 shift data. The flip-flops with a set function 87 to 84 also shift data. The output PWM7-0 immediately before is "11000000", the flip-flop 80 with set function latches "0", and the flip-flop 87 with set function latches "1", so that the output PWM7-0 becomes "11100000". .

  At time t14, since the selection signal SEL3 is "0", when the clock CLK rises, the flip-flops with selector function 97 to 90 latch the outputs PWM7 to 0. Then, the value of the output PWM0 (in this case, “0”) is output to the P output. At time t15, which is the next rising of the clock CLK, the selection signal SEL3 is "1", so that the flip-flops 97 to 90 with the selector function operate as shift registers. That is, the P output is set to “0”, “0”, “0”, “0”, “0”, “1”, “1”, “1” in synchronization with the rise of the clock until time t17.

  At time t17, the flip-flops with selector function 97 to 90 perform the same operation as at time t4b to latch the outputs PWM7 to PWM0. .., 7 in synchronization with the rise of the clock CLK. That is, the P output is set to “0”, “0”, “0”, “0”, “1”, “1”, “1”, “1” in synchronization with the rise of the clock.

  The data selection circuit 132 and the output data register circuit 133 repeat such an operation until time t18 when the selection signal SEL1 becomes "1", and changes the P output one step at a time to fix it at the center output. During this time, since the selection signal SEL4 is “1”, the output selection circuit 134 outputs a signal obtained by inverting the P output to the N output.

  At time t18, when detecting the start of the sound data by the start / stop signal, the timing control circuit 131 sets the selection signal SEL1 to “1”. As a result, the normal operation mode is set, and the P output and the N output based on the sound data DATA7 to DATA0 are obtained.

  Next, the operation of the pulse width modulation circuit 13 when the power is turned off will be described with reference to the time chart of FIG. Until time t19, the pulse width modulation circuit 13 operates normally. That is, the pulse width modulation circuit 13 outputs a P output and an N output based on the sound data DATA7 to DATA0.

  At time t19, the timing control circuit 131 sets the selection signal SEL1 to "0" when the power ON / OFF signal changes from "0" to "1", that is, when detecting that the power has fallen.

  While the selection signal SEL1 is “0”, the output of the AND 65 is “0” without being affected by the selection signal SEL0, and the ANDs 50 to 57 are connected to the terminals S of the flip-flops 80 to 87 with the set function by “0”. Is output. Thus, the flip-flops with a set function 80 to 87 latch the data input to the terminal D at the rising edge of the clock input to the terminal CK and output the latched data. Since the selection signal SEL2 is “0”, the flip-flops with a set function 87 to 84 operate as four-stage shift registers.

  At time t20, when the data setting clock CLK8 rises, the flip-flops with a set function 80 to 83 shift data. The flip-flops with a set function 87 to 84 also shift data. The output PWM7-0 immediately before is "11100000", the flip-flop 80 with set function latches "0", and the flip-flop 87 with set function latches "1", so that the output PWM7-0 becomes "111110000". .

  At time t21, since the selection signal SEL3 is "0", when the clock CLK rises, the flip-flops with selector function 97 to 90 latch the outputs PWM7 to 0. Then, the value of the output PWM0 (in this case, “0”) is output to the P output. At time t22, which is the next rising of the clock CLK, the selection signal SEL3 is “1”, so that the flip-flops 97 to 90 with the selector function operate as shift registers. That is, the P output is set to “0”, “0”, “0”, “0”, “1”, “1”, “1”, “1” in synchronization with the rise of the clock.

  At time t23, the timing control circuit 131 sets the selection signal SEL4 to “0”. That is, the timing control circuit 131 sets the selection signal SEL4 to "0" after the P output is fixed to the center output (in this case, four cycles or more from the first rise of the data setting clock CLK8).

  When the selection signal SEL4 becomes “0”, the output selection circuit 134 outputs a signal having the same phase as the P output to the N output.

  The timing control circuit 131 sets the selection signal SEL2 to "1" at time t24 after setting the selection signal SEL4 to "0". Since the selection signal SEL1 is “0”, when the selection signal SEL2 becomes “1”, the flip-flops with a set function 80 to 87 become eight-stage shift registers.

  At time t25, when the data setting clock CLK8 rises, the flip-flops with a set function 80 to 87 shift data. Since the flip-flop 80 with the set function latches “0”, the output PWMs 7 to 0 become “11100000”.

  At time t26, since the selection signal SEL3 is "0", when the clock CLK rises, the flip-flops with selector function 97 to 90 latch the outputs PWM7 to 0. Then, the value of the output PWM0 (in this case, “0”) is output to the P output. At time t27, which is the next rising of the clock CLK, the selection signal SEL3 is “1”, so that the flip-flops 97 to 90 with the selector function operate as shift registers. That is, the P output is set to "0", "0", "0", "0", "0", "1", "1", "1" in synchronization with the rise of the clock.

  The data selection circuit 132 and the output data register circuit 133 repeat such an operation to change the P output one step at a time to “−4” (see FIG. 2).

  Thus, in this embodiment, when the power is turned on, the N output is output in the same phase as the P output, and the N output and the P output are changed one step at a time to be fixed at the center output. After being fixed to the center output, the N output is switched to an output in which the polarity of the P output is inverted. As a result, the BTL circuit driven by the digital amplifier rises smoothly and can be changed to the center output without generating noise. Since the sound data starts from the center output, the pop-up can be performed without using the mute circuit. The reproduction of the sound data can be started by removing the noise.

  When the power supply is turned off, the P output and the N output are changed one step at a time and fixed at the center output, and then the N output is output in the same phase as the P output, and the P output and the N output are decreased one step at a time. Since the lowest output is used, pop noise can be reduced.

  Further, when the sound data is stopped, the P output and the N output are changed one step at a time to be fixed to the center output. That is, the P output and the N output are set to be center outputs. This makes it possible to suppress the occurrence of a sudden change at the start of sound data without using a mute circuit, and to start reproduction of sound data without generating pop noise.

  Note that a clock of a noise shaper may be used instead of the data setting clock. Thus, the P output and the N output can be changed to the center output or the lowest output in synchronization with the noise shaper, and the pop noise can be further suppressed.

  The circuit driven by the digital amplifier of the present invention is not limited to the BTL circuit, but may be any circuit driven by a differential input such as an operational amplifier circuit or a filter circuit.

  As described above, the digital amplifier according to the present invention is useful for a pulse width modulation type digital amplifier, and is particularly suitable for a case where a digital amplifier and a speaker are used in a BTL connection.

FIG. 1 is a block diagram illustrating a configuration of a digital amplifier according to an embodiment of the present invention and a configuration of an audio system to which the digital amplifier is applied. FIG. 3 is a diagram illustrating a P output and an N output of a digital amplifier. FIG. 4 is a diagram illustrating P output and N output of a pulse width modulation circuit and output of a BTL circuit at power-on. FIG. 7 is a diagram showing P and N outputs of a pulse width modulation circuit and outputs of a BTL circuit when sound data stops and starts. FIG. 4 is a diagram illustrating P output and N output of a pulse width modulation circuit and output of a BTL circuit at the time of power-down. FIG. 3 is a block diagram illustrating a configuration of a pulse width modulation circuit. FIG. 3 is a diagram illustrating an example of a data selection circuit. FIG. 3 is a diagram illustrating an example of an output data register circuit. 5 is a time chart for explaining an operation of the pulse width modulation circuit during a normal operation. 5 is a time chart for explaining an operation of the pulse width modulation circuit at the time of power-on. 6 is a time chart for explaining the operation of the pulse width modulation circuit when sound data stops and starts. 5 is a time chart for explaining the operation of the pulse width modulation circuit when the power is turned off.

Explanation of reference numerals

Reference Signs List 1 digital amplifier 2 BTL circuit 3 low-pass filter 4 speaker 10 sampling rate converter 11 volume circuit 12 noise shaper 13 pulse width modulation circuit 20 bridge pre-driver 21 switching element 41 inverting circuit 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65 AND gate 70, 71, 72, 73 Selector 80, 81, 82, 83, 84, 85, 86, 87 Flip with set function 90, 91, 92, 93, 94, 95, 96, 97 Flip-flop with selector function 131 Timing control circuit 132 Data selection circuit 133 Output data register circuit 134 Output selection circuit

Claims (5)

Pulse width modulation of n (n> 1, n is an integer) -bit sound data from which quantization noise has been removed by the noise shaper is pulse-width-modulated to output two systems: a P output and an N output in which the polarity of the P output is inverted. In digital amplifiers,
When a power-on is detected, when a sound data stop is detected, or when a power-down is detected, a cycle of a data setting clock obtained by dividing the P output and the N output by n from a pulse width modulation basic clock. A data selection circuit that increases or decreases by one step every time and is fixed at the center output,
A digital amplifier comprising: The data selection circuit includes:
When the power-down is detected, the P output and the N output are fixed to the center output, and then the P output and the N output are reduced by one stage at every cycle of the data setting clock, and the lowest output is output. 2. The digital amplifier according to claim 1, wherein the digital amplifier is fixed to the digital amplifier. When the power supply is detected, a signal having the same phase as the P output is output to the N output. After fixing the P output and the N output to the center output, a signal obtained by inverting the polarity of the P output to the N output is output. Output selection circuit to output,
The digital amplifier according to claim 1, further comprising: The output selection circuit includes:
4. The digital amplifier according to claim 3, wherein a signal in phase with the P output is output to the N output after fixing the P output and the N output to a center output upon detecting a power supply fall. 5.   The digital amplifier according to claim 1, wherein a clock of the noise shaper is used instead of the data setting clock.

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