JP2004030884A5 - - Google Patents
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- Publication number
- JP2004030884A5 JP2004030884A5 JP2003126443A JP2003126443A JP2004030884A5 JP 2004030884 A5 JP2004030884 A5 JP 2004030884A5 JP 2003126443 A JP2003126443 A JP 2003126443A JP 2003126443 A JP2003126443 A JP 2003126443A JP 2004030884 A5 JP2004030884 A5 JP 2004030884A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/138,074 US6762952B2 (en) | 2002-05-01 | 2002-05-01 | Minimizing errors in a magnetoresistive solid-state storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004030884A JP2004030884A (ja) | 2004-01-29 |
| JP2004030884A5 true JP2004030884A5 (ja) | 2006-06-15 |
Family
ID=29249762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003126443A Pending JP2004030884A (ja) | 2002-05-01 | 2003-05-01 | 磁気抵抗固体記憶素子における誤りを最小限にする方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6762952B2 (ja) |
| JP (1) | JP2004030884A (ja) |
| FR (1) | FR2839380B1 (ja) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100988087B1 (ko) * | 2003-11-24 | 2010-10-18 | 삼성전자주식회사 | Ｍｒａｍ 특성 분석 장치 및 그 분석 방법 |
| US7027323B2 (en) * | 2004-04-02 | 2006-04-11 | Hewlett-Packard Development Company, L.P. | Storage device having parallel connected memory cells that include magnetoresistive elements |
| US7362549B2 (en) * | 2004-05-19 | 2008-04-22 | Seagate Technology Llc | Storage device having first and second magnetic elements that interact magnetically to indicate a storage state |
| WO2006080908A1 (en) * | 2005-01-25 | 2006-08-03 | Chien-Chiang Chan | A single chip having a magnetoresistive memory |
| JP2008090451A (ja) * | 2006-09-29 | 2008-04-17 | Toshiba Corp | 記憶装置 |
| US20080198674A1 (en) * | 2007-02-21 | 2008-08-21 | Jan Keller | Method of testing an integrated circuit, method of determining defect resistivity changing cells, testing device, and computer program adapted to perform a method for testing an integrated circuit |
| US8406033B2 (en) * | 2009-06-22 | 2013-03-26 | Macronix International Co., Ltd. | Memory device and method for sensing and fixing margin cells |
| WO2011030410A1 (ja) * | 2009-09-09 | 2011-03-17 | 株式会社 東芝 | メモリ装置 |
| US8634235B2 (en) | 2010-06-25 | 2014-01-21 | Macronix International Co., Ltd. | Phase change memory coding |
| US8374019B2 (en) | 2011-01-05 | 2013-02-12 | Macronix International Co., Ltd. | Phase change memory with fast write characteristics |
| US8891293B2 (en) | 2011-06-23 | 2014-11-18 | Macronix International Co., Ltd. | High-endurance phase change memory devices and methods for operating the same |
| US8923041B2 (en) * | 2012-04-11 | 2014-12-30 | Everspin Technologies, Inc. | Self-referenced sense amplifier for spin torque MRAM |
| US9001550B2 (en) | 2012-04-27 | 2015-04-07 | Macronix International Co., Ltd. | Blocking current leakage in a memory array |
| US8964442B2 (en) | 2013-01-14 | 2015-02-24 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
| US9552244B2 (en) | 2014-01-08 | 2017-01-24 | Qualcomm Incorporated | Real time correction of bit failure in resistive memory |
| US9779810B2 (en) | 2015-09-11 | 2017-10-03 | Macronix International Co., Ltd. | Adjustable writing circuit |
| US10817392B1 (en) * | 2017-11-01 | 2020-10-27 | Pure Storage, Inc. | Ensuring resiliency to storage device failures in a storage system that includes a plurality of storage devices |
| JP2022050059A (ja) | 2020-09-17 | 2022-03-30 | キオクシア株式会社 | 磁気記憶装置及びメモリシステム |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2870523B2 (ja) * | 1997-06-25 | 1999-03-17 | 日本電気株式会社 | メモリモジュール |
| US6011734A (en) * | 1998-03-12 | 2000-01-04 | Motorola, Inc. | Fuseless memory repair system and method of operation |
| US6910152B2 (en) * | 1998-08-28 | 2005-06-21 | Micron Technology, Inc. | Device and method for repairing a semiconductor memory |
| US5953269A (en) * | 1998-09-03 | 1999-09-14 | Micron Technology, Inc. | Method and apparatus for remapping addresses for redundancy |
| US6041000A (en) * | 1998-10-30 | 2000-03-21 | Stmicroelectronics, Inc. | Initialization for fuse control |
| US6154413A (en) * | 1999-04-05 | 2000-11-28 | Longwell; Michael L. | Method for designing a memory tile for use in a tiled memory |
| US6297983B1 (en) * | 2000-02-29 | 2001-10-02 | Hewlett-Packard Company | Reference layer structure in a magnetic storage cell |
| DE10043218C2 (de) * | 2000-09-01 | 2003-04-24 | Infineon Technologies Ag | Schaltungsanordnung und Verfahren zur Alterungsbeschleunigung bei einem MRAM |
| JP3667244B2 (ja) * | 2001-03-19 | 2005-07-06 | キヤノン株式会社 | 磁気抵抗素子、それを用いたメモリ素子、磁気ランダムアクセスメモリ及び磁気ランダムアクセスメモリの記録再生方法 |
| JP5119563B2 (ja) * | 2001-08-03 | 2013-01-16 | 日本電気株式会社 | 不良メモリセル救済回路を有する半導体記憶装置 |
| US6545906B1 (en) * | 2001-10-16 | 2003-04-08 | Motorola, Inc. | Method of writing to scalable magnetoresistance random access memory element |
| US6906396B2 (en) * | 2002-01-15 | 2005-06-14 | Micron Technology, Inc. | Magnetic shield for integrated circuit packaging |
| US6735111B2 (en) * | 2002-01-16 | 2004-05-11 | Micron Technology, Inc. | Magnetoresistive memory devices and assemblies |
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2002
- 2002-05-01 US US10/138,074 patent/US6762952B2/en not_active Expired - Lifetime
-
2003
- 2003-04-23 FR FR0304960A patent/FR2839380B1/fr not_active Expired - Lifetime
- 2003-05-01 JP JP2003126443A patent/JP2004030884A/ja active Pending