JP2004030339A - Clock distribution circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To distribute a clock to a circuit which performs two-way data transmission through a data transmission line without being restricted by the length and transmission frequency of the data transmission line in . <P>SOLUTION: A clock transmission line 41 for transmitting the clock to data transmission circuits 1 and 2 has the same characteristic as that of the data transmission line 3, one end of the clock transmission line 41 is connected to an input-output port P1 of a clock transmission control part 42, and the other end is connected to an input-output port P2 of the clock transmission control part 42 via a clock input port 15 of the data transmission circuit 1 and a clock input port 25 of the data transmission circuit 2. The length of the clock transmission line between the clock input ports 15 and 25 is set in the same length as that of the data transmission line 3. The clock transmission control part 42 transmits the clock to the clock transmission line 41 so as to transmit the clock in the same direction as a data transmission direction shown by a transmission direction control signal Sc and makes the clock returning from the clock transmission line input to a termination resistor 43 with the same value as that of a characteristic impedance of the data transmission line. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock distribution circuit that distributes a clock to a circuit that performs bidirectional data transmission in accordance with a transmission direction control signal that is connected via a data transmission line and indicates a data transmission direction.
[0002]
[Prior art]
A clock distribution circuit for distributing a clock to these data transmission circuits is provided in order to set the transmission timing of circuits that perform bidirectional data transmission via the data transmission lines.
[0003]
FIG. 4 is a circuit diagram showing an example of a conventional clock distribution circuit.
[0004]
Here, the data transmission circuits 1 and 2 are circuits provided in, for example, a unit of the apparatus, and are connected to each other via a data transmission line 3 having a wiring length Ld, and clocks CLK1 and CLK1 supplied from the clock distribution circuit 5 are provided. Data is bidirectionally transmitted from one circuit to the other circuit based on CLK2 and a transmission direction control signal Sc supplied from the outside.
[0005]
The data transmission circuits 1 and 2 perform transmission operations according to a transmission direction control signal Sc indicating a data transmission direction, and receive operations according to a transmission direction control signal Sc indicating a data transmission direction. Receiving units 12 and 22 and flip-flop circuits 13, 14 and 23 and 24 which take in data according to the clocks CLK 1 and CLK 2 supplied from the clock distribution circuit 5 and hold and output the data.
[0006]
The clock distribution circuit 5 includes a branch unit 51 that branches the clock CLK input from the outside into two, a clock transmission line 52 that transmits one of the two branched clocks to the clock input terminal 15 of the data transmission circuit 1, and a two-branch And a clock transmission line 53 for transmitting the other clock signal to the clock input terminal 25 of the data transmission circuit 2.
[0007]
[Problems to be solved by the invention]
However, in the above-described conventional example, the clock delay associated with the recent high-speed data transmission has made it impossible to ignore the wiring delay time on the data transmission line with respect to the clock cycle.
[0008]
If the wiring delay time on the data transmission line is sufficiently shorter than the clock cycle (for example, 1/100 or less), the data transmission can be performed without any trouble. However, as the clock frequency increases, the data transmission time increases. Data cannot be reliably received in circuits.
[0009]
FIG. 5 is a timing chart showing an example of a phase relationship between transmission data and a clock when a conventional clock distribution circuit is used.
[0010]
Here, a case where data is transmitted from the data transmission circuit 1 to the data transmission circuit 2 will be described. Note that the same applies to the case where data is transmitted from the data transmission circuit 2 to the data transmission circuit 1, and a description thereof will be omitted.
[0011]
First, the transmission direction control signal Sc indicating the data transmission direction is supplied to the transmission units 11 and 21 and the reception units 12 and 22 of the data transmission circuits 1 and 2 so that the data transmission circuit 1 transmits the data to the data transmission circuit 2. Data transmission becomes possible.
[0012]
The clock CLK1 is supplied to the clock input terminal 15 of the data transmission circuit 1 via the clock transmission line 52 of the clock distribution circuit 5 (FIG. 5A), and the data transmission circuit 2 is transmitted via the clock transmission line 53. Is supplied to the clock input terminal 25 (FIG. 5D). Here, due to the line length difference between the clock transmission lines 52 and 53, CLK2 is supplied after being delayed by a delay time tskw from CLK1.
[0013]
The flip-flop circuit 13 of the data transmission circuit 1 captures the data DATA1 at the rising timing of the clock CLK1, holds the held data until the next rising of the clock CLK1, and outputs the held data to the transmission unit 11. Here, since a delay is caused by the circuit element, data is output to the data transmission line 3 with a delay of the element delay time td1 from the rising timing of CLK1 (FIG. 5B).
[0014]
The data transmitted from the data transmission circuit 1 is input to the data transmission circuit 2 via the data transmission line 3 having the wiring length Ld with a further delay of the wiring delay time (tdLd) (FIG. 5C).
[0015]
Then, the data transmission circuit 2 takes in data from the data transmission line at the rising timing of the clock CLK2.
[0016]
In the case where such a delay occurs, the data receivable condition of the data transmission circuit 2 is as follows, assuming that the hold time of the data transmission circuit 2 is thold, the setup time is tsetup, and the clock cycle is T.
td1 + tdLd-tskey ≧ thold
T− (td1 + tdLd + tskew) ≧ tsetup
[0017]
Even if td1 ≒ 0 and tskew ≒ 0,
tdLd ≧ thold
T-tdLd ≧ tsetup, and there is a problem that the data transmission line 3 is limited by the wiring delay time tdLd and the transmission frequency.
[0018]
An object of the present invention is to provide a clock distribution circuit that is not limited by the length of a data transmission line or the transmission frequency in high-speed bidirectional data transmission.
[0019]
[Means for Solving the Problems]
The clock distribution circuit according to the present invention is connected to a first data transmission circuit and a second data transmission circuit that are connected via a data transmission line and perform bidirectional data transmission according to a transmission direction control signal indicating a data transmission direction. In a clock distribution circuit for distributing a clock, a clock transmission line for transmitting a clock to a clock input terminal of the first data transmission circuit and a clock input terminal of the second data transmission circuit; Clock transmission control means for transmitting a clock to the clock transmission line.
[0020]
In the above configuration, the clock transmission line has the same characteristics as the data transmission line, and a clock input terminal of the first data transmission circuit and a clock of the second data transmission circuit are connected from an output terminal of the clock transmission control means. The clock is wired so as to return to the clock transmission control means via the input terminal and the clock between the clock input terminal of the first data transmission circuit and the clock input terminal of the second data transmission circuit. The length of the transmission line is set to be the same as the length of the data transmission line.
[0021]
Further, the clock transmission control means transmits a clock to the clock transmission line so that the clock is transmitted in the same direction as the data transmission direction indicated by the transmission direction control signal, and transmits the clock returned from the clock transmission line. To a terminating resistor having the same value as the characteristic impedance of the data transmission line.
[0022]
Further, the clock transmission control means includes a clock input terminal to which a clock to be distributed is input, a first input / output terminal connected to one end of the clock transmission line, and a second input / output terminal connected to the other end of the clock transmission line. 2, a terminating resistor having the same value as the characteristic impedance of the data transmission line, and operating in response to the transmission direction control signal to set the first and second input / output terminals to the clock. A switch connected to an input terminal or the terminating resistor, the first input / output terminal or the second input / output terminal so that a clock can be transmitted in the same direction as the data transmission direction indicated by the transmission direction control signal. Terminal and the clock input terminal are connected by the switch, and the first input / output terminal or the second input / output terminal from which the clock returns from the clock transmission line and the terminal Anti city is connected by the switch.
[0023]
Note that the switch may be formed of a semiconductor element or may be formed of an electromagnetic relay.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0025]
FIG. 1 is a circuit configuration diagram showing one embodiment of the present invention, and shows a clock distribution circuit 4 that distributes a clock to data transmission circuits 1 and 2 that perform bidirectional data transmission via a data transmission line 3. I have.
[0026]
Here, the data transmission circuits 1 and 2 are connected via the data transmission line 3 having a wiring length Ld, and the clocks CLK1 and CLK2 supplied from the clock distribution circuit 4 and the transmission direction control signal Sc supplied from the outside. , Data is transmitted from one circuit to the other circuit.
[0027]
Also, the data transmission circuits 1 and 2 include transmission units 11 and 21 that perform a transmission operation in accordance with a transmission direction control signal Sc indicating a data transmission direction, as in FIG. The receiving units 12 and 22 perform a receiving operation in accordance with the transmission direction control signal Sc shown in the figure, and the flip-flop circuits 13, 14 and 23 fetch and hold and output data in accordance with the clocks CLK 1 and CLK 2 supplied from the clock distribution circuit 4. , 24 and clock input terminals 15, 25.
[0028]
The clock distribution circuit 4 of the present invention includes: a clock transmission line 41 for transmitting a clock to the data transmission circuits 1 and 2; a clock transmission control unit 42 for transmitting a clock to the clock transmission line 41 according to a transmission direction control signal Sc; It has a terminating resistor 43 for terminating the clock transmission line 41 without reflection, and a clock driver 44 for amplifying a clock CLK supplied from the outside to a predetermined level.
[0029]
Here, the clock transmission line 41 has the same characteristics as the data transmission line 3 connected between the data transmission circuits 1 and 2, and the resistance value of the terminating resistor 43 is the same as the characteristic impedance of the data transmission line 3.
[0030]
One end of the clock transmission line 41 is connected to the input / output terminal P1 of the clock transmission control unit 42, and is connected to the clock input terminal 15 of the data transmission circuit 1 and the clock input terminal 25 of the data transmission circuit 2 while the other end. The terminal is connected to the input / output terminal P2 of the clock transmission control unit 42.
[0031]
Further, the wiring length Lc of the clock transmission line 41 from the clock input terminal 15 of the data transmission circuit 1 to the clock input terminal 25 of the data transmission circuit 2 is set to be the same as the wiring length Ld of the data transmission line 3 (Lc = Ld). are doing.
[0032]
The clock transmission control unit 42 includes a clock input terminal P0 to which the clock CLK0 output from the clock driver 44 is input, input / output terminals P1 and P2 connected to the clock transmission line 41, and a termination terminal P3 connected to the termination resistor 43. And a switch that operates according to the transmission direction control signal Sc to connect the input / output terminals P1 and P2 to the clock input terminal P0 and the terminal terminal P3.
[0033]
When the switch operates in response to the transmission direction control signal Sc, the clock CLK0 input to the input terminal P0 is transmitted to the clock transmission line 41 from one of the input / output terminal P1 and the input / output terminal P2, and the clock CLK0 is input to the input terminal P2. The clock returned to either the output terminal P1 or the input / output terminal P2 is input to the termination resistor 43 via the termination terminal P3.
[0034]
If the transmission direction control signal Sc indicates that data is to be transmitted from the data transmission circuit 1 to the data transmission circuit 2, a clock is transmitted from the input / output terminal P1 to the clock transmission line 41 and is indicated by a solid line. Clock in the direction indicated. When the data transmission circuit 2 is instructed to transmit data to the data transmission circuit 1, a clock is transmitted from the input / output terminal P2 to the clock transmission line 41, and the clock is supplied in the direction indicated by the broken line. .
[0035]
Next, the operation will be described.
[0036]
Here, a case where data is transmitted from the data transmission circuit 1 to the data transmission circuit 2 will be described. Note that the same applies to the case where data is transmitted from the data transmission circuit 2 to the data transmission circuit 1, and a description thereof will be omitted.
[0037]
FIG. 2 is a timing chart showing an example of a phase relationship between transmission data and a clock.
[0038]
First, the transmission direction control signal Sc is supplied to the transmission units 11 and 21 and the reception units 12 and 22 of the data transmission circuits 1 and 2, so that data transmission from the data transmission circuit 1 to the data transmission circuit 2 becomes possible. .
[0039]
The clock transmission control unit 42 of the clock distribution circuit 4 operates the switch in response to the transmission direction control signal Sc to transmit the clock CLK0 input to the clock input terminal P0 from the input / output terminal P1 to the clock transmission line 41. At the same time, the clock returned to the input / output terminal P2 is input to the termination resistor 43 via the termination terminal P3.
[0040]
The clock transmitted from the input / output terminal P1 to the clock transmission line 41 is supplied to the data transmission circuit 1 as the clock CLK1 at the clock input terminal 15 of the data transmission circuit 1 (FIG. 2A). Of the wiring length Lc (Lc = Ld) to the clock input terminal 25, and is supplied to the data transmission circuit 2 as the clock CLK2 with a delay of the delay time tdLd due to the wiring length Ld from the clock CLK1 (FIG. 2D). ).
[0041]
Thereafter, the clock returns to the input / output terminal P2 via the clock transmission line 41, and is input to the termination resistor 43 via the termination terminal P3. Since the terminating resistor 43 is equal to the characteristic impedance of the clock transmission line 41, that is, the characteristic impedance of the data transmission line 3, it is possible to supply a clock to the data transmission circuits 1 and 2 without generating a waveform distortion due to a reflected wave.
[0042]
On the other hand, the flip-flop circuit 13 of the data transmission circuit 1 captures the data DATA1 at the rising timing of the clock CLK1, and outputs the held data to the transmission unit 11 until the next rising of the clock CLK1.
[0043]
Here, since a delay is caused by the circuit element, data is output to the data transmission line with a delay of the element delay time td1 from the rising timing of CLK1 (FIG. 2B).
[0044]
The data transmitted from the data transmission circuit 1 is input to the data transmission circuit 2 via the data transmission line 3 having the wiring length Ld, with a further delay of the wiring delay time (tdLd) (FIG. 2C). That is, data is input to the data transmission circuit 2 with a delay of td1 + tdLd from the rising point of CLK1.
[0045]
Then, the data transmission circuit 2 takes in data from the data transmission line at the rising timing of the clock CLK2. Here, the wiring length Lc of the clock transmission line 41 from the clock input terminal 15 of the data transmission circuit 1 to the clock input terminal 25 of the data transmission circuit 2 is set to be the same as the wiring length Ld of the data transmission line 3. The clock CLK2 lags behind the clock CLK1 by the wiring delay time tdLd. Therefore, the phase relationship between the clock and the data when the data transmission circuit 1 outputs the data is the same as the phase relationship between the clock and the data when the data transmission circuit 2 inputs the data.
[0046]
Therefore, the data receivable condition of the data transmission circuit 2 is as follows: when the hold time of the data transmission circuit 2 is “thold”, the setup time is “tsetup”, and the clock cycle is “T”.
td1> thold
It suffices that T-td1> tsetup, and there is no limitation by the wiring delay time and the transmission frequency in the data transmission line as in the related art.
[0047]
FIG. 3 is a circuit configuration diagram showing another embodiment of the clock transmission control unit 42, and shows an example in which a semiconductor element is used as a switch that operates according to the transmission direction control signal Sc.
[0048]
Here, four FETs (field effect transistors), an inverter that inverts the polarity of the transmission direction control signal Sc and applies the same to the gates of the two FETs, and an inverter that applies the transmission direction control signal Sc to the gates of the two FETs And the driver to be used.
[0049]
As described above, the switch that operates in response to the direction control signal Sc can be similarly operated by using a semiconductor element or by using an electromagnetic relay.
[0050]
【The invention's effect】
As described above, according to the present invention, in a clock distribution circuit that is connected via a data transmission line and distributes a clock to a circuit that performs bidirectional data transmission according to a transmission direction control signal indicating a data transmission direction, The clock transmission line that supplies the clock to the data transmission circuit has the same characteristics as the data transmission line, and the clock transmitted to this clock transmission line is terminated from one data transmission circuit via the other data transmission circuit. The length of the clock transmission line between the data transmission circuits should be the same as the length of the data transmission line, and the data transmission direction indicated by the transmission direction control signal should be the same as the clock transmission direction. The phase relationship between the clock and data in the data transmission circuit on the transmission side is directly input to the data transmission circuit on the reception side by controlling It is possible to be realized high-speed bidirectional data transmission without being restricted by the wiring length and the transmission frequency of the data transmission line.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.
FIG. 2 is a timing chart illustrating an example of a phase relationship between transmission data and a clock.
FIG. 3 is a circuit configuration diagram showing another embodiment of the clock transmission control unit 42 shown in FIG.
FIG. 4 is a circuit configuration diagram showing a conventional example.
FIG. 5 is a timing chart showing an example of a phase relationship between transmission data and a clock in a conventional example.
[Explanation of symbols]
1, 2 Data transmission circuit 3 Data transmission line 4 Clock distribution circuit 41 Clock transmission line 42 Clock transmission control unit 43 Termination resistor CLK Clock DATA Data Sc Transmission direction control signal

Claims (7)

A clock distribution circuit that distributes a clock to a first data transmission circuit and a second data transmission circuit that are connected via a data transmission line and perform bidirectional data transmission in accordance with a transmission direction control signal indicating a data transmission direction A clock transmission line for transmitting a clock to a clock input terminal of the first data transmission circuit and a clock input terminal of the second data transmission circuit; and transmitting a clock to the clock transmission line in response to the transmission direction control signal. And a clock transmission control means. The clock transmission line has the same characteristics as the data transmission line, and is connected from the output terminal of the clock transmission control means to the clock input terminal of the first data transmission circuit and the clock input terminal of the second data transmission circuit. And the wiring of the clock transmission line between the clock input terminal of the first data transmission circuit and the clock input terminal of the second data transmission circuit. 2. The clock distribution circuit according to claim 1, wherein the length is set to be equal to the length of the data transmission line. The clock transmission control means transmits a clock to the clock transmission line so that the clock transmits in the same direction as the data transmission direction indicated by the transmission direction control signal, and outputs the clock returned from the clock transmission line to the clock transmission line. 3. The clock distribution circuit according to claim 2, wherein the input is made to a termination resistor having the same value as the characteristic impedance of the data transmission line. The clock transmission control means includes a clock input terminal to which a clock to be distributed is input, a first input / output terminal connected to one end of the clock transmission line, and a second input / output terminal connected to the other end of the clock transmission line. And a terminating resistor having the same value as the characteristic impedance of the data transmission line, and operating in response to the transmission direction control signal to connect the first input / output terminal and the second input / output terminal to the clock input terminal. 3. The clock distribution circuit according to claim 2, further comprising a switch connected to an end or the terminating resistor. The clock transmission control means is configured to connect the first input / output terminal or the second input / output terminal and the clock input terminal so that a clock can be transmitted in the same direction as the data transmission direction indicated by the transmission direction control signal. The terminal is connected by the switch, and the first input / output terminal or the second input / output terminal from which a clock returns from the clock transmission line and the terminating resistor are connected by the switch. 5. The clock distribution circuit according to 4. The clock distribution circuit according to claim 4, wherein the switch is configured by a semiconductor element. The clock distribution circuit according to claim 4, wherein the switch is configured by an electromagnetic relay.

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