JP2004030100A - Electric power management method, and computer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric power management method and a computer by which electric power can be managed scrupulously with a high responsiveness. <P>SOLUTION: The computer comprises: a corresponding information management means managing an executing function and information on hardware corresponding to the function; an electric power management means managing the power of the specified hardware based on the information managed by the corresponding information management means; and a function request means requesting the start or suspension of the function to the power management means. The electric power management means manages the power based on the request by the function request means. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technique for reducing power consumption, which is a problem in a computer including an LSI, which mainly executes a plurality of applications.
[0002]
[Prior art]
FIG. 6 is an explanatory diagram showing a configuration of a computer using a conventional power management method used in, for example, a mobile terminal. 6, reference numeral 100 denotes a CPU; 101, an SRAM; 102, a flash memory; 103, a peripheral IP (Intellectual Property; circuit or LSI logic block); 104, a power control circuit; 105, a clock control circuit; And a power management IP 1061 for controlling power, a power management register 1061 in the power management IP 106, an operating system (hereinafter referred to as OS) 200 for managing power, and a command 201 for the power management IP 106 based on a notification from the OS 200. A power management driver 2011 is a hardware control unit in the power management driver 201. Here, the CPU 100, the SRAM 101, the flash memory 102, the peripheral IP 103, the power control circuit 104, the clock control circuit 105, the power management IP 106, and the power management register 1061 are included in the hardware layer, and the OS 200, the power management driver 201, the hardware control Means 2011 is included in the driver layer.
[0003]
Next, the operation will be described. The OS 200 manages the execution task, and when there are no more tasks to be executed, detects that the system is in an idle state, and requests the power management driver 201 to shift to the low power mode. I do. The hardware control unit 2011 in the power management driver 201 converts volatile memory data such as the SRAM 101 and register information of each peripheral IP 103 into the flash memory 102 and the like using software processing as a process for shifting to the low power mode. The backup is performed in the non-volatile memory, and a clock stop and a power drop are requested to the power management IP 106. The power management IP 106 changes the power management register 1061 based on a request from the hardware control unit 2011, and sends a power control signal to the power control circuit 104 and the clock control circuit 105 based on the changed register value. Each outputs a clock control signal. The power control circuit 104 and the clock control circuit 105 change the internal power and the internal clock to the low power mode based on the control signal from the power management IP 106. During the transition to the low-power mode, the system becomes unstable. Therefore, the OS 200 processes the transition to the low-power mode with a high priority. Even if another task is activated during the transition, the OS 200 is not processed.
[0004]
When an interrupt occurs after the transition to the low power mode is completed, the power management IP 106 detects this and returns the power and clock via the power control circuit 104 and the clock control circuit 105. Further, the OS 200 requests the power management driver 201 to perform a recovery process, and the hardware control unit 2011 in the power management driver 201 transfers the backup data in the nonvolatile memory such as the flash memory 102 to a volatile memory such as the SRAM 101 or the like. Return to the register of each peripheral IP 103, and return the system to the normal state.
[0005]
[Problems to be solved by the invention]
In the computer using the above-described conventional power management method, there is a problem that the power does not shift to the low power mode unless the system is in an idle state, so that fine power control cannot be performed.
[0006]
In addition, since the driver performs the backup processing and the power / clock control using software processing, the mode transition processing takes a long time, and there is a problem that the response performance to the interrupt in the low power mode is poor.
[0007]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a power management method and a computer having good responsiveness and capable of performing fine power control.
[0008]
[Means for Solving the Problems]
A power management method according to the present invention manages a function to be executed and hardware information corresponding to the function, and manages power of predetermined hardware based on the managed information.
[0009]
According to the present invention, there is provided a computer which manages a function to be executed and hardware information corresponding to the function, and powers predetermined hardware based on the information managed by the corresponding information management means. Power management means for managing.
[0010]
The power management unit includes a function request unit that requests the power management unit to start or stop the function, and the power management unit manages power based on a request from the function request unit.
[0011]
Further, the power management means controls an operation start timing of predetermined hardware.
[0012]
Further, the hardware includes a volatile storage unit, is connected to the hardware via a bus, has a bus master function and a nonvolatile storage unit, and is stored in the volatile storage unit corresponding to the hardware. Volatile information storage means for storing the information stored in the nonvolatile storage means via the bus using the bus master function.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is an explanatory diagram illustrating a configuration of a computer using the power management method according to the first embodiment. 1, reference numeral 10 denotes a CPU, 11 denotes an SRAM, 12 denotes a flash memory, 13 denotes a peripheral IP, 14 denotes a power control circuit, 15 denotes a clock control circuit, 16 denotes a power management IP, 20 denotes an operating system, and 21 denotes a power management driver. , 30 (30a, 30b) are the main tasks of the application. The peripheral IP 13 includes a serial I / F 131, a communication I / F 132, and an LCD controller 133, the power management IP includes a power management register 161, and the power management driver 21 functions as a request management unit 211 and a hardware control unit 212. The main task 30 includes a plurality of tasks 301a to 301d (communication processing, processing priority setting, LCD display, key input processing, etc.). The computer shown in FIG. 1 includes a hardware layer composed of physical circuits and LSI logic logic, a driver layer that is software that centrally controls the hardware independently of applications, and an application layer that is software that provides services to users. Consists of
The function-hardware correspondence information 213 corresponds to correspondence information management means, the power management driver 21, the power management IP 16, the power supply control circuit 14, and the clock control circuit 15 correspond to power management means, and the task 301 is a function request means. Is equivalent to
[0014]
In the hardware layer, the power management IP 16 includes a clock control signal for controlling the clock control circuit 15, and can notify the CPU 10, the SRAM 11, and various peripheral IPs 13 of clock frequency switching and stop. The power management IP 16 further includes a power supply control signal for controlling the power supply control circuit 14, and can notify the CPU 10, the SRAM 11, the flash memory 12, and the power supply voltage switching of the peripheral IP 13 and the power-off. These controls are performed by accessing the power management register 161 of the power management IP 16 from the CPU 10.
[0015]
In the driver layer, the OS 20 manages activation of the task 301 having an execution request, interruption of the task 301 due to an interruption, and switching to another task 301. The power management driver 21 is called from the application and the OS 20 and performs data backup for restoring and stopping the requested function and controls the power management IP 16.
[0016]
In the application layer, each of the main tasks 30a and 30b is composed of one or a plurality of program units, that is, tasks 301. Depending on the application, key input processing (301d), display display (301c), priority processing (301b) ) And communication processing (301a) to realize various services.
[0017]
Next, the operation will be described. When a request to execute a certain application is made by an external interrupt or another task, the OS 20 activates a main task 30a of the requested application. Here, in order to activate a function that is absolutely necessary for executing the application, the power management driver 21 is requested to activate. The function refers to a communication function (301a) such as a network or wireless communication, a priority processing function (301b), a display function (301c) such as a display, an input function (301d) such as a keyboard, and the like. For example, when executing an application, if it is known that the image is to be constantly displayed on the display, a request to start the LCD display is made. In addition, a limited function that is used only under certain conditions is not requested here, and an activation request is issued when the use of the function is determined. For example, when performing communication via a network after performing a certain image process, the communication function is not used in the initial stage, and therefore, a request to start the communication process is made at the stage of using the communication function.
[0018]
In the power management driver 21, the request management unit 211 receives a start request from the main task 30a, and based on information from the request management unit 211, the hardware control unit 212 determines hardware necessary for executing the function. Each function is realized by the operation of a plurality of hardware. The hardware control unit 212 manages the function-hardware correspondence information 213, determines the hardware to be activated by referring to the information, and starts the power management, activates the clock, restores the register information, and the like to the power management IP 16. Execute.
[0019]
FIG. 2 is an explanatory diagram illustrating a configuration example of the function-hardware correspondence information 213 according to the first embodiment. For example, when the request management unit 211 receives an LCD display activation request from the main task 30a, the hardware control unit 212 determines hardware necessary for executing the function based on information from the request management unit 211. Do. The hardware control unit 212 refers to the function-hardware correspondence information 213, and in the case of the LCD display function, determines that the hardware to be started is the LCD controller 133, the flash memory 12, and the CPU 10 for processing. As a result, the hardware control unit 212 notifies the power management IP 16 of signals for instructing peripheral IP power ON, LCD controller clock ON, register restoration, flash memory power Up, and CPU performance 20 point Up. In the example of FIG. 2, the required processing performance of the CPU is divided into stages such as 1 PointUp and 10 PointDown and added to the function-hardware correspondence information 213 so that the CPU and the like can control the processing performance in multiple stages as well as start and stop. are doing.
[0020]
Further, during the execution of the application, the main task 30a issues a stop request to the power management driver 21 for functions that are no longer used or functions that are used less frequently. The request management unit 211 of the power management driver 21 receives the request, and specifies the hardware to be stopped by the hardware control unit 212 based on the information from the request management unit 211 and with reference to the function-hardware correspondence information 213. I do. At this time, if the hardware corresponding to another activated function and the hardware to be stopped overlap, the hardware is not stopped. The processing performance of the CPU 10 reduces only the required performance for the function to be stopped. Then, the hardware control unit 212 instructs the power management IP 16 to stop the hardware determined to stop.
[0021]
For example, after the task 301a (communication processing) and the task 301c (LCD display) are executed, if the communication function used in the task 301a is no longer used, the main task 30a issues a request to the power management driver 21 to stop the communication function. Do. The request management unit 211 of the power management driver 21 receives the stop request, and based on the information from the request management unit 211 and referring to the function-hardware correspondence information 213, the hardware control unit 212 stops the communication function. It is determined that the hardware to be executed is the communication I / F 132, the flash memory 12, the SRAM 11, and the CPU 10. However, since the LCD display will be executed in the future, the flash memory 12 and the CPU 10 used for the LCD display will not be stopped. Therefore, the hardware control unit 212 notifies the power management IP 16 of a signal instructing the communication I / F clock OFF, peripheral IP power OFF, and SRAM power Down to stop the communication I / F 132 and the SRAM 11. Also, the hardware control unit 212 notifies the power management IP 16 of an instruction (CPU performance 10 Point Down) to reduce the processing performance by the amount of the communication function stop, without stopping the CPU 10. Further, since the communication I / F 132 to be stopped has information in the volatile memory, the hardware control unit 212 uses software to register the volatile memory in the volatile memory of the communication I / F 132 via the internal bus of the hardware layer. The information and the like are backed up to the flash memory 12 which is a nonvolatile memory.
[0022]
Then, in the hardware layer, the power management IP 16 changes the power management register 161 based on the instruction signal from the hardware control unit 212 and, based on the changed register value, the power control circuit 14 and the clock control circuit 15. Output a power control signal and a clock control signal. The power supply control circuit 14 and the clock control circuit 15 change the power supply and clock of the SRAM 11 and the peripheral IP 13 based on the notified control signal.
[0023]
For example, the power management IP 16 changes the power management register 161 based on an instruction signal from the hardware control unit 212 that the communication I / F clock is OFF, the peripheral IP power is OFF, the SRAM power is Down, and the CPU performance is 10 Point Down. The power management IP 16 outputs a power control signal of peripheral IP power OFF and SRAM power Down to the power control circuit 14 based on the changed register value. Similarly, a clock control signal of communication I / F clock OFF is output to the clock control circuit 15. The power supply control circuit 14 also outputs a power control signal and a clock control signal corresponding to the CPU performance 20PointDown to the power control circuit 14 and the clock control circuit 15. The power supply control circuit 14 and the clock control circuit 15 receiving these control signals perform communication I / F clock OFF, peripheral IP power OFF, SRAM power Down, and CPU performance 10 Point Down.
[0024]
Further, when the OS 20 forcibly terminates the current application and switches to another task due to an interrupt or another high-priority task activation request, the OS 20 notifies the power management driver 21 of a task switching instruction. The power management driver 21 stops the function started by the current application.
[0025]
For example, when the OS 20 switches the main task 30a of the current application to another main task 30b due to an interrupt or another high-priority task activation request, the OS 20 notifies the power management driver 21 of a task switching instruction. Then, the power management driver 21 backs up the register information of the volatile memory of the peripheral IP 13 and the like to the flash memory 12 which is the nonvolatile memory by software via the internal bus of the hardware layer, as described above. The running hardware corresponding to the main task 30a is stopped via the power management IP16.
[0026]
As described above, the computer according to the first embodiment determines the functions required for executing an application and the hardware necessary for executing the functions, and performs power management for each hardware to determine the necessary functions. In this case, fine power management for activating only necessary hardware at any time can be performed, and power consumption of the system can be reduced.
In addition, the power management driver in the driver layer determines the functions necessary for executing the application and the hardware necessary for executing the functions by using the correspondence information between the functions and the hardware, so that the hardware in the application layer is determined. Power management corresponding to individual hardware can be performed without showing hardware.
[0027]
In the first embodiment, the case where the task requests activation and stop of a function has been described. However, it is only necessary to know which function to start and stop. For example, if a function execution schedule is determined, the The function may be started and stopped according to a schedule, but is not limited to this.
[0028]
Further, in the first embodiment, it is assumed that the activation and stop of the functions in the main task 30a are manually added at the time of creating a program, but the functions can be automatically added by a compiler or the like. In this case, the compiler recognizes the calling location of each function in the program, and the compiler automatically adds a start / stop request according to the called function. For example, when compiling the main task 30a, the compiler recognizes calls of the functions 301a to 301c written in the program, and adds activation and stoppage of the recognized functions.
[0029]
Embodiment 2 FIG.
In the first embodiment, the case where the stop processing is started as soon as the hardware power stop instruction is given has been described. In the second embodiment, the case where the timer function is used when the hardware power is stopped will be described. I do.
[0030]
When stopping the hardware involves stopping the power supply, a backup of the non-volatile memory may be required, and processing may take time. In addition, there is a waiting time until the power supply voltage once dropped is increased and stabilized, and it is difficult to immediately return from the stop. Therefore, once the hardware stop processing is started, a significant time loss occurs until stable power is supplied in response to a start request immediately after the start of the stop processing.
[0031]
Therefore, in the second embodiment, a case where the power management driver 21 has a timer function will be described.
FIG. 3 is an explanatory diagram illustrating a configuration of a computer using the power management method according to the second embodiment. In FIG. 3, reference numeral 214 denotes a stop processing start timer. Other components denoted by the same reference numerals are the same as those in FIG.
FIG. 4 is an explanatory diagram showing a configuration example of the function-hardware correspondence information 213 according to the second embodiment. In FIG. 4, a stop processing start time is added to the configuration of FIG. 2 as start-up hardware information.
[0032]
Next, the operation of the power management driver 21 including the stop processing start timer 214 will be described with reference to FIGS. A case will be described in which the main task 30a issues a stop request to the power management driver 21 for a function that is no longer used or a function that is used less frequently during execution of an application. The request management unit 211 of the power management driver 21 receives the request, and based on the information from the request management unit 211 and referring to the function-hardware correspondence information 213, the hardware that the hardware control unit 212 stops and Specify the stop processing start time. At this time, if the hardware corresponding to another activated function and the hardware to be stopped overlap, the hardware is not stopped. The processing performance of the CPU 10 reduces only the required performance for the function to be stopped. Then, the hardware control unit 212 uses the stop processing start timer 214 to delay the hardware determined to be stopped by the stop processing start time corresponding to the hardware, and then instructs the power management IP for the stop processing. I do. As a result, when the function requested to be stopped in the previous task is restarted in the next task due to switching of tasks or the like, the restart processing is requested within the range of the stop processing start time. , It is possible to prevent a return time loss.
[0033]
For example, after the task 301a (communication processing) and the task 301c (LCD display) are executed, if the communication function used in the task 301a is no longer used, the main task 30a issues a request to the power management driver 21 to stop the communication function. Do. The request management unit 211 of the power management driver 21 receives the stop request, and based on the information from the request management unit 211 and referring to the function-hardware correspondence information 213, the hardware control unit 212 stops the communication function. The hardware to be executed is the communication I / F 132, the flash memory 12, the SRAM 11, and the CPU 10, and it is determined that the respective stop processing start times are 10 msec, 10 msec, 5 msec, and 0 msec. However, since the LCD display will be executed in the future, the flash memory 12 and the CPU 10 used for the LCD display will not be stopped. Therefore, the hardware control unit 212 uses the stop process start timer 214 to notify the power management IP 16 by delaying the signal instructing the communication I / F clock OFF and the peripheral IP power OFF by 10 msec to stop the communication I / F 132. I do. Similarly, the hardware control unit 212 uses the stop processing start timer 214 to notify the power management IP 16 by delaying the signal instructing the SRAM power down by 5 msec to stop the SRAM 11. Also, the hardware control unit 212 notifies the power management IP 16 of an instruction (CPU performance 10 Point Down) to reduce the processing performance by the amount of the communication function stop, without stopping the CPU 10. Further, when notifying the power management IP 16 by delaying the processing start time by 10 msec using the stop processing start timer 214, the hardware control unit 212 volatilizes the communication I / F 132 by software via the internal bus of the hardware layer. The register information of the non-volatile memory is backed up to the flash memory 12 which is a non-volatile memory.
[0034]
As a result, immediately after the request to stop the communication function in the main task 30a is made, the task 30a is switched by an interrupt or the like, and when the power management driver 21 is again requested to start the communication function, the request from the power management driver 21 The management unit 211 receives the activation request, and based on the information from the request management unit 211 and with reference to the function-hardware correspondence information 213, the hardware control unit 212 determines that the hardware that activates the communication function is the communication I / O. / F 132, the flash memory 12, the SRAM 11, and the CPU 10, and recognizes that the stop processing start timer 214 is waiting for the time according to the stop request. Therefore, the hardware control unit 212 stops the stop processing start timer 214 and interrupts the stop request processing.
Other operations are the same as those in the first embodiment, and a description thereof will not be repeated.
[0035]
As described above, the computer according to the second embodiment uses the stop processing start timer to wait for a certain period of time from the stop request for the hardware that needs to be backed up, and then performs the stop processing to stop the hardware. In the case where the period from the start to the restart is short, the stop processing can be canceled, and the performance degradation due to the task switching can be prevented.
[0036]
Embodiment 3 FIG.
In the first embodiment, the case where the power management driver 21 backs up the register information and the like of the volatile memory of the peripheral IP 13 to the flash memory 12 which is the non-volatile memory by the software has been described. The case where the information of the volatile memory of the peripheral IP 13 is backed up by hardware will be described.
[0037]
FIG. 5 is an explanatory diagram illustrating a configuration of a hardware layer of a computer using the power management method according to the third embodiment. 3, reference numeral 134 denotes an internal register of the serial I / F 131, 135 denotes an internal register of the communication I / F 132, 136 denotes an internal register of the LCD controller 133, 162 denotes a bus master I / F in the power management IP 16, and 163 denotes a power management IP 16 Is a backup register buffer which is a non-volatile memory in the inside. The other components denoted by the same reference numerals are the same as those in FIG. 1, and the application layer and the driver layer not shown in FIG. 5 are also the same as those in FIG.
The power management IP 16 corresponds to a volatile information storage unit.
[0038]
The operation of the power management IP 16 including the bus master I / F 162 and the backup register buffer 163 will be described with reference to FIG. The power management IP 16 changes the power management register 161 based on the instruction signal when the hardware control unit 212 receives an instruction to stop the hardware that needs backup from the hardware control unit 212. The power management IP 16 uses the bus master I / F 162 to back up the register information of the volatile memory of the peripheral IP 13 to the backup register buffer 163 which is a nonvolatile memory, based on the changed register value. Then, after this backup operation, the power management IP 16 stops the power supply of the peripheral IP 13 that has received the stop instruction.
[0039]
For example, upon receiving an instruction from the hardware control unit 212 to stop the communication I / F 132 requiring backup, the power management IP 16 changes the power management register 161 based on the instruction signal. The power management IP 16 uses the bus master I / F 162 to back up the register information and the like of the volatile memory of the communication I / F 132 to the backup register buffer 163 which is a nonvolatile memory based on the changed register value. Then, after this backup operation, the power management IP 16 outputs a power control signal indicating that the communication I / F 132 is turned off to the power control circuit 14, and the power control circuit 14 having received this control signal causes the power of the communication I / F 132 to be turned off. Turn off the power.
It should be noted that the activation is performed in the reverse operation, and the power management IP 16 performs power activation and register restoration.
[0040]
As described above, in the third embodiment, at the time of backup processing before hardware stoppage, the power management IP in the hardware layer uses the bus master function to transfer the hardware to the backup memory in the power management IP. By performing the backup processing, since software does not intervene, it is possible to reduce the processing time when resuming from a stopped state, and at the same time, it is possible to prevent an increase in the load on the CPU.
[0041]
In the third embodiment, backup and power-off of the communication I / F 132 have been described, but the same applies to power-off and clock-off of the serial I / F 131 and the LCD controller 133.
[0042]
【The invention's effect】
As described above, the correspondence information management unit that manages the function to be executed and hardware information corresponding to the function, and manages the power of predetermined hardware based on the information managed by the correspondence information management unit. By providing the power management means, it is possible to perform fine power management for activating only necessary hardware when needed, and to reduce power consumption.
[0043]
The power management unit further includes a function request unit that requests the power management unit to start or stop the function, and the power management unit manages power based on a request from the function request unit, so that a hardware There is an effect that the power management corresponding to the individual hardware can be performed without showing the information.
[0044]
In addition, the power management unit can cancel the stop process when the period from the stop to the restart is short by controlling the operation start timing of the predetermined hardware, and can prevent performance degradation due to task switching. There is an effect that can be.
[0045]
Further, the hardware includes a volatile storage unit, is connected to the hardware via a bus, has a bus master function and a nonvolatile storage unit, and is stored in the volatile storage unit corresponding to the hardware. The volatile information storage means for storing the read information in the non-volatile storage means via the bus using the bus master function, thereby reducing the processing time when resuming from a stopped state because no software is interposed. At the same time, the CPU load can be prevented from increasing.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a configuration of a computer using a power management method according to a first embodiment.
FIG. 2 is an explanatory diagram showing a configuration example of function-hardware correspondence information 213 according to the first embodiment;
FIG. 3 is an explanatory diagram showing a configuration of a computer using a power management method according to a second embodiment.
FIG. 4 is an explanatory diagram showing a configuration example of function-hardware correspondence information 213 according to the second embodiment;
FIG. 5 is an explanatory diagram showing a configuration of a hardware layer of a computer using the power management method according to the third embodiment.
FIG. 6 is an explanatory diagram showing a configuration of a computer using a conventional power management method.
[Explanation of symbols]
10 CPU
11 SRAM
12 Flash memory
13 Peripheral IP
14 Power supply control circuit
15 Clock control circuit
16 Power Management IP
20 Operating system
21 Power Management Driver
30a, 30b Main task
131 Serial I / F
132 Communication I / F
133 LCD controller
134 to 136 Internal register
161 Power management register
162 bus master I / F
163 Backup register buffer
211 Request management means
212 hardware control means
213 Function-Hardware Support Information
214 Stop processing start timer
301a to 301d tasks

Claims (5)

Manages information about the functions to be performed and the hardware corresponding to those functions,
A power management method, wherein power of predetermined hardware is managed based on the managed information. Correspondence information management means for managing information on a function to be executed and hardware corresponding to the function,
A computer comprising: power management means for managing power of predetermined hardware based on information managed by the correspondence information management means. A function requesting unit that requests the power management unit to start or stop the function,
3. The computer according to claim 2, wherein the power management unit manages power based on a request from the function request unit. 3. The computer according to claim 2, wherein the power management unit controls an operation start timing of a predetermined hardware. The hardware includes a volatile storage unit,
It is connected to the hardware via a bus, has a bus master function and a non-volatile storage means, and stores information stored in a volatile storage means corresponding to the hardware through the bus using the bus master function. 3. The computer according to claim 2, further comprising volatile information storage means for storing the volatile information in the nonvolatile storage means.

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