JP2004029384A - Display panel driving device, display control device and driving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display panel driving device, etc. capable of excluding skews between signals. <P>SOLUTION: The display panel driving device is provided with parallel/serial (P/S) converters 73 and 113 for P/S converting driving pulse generation control data and clocks, transmission parts 74 and 114 for converting signals converted by respective P/S converters 73 and 113 into signals corresponding to a differential serial transmission system and transferring the converted signals through transmission lines L1 and L2, receiving parts 81 and 121 for receiving the driving pulse generation control data and the clocks transferred through the transmission lines L1 and L2, and a serial/parallel (S/P) converter 83 for S/P converting the driving pulse generation control data and the clocks received by the receiving parts 81 and 121. A drive control part 22, an address driver part 18, sustain drivers 19 and 21, a scanning driver 20, etc. are used for generating drive pulses on the basis of the pulse generation control data and the clocks converted by the S/P converter 83. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display panel driving device for driving a matrix display panel such as a plasma display panel.
[0002]
[Prior art]
Japanese Patent Application Laid-Open No. H11-95713 describes a display panel driving device for transmitting image data or the like, which is digital data, on a line in a display device. Here, a method of transmitting this digital signal by LVDS (Low Voltage Differential Signaling) (differential serial transmission method) is used. The LVDS transmission system is a system in which two signal lines are driven symmetrically in opposite phases and the difference between the signals on the two signal lines is transmitted, so that noise mixed in from the outside cancels out the signal. Has the advantage that it is difficult to give
[0003]
[Problems to be solved by the invention]
However, in the device described in JP-A-11-95713, only control signals such as image data and synchronization signals are transferred by the LVDS method, and clock signals and the like used on the receiving side are transmitted via another transmission path. Transfer. However, when such a configuration is adopted, skew (timing shift) may occur between the clock signal and the image data or the like received on the receiving side. In order to eliminate the skew, for example, it is conceivable to adjust the timing by providing a delay circuit or the like on the clock signal path, but in this case, the operation of adjusting the timing becomes complicated.
[0004]
An object of the present invention is to provide a display panel driving device or the like that can eliminate skew between signals.
[0005]
[Means for Solving the Problems]
The display panel driving device according to the first aspect is converted by the parallel / serial converters (73, 113) for parallel / serial conversion of the drive pulse generation control data and the clock, and the parallel / serial converters (73, 113). The transmission unit (74, 114) which converts the received signal into a signal in accordance with the differential serial transmission method and transfers the signal via the transmission line (L1, L2), and the signal transmitted via the transmission line (L1, L2). A receiving unit (81, 121) for receiving the driving pulse generation control data and the clock; and a serial / parallel converter (83) for serial / parallel converting the driving pulse generation control data and the clock received by the receiving unit (81, 121). ) And the pulse generation control data and clock converted by the serial / parallel converter (83). Characterized by comprising driving pulse output unit for generating a driving pulse for driving the display panel (30) and (18,19,20,21,22, etc.), the.
[0006]
According to this display panel driving device, since the drive pulse generation control data and the clock are parallel / serial converted and transferred, no skew occurs between the drive pulse generation control data and the clock.
[0007]
The display panel driving device according to claim 2 drives the display panel (30) based on a signal from the display control unit (100A) for controlling display of the display panel (30) and the display control unit (100A). In a display panel driving apparatus including a driving unit (100B) and a data transfer unit that transfers data between the display control unit (100A) and the driving unit (100B), the data transfer unit includes a display control unit (100A) And a parallel / serial converter (73, 113) for parallel / serial conversion of the drive pulse generation control data and clock, and a differential serial transmission of a signal serial-converted by the parallel / serial converter (73, 113). A transmission unit (74, 114) that converts the signal into a signal according to the system and transfers the signal to the driving unit (100B) via the transmission line (L1, L2). Receiving units (81, 121) for receiving the drive pulse generation control data and the clock transferred via the transmission lines (L1, L2) in the driving unit (100B); and a receiving unit (81). , 121) for serial-to-parallel conversion of the drive pulse generation control data and the clock received by the serial-to-parallel converter (83, 123).
[0008]
According to this display panel driving device, since the drive pulse generation control data and the clock are parallel / serial converted and transferred, no skew occurs between the drive pulse generation control data and the clock.
[0009]
The display panel driving device according to claim 5, wherein the storage unit (1) stores address data, the read unit (3) reads out the address data stored in the storage unit (1), and a shift clock that generates a shift clock. A display controller (100A) including a generator (5); a shift register (15) for sequentially accumulating address data according to a shift clock; and a latch circuit (16) for latching the address data accumulated in the shift register (15). And a drive unit (100B) including a drive circuit (17) for driving a display panel based on address data output from the latch circuit (16), and a display control unit (100A) and a drive unit (100B). And a data transfer means for transferring the data in the display panel driving device. 0A), a parallel / serial converter (73) for parallel / serial conversion of the address data and the shift clock, and a signal in accordance with the differential serial transmission system in which the signal serial-converted by the parallel / serial converter (73) is converted. And a transmission unit (74) that transfers the data to the drive unit (100B) via the transmission line (L1), and transfers the data to the drive unit (100B) via the transmission line (L1). And a serial / parallel converter (83) for serially / parallel converting the address data and the shift clock received by the receiver (81). It is characterized by.
[0010]
According to this display panel driving device, since the address data and the shift clock are converted from parallel to serial and transferred, no skew occurs between the address data and the shift clock. Therefore, there is no timing shift between the accumulation of the address data in the shift register and the latch of the accumulated address data, and there is no risk of malfunction.
[0011]
In addition, in order to facilitate understanding of the present invention, reference numerals in the accompanying drawings are added in parentheses, but the present invention is not limited to the illustrated embodiment.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a display panel driving device according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a display panel driving device of the present embodiment.
[0013]
As shown in FIG. 1, the display panel driving device 100 of the present embodiment is configured by connecting a display control unit 100A and a driving unit 100B to each other by transmission lines L1 and L2.
[0014]
As shown in FIG. 1, the display control unit 100A includes a frame memory 1 for sequentially storing address data, a write control unit 2 for writing address data to the frame memory 1, and a read control unit for reading address data from the frame memory 1. A read control unit 3, a control unit 5 for controlling each unit of the device, an AND circuit 6 for calculating a logical product of a clock output from the control unit 5 and a signal HA output from the read control unit 3, A serializer 7 that converts read multi-bit parallel data such as address data into a serial differential signal, and a serializer that converts multi-bit parallel data such as control data output from the control unit 5 into a serial differential signal 11 is provided.
[0015]
The driving unit 100B includes a deserializer 8 that converts a serial differential signal transferred from the serializer 7 via the transmission line L1 into multi-bit parallel data, and a serial differential signal transferred from the serializer 11 via the transmission line L2. , A shift register 15 for storing one line of address data, and one line of address data when the one line of address data is stored in the shift register 15. A latch circuit 16 for latching, and an address driver 17 for generating a data pulse for one line according to the address data for one line and applying the data pulse simultaneously to the column electrodes Z1 to Zm of the plasma display panel 30 are provided. Address driver 18 and Y sustain A sustain driver 19 for simultaneously applying pulses to the sustain electrodes Y1 to Yn of the plasma display panel 30, a scan driver 20 for sequentially applying scan pulses to the sustain electrodes Y1 to Yn, and a sustain electrode X1 for applying the X sustain pulse to the plasma display panel 30. To Xn, and a drive control unit 22 that controls the reset pulse generation circuits 20A and 21A that generate reset pulses, the sustain driver 19, the scan driver 20, the sustain driver 21, and the like.
[0016]
As shown in FIG. 1, the serializer 7 includes a PLL unit 71 that receives a clock from the control unit 5 to generate a transmission clock, address data read from the frame memory 1, and a shift clock output from the AND circuit 6. And an input latch unit 72 for latching the pulse generation control data output from the control unit 5 based on the clock from the control unit 5, and parallel data latched by the input latch unit 72 from the PLL unit 71. A parallel / serial conversion unit 73 for serializing based on a clock having a frequency n times the clock input from the control unit 5 and a transmission line L1 formed of a twisted cable or the like for converting the serial data output from the parallel / serial conversion unit 73 And a transmission output unit 74 for performing differential serial transmission via the.
[0017]
The deserializer 8 includes a receiving unit 81 that receives a differential serial signal transferred via the transmission line L1, a PLL unit 82 that receives a transfer clock transferred via the transmission line L1, and generates a clock, A serial / parallel conversion unit 83 that converts a serial signal output from 81 into parallel data based on a clock having a frequency n times as high as a transfer clock from a PLL unit 82, and parallel data output from the serial / parallel conversion unit 83 And an output latch unit 84 that latches the clock with the clock from the PLL unit 82. The transfer clock and the clock supplied to the output latch unit 84 have the same frequency as the clock input to the PLL unit 71.
[0018]
As described above, in the display panel driving apparatus 100 of the present embodiment, both the address data and the shift clock are converted into a series of serial data by the serializer 7 and both are transferred at a time. Therefore, there is no possibility that skew (timing shift) occurs between the address data and the shift clock. As described later, the shift clock is used as a timing clock for latching the address data in the address driver unit 18 on the receiving side (drive unit 100B side). However, since no skew occurs between the address data and the shift clock, There is no risk of malfunction. Also, there is no need for a means for timing adjustment such as a delay circuit for canceling skew.
[0019]
As shown in FIG. 1, the serializer 11 includes a PLL unit 111 that receives a clock from the control unit 5 and generates a transmission clock, a scan driver control data output from the control unit 5, a sustain driver control data, and the like. The input latch unit 112 for latching the pulse generation control data and the clock based on the clock output from the control unit 5, respectively, and the parallel data latched by the input latch unit 112 are input from the control unit 5. A parallel / serial converter 113 for serializing based on a clock having a frequency n times the clock, and differential serial transmission of serial data output from the parallel / serial converter 113 via a transmission line L2 such as a twisted cable. And a transmission output unit 114 that performs the transmission.
[0020]
The deserializer 12 includes: a receiving unit 121 that receives a differential serial signal transferred via the transmission line L2; a PLL unit 122 that receives a transfer clock transferred via the transmission line L2 to generate a clock; A serial / parallel conversion unit 123 that converts a serial signal output from the serial signal 121 into parallel data based on a clock having a frequency n times the transfer clock from a PLL unit 122, and parallel data output from the serial / parallel conversion unit 123 And an output latch unit 124 for latching the clock with the clock from the PLL unit 122. The transfer clock and the clock supplied to the output latch unit 124 have the same frequency as the clock input to the PLL unit 111.
[0021]
As shown in FIG. 1, a clock output from the deserializer 12 is provided to the drive control unit 22, and the drive control unit 22 controls the generation timing of the drive pulse based on the clock.
[0022]
As described above, in the display panel driving apparatus 100 of the present embodiment, the serializer 11 uses the serializer 11 to convert the control data such as the scan driver control data, the sustain driver control data, and other pulse generation control data into a series of serial data. Is converted and transferred, and both are transferred collectively. Therefore, there is no possibility that skew (timing shift) occurs between the control data and the clock. As will be described later, the transferred clock is used as a timing clock when a drive pulse is generated based on the control data in the drive control unit 22 on the receiving side (drive unit 100B side). However, in the present embodiment, since no skew occurs between the control data and the clock, there is no possibility of causing a malfunction. Also, there is no need for a means for timing adjustment such as a delay circuit for canceling skew.
[0023]
Next, the operation of the panel driving device 100 will be described.
[0024]
One field as a period for driving the plasma display panel 30 includes a plurality of subfields SF1 to SFN. As shown in FIG. 2, each subfield is provided with an address period for selecting a cell to be lit and a sustain period for keeping the cell selected in the address period lit for a predetermined time. Further, a reset period for resetting the lighting state in the previous field is further provided at the head of SF1, which is the first subfield. In this reset period, all cells are reset to lighting cells (cells on which wall charges are formed) or off cells (cells on which no wall charges are formed). In the former case, a predetermined cell is switched to a non-lighted cell, and in the latter case, a predetermined cell is switched to a lighted cell in a subsequent address period. The sustain period is gradually increased in the order of the subfields SF1 to SFN, and a predetermined gradation display is enabled by changing the number of the subfields to be continuously turned on.
[0025]
In the address period of each subfield shown in FIG. 3, address scanning is performed for each line. That is, at the same time as the scanning pulse is applied to the row electrode Y1 forming the first line, the data pulse DP1 corresponding to the address data corresponding to the cell of the first line is applied to the column electrodes Z1 to Zm. At the same time, a scan pulse is applied to the row electrode Y2 forming the second line, and at the same time, a data pulse DP2 corresponding to the address data corresponding to the second cell is applied to the column electrodes Z1 to Zm. Similarly, the scanning pulse and the data pulse are simultaneously applied to the third and subsequent lines. Lastly, the scan pulse is applied to the row electrodes Yn forming the n-th line, and at the same time, the data pulses DPn corresponding to the address data corresponding to the cells of the n-th line are applied to the column electrodes Z1 to Zm. . As described above, in the address period, a predetermined cell is switched from a lit cell to a non-lit cell or from a non-lit cell to a lit cell.
[0026]
When the address scanning is completed in this way, all the cells in the subfield are set as either the lighted cells or the lighted cells, and only the lighted cells emit light each time a sustain pulse is applied in the next sustain period. repeat. As shown in FIG. 3, during the sustain period, an X sustain pulse and a Y sustain pulse are repeatedly applied to the row electrodes X1 to Xn and the row electrodes Y1 to Yn at predetermined timings. In the last subfield SFN, there is provided an erasing period in which all cells are set to non-lighted cells.
[0027]
Next, signal processing of various control data and clocks used for driving the plasma display panel 30 will be described.
[0028]
As shown in FIG. 1, the address data read from the frame memory 1, the shift clock output from the AND circuit 6, and the control data for pulse generation output from the control unit 5 are used as clocks from the control unit 5. Then, the signal is converted into a serial signal by a parallel / serial conversion unit 73 and converted into a signal according to a differential serial transmission system (LVDS transmission system) by a transmission output unit 74. The differential serial signal (LVDS signal) thus obtained is transferred at high speed LVDS data via the transmission line L1. Here, the address data is bit data (serial data) for each subfield for each cell of R, G, and B, and the serial data of each of R, G, and B is stored in the serializer 7 together with the shift clock and the control data for pulse generation. Are input in parallel. These parallel data are serial-converted in the serializer 7.
[0029]
The serial signal transferred via the transmission line L1 is parallel-converted in the deserializer 8, and the original parallel signal is restored.
[0030]
FIG. 4 is a diagram showing the timing of writing address data and latch enable. The address data output from the deserializer 8 is sequentially written into the shift register 15 line by line. As shown in FIG. 4, the latch enable input to the latch circuit 16 rises at the same time as the rise of the shift clock for writing the last data (data z) for one line, so that the data for one line (for example, Data a to data z) are latched and input to the address driver 17 at the same time. Thus, as described above, at the same time as the scanning pulse is sequentially applied to the row electrodes Y1 to Yn in the address period, the data pulses DP1 to DPn corresponding to the predetermined address data are applied to the column electrodes Z1 to Zm. This latch enable is generated in the latch enable generation unit 16A based on the shift clock.
[0031]
In the present embodiment, the signal HA is output from the read control unit 3 only while the address data is being read from the frame memory 1. As shown in FIG. 1, by inputting the signal HA and the clock output from the control unit 5 to the AND circuit 6, the clock passes only during the period in which the signal HA is output ("H"). And outputs it as a shift clock. That is, the supply of the shift clock is stopped during a period in which the address data is not read from the frame memory 1. For this reason, as shown in FIG. 4, the shift clock is not supplied during the period in which the address data is not read, and during this period, the data in the shift register 15 is not updated, and the normal latch enable signal is not The memory state at the time of starting up is maintained. Therefore, as shown in FIG. 4, even when the noise is superimposed on the latch enable, the data latched by the noise becomes the same as the normal address data. Therefore, even if the address data is latched at an incorrect timing due to noise, a data pulse according to the normal address data is applied to the plasma display 30.
[0032]
The pulse generation control data output from the deserializer 8 is data for controlling on / off of a switch provided in an address resonance power supply circuit 17A (FIG. 1) that outputs a drive pulse to the address driver 17. . A specific example of the address resonance power supply circuit 17A will be described later.
[0033]
On the other hand, as shown in FIG. 1, the control data for the scan driver, the control data for the sustain driver, the other control data for pulse generation, and the clock output from the control unit 5 are parallelized based on the clock from the control unit 5. / Serial conversion is performed by the serial conversion unit 113, and is converted into a signal according to the differential serial transmission system (LVDS transmission system) by the transmission output unit 114. The differential serial signal (LVDS signal) thus obtained is transferred at high speed LVDS data via the transmission line L2. Here, the scan driver control data, the sustain driver control data, the other pulse generation control data, and the clock are input to the serializer 11 in parallel, and these parallel data are serial-converted in the serializer 11.
[0034]
The serial signal transferred via the transmission line L2 is parallel-converted in the deserializer 12, and the original parallel signal is restored.
[0035]
The scan driver control data, the sustain driver control data, and other pulse generation control data output from the deserializer 12 are input to the drive control unit 22, respectively. The drive control unit 22 sends a signal for turning on / off a switching element provided in the scan driver 20 based on the scan driver control data to a switching element provided in the sustain drivers 19 and 21 based on the sustain driver control data. , And a signal for turning on / off a switching element for generating a reset pulse, an erase pulse, and the like based on other pulse generation control data.
[0036]
As described above, the clock included in the parallel signal output from the deserializer 12 is provided to the drive control unit 22, and the drive control unit 22 controls the operation timing based on the clock.
[0037]
Next, a specific example of the address resonance power supply circuit 17A and the address driver 17 will be described with reference to FIGS.
[0038]
The address resonance power supply circuit 17A shown in FIG. 5 generates a resonance pulse power supply potential having a predetermined amplitude and outputs it to the power supply line Z shown in FIG. One end of the capacitor C1P in the address resonance power supply circuit 17A is grounded to the ground potential Vs of the plasma display 30. When the switching element S1P is on, the potential generated at the other end of the capacitor C1P is applied to the power supply line Z via the coil L1P and the diode D1P. When the switching element S2P is ON, the potential of the power supply line Z is applied to the other end of the capacitor C1P via the coil L2P and the diode D2P. At this time, the capacitor C1P is charged by the potential on the power supply line Z. When the switching element S3P is in the ON state, the power supply potential Va from the DC power supply B1P is applied to the power supply line Z. The negative terminal of the DC power supply B1P is grounded to the ground potential Vs of the plasma display panel 30.
[0039]
As shown in FIG. 5, the address driver 17 performs switching that is independently turned on / off in accordance with each of (m) pixel data bits DB <b> 1 to DBm for one row output from the deserializer 8. Elements SWZ1 to SWZm and SSWZ1o to SWZmo are provided. Each of the switching elements SWZ1 to SWZm is turned on only when the pixel data pit DB supplied thereto is at the logic level “1”, and the switching elements SWZ1 to SWZm apply the resonance pulse power supply potential applied on the power supply line Z to the plasma. It is applied to the column electrodes Z1 to Zm of the display panel 30. On the other hand, each of switching elements SWZ1o to SWZmo is turned on only when pixel data bit DB is at logic level "0", and the potential on the column electrode is grounded to ground potential Vs.
[0040]
Hereinafter, the operation of the address resonance power supply circuit 17A and the address driver 17 during the address period will be described with reference to FIG.
[0041]
As shown in FIG. 5, the pulse resonance control data output from the control unit 5 and transferred is input to the address resonance power supply circuit 17A. The pulse generation control data is data for turning on / off the switching elements SW1P to SW3P. As shown in FIG. 6, each switching element repeats inversion so that the switching elements SW1P, SW3P, and SW2P are repeatedly turned on sequentially in accordance with the pulse generation control data. With such an operation, the potential on the power supply line Z is periodically increased. This period in which the potential increases periodically coincides with the scan timing by the scan driver 20.
[0042]
At this time, the pixel data bits DB corresponding to the predetermined column electrodes Z1 to Zm are provided to the switching elements SWZ1 to SWZm and SWZ1o to SWZmo of the address driver 17 in accordance with the timing when the potential on the power supply line Z rises. Is entered. In FIG. 6, the bit sequence of the pixel data bits DB corresponding to the first to seventh rows in the i-th column is
[1, 0, 1, 0, 1, 0, 1]
Is shown. This pixel data bit DB is nothing but the address data latched by the latch circuit 16. In the address period, the above-described operation is sequentially performed on each column, so that the cells can be set to the lit cells / the non-lit cells for each column.
[0043]
Next, specific examples of the sustain drivers 19 and 21 and the scan driver 20 will be described with reference to FIGS.
[0044]
The sustain driver 21 includes a DC power supply B1 that generates a DC voltage VS, switching elements S1 to S4, coils L1 and L2, diodes D1 and D2, and a capacitor C1. When the switching element S1 is in the ON state, the potential on one end of the capacitor C1 is applied to the row electrode Xi via the coil L1 and the diode D1. When the switching element S2 is in the ON state, the potential on the row electrode Xi is applied to one end of the capacitor C1 via the coil L2 and the diode D2. When switching element S3 is on, voltage VS generated by DC power supply B1 is applied to row electrode Xi. When the switching element S4 is on, the row electrode Xi is grounded.
On / off of the switching elements S1 to S4 of the sustain driver 21 is controlled based on the sustain driver control data output from the control unit 5 and transferred.
[0045]
The reset pulse generation circuit 21A includes a DC power supply B2 that generates a DC voltage VRx, a switching element S7, and a resistor R1. The positive terminal of the DC power supply B2 is grounded, and its negative terminal is connected to the switching element S7. When the switching element S7 is in the ON state, the voltage −VR that is the negative terminal voltage of the DC power supply B2 is applied to the row electrode Xi via the resistor R1.
On / off of the switching element S7 of the reset pulse generation circuit 21A is controlled based on other pulse generation control data output from the control unit 5 and transferred.
[0046]
The sustain driver 19 includes a DC power supply B3 that generates a DC voltage VS, switching elements S11 to S14, coils L3 and L4, diodes D3 and D4, and a capacitor C2. When the switching element S11 is on, the potential on one end of the capacitor C2 is applied to the line 31 via the coil L3 and the diode D3. When the switching push S12 is in the ON state, the potential on the line 31 is applied to one end of the capacitor C2 via the coil L4 and the diode D4. When the switching element S13 is in the ON state, the voltage VS generated by the DC power supply B3 is applied to the line 31. When the switching element S14 is on, the line 31 is grounded.
[0047]
On / off of the switching elements S11 to S14 of the sustain driver 19 is controlled based on the sustain driver control data output from the control unit 5 and transferred.
[0048]
Next, the reset pulse generation circuit 20A includes a DC power supply B4 that generates a DC voltage VRy (where | VRy | <| VRx |), switching elements S15 and S16, and a resistor R2. The positive terminal of the DC power supply B4 is grounded, and its negative terminal is connected to the switching element S16. When the switching element S16 is in the ON state, the voltage VRy, which is the positive terminal voltage of the DC power supply B4, is applied to the line 32 via the resistor R2. When the switching element S15 is on, the line 31 and the line 32 are connected.
[0049]
On / off of the switching elements S15 and S16 of the reset pulse generation circuit 20A is controlled based on other pulse generation control data output from the control unit 5 and transferred.
[0050]
The scan driver 20 is provided for each of the row electrodes Y1 to Yn, and includes a DC power supply B5 that generates a DC voltage Vh, switching elements S21 and S22, and diodes D5 and D6. When the switching element S21 is in the ON state, the positive terminal of the DC power supply B5, the row electrode Y, and the cathode end of the diode D6 are connected together. When the switching element S22 is on, the negative terminal of the DC power supply B5, the row electrode Y, and the anode end of the diode D5 are connected together.
[0051]
On / off of the switching elements S21 and S22 of the scan driver 20 is controlled based on the scan pulse control data output from the control unit 5 and transferred.
[0052]
FIG. 8 shows that each of the address driver 17, the sustain drivers 19 and 21, the scan driver 20, and the reset pulse generating circuits 20A and 21A applies the address electrodes Z1 to Zm, the row electrodes X1 to Xn, and the Y1 to Yn of the plasma display panel 30. FIG. 3 is a diagram showing an example of application timings of various driving pulses to be applied.
[0053]
As shown in FIG. 8, in the reset period Rc, the reset pulse generation circuits 21A and 20A simultaneously apply the reset pulses RPX1 and RPY1 to the row electrodes X1 to Xn and Y1 to Yn, respectively. As a result, discharge occurs between the row electrodes in all cells, and uniform wall charges are formed in each cell. Thereby, all the cells are initialized to the lighting cells.
[0054]
In the address period Wc, the address driver 17 sequentially applies the pixel data pulse group for each row to the column electrodes Z1 to Zm. This pixel data pulse group corresponds to the bit sequence of the pixel data bits DB. At this time, the scan driver 20 generates a scan pulse SP at the same timing as the application of the pixel data pulse group, and sequentially applies the scan pulse SP to the row electrodes Y1 to Yn. At this time, in the cell, a discharge (selective erase discharge) occurs between the row electrode and the address electrode only when the scan pulse SP is applied to one of the row electrodes and a high-voltage pixel data pulse is applied to the address electrode. Then, the wall charges remaining in the cell are erased, and the cell shifts to a non-lighted cell. Wall charges remain in other cells, and those cells are maintained as lit cells. In this way, in the address period Wc, all the cells are set as the lit cells and the lit cells according to the address data.
[0055]
Next, in the sustain period Ic, the sustain drivers 21 and 19 alternately apply the sustain pulses IPX and IPY having the pulse amplitude Vs to the row electrodes X1 to Xn and Y1 to Yn. At this time, only the lighting cells in which the wall charges remain in the address period repeatedly emit light.
[0056]
An erasing period E is provided in the last subfield (subfield SF14 in FIG. 8) in one field. In this case, the address driver 17 generates an erasing pulse AP, and applies this to the column electrodes Z1 to Zm. Apply. On the other hand, the scan driver 20 generates an erasing pulse EP at the same time as the erasing pulse AP and applies this to each of the row electrodes Y1 to Yn. By the simultaneous application of these erasing pulses AP and EP, an erasing discharge occurs in all cells, and the wall charges disappear.
[0057]
FIG. 9 shows the application timing of the drive pulse applied from the address driver 17, the sustain drivers 19 and 21, the scan driver 20, and the reset pulse generation circuits 20A and 21A to the plasma display panel 30 when such a selective erase address method is employed. FIG. 3 is a diagram illustrating switching timings of the respective switching elements.
[0058]
Although detailed description of FIG. 9 is omitted, as described above, by controlling a large number of switching elements provided in the address driver 17, the sustain drivers 19 and 21, the scan driver 20, and the reset pulse generation circuits 20A and 21A, A desired drive pulse can be applied to each electrode of the plasma display panel 30.
[0059]
As described above, in the display panel driving apparatus 100 according to the embodiment, the address data is stored in the shift register 15 by using the shift clock generated by using the clock output from the control unit 5, and the shift clock is generated. The address data stored in the register 15 is latched. However, in the display panel driving apparatus 100, both the address data and the shift clock are converted into a series of serial data by the serializer 7 and transferred. In other words, the shift clock is converted into data at the same time as the address data, and then both are batched. Transfer. For this reason, there is no possibility that skew occurs between the address data and the shift clock, and no means for timing adjustment such as a delay circuit is required.
[0060]
In addition, control data such as scan driver control data, sustain driver control data, and other pulse generation control data, and a clock are converted by the serializer 11 into a series of serial data and transferred. Therefore, there is no possibility that skew occurs between the control data and the clock. Therefore, there is no need for a means for timing adjustment such as a delay circuit for canceling skew.
[0061]
In this embodiment, since the differential serial transmission system using the LVDS is employed, there are advantages such as being less susceptible to noise and reducing noise radiation to the outside.
[0062]
The address data, the pulse generation control data, the scan driver control data, the sustain driver control data, and the other pulse generation control data in the above-described embodiment are respectively referred to as “drive pulse generation control data” described in each claim. Corresponding to The drive pulse generation control data is not limited to the data described in the above embodiment.
[0063]
In the above embodiments, the plasma display panel is exemplified as the display panel, but the present invention can be applied to various panels such as a liquid crystal display panel and an EL display panel as the display panel.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a display panel driving device according to an embodiment.
FIG. 2 is a diagram showing a configuration of one field.
FIG. 3 is a diagram showing a driving pulse in one subfield.
FIG. 4 is a diagram showing address data latched by a latch enable;
FIG. 5 is a diagram showing a configuration of an address resonance power supply circuit and an address driver.
FIG. 6 is a diagram showing an operation of an address resonance power supply circuit and an address driver during an address period.
FIG. 7 is a diagram illustrating a configuration of a sustain driver, a scan driver, and the like.
FIG. 8 is a diagram illustrating an example of application timings of various drive pulses applied to an address electrode and a row electrode.
FIG. 9 is a diagram showing a drive pulse application timing and a switching timing of each switch element when a selective erase address method is adopted.
[Explanation of symbols]
1 Frame memory (storage unit)
3 Read control unit (read unit)
5 control unit (shift clock generation unit)
15 shift register
16 Latch circuit
17 Address Driver (Drive Circuit)
18 Address driver section (drive pulse output section)
19, 21 Sustain driver (drive pulse output unit)
20 scan driver (drive pulse output unit)
20A, 21A reset pulse generation circuit (drive pulse output unit)
22 Drive control unit (drive pulse output unit)
30 Plasma display panel (display panel)
73,113 Parallel / serial converter
74,114 transmission output unit (transmission unit)
81, 121 receiver
83 Serial / Parallel Converter
100A display control unit
100B drive unit
L1, L2 transmission line

Claims (7)

A parallel / serial converter for parallel / serial conversion of drive pulse generation control data and clock;
A transmitting unit that converts a signal converted by the parallel / serial converter into a signal according to a differential serial transmission method and transfers the signal via a transmission line;
A receiving unit that receives the drive pulse generation control data and the clock transferred through the transmission line,
A serial / parallel converter for serial / parallel converting the drive pulse generation control data and the clock received by the receiving unit;
A drive pulse output unit that generates a drive pulse for driving a display panel based on the pulse generation control data and the clock converted by the serial / parallel converter;
A display panel driving device comprising: A display control unit that controls display on a display panel, a driving unit that drives the display panel based on a signal from the display control unit, and a data transfer unit that transfers data between the display control unit and the driving unit. A display panel driving device comprising:
The data transfer means,
A parallel / serial converter for parallel / serial conversion of drive pulse generation control data and a clock in the display control unit;
A transmission unit that converts a signal serial-converted by the parallel / serial converter into a signal according to a differential serial transmission method and transfers the signal to the driving unit via a transmission line;
In the driving unit, a receiving unit that receives the driving pulse generation control data and the clock transferred through the transmission line,
A display panel driving device, comprising: a serial / parallel converter for serial / parallel converting the drive pulse generation control data and the clock received by the receiving unit. In a display control device that controls display on a display panel,
A display control device comprising the display control unit of the display panel driving device according to claim 2. In a driving device for driving a display panel,
A drive device comprising the drive unit of the display panel drive device according to claim 2. A storage unit that stores the address data, a reading unit that reads the address data stored in the storage unit, and a display control unit that includes a shift clock generation unit that generates a shift clock;
A shift register for sequentially storing the address data in accordance with the shift clock, a latch circuit for latching the address data stored in the shift register, and a drive for driving a display panel based on the address data output from the latch circuit A driving unit including a circuit;
Data transfer means for transferring data between the display control unit and the drive unit;
In a display panel drive device comprising:
The data transfer means,
A parallel / serial converter for parallel / serial conversion of the address data and the shift clock in the display control unit;
A transmitting unit that converts a signal serial-converted by the parallel / serial converter into a signal according to a differential serial transmission method and transfers the signal to the driving unit via a transmission line;
With
A receiving unit for receiving the address data and the shift clock transferred via the transmission line in the driving unit; and a serial / parallel converter for serial / parallel converting the address data and the shift clock received by the receiving unit. A parallel conversion unit,
A display panel driving device comprising: In a display control device that controls display on a display panel,
A display control device comprising the display control unit of the display panel driving device according to claim 5. In a driving device for driving a display panel,
A driving device comprising the driving unit of the display panel driving device according to claim 5.

Images