JP2004022996A - Method for stacking semiconductor chip - Google Patents

Method for stacking semiconductor chip Download PDF

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Publication number
JP2004022996A
JP2004022996A JP2002179013A JP2002179013A JP2004022996A JP 2004022996 A JP2004022996 A JP 2004022996A JP 2002179013 A JP2002179013 A JP 2002179013A JP 2002179013 A JP2002179013 A JP 2002179013A JP 2004022996 A JP2004022996 A JP 2004022996A
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protective film
semiconductor chip
semiconductor
circuit
circuit surface
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JP4343493B2 (en
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Hitoshi Kinoshita
木下　仁
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Mitsui Chemicals Inc
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Mitsui Chemicals Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress warping of a thin semiconductor wafer 22 while enhancing productivity and bonding strength. <P>SOLUTION: A protective film 3 of heat resistant thermoplastic resin having a glass transition point not higher than 150°C is formed on the circuit plane 4 of the semiconductor wafer 22. A contact hole 6 for exposing the electric signal connecting part of a first semiconductor chip 2 is made in the protective film 3. The semiconductor wafer 22 is then individuated to obtain the first semiconductor chip 2 having a protective film. Back surface 31 of another second semiconductor chip 12 is then bonded onto the protective film 3 by hot press, thus stacking the semiconductor chips 2 and 12. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路などの半導体装置における半導体チップの積層方法に関し、またその半導体チップが積層された構成を有する半導体装置に関する。
【０００２】
【従来の技術】
先行技術では、半導体チップの電気回路が形成された回路面に、ポリイミドから成る保護膜を形成し、この保護膜によって、バッファコート膜の働きであるα線を遮蔽するとともに、封止用合成樹脂と半導体チップとの温度変化に起因した応力発生を緩和する。電気信号接続部やダイシング部位を開口後、半導体ウエハは、保護膜とともにダイシングされ、保護膜付き半導体チップが得られる。この半導体チップの上に、もう１つの半導体チップを積層して固定するには、従来では、保護膜上に、ペーストもしくはフィルム状の接着剤を介在して、前記もう１つの半導体の裏面を接着する。
【０００３】
この先行技術では、保護膜上に、接着剤を用いて前記もう１つの半導体チップを接着するので、その積層のための工程が煩雑であり、生産性が悪いという問題がある。
【０００４】
近年、パッケージの厚みを小さくするために、半導体チップを薄く形成する傾向がある。半導体チップ、したがって半導体ウエハの厚みが、１５０μｍ以下になると、ポリイミドから成る保護膜が回路面に形成された構成では、その半導体ウエハの回路面と保護膜との間の温度の変化に起因した応力によって、半導体ウエハが反り、湾曲変形する。これによって半導体ウエハの真空吸着などによる運搬が困難になるという新たな問題が生じる。
【０００５】
また半導体チップ、したがって半導体ウエハの厚みが、たとえば５０μｍ程度まで小さくされた構成では、積層時における保護膜および接着剤の厚みが、半導体チップの厚みに比べて大きい値になりすぎる。したがって積層される複数の半導体チップ間の接着のための構成を、薄くする要求が高まっている。
【０００６】
【発明が解決しようとする課題】
本発明の目的は、積層される複数の半導体チップの接着のための構成を簡略化して、生産性を向上し、接着強度を向上し、薄くすることができるようにした半導体チップの積層方法およびその積層された半導体チップを備える半導体装置を提供することである。
【０００７】
【課題を解決するための手段】
本発明は、第１の半導体チップの電気回路が形成された回路面に、
ガラス転移温度が１５０℃以下である保護膜を介して、
第２の半導体チップの裏面を、接着することを特徴とする半導体チップの積層方法である。
【０００８】
また本発明は、電気回路が形成された回路面と、その回路面の厚み方向反対側の裏面とを有し、回路面には、電気信号接続部が形成される第１の半導体チップと、
ガラス転移温度が１５０℃以下であり、回路面に形成され、回路面の電気信号接続部を露出する接続孔が形成される保護膜と、
保護膜の接続孔が形成されていない領域に接着される裏面を有する第２の半導体チップとを含むことを特徴とする半導体装置である。
【０００９】
本発明に従えば、図１〜図１０に関連して後述されるように、第１半導体チップ２の回路面４と第２の半導体チップ１２の裏面３１との間に、ガラス転移温度Ｔｇが１５０℃以下である保護膜３が介在され、この保護膜によって、第１および第２半導体チップが接着されて固定される。この保護膜は、第１半導体チップの回路面にα線が照射することを防いでα線を遮蔽する働きをするとともに、封止のための合成樹脂２１と第１半導体チップとの温度変化に起因した応力を緩和する働きを果たす。
【００１０】
保護膜は、１５０℃以下、好ましくは１００℃以下のできるだけ常温に近いガラス転移温度Ｔｇを有する。ガラス転移温度Ｔｇが前述のように低いことによって、より低温で、より低い圧力で短時間に、第１および第２半導体チップの接着を行うことができる。低温で接着が可能であることによって、接着時において、第１および第２半導体チップおよびそのほかの材料は、耐熱性が低くても、損傷を生じることはなく、また低い圧力で接着が可能となるので、第１および第２半導体チップなどが破損することが防がれる。このようにして優れたチップ接合のための特性を得ることができる。比較的低いガラス転移温度Ｔｇを有する保護膜は、たとえば（Ａ）熱可塑性樹脂と、（Ｂ）熱硬化性樹脂とから成る樹脂組成物を含む。このような樹脂組成物は、短時間低温接着性、応力緩和性および耐熱性の面で優れている。
【００１１】
第１および第２半導体チップは、たとえば１５０μｍ以下であり、その一例としてたとえば５０μｍであってもよい。このような比較的薄い第１および第２半導体チップであっても、前述のように１５０℃以下、好ましくは１００℃以下のガラス転移温度Ｔｇを有する保護膜を用いることによって、第１および第２半導体チップ、およびその第１および第２半導体チップを得るための半導体ウエハが、反りを生じる現象を抑制することができる。これによって半導体ウエハの真空吸着などによる搬送を確実に行うことができる。さらにこのような低いガラス転移温度Ｔｇを有する保護膜は、たとえば溶剤を用いるスピンコートによる手法で第１半導体チップの回路面に形成することでき、その工程において、溶剤乾燥性が優れており、そのため生産性が改善される。
【００１２】
本発明では、保護膜が、第１半導体チップの回路面を保護するための働きをするとともに、第２半導体チップとの接着の働きを兼ねており、したがって前述の先行技術における接着剤を別途必要とすることはない。このことによっても、生産性が向上され、また全体の厚みを小さくすることができる。
【００１３】
また本発明は、第１の半導体チップの電気回路が形成された回路面に、
ガラス転移温度が１５０℃以下である保護膜を介して
スペーサの一表面を接着し、
このスペーサの他表面に、接着剤を介して、第２の半導体チップの裏面を、接着することを特徴とする半導体チップの積層方法である。
【００１４】
また本発明は、電気回路が形成された回路面と、その回路面の厚み方向反対側の裏面とを有し、回路面には、電気信号接続部が形成される第１の半導体チップと、
ガラス転移温度が１５０℃以下であり、回路面に形成され、回路面の電気信号接続部を露出する接続孔が形成される保護膜と、
保護膜の接続孔が形成されていない領域に一表面が接着されるスペーサと、
スペーサの他表面に、接着剤を介して裏面が接着される第２の半導体チップとを含むことを特徴とする半導体装置である。
【００１５】
本発明に従えば、図１１に関連して後述されるように、スペーサ３９（材質としてはたとえばシリコン）を用いることによって、第１および第２半導体チップの平面形状の寸法がたとえばほぼ同一であっても、その第１および第２半導体チップの平面形状よりも小さい平面形状を有するスペーサを用いることによって、第１および第２半導体チップの積層が可能になる。スペーサ３９が第１および第２半導体チップ間に介在される。保護膜３は、第１半導体チップとスペーサ３９との接着の働きを果たす。したがって前述と同様に、生産性が向上され、優れた接着強度を得ることができ、薄く構成することができ、半導体ウエハの反りが生じることを防ぐことができる。
【００１６】
また本発明は、複数の第１の半導体チップにダイシングされるべき半導体ウエハの回路面に、前記保護膜を形成し、
この保護膜に、各第１半導体チップの回路面の電気信号接続部用接続孔およびダイシング用長孔を、形成し、
その後、半導体ウエハを、前記保護膜とともに、複数の第１の半導体チップにダイシングすることを特徴とする。
【００１７】
また本発明は、第１半導体チップの厚みは、１５０μｍ以下であることを特徴とする。
【００１８】
本発明に従えば、第１の半導体チップ２を得るために、半導体ウエハ２２の回路面に保護膜３を形成し、こうして製造された保護膜付き半導体ウエハ２７の前記保護膜に、第１半導体チップの回路面における電気信号接続部を露出する接続孔６およびダイシング用長孔を形成し、その後、個別の第１半導体チップにダイシングをする。こうして保護膜付き第１半導体チップ２を得る。
【００１９】
裏面にダイアタッチフィルムを貼付け、ダイシングする方法に比べ、ダイアタッチフィルムをダイシングしないため、ダイシング性に優れる。また、ピックアップ時も、ダイシングテープとダイアタッチフィルムの剥離性が問題とならないので優れる。
【００２０】
このような第１半導体チップの厚みは、前述のように１５０μｍ以下であってもよく、たとえば５０μｍであってもよく、さらに５０μｍ以下のもっと薄い値であってもよい。
【００２１】
また本発明は、保護膜は、熱可塑性合成樹脂および熱硬化性合成樹脂から成ってもよいが、さらに他の添加剤、充填剤などの物質を含んでもよい。
【００２２】
また本発明は、保護膜は、シリコーン系材料から成ることを特徴とする。
本発明に従えば、保護膜は、不純物イオン分含有量が少ないこと、第１半導体チップのための半導体ウエハの反りが生じないことが要求され、半導体ウエハの反りを抑制するには、保護膜を構成する合成樹脂の硬化収縮率、ガラス転移温度Ｔｇ、線膨張率などの選択が重要であり、ガラス転移温度Ｔｇを、前述のように１５０℃以下、好ましくは１００℃以下に選び、常温に近づけることによって、半導体ウエハの反りの問題を改善することができる。保護膜を、熱可塑性合成樹脂層とし、耐熱性を架橋構造とすることによって付与し、好ましいチップ接合特性を達成する保護膜が得られる。このような保護膜は、各種信頼性テストに合格する合成樹脂が好ましく、熱可塑性合成樹脂および熱硬化性合成樹脂は、このような各種信頼性テストに合格する特性を有する。
【００２３】
保護膜はまた、シリコーン系材料から成り、たとえば有機ケイ素系合成樹脂であってもよく、シリコーン樹脂であってもよい。シリコーン系接着剤は、Ｓｉ系材料に対する接着強度が高いので、シリコーン系接着剤の表面にある第１および第２半導体チップは、シリコーン系材料から成る保護膜を用いることによって、またさらにスペーサを用いる構成では、そのスペーサもシリコン系材料製とし、これによって高い接着信頼性を得て接着されることができる。
【００２４】
また本発明は、２段スタック構造に限定されるものではなく、３以上の半導体チップが前述と同様に保護膜、スペーサを介して３段以上の複数段のスタック構造が実現されてもよい。
【００２５】
【発明の実施の形態】
図１は、本発明の実施の一形態の保護膜付き半導体チップ１の斜視図である。この保護膜付き半導体チップ１は、第１半導体チップ２と保護膜３とを含む。第１半導体チップ２は、半導体サブストレートの回路面４に、電気回路が形成され、その厚み方向の回路面４と反対側は裏面５となっている。回路面４には、前記保護膜３が形成される。保護膜３には、第１半導体チップ２の回路面４に形成された電気信号接続部を露出する１または複数の接続孔６が形成される。接続孔６には、領域７の外方に形成され、したがって領域７には、接続孔６が形成されていない。
【００２６】
図２は、図１に示される保護膜付き半導体チップ１を含む半導体装置８の断面図である。保護膜３の前記領域７には、もう１つの保護膜付き半導体チップ１１が接着されて固定され、積層される。この保護膜付き半導体チップ１１は、第２半導体チップ１２と、その第２半導体チップ２の回路面に形成された保護膜１３とを含む。第１半導体チップ２の平面形状の寸法は、第２半導体チップ１２の平面形状よりも大きい。第２半導体チップ１２に形成される保護膜１３は、前述の第１半導体チップ２の保護膜３と同様な材料から成ってもよいが、接着機能を有さないそのほかの材料から成ってもよい。
【００２７】
第１半導体チップ２の裏面５は、接着剤１４を介して電気絶縁性材料から成る基板１５に接着されて固定される。基板１５は、たとえば合成樹脂製であってもよく、またはセラミックなどから成ってもよい。保護膜３に形成された接続孔６を挿通するボンディングワイヤ１６の一端部は、その接続孔６に露出する回路面４の電気信号接続部に接続される。このワイヤ１６の他端部は、基板１５に設けられた端子１７に接続される。また同様にして第２半導体チップ１２も、ボンディングワイヤ１８を介して、端子１９に接続される。基板１５には、これらの保護膜付き半導体チップ１，１１およびボンディングワイヤ１６，１８などを被覆する合成樹脂２１によって封止される。
【００２８】
図３は、第１半導体ウエハ２２の断面図である。図３〜図９を参照して、半導体装置８の製造方法を説明する。まず図３に示されるように、半導体ウエハ２２の厚みｄ１は、１５０μｍ以下であり、たとえば５０μｍであってもよく、薄く形成される。この半導体ウエハ２２は、ほぼ円板状であり、ダイシングによって複数の第１半導体チップ２が得られる。
【００２９】
図４は、図３に示される半導体ウエハ２の回路面４に保護膜３が形成された状態を示す断面図である。保護膜３は、たとえばスピンコートやフィルムのラミネートで形成される。保護膜３の厚みｄ２は、たとえば５μｍであってもよい。
【００３０】
図５は、図５〜図８に示されるフォトリソグラフィの手法によって、保護膜３に、接続孔６やダイシング用長孔を、形成する工程を示す断面図である。フォトレジスト膜２４は、たとえば溶媒に溶解されたフォトレジスト膜２４の材料を含むワニスを、スピンコートの手法で、塗布されて形成される。
【００３１】
図６は、図５に示されるフォトレジスト膜２４を露光する工程を示す断面図である。フォトレジスト膜２４上にフォトマスク２５を配置し、紫外線などの光２６を照射することによって、フォトレジスト膜２４を選択的に露光する。
【００３２】
図７は、図６に示される露光の後、現像を行ったフォトレジスト膜２４およびドライまたはウエットエッチングによって保護膜３の接続孔６およびダイシング用長孔などの予め定める指定場所をエッチングした状態を示す断面図である。
【００３３】
図８は、図７に示される現像後のフォトレジスト膜２４を除去してエッチングを完了した状態における半導体ウエハ２２と保護膜３とを有する保護膜付き半導体ウエハ２７を示す断面図である。保護膜３には、半導体ウエハ２２の回路面４における複数の第１半導体チップ２のための電気信号接続部にそれぞれ対応して、接続孔６が形成される。
【００３４】
図９は、図８に示される保護膜３が形成された半導体ウエハ２２をダイシングする状態を示す断面図である。半導体ウエハ２２の裏面には、ダイシングテープ２８が接着され、基台２９に固定される。ダイシングブレードなどの回転刃物によって、保護膜３が形成された半導体ウエハ２２が切断されて、またダイシングテープ２８が厚み方向に部分的に切断されて、個別の保護膜付き半導体チップ１が得られる。ダイシングされる部分もエッチング工程で保護膜３が除かれてダイシング用長孔が形成されることによって、ダイシングブレードなどの刃物で半導体ウエハ２２を半導体チップに良好にダイシングすることができる。
【００３５】
こうしてダイシングされた保護膜付き半導体チップ１は、図１に示される形状となり、領域７において、第２半導体チップ１２の裏面３１が保護膜１３上に、加熱状態で、加圧されて接着される。その後、ボンディングワイヤ１６，１８による配線が行われる。さらに封止のために合成樹脂２１によって全体が被覆され、集積回路素子などの半導体装置が完成する。
【００３６】
図１０は、本発明の実施の他の形態の断面図である。前述の図１〜図９の実施の形態では、半導体ウエハ２２の回路面４に、スピンコートの手法で保護膜３が形成されたけれども、図１０に示される実施の形態では、半導体ウエハ２２の回路面４に、フィルム状保護膜３２が接着される。フィルム状保護膜３２は、セパレータ３３の一表面に予め付着形成されて保護膜シート３４として準備される。このセパレータ３３を介して保護膜３２が半導体ウエハ２２の回路面４上に、ロール３５によって加圧されながら、ロール３５を回転して移動方向３６に移動する。ロール３５の軸線は、図１０の紙面に垂直である。ロール３５を、半導体ウエハ２２の図１０における右方の端部から左方の端部に移動方向３６に沿って移動しながら接着することによって、半導体ウエハ２２の回路面４と保護膜３２との間に空気の気泡が巻き込まれることはなく、ボイドの発生が防がれる。この加圧時、半導体ウエハ２２を支持する支持部材３７およびロール３５の少なくとも一方は、加熱され、したがって半導体ウエハ２２の回路面４と保護膜３２との接着強度が充分に得られる。
【００３７】
セパレータ３３が設けられることによって、保護膜３２がロール３５の表面に接触することはなく、したがって半導体ウエハ２２と保護膜３２との接着強度が充分に得られるための加熱温度および加圧力を選ぶことができる。
【００３８】
こうして図１０に示される半導体ウエハ２２の回路面４の全面に保護膜３２を接着した後、半導体ウエハ２２側（図１０の下方）からカッタで、半導体ウエハ２２の外周部に沿って保護膜シート３４を切断する。その後、セパレータ３３を剥離することによって、保護膜３２が回路面４に接着された半導体ウエハ２２が得られる。その後の製造工程は、前述の実施の形態における図５以降と同様である。
【００３９】
図１１は、本発明の実施の他の形態の半導体装置８ａの断面図である。この実施の形態は、前述の実施の形態に類似し、対応する部分には同一の参照符を付し、または同一の数字に添え字ａを付して示す。注目すべきはこの実施の形態では、第１半導体チップ２の平面形状の寸法と第２半導体チップ１２ａの平面形状とが、ほぼ等しく、したがって第１半導体チップ２と端子１７とのボンディングワイヤ１６による接続を可能とするために、第１半導体チップ２よりも平面形状が小さいスペーサ３９が介在される。
【００４０】
このスペーサ３９は、たとえば合成樹脂またはシリコンなどの無機物質から成ってもよい。スペーサ３９は、前述の図１に示される保護膜付き半導体チップ１の領域７に、前述と同様にして接着される。このスペーサ３９の上面には、接着剤４１を介して、第２保護膜付き半導体チップ１１ａの第２半導体チップ１２ａの裏面３１ａが接着される。接着剤３１ａは、保護膜３と同様な材料から成ってもよいが、異なる材料から成ってもよい。シリコーン樹脂から成るスペーサ３９上の接着剤４１を、回路面上の保護膜３，１３ａとして、同様に形成してもよい。
【００４１】
本件発明者の実験結果を述べる。
【実施例】
（実施例１）
次の化学式１，２の構造の酸無水物、化学式３（Ｒ１およびＲ２が　−Ｃ３Ｈ６−　、Ｒ３〜Ｒ６が　−ＣＨ３、ｍ＝１０）、化学式４の構造のジアミンを表１の配合で溶剤に溶解し、キシレンを還流し水を系外に排出させながら１６０〜１７０℃で８時間イミド化し、溶剤可溶イミド樹脂（Ａ）を得た。
【００４２】
【化１】

Figure 2004022996
【００４３】
【化２】
Figure 2004022996
【００４４】
【化３】
Figure 2004022996
【００４５】
（式中、Ｒ１，Ｒ２は二価の炭素数１〜４の脂肪族基または芳香族基を、Ｒ３〜Ｒ６は一価の脂肪族基または芳香族基を、ｍは１〜２０の整数を表わす。）
【００４６】
【化４】
Figure 2004022996
【００４７】
【表１】
Figure 2004022996
【００４８】
溶剤可溶ポリイミド樹脂（Ａ）１００部に、エポキシ樹脂（ＨＰ７２００Ｈ：大日本インキ化学製、ジシクロペンタジエン型エポキシ樹脂（エポキシ当量２８０））２０部、硬化剤（２Ｅ４ＭＺ：四国化成製、イミダゾール硬化剤）１部を配合しＮＭＰに溶解したワニス（Ｂ）を作成した。
【００４９】
８インチウエハ２２にワニス（Ｂ）をスピンコートし、９０℃２０分で乾燥し、膜厚５μｍのウエハ保護膜兼接着膜３を図５のように形成した。
【００５０】
さらにフォトレジスト膜２４をスピンコートで形成し、パッドパターンを図６のように露光、現像し、ドライエッチングによりパッドを露出するための接続孔６を図７のように開口させ、フォトレジスト膜２４を図８のように除去した。
【００５１】
（実施例２）
ワニス（Ｂ）を離型処理したＰＥＮ（ポリエチレンナフタレート）フィルム３３上にコートし、９０℃２０分で乾燥し、膜厚５μｍのポリイミド系フィルム３２をＰＥＮフィルム３３上に形成した。
【００５２】
このポリイミド系フィルム３２をＰＥＮフィルム３３ごと８インチウエハ表面に１１０℃でロールラミネートし、ウエハ外周でフィルムシートを切断し、ＰＥＮフィルム３３をはがし、ウエハ２２にポリイミド系フィルム３２を接着した。接着を完全なものにするため、１８０℃で１分間加熱保持した。
【００５３】
さらに図５〜図８のようにフォトレジスト膜をスピンコートで形成し、パッドパターンを露光、現像し、ドライエッチングによりパッドを開口させ、フォトレジストを除去した。
実施例１，２では、いずれもパッドパターンが良好に形成された。
【００５４】
（実施例３）
前述と同様にワニス（Ｂ）を８インチウエハにスピンコートし、９０℃２０分で乾燥し、膜厚５μｍのウエハ保護膜兼接着膜を形成した。これの表面にＢＧテープ（裏面研削時の表面保護テープ　Ｂａｃｋ　Ｇｒｉｎｄｉｎｇ）を貼り付け、１００μｍ厚まで薄削りした。
【００５５】
（実施例４）
前述と同様にワニス（Ｂ）を離型処理したＰＥＮフィルム上にコートし、９０℃２０分で乾燥し、膜厚５μｍのポリイミド系フィルムをＰＥＮフィルム上に形成した。
【００５６】
このポリイミド系フィルムをＰＥＮフィルムごと８インチウエハ表面に１１０℃でロールラミネートし、ウエハ外周でフィルムを切断し、ＰＥＮフィルムをはがし、ウエハにポリイミド系フィルムを接着した。接着を完全なものにするため、１８０℃で１分間加熱保持した。
【００５７】
これの表面にＢＧテープを貼り付け、１００μｍ厚まで薄削りした。
実施例３，４では、いずれもウエハ反り量が５ｍｍ以下で、ウエハカートリッジ収納に問題はなかった。
【００５８】
（実施例５）
前述と同様にワニス（Ｂ）を８インチウエハにスピンコートし、９０℃２０分で乾燥し、膜厚５μｍのウエハ保護膜兼接着膜を形成した。
【００５９】
この上に５ｍｍ角のシリコンチップを１８０℃１秒で加熱圧着後、１８０℃、３時間加熱硬化した。
【００６０】
この５ｍｍ角チップのせん断接着強度を２６０℃にて測定したところ、０．５ｋｇｆ以上あり、良好な熱時接着強度を示した。
【００６１】
（実施例６）
前述と同様にワニス（Ｂ）を離型処理したＰＥＮフィルム上にコートし、９０℃２０分で乾燥し、膜厚５μｍのポリイミド系フィルムをＰＥＮフィルム上に形成した。
【００６２】
このポリイミド系フィルムをＰＥＮフィルムごと８インチウエハ表面に１１０℃でロールラミネートし、ウエハ外周でフィルムをカットし、ＰＥＮフィルムをはがし、ウエハにポリイミド系フィルムを接着した。接着を完全なものにするため、１８０℃で１分間加熱保持した。
【００６３】
この上に５ｍｍ角のシリコンチップを１８０℃１ｓで加熱圧着後、１８０℃、３時間加熱した。
【００６４】
この５ｍｍ角チップのせん断接着強度を２６０℃にて測定したところ、０．５ｋｇｆ以上あり、良好な熱時接着強度を示した。
実施例２〜６の他の工程は、前述の実施例１と同様である。
【００６５】
以上の実施例１〜６で、本発明によれば、電気信号接続部が良好に開口でき、ウエハ反りの問題もなく、耐熱性も良好なチップ積層体を形成することができることが確認された。
【００６６】
本発明の実施の他の形態では、前述の化学式４の構造のジアミンに代えて、化学式５の構造を有するジアミンとテトラカルボン酸２無水物とを反応させて得られるガラス転移温度Ｔｇが１５０℃以下の溶剤可溶ポリイミドを、シリコーン変成ポリイミドとして用いることもできる。
【００６７】
【化５】
Figure 2004022996
【００６８】
保護膜は熱可塑性樹脂と熱硬化性樹脂とから成ってもよいが、さらに充填剤などを含んでもよい。
【００６９】
【発明の効果】
本発明によれば、第１半導体チップのバッファコート膜である保護膜が、第２半導体チップまたはスペーサとの接着のためのダイボンド接着剤機能を達成するようにしたので、別途、接着剤を用いる必要がなく、これによって第１および第２半導体チップの積層のための工程が簡略化され、生産性が向上される。さらにこの保護膜は、１５０℃以下の低いガラス転移温度Ｔｇを有し、接着強度を向上することができるとともに、前述のように接着剤を別途、準備する必要はないので、薄く構成することができ、小形化が可能である。さらにガラス転移温度Ｔｇが前述のように低い保護膜を用いることによって、半導体ウエハの反りが生じることを抑制し、半導体ウエハの真空吸着などによる搬送が容易となり、半導体ウエハが障害物などに衝突して破損するおそれをなくすことができる。こうして本発明では、第１および第２半導体チップを薄くすることができ、半導体装置の小形化が可能になる。
【図面の簡単な説明】
【図１】本発明の実施の一形態の保護膜付き半導体チップ１の斜視図である。
【図２】図１に示される保護膜付き半導体チップ１を含む半導体装置８の断面図である
。
【図３】第１半導体チップ２の断面図である。
【図４】図３に示される半導体ウエハ２の回路面４に保護膜３が形成された状態を示す
断面図である。
【図５】図４に示される保護膜３上にフォトレジスト膜２４を形成した状態を示す断面
図である。
【図６】図５に示されるフォトレジスト膜２４を露光する工程を示す断面図である。
【図７】図６に示される露光の後、現像を行った保護膜３とフォトレジスト膜２４とを示す断面図である。
【図８】図７に示される現像後のフォトレジスト膜２４を除去してエッチングを完了し
た状態を示す半導体ウエハ２２と保護膜３とを示す断面図である。
【図９】図８に示される保護膜３が形成された半導体ウエハ２２をダイシングする状態を示す断面図である。
【図１０】本発明の実施の他の形態の断面図である。
【図１１】本発明の実施の他の形態の半導体装置８ａの断面図である。
【符号の説明】
１　保護膜付き半導体チップ
２　第１半導体チップ
３　保護膜
４　回路面
５　裏面
６　接続孔
７　領域
８　半導体装置
１１　保護膜付き半導体チップ
１２　第２半導体チップ
１３　保護膜
１４　接着剤
２２　半導体ウエハ
２４　フォトレジスト膜
３２　フィルム状保護膜
３３　セパレータ
３４　保護膜シート
３５　ロール
３９　スペーサ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for stacking semiconductor chips in a semiconductor device such as a semiconductor integrated circuit, and also relates to a semiconductor device having a configuration in which the semiconductor chips are stacked.
[0002]
[Prior art]
In the prior art, a protective film made of polyimide is formed on a circuit surface of a semiconductor chip on which an electric circuit is formed, and this protective film shields α-rays, which function as a buffer coat film, and forms a synthetic resin for sealing. Of stress caused by a temperature change between the semiconductor chip and the semiconductor chip. After opening the electrical signal connection portion and the dicing portion, the semiconductor wafer is diced together with the protective film to obtain a semiconductor chip with a protective film. In order to stack and fix another semiconductor chip on this semiconductor chip, conventionally, the back surface of the other semiconductor is bonded to the protective film with a paste or film-like adhesive interposed therebetween. I do.
[0003]
In this prior art, the another semiconductor chip is bonded on the protective film using an adhesive, so that there is a problem that a process for laminating the semiconductor chips is complicated and productivity is poor.
[0004]
In recent years, there has been a tendency to make semiconductor chips thinner in order to reduce the thickness of the package. When the thickness of the semiconductor chip and thus the thickness of the semiconductor wafer becomes 150 μm or less, in a configuration in which a protective film made of polyimide is formed on the circuit surface, the stress caused by a change in temperature between the circuit surface of the semiconductor wafer and the protective film is reduced As a result, the semiconductor wafer is warped and curvedly deformed. This causes a new problem that it becomes difficult to transport the semiconductor wafer by vacuum suction or the like.
[0005]
Further, in a configuration in which the thickness of the semiconductor chip, that is, the semiconductor wafer is reduced to, for example, about 50 μm, the thickness of the protective film and the adhesive at the time of lamination becomes too large compared to the thickness of the semiconductor chip. Accordingly, there is an increasing demand for a thin configuration for bonding between a plurality of semiconductor chips to be stacked.
[0006]
[Problems to be solved by the invention]
An object of the present invention is to simplify a configuration for bonding a plurality of semiconductor chips to be stacked, improve productivity, improve bonding strength, and reduce the thickness of a semiconductor chip. An object of the present invention is to provide a semiconductor device including the stacked semiconductor chips.
[0007]
[Means for Solving the Problems]
The present invention relates to a circuit surface of a first semiconductor chip on which an electric circuit is formed,
Through a protective film having a glass transition temperature of 150 ° C. or lower,
A method of laminating semiconductor chips, comprising bonding a back surface of a second semiconductor chip.
[0008]
Further, the present invention has a circuit surface on which an electric circuit is formed, and a back surface opposite to the thickness direction of the circuit surface, and the circuit surface has a first semiconductor chip on which an electric signal connection portion is formed;
A protective film having a glass transition temperature of 150 ° C. or lower, formed on a circuit surface, and formed with a connection hole exposing an electric signal connection portion on the circuit surface;
A second semiconductor chip having a back surface adhered to a region of the protective film where the connection hole is not formed.
[0009]
According to the present invention, the glass transition temperature Tg is set between the circuit surface 4 of the first semiconductor chip 2 and the back surface 31 of the second semiconductor chip 12, as described later with reference to FIGS. A protective film 3 at a temperature of 150 ° C. or lower is interposed, and the first and second semiconductor chips are bonded and fixed by the protective film. The protective film functions to block the α-ray by irradiating the circuit surface of the first semiconductor chip with the α-ray, and to prevent the temperature change between the synthetic resin 21 for sealing and the first semiconductor chip. It acts to alleviate the resulting stress.
[0010]
The protective film has a glass transition temperature Tg of 150 ° C. or lower, preferably 100 ° C. or lower, which is as close to room temperature as possible. When the glass transition temperature Tg is low as described above, the first and second semiconductor chips can be bonded at a lower temperature and a lower pressure in a short time. Since the bonding can be performed at a low temperature, the first and second semiconductor chips and other materials do not cause damage even if they have low heat resistance and can be bonded at a low pressure during bonding. This prevents the first and second semiconductor chips from being damaged. In this manner, excellent characteristics for chip bonding can be obtained. The protective film having a relatively low glass transition temperature Tg includes, for example, a resin composition composed of (A) a thermoplastic resin and (B) a thermosetting resin. Such a resin composition is excellent in short-time low-temperature adhesion, stress relaxation, and heat resistance.
[0011]
The first and second semiconductor chips are, for example, 150 μm or less, and may be, for example, 50 μm, for example. Even with such relatively thin first and second semiconductor chips, the first and second semiconductor chips can be formed by using a protective film having a glass transition temperature Tg of 150 ° C. or lower, preferably 100 ° C. or lower as described above. The semiconductor chip and the semiconductor wafer for obtaining the first and second semiconductor chips can suppress the phenomenon of warpage. As a result, the semiconductor wafer can be reliably transferred by vacuum suction or the like. Furthermore, the protective film having such a low glass transition temperature Tg can be formed on the circuit surface of the first semiconductor chip by, for example, a technique of spin coating using a solvent, and in the process, the solvent drying property is excellent, and Productivity is improved.
[0012]
In the present invention, the protective film functions to protect the circuit surface of the first semiconductor chip and also functions to adhere to the second semiconductor chip. Therefore, the above-mentioned adhesive in the prior art is separately required. I do not. This also improves the productivity and reduces the overall thickness.
[0013]
Further, according to the present invention, on the circuit surface of the first semiconductor chip on which the electric circuit is formed,
One surface of the spacer is adhered through a protective film having a glass transition temperature of 150 ° C. or lower,
A method of laminating semiconductor chips, comprising bonding the back surface of the second semiconductor chip to the other surface of the spacer via an adhesive.
[0014]
Further, the present invention has a circuit surface on which an electric circuit is formed, and a back surface opposite to the thickness direction of the circuit surface, and the circuit surface has a first semiconductor chip on which an electric signal connection portion is formed;
A protective film having a glass transition temperature of 150 ° C. or lower, formed on a circuit surface, and formed with a connection hole exposing an electric signal connection portion on the circuit surface;
A spacer having one surface adhered to a region where the connection hole of the protective film is not formed,
A semiconductor device comprising: a second semiconductor chip having a back surface bonded to another surface of the spacer via an adhesive.
[0015]
According to the present invention, as will be described later with reference to FIG. 11, by using the spacer 39 (for example, silicon as a material), the dimensions of the planar shapes of the first and second semiconductor chips are substantially the same, for example. However, by using a spacer having a planar shape smaller than the planar shape of the first and second semiconductor chips, the first and second semiconductor chips can be stacked. A spacer 39 is interposed between the first and second semiconductor chips. The protective film 3 functions to bond the first semiconductor chip to the spacer 39. Therefore, as described above, productivity can be improved, excellent adhesive strength can be obtained, a thin structure can be achieved, and warpage of the semiconductor wafer can be prevented.
[0016]
Further, according to the present invention, the protective film is formed on a circuit surface of a semiconductor wafer to be diced into a plurality of first semiconductor chips,
A connection hole for an electric signal connection portion and a long hole for dicing on the circuit surface of each first semiconductor chip are formed in the protection film.
Thereafter, the semiconductor wafer is diced together with the protective film into a plurality of first semiconductor chips.
[0017]
Further, the present invention is characterized in that the thickness of the first semiconductor chip is 150 μm or less.
[0018]
According to the present invention, in order to obtain the first semiconductor chip 2, the protective film 3 is formed on the circuit surface of the semiconductor wafer 22, and the first semiconductor chip 2 is provided with the first semiconductor chip 2. A connection hole 6 for exposing an electric signal connection portion on a circuit surface of the chip and a long hole for dicing are formed, and then the individual first semiconductor chips are diced. Thus, the first semiconductor chip 2 with the protective film is obtained.
[0019]
Since the die attach film is not diced as compared with the method of attaching the die attach film to the back surface and dicing, the dicing property is excellent. Also, during pick-up, the peeling property between the dicing tape and the die attach film is not a problem, so that it is excellent.
[0020]
As described above, the thickness of such a first semiconductor chip may be 150 μm or less, for example, may be 50 μm, or may be a thinner value of 50 μm or less.
[0021]
In the present invention, the protective film may be made of a thermoplastic synthetic resin and a thermosetting synthetic resin, but may further contain other additives, fillers, and other substances.
[0022]
Further, the invention is characterized in that the protective film is made of a silicone-based material.
According to the present invention, the protective film is required to have a low content of impurity ions and to prevent warpage of the semiconductor wafer for the first semiconductor chip. It is important to select the curing shrinkage, glass transition temperature Tg, linear expansion coefficient, and the like of the synthetic resin constituting the resin, and the glass transition temperature Tg is selected to be 150 ° C. or lower, preferably 100 ° C. or lower as described above, By approaching, the problem of the warpage of the semiconductor wafer can be improved. The protective film is made of a thermoplastic synthetic resin layer, and the heat resistance is imparted by a cross-linked structure, whereby a protective film that achieves preferable chip bonding characteristics is obtained. Such a protective film is preferably a synthetic resin that passes various reliability tests, and a thermoplastic synthetic resin and a thermosetting synthetic resin have characteristics that pass such various reliability tests.
[0023]
The protective film is also made of a silicone-based material, for example, an organic silicon-based synthetic resin or a silicone resin. Since the silicone-based adhesive has a high adhesive strength to a Si-based material, the first and second semiconductor chips on the surface of the silicone-based adhesive use a protective film made of a silicone-based material, and further use a spacer. In the configuration, the spacer is also made of a silicon-based material, so that the bonding can be performed with high bonding reliability.
[0024]
Further, the present invention is not limited to the two-stage stack structure, and a three- or more-stage stack structure in which three or more semiconductor chips are interposed via a protective film and a spacer as described above may be realized.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a perspective view of a semiconductor chip 1 with a protective film according to one embodiment of the present invention. The semiconductor chip 1 with a protective film includes a first semiconductor chip 2 and a protective film 3. In the first semiconductor chip 2, an electric circuit is formed on the circuit surface 4 of the semiconductor substrate, and the back surface 5 is provided on the side opposite to the circuit surface 4 in the thickness direction. The protective film 3 is formed on the circuit surface 4. In the protective film 3, one or a plurality of connection holes 6 exposing an electric signal connection portion formed on the circuit surface 4 of the first semiconductor chip 2 are formed. The connection hole 6 is formed outside the region 7, and therefore, the connection hole 6 is not formed in the region 7.
[0026]
FIG. 2 is a sectional view of a semiconductor device 8 including the semiconductor chip 1 with a protective film shown in FIG. Another semiconductor chip 11 with a protective film is bonded and fixed to the region 7 of the protective film 3 and laminated. The semiconductor chip 11 with a protective film includes a second semiconductor chip 12 and a protective film 13 formed on a circuit surface of the second semiconductor chip 2. The dimension of the planar shape of the first semiconductor chip 2 is larger than the planar shape of the second semiconductor chip 12. The protective film 13 formed on the second semiconductor chip 12 may be made of the same material as the protective film 3 of the first semiconductor chip 2 described above, or may be made of another material having no adhesive function. .
[0027]
The back surface 5 of the first semiconductor chip 2 is adhered and fixed to a substrate 15 made of an electrically insulating material via an adhesive 14. The substrate 15 may be made of, for example, a synthetic resin, or may be made of ceramic or the like. One end of the bonding wire 16 that passes through the connection hole 6 formed in the protective film 3 is connected to an electric signal connection portion of the circuit surface 4 exposed to the connection hole 6. The other end of the wire 16 is connected to a terminal 17 provided on the substrate 15. Similarly, the second semiconductor chip 12 is connected to the terminal 19 via the bonding wire 18. The substrate 15 is sealed with a synthetic resin 21 that covers the semiconductor chips 1 and 11 with protective films and the bonding wires 16 and 18.
[0028]
FIG. 3 is a sectional view of the first semiconductor wafer 22. A method for manufacturing the semiconductor device 8 will be described with reference to FIGS. First, as shown in FIG. 3, the thickness d1 of the semiconductor wafer 22 is 150 μm or less, for example, may be 50 μm, and is formed thin. The semiconductor wafer 22 has a substantially disk shape, and a plurality of first semiconductor chips 2 are obtained by dicing.
[0029]
FIG. 4 is a cross-sectional view showing a state where the protective film 3 is formed on the circuit surface 4 of the semiconductor wafer 2 shown in FIG. The protective film 3 is formed by, for example, spin coating or film lamination. The thickness d2 of the protective film 3 may be, for example, 5 μm.
[0030]
FIG. 5 is a cross-sectional view showing a step of forming a connection hole 6 and a long dicing hole in the protective film 3 by the photolithography method shown in FIGS. The photoresist film 24 is formed, for example, by applying a varnish containing the material of the photoresist film 24 dissolved in a solvent by a spin coating technique.
[0031]
FIG. 6 is a sectional view showing a step of exposing the photoresist film 24 shown in FIG. A photomask 25 is disposed on the photoresist film 24, and the photoresist film 24 is selectively exposed by irradiating light 26 such as ultraviolet rays.
[0032]
FIG. 7 shows a state where, after the exposure shown in FIG. 6, a predetermined designated place such as the developed photoresist film 24 and the connection hole 6 and the dicing long hole of the protective film 3 are etched by dry or wet etching. FIG.
[0033]
FIG. 8 is a sectional view showing a semiconductor wafer 27 with a protective film having the semiconductor wafer 22 and the protective film 3 in a state where the photoresist film 24 after development shown in FIG. Connection holes 6 are formed in the protective film 3 so as to correspond to electric signal connection portions for the plurality of first semiconductor chips 2 on the circuit surface 4 of the semiconductor wafer 22.
[0034]
FIG. 9 is a cross-sectional view showing a state in which the semiconductor wafer 22 on which the protective film 3 shown in FIG. 8 is formed is diced. A dicing tape 28 is adhered to the back surface of the semiconductor wafer 22 and fixed to a base 29. The semiconductor wafer 22 on which the protective film 3 is formed is cut by a rotary blade such as a dicing blade, and the dicing tape 28 is partially cut in the thickness direction to obtain the individual semiconductor chip 1 with a protective film. Since the protective film 3 is also removed from the portion to be diced in the etching step to form a long hole for dicing, the semiconductor wafer 22 can be satisfactorily diced into the semiconductor chip with a blade such as a dicing blade.
[0035]
The semiconductor chip 1 with the protective film thus diced has the shape shown in FIG. 1, and in the region 7, the back surface 31 of the second semiconductor chip 12 is adhered to the protective film 13 by applying pressure in a heated state. . After that, wiring is performed by the bonding wires 16 and 18. Further, the whole is covered with a synthetic resin 21 for sealing, and a semiconductor device such as an integrated circuit element is completed.
[0036]
FIG. 10 is a sectional view of another embodiment of the present invention. In the embodiments of FIGS. 1 to 9 described above, the protective film 3 is formed on the circuit surface 4 of the semiconductor wafer 22 by a spin coating method, but in the embodiment shown in FIG. The film-like protective film 32 is adhered to the circuit surface 4. The film-like protective film 32 is previously formed on one surface of the separator 33 and is prepared as a protective film sheet 34. While the protective film 32 is pressed by the roll 35 on the circuit surface 4 of the semiconductor wafer 22 via the separator 33, the roll 35 rotates and moves in the moving direction 36. The axis of the roll 35 is perpendicular to the paper surface of FIG. The roll 35 is adhered to the semiconductor wafer 22 from the right end to the left end in FIG. 10 while moving along the moving direction 36, so that the circuit surface 4 of the semiconductor wafer 22 and the protective film 32 are bonded. No air bubbles are trapped between them, and the generation of voids is prevented. At the time of this pressurization, at least one of the support member 37 and the roll 35 supporting the semiconductor wafer 22 is heated, and thus the bonding strength between the circuit surface 4 of the semiconductor wafer 22 and the protective film 32 is sufficiently obtained.
[0037]
By providing the separator 33, the protective film 32 does not come into contact with the surface of the roll 35. Therefore, it is necessary to select a heating temperature and a pressure for sufficiently obtaining the adhesive strength between the semiconductor wafer 22 and the protective film 32. Can be.
[0038]
After the protective film 32 is bonded to the entire surface of the circuit surface 4 of the semiconductor wafer 22 shown in FIG. 10 in this manner, the protective film sheet is formed along the outer peripheral portion of the semiconductor wafer 22 with a cutter from the semiconductor wafer 22 side (the lower part in FIG. 10). 34 is cut. Then, the semiconductor wafer 22 with the protective film 32 adhered to the circuit surface 4 is obtained by removing the separator 33. Subsequent manufacturing steps are the same as those in the above-described embodiment shown in FIG.
[0039]
FIG. 11 is a cross-sectional view of a semiconductor device 8a according to another embodiment of the present invention. This embodiment is similar to the above-described embodiment, and the corresponding portions are denoted by the same reference numerals or the same numerals with the suffix a. It should be noted that in this embodiment, the dimensions of the planar shape of the first semiconductor chip 2 and the planar shape of the second semiconductor chip 12a are substantially equal, and thus the bonding wires 16 between the first semiconductor chip 2 and the terminals 17 are used. In order to enable connection, a spacer 39 having a smaller planar shape than the first semiconductor chip 2 is interposed.
[0040]
The spacer 39 may be made of, for example, an inorganic substance such as a synthetic resin or silicon. The spacer 39 is bonded to the region 7 of the semiconductor chip 1 with a protective film shown in FIG. 1 in the same manner as described above. The back surface 31a of the second semiconductor chip 12a of the second semiconductor chip 11a with a protective film is adhered to the upper surface of the spacer 39 via an adhesive 41. The adhesive 31a may be made of the same material as the protective film 3, or may be made of a different material. The adhesive 41 on the spacer 39 made of silicone resin may be similarly formed as the protective films 3 and 13a on the circuit surface.
[0041]
The experimental results of the present inventor will be described.
【Example】
(Example 1)
An acid anhydride having the structure of the following Chemical Formulas 1 and 2, a chemical formula 3 (R 1 and R 2 are —C 3 H 6 −, R 3 to R 6 are —CH 3 , m = 10), and a diamine having a structure of Chemical Formula 4 Was dissolved in a solvent with the formulation shown in Table 1, and xylene was refluxed and imidized at 160 to 170 ° C. for 8 hours while discharging water out of the system to obtain a solvent-soluble imide resin (A).
[0042]
Embedded image
Figure 2004022996
[0043]
Embedded image
Figure 2004022996
[0044]
Embedded image
Figure 2004022996
[0045]
(Wherein, R 1 and R 2 are divalent aliphatic groups or aromatic groups having 1 to 4 carbon atoms, R 3 to R 6 are monovalent aliphatic groups or aromatic groups, and m is 1 to 4) Represents an integer of 20.)
[0046]
Embedded image
Figure 2004022996
[0047]
[Table 1]
Figure 2004022996
[0048]
To 100 parts of the solvent-soluble polyimide resin (A), 20 parts of an epoxy resin (HP7200H: dicyclopentadiene type epoxy resin (epoxy equivalent: 280) manufactured by Dainippon Ink and Chemicals, Inc.), and a curing agent (2E4MZ: Shikoku Chemicals, imidazole curing agent) 1) A varnish (B) was prepared in which 1 part was blended and dissolved in NMP.
[0049]
A varnish (B) was spin-coated on the 8-inch wafer 22 and dried at 90 ° C. for 20 minutes to form a 5 μm-thick wafer protective film / adhesive film 3 as shown in FIG.
[0050]
Further, a photoresist film 24 is formed by spin coating, the pad pattern is exposed and developed as shown in FIG. 6, and a connection hole 6 for exposing the pad by dry etching is opened as shown in FIG. Was removed as shown in FIG.
[0051]
(Example 2)
The varnish (B) was coated on a release-treated PEN (polyethylene naphthalate) film 33 and dried at 90 ° C. for 20 minutes to form a 5 μm-thick polyimide film 32 on the PEN film 33.
[0052]
The polyimide film 32 was roll-laminated together with the PEN film 33 on an 8-inch wafer surface at 110 ° C., the film sheet was cut around the wafer, the PEN film 33 was peeled off, and the polyimide film 32 was bonded to the wafer 22. In order to complete the adhesion, it was heated and held at 180 ° C. for 1 minute.
[0053]
Further, as shown in FIGS. 5 to 8, a photoresist film was formed by spin coating, the pad pattern was exposed and developed, the pad was opened by dry etching, and the photoresist was removed.
In Examples 1 and 2, the pad pattern was formed favorably in each case.
[0054]
(Example 3)
In the same manner as described above, the varnish (B) was spin-coated on an 8-inch wafer and dried at 90 ° C. for 20 minutes to form a 5-μm-thick wafer protective film / adhesive film. A BG tape (a surface protection tape Back Grinding at the time of back surface grinding) was adhered to the surface of this, and thinly cut to a thickness of 100 μm.
[0055]
(Example 4)
The varnish (B) was coated on the release-treated PEN film in the same manner as described above, and dried at 90 ° C. for 20 minutes to form a 5 μm-thick polyimide film on the PEN film.
[0056]
This polyimide film together with the PEN film was roll-laminated on an 8-inch wafer surface at 110 ° C., the film was cut around the wafer periphery, the PEN film was peeled off, and the polyimide film was bonded to the wafer. In order to complete the adhesion, it was heated and held at 180 ° C. for 1 minute.
[0057]
A BG tape was stuck on the surface of this, and thinned to a thickness of 100 μm.
In Examples 3 and 4, the amount of wafer warpage was 5 mm or less, and there was no problem in storing the wafer cartridge.
[0058]
(Example 5)
In the same manner as described above, the varnish (B) was spin-coated on an 8-inch wafer and dried at 90 ° C. for 20 minutes to form a 5-μm-thick wafer protective film / adhesive film.
[0059]
A 5 mm square silicon chip was heat-pressed at 180 ° C. for 1 second, and then heat-cured at 180 ° C. for 3 hours.
[0060]
When the shear bond strength of the 5 mm square chip was measured at 260 ° C., it was 0.5 kgf or more, indicating good hot bond strength.
[0061]
(Example 6)
The varnish (B) was coated on the release-treated PEN film in the same manner as described above, and dried at 90 ° C. for 20 minutes to form a 5 μm-thick polyimide film on the PEN film.
[0062]
This polyimide film was roll-laminated together with the PEN film on an 8-inch wafer surface at 110 ° C., the film was cut around the wafer periphery, the PEN film was peeled off, and the polyimide film was bonded to the wafer. In order to complete the adhesion, it was heated and held at 180 ° C. for 1 minute.
[0063]
A 5 mm square silicon chip was heated and pressed at 180 ° C. for 1 s, and then heated at 180 ° C. for 3 hours.
[0064]
When the shear bond strength of the 5 mm square chip was measured at 260 ° C., it was 0.5 kgf or more, indicating good hot bond strength.
Other steps of the second to sixth embodiments are the same as those of the first embodiment.
[0065]
In the above Examples 1 to 6, according to the present invention, it was confirmed that the electrical signal connection portion could be opened favorably, and there was no problem of wafer warpage, and a chip laminate having good heat resistance could be formed. .
[0066]
In another embodiment of the present invention, a glass transition temperature Tg obtained by reacting a diamine having the structure of Chemical Formula 5 with tetracarboxylic dianhydride instead of the diamine having the structure of Chemical Formula 4 is 150 ° C. The following solvent-soluble polyimides can also be used as the silicone-modified polyimide.
[0067]
Embedded image
Figure 2004022996
[0068]
The protective film may be made of a thermoplastic resin and a thermosetting resin, but may further contain a filler or the like.
[0069]
【The invention's effect】
According to the present invention, since the protective film, which is the buffer coat film of the first semiconductor chip, achieves a die-bonding adhesive function for bonding to the second semiconductor chip or the spacer, an adhesive is separately used. There is no need to do so, which simplifies the steps for laminating the first and second semiconductor chips and improves productivity. Furthermore, this protective film has a low glass transition temperature Tg of 150 ° C. or less, can improve the adhesive strength, and does not require a separate adhesive as described above. It can be downsized. Furthermore, by using a protective film having a low glass transition temperature Tg as described above, warpage of the semiconductor wafer is suppressed, the semiconductor wafer is easily transported by vacuum suction, etc., and the semiconductor wafer collides with an obstacle or the like. And the possibility of breakage can be eliminated. Thus, according to the present invention, the first and second semiconductor chips can be thinned, and the semiconductor device can be downsized.
[Brief description of the drawings]
FIG. 1 is a perspective view of a semiconductor chip with a protective film 1 according to an embodiment of the present invention.
FIG. 2 is a sectional view of a semiconductor device 8 including the semiconductor chip 1 with a protective film shown in FIG.
FIG. 3 is a cross-sectional view of the first semiconductor chip 2.
FIG. 4 is a cross-sectional view showing a state where a protective film 3 is formed on a circuit surface 4 of the semiconductor wafer 2 shown in FIG.
FIG. 5 is a cross-sectional view showing a state where a photoresist film 24 is formed on the protective film 3 shown in FIG.
FIG. 6 is a cross-sectional view showing a step of exposing the photoresist film 24 shown in FIG.
7 is a cross-sectional view showing a protective film 3 and a photoresist film 24 that have been developed after the exposure shown in FIG.
8 is a cross-sectional view showing the semiconductor wafer 22 and the protective film 3 in a state where the photoresist film 24 after development shown in FIG. 7 is removed and etching is completed.
FIG. 9 is a cross-sectional view showing a state in which the semiconductor wafer 22 on which the protective film 3 shown in FIG. 8 is formed is diced.
FIG. 10 is a sectional view of another embodiment of the present invention.
FIG. 11 is a sectional view of a semiconductor device 8a according to another embodiment of the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor chip with protective film 2 first semiconductor chip 3 protective film 4 circuit surface 5 back surface 6 connection hole 7 area 8 semiconductor device 11 semiconductor chip with protective film 12 second semiconductor chip 13 protective film 14 adhesive 22 semiconductor wafer 24 photoresist Film 32 film-like protective film 33 separator 34 protective film sheet 35 roll 39 spacer

Claims (13)

第１の半導体チップの電気回路が形成された回路面に、
ガラス転移温度が１５０℃以下である保護膜を介して、
第２の半導体チップの裏面を、接着することを特徴とする半導体チップの積層方法。On the circuit surface of the first semiconductor chip on which the electric circuit is formed,
Through a protective film having a glass transition temperature of 150 ° C. or lower,
A method for laminating semiconductor chips, comprising bonding a back surface of a second semiconductor chip. 第１の半導体チップの電気回路が形成された回路面に、
ガラス転移温度が１５０℃以下である保護膜を介して
スペーサの一表面を接着し、
このスペーサの他表面に、接着剤を介して、第２の半導体チップの裏面を、接着することを特徴とする半導体チップの積層方法。On the circuit surface of the first semiconductor chip on which the electric circuit is formed,
One surface of the spacer is adhered through a protective film having a glass transition temperature of 150 ° C. or lower,
A method of laminating semiconductor chips, comprising bonding the back surface of the second semiconductor chip to the other surface of the spacer via an adhesive. 複数の第１の半導体チップにダイシングされるべき半導体ウエハの回路面に、前記保護膜を形成し、
この保護膜に、各第１半導体チップの回路面の電気信号接続部用接続孔およびダイシング用長孔を、形成し、
その後、半導体ウエハを、前記保護膜とともに、複数の第１の半導体チップにダイシングすることを特徴とする請求項１または２記載の半導体チップの積層方法。Forming the protective film on a circuit surface of a semiconductor wafer to be diced into a plurality of first semiconductor chips;
A connection hole for an electric signal connection portion and a long hole for dicing on the circuit surface of each first semiconductor chip are formed in the protection film.
3. The method according to claim 1, further comprising dicing the semiconductor wafer into a plurality of first semiconductor chips together with the protective film. 第１半導体チップの厚みは、１５０μｍ以下であることを特徴とする請求項１〜３のうちの１つに記載の半導体チップの積層方法。4. The method according to claim 1, wherein a thickness of the first semiconductor chip is 150 [mu] m or less. 電気回路が形成された回路面と、その回路面の厚み方向反対側の裏面とを有し、回路面には、電気信号接続部が形成される第１の半導体チップと、
ガラス転移温度が１５０℃以下であり、回路面に形成され、回路面の電気信号接続部を露出する接続孔が形成される保護膜と、
保護膜の接続孔が形成されていない領域に接着される裏面を有する第２の半導体チップとを含むことを特徴とする半導体装置。A first semiconductor chip having a circuit surface on which an electric circuit is formed and a back surface opposite to the thickness direction of the circuit surface, wherein a first semiconductor chip on which an electric signal connection portion is formed;
A protective film having a glass transition temperature of 150 ° C. or lower, formed on a circuit surface, and formed with a connection hole exposing an electric signal connection portion on the circuit surface;
A second semiconductor chip having a back surface adhered to a region of the protective film where the connection hole is not formed. 電気回路が形成された回路面と、その回路面の厚み方向反対側の裏面とを有し、回路面には、電気信号接続部が形成される第１の半導体チップと、
ガラス転移温度が１５０℃以下であり、回路面に形成され、回路面の電気信号接続部を露出する接続孔が形成される保護膜と、
保護膜の接続孔が形成されていない領域に一表面が接着されるスペーサと、
スペーサの他表面に、接着剤を介して裏面が接着される第２の半導体チップとを含むことを特徴とする半導体装置。A first semiconductor chip having a circuit surface on which an electric circuit is formed and a back surface opposite to the thickness direction of the circuit surface, wherein a first semiconductor chip on which an electric signal connection portion is formed;
A protective film having a glass transition temperature of 150 ° C. or lower, formed on a circuit surface, and formed with a connection hole exposing an electric signal connection portion on the circuit surface;
A spacer having one surface adhered to a region where the connection hole of the protective film is not formed,
A semiconductor device comprising, on the other surface of the spacer, a second semiconductor chip whose back surface is bonded via an adhesive. 第１の半導体チップの厚みが、１５０μｍ以下であることを特徴とする請求項５または６記載の半導体装置。7. The semiconductor device according to claim 5, wherein the thickness of the first semiconductor chip is 150 μm or less. 保護膜が、熱可塑性樹脂と熱硬化性樹脂とを含むことを特徴とする請求項５〜７のうちの１つに記載の半導体装置。The semiconductor device according to claim 5, wherein the protection film includes a thermoplastic resin and a thermosetting resin. 前記熱可塑性樹脂が、シリコーン変成ポリイミドであることを特徴とする請求項８記載の半導体装置。9. The semiconductor device according to claim 8, wherein the thermoplastic resin is a silicone modified polyimide. 前記シリコーン変成ポリイミドが、式１で表されるジアミンを含むジアミンとテトラカルボン酸２無水物とを反応させて得られるガラス転移温度Ｔｇが１５０℃以下の溶剤可溶ポリイミドであることを特徴とする請求項９記載の半導体装置。
Figure 2004022996
式１中、Ｒ１，Ｒ２は二価の炭素数１〜４の脂肪族基または芳香族基を、Ｒ３〜Ｒ６は一価の脂肪族基または芳香族基を、ｍは１〜２０の整数を表わす。The silicone-modified polyimide is a solvent-soluble polyimide having a glass transition temperature Tg of 150 ° C. or lower obtained by reacting a diamine containing a diamine represented by Formula 1 with tetracarboxylic dianhydride. The semiconductor device according to claim 9.
Figure 2004022996
In Formula 1, R 1 and R 2 represent a divalent aliphatic group or aromatic group having 1 to 4 carbon atoms, R 3 to R 6 represent a monovalent aliphatic group or aromatic group, and m represents 1 to 4 Represents an integer of 20. シリコーン変成ポリイミドが、式２で表されるジアミンを含むジアミンとテトラカルボン酸２無水物とを反応させて得られるガラス転移温度Ｔｇが１５０℃以下の溶剤可溶ポリイミドであることを特徴とする請求項９または１０記載の半導体装置。
Figure 2004022996
The silicone-modified polyimide is a solvent-soluble polyimide having a glass transition temperature Tg of 150 ° C. or less obtained by reacting a diamine containing a diamine represented by Formula 2 with tetracarboxylic dianhydride. Item 11. The semiconductor device according to item 9 or 10.
Figure 2004022996
 前記シリコーン変成ポリイミドが、式３で表されるジアミンを含むジアミンとテトラカルボン酸２無水物とを反応させて得られるガラス転移温度Ｔｇが１５０℃以下の溶剤可溶ポリイミドであることを特徴とする請求項１１記載の半導体装置。
Figure 2004022996
The silicone-modified polyimide is a solvent-soluble polyimide having a glass transition temperature Tg of 150 ° C. or lower obtained by reacting a diamine containing a diamine represented by Formula 3 with tetracarboxylic dianhydride. The semiconductor device according to claim 11.
Figure 2004022996
 前記熱硬化性樹脂が、エポキシ樹脂であることを特徴とする請求項８〜１２のいずれかに記載の半導体装置。The semiconductor device according to claim 8, wherein the thermosetting resin is an epoxy resin.
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