JP2004021997A - Error correcting circuit for disk reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an error correcting circuit capable of preventing the occurrence of data omission caused by excessive time required for the re-reading of error detection data and stably controlling a DVD reproducing device. <P>SOLUTION: The circuit is provided with a track cross detecting means 51 which detects the fact that a head crosses a track on a recording disk 1 and outputs track cross detection data, a track cross detection data storing means 52 which stores the data, a track cross detection data reading means 53 which reads the data stored in the means 52, a reset means 54 which resets a sequencer 15 and a counter 14 and outputs the data, an externally reporting means 55 which outputs the data to the external and a control section 6 which rereads an error correcting block corresponding to the data from the disk 1. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an error correction circuit for reading data stored on a disk in a disk reproducing apparatus for reproducing a recording disk such as a DVD disk.
[0002]
[Prior art]
When reproducing data stored on a disc such as a CD-ROM or a DVD, random error data or burst error may occur due to noise signals from the apparatus and surroundings, or scratches on the disc when reproducing the data stored on the disc. Occurs during data playback. Therefore, in order to obtain correct data at the time of reproduction, the data stored on the disc includes, in addition to the error detection data added subsequent to the main data, a first error correction code serving as an inner code. , And a second error correction code as an outer code. Then, in the disc reproducing apparatus, an error correction process is performed using the added first error correction code, second error correction code, and error detection data.
[0003]
Here, a DVD disk will be described as an example of a reproduction disk. FIG. 10 is a diagram showing the relationship between the data structure of a DVD and error correction blocks. FIG. 10 shows that a unit block 40 is constituted by using 16 sectors 30 which is a basic data structure of a DVD disk.
[0004]
FIG. 10A is a diagram showing a configuration in which the sectors 30 read from the DVD disk are vertically arranged by 16 sectors (a to p).
The sector 30 is 182 bytes horizontally × 13 lines vertically, 2366 bytes. The header information 32 is added to the leftmost part of the top line of the main data 31 of 2048 bytes, and the error detection data EDC (Error Detection Code) 33 is added to the rightmost part of the bottom line of the main data 31 to be 172 bytes × 12 lines. (= 2064 bytes). On the right side of the main data 31, an inner code parity (PI) 34, which is error correction data (ECC: Error Correction Code), is added 10 bytes horizontally × 12 lines vertically (= 120 bytes). Further, below the main data 31 and the inner code parity 34, an outer code parity (PO) 35 which is error correction data (ECC: Error Correction Code) is 182 bytes horizontally × one line vertically (= 182 bytes). ) Is added. The calculation result of 182 bytes × 13 lines, which is the sum of the above 2064 bytes, 120 bytes, and 182 bytes, that is, 2366 bytes, is the number of bytes of the sector 30. As the number of bytes for 16 sectors of the unit block 40, 37856 bytes of the operation result of 182 bytes × 208 lines is the number of bytes of the unit block 40.
[0005]
FIG. 10B shows that each outer code parity PO (a to p) in each of the sectors a to p is added to the end of the unit block 40 in order to configure the unit block 40 for the 16 sectors in FIG. This shows the state in which they are put together. That is, all the outer code parities PO (a to p) of 16 sectors are collected in the last 16 lines of 208 lines for 16 sectors, and the main data (a to p) and the inner code parities PI (a to p) are correspondingly collected. ) At the top.
[0006]
FIG. 11 is a diagram illustrating a configuration of a unit block.
The unit block 40 in FIG. 11 is composed of 16 sectors as one block as shown in FIG. 10 (b), and is 182 bytes in width × 208 lines in length, which is a total of 37856 bytes (バ イ ト 37 kB: kilobyte). The error correction block 41 has 2048 bytes × 16 sectors = 31668 bytes (= 32 kB: kilobyte).
[0007]
The error correction data in FIG. 11 is configured by a product-sum code, and an inner code parity (PI) 44 for performing a first error correction process on the error correction block 41 in the row direction is an error correction block. An outer code parity (PO) 45 for performing a second error correction process in the column direction on the error correction block 41 and the inner code parity 44 is disposed on the right side of the error correction block 41 and the inner code parity 41. It is arranged below the parity 44.
[0008]
The error correction is performed by performing a first error correction process on the error correction block 41 using the inner code parity 44 and then performing a second error correction process on the error correction block 41 using the outer code parity 45. Complete the process.
[0009]
In addition, regarding whether or not there is an error in the main data 31 for each of the sectors a to p, after the correction of the entire 32 kB of the error correction block 41 is completed, data descrambling is performed for each sector. Further, the determination is made by detecting an error using the error detection data EDC.
[0010]
Alternatively, for example, as disclosed in Japanese Patent Application Laid-Open No. 9-180379, the interval between timing signals in sector units is compared with a reference interval to determine whether there is an error in the main data 31 for each sector. Judge.
[0011]
FIG. 12 is a block diagram showing a configuration of an error correction circuit of a conventional DVD reproducing apparatus.
In the DVD reproducing apparatus 100 shown in FIG. 12, reference numeral 1 denotes a DVD disk on which signals such as images and sounds are recorded. Reference numeral 2 denotes a head amplifier that extracts a signal recorded from the DVD 1 and converts the signal into a binary signal. An error correction circuit 3 demodulates the binarized signal, corrects errors in the signal, and outputs the corrected signal. Reference numeral 4 denotes a bus serving as a path for carrying signals such as data and commands. Reference numeral 5 denotes a storage unit that records and holds the data demodulated by the demodulation unit 1, the data after the error correction processing, and the data descrambled, subjected to the error detection, and output to the outside. When an error detection signal S0 is input from the error detection means 20, for example, for the error correction block in which an error is detected, the DVD disk 1 is reproduced and instructed to re-read, so that the servo controller 7 described later The controller is a controller that performs control and controls the entire operation of the DVD playback device 100. Reference numeral 7 denotes a servo controller for controlling disk rotation for detecting data from the DVD disk 100 and tracking control of the pickup.
[0012]
In the error correction circuit 3, reference numeral 11 denotes demodulation means for demodulating the binarized signal and generating timing for each sector data unit. Reference numeral 12 denotes a memory writing unit that writes the demodulated data into the recording unit. Reference numeral 13 denotes a timing generation unit that generates a timing in units of error correction blocks composed of 16 sectors from a timing signal in units of sectors obtained from the demodulation unit 11. Reference numeral 14 denotes an operation that is initialized by input of a timing signal in units of error correction blocks obtained from the timing generation unit 13 and updates the count by input of a signal indicating completion of processing in each correction mode from the error correction unit 16 described later. It is a counter to do. Reference numeral 15 denotes a sequencer for setting a processing operation in an error correction unit 16 described later according to the value of the counter 14. Reference numeral 16 accesses the storage unit 5 via a first memory read / write unit 17 described later, and switches between the first error correction process and the second error correction process in accordance with an instruction from the sequencer 15 and then issues an instruction. Error correction means for executing the error correction processing performed and outputting a signal indicating the completion of processing in each correction mode for counting by the counter 14. Reference numeral 17 denotes a first memory read / write unit that accesses the storage unit 5 according to the correction result of the error correction unit 16. Reference numeral 20 denotes an access to the data held in the storage means after the error correction processing is completed, descrambling processing for each sector, and then performing error detection using the error detection data EDC. Error detection means for outputting the detection signal S0. Reference numeral 21 denotes a second memory read / write unit that accesses the storage unit 5 according to the operation of the error detection unit 20. Reference numeral 22 denotes a data output unit that performs control to output data held in the storage unit 5 as an output signal in response to an external access. Reference numeral 23 denotes data reading means for reading data from the storage means 5 in accordance with an instruction from the data output means 22.
[0013]
FIG. 13 is a timing chart showing operation timings of the error correction circuit in the conventional DVD reproducing apparatus shown in FIG.
The first row (1) in FIG. 13 shows a signal read from the DVD disk 1 and includes data of a sector number M that cannot be corrected (cannot be corrected) by the error correction by the error correction means 16. . The (2) -th row in FIG. 13 indicates a sector unit timing signal output from the demodulation unit 11 by a pulse signal. For example, 16 sectors a to p are arranged in order. The (3) -th row in FIG. 13 shows a timing signal output from the timing generation unit 13 in units of error correction blocks by a pulse signal.
[0014]
The (4) -th row in FIG. 13 indicates the error correction period output from the sequencer 15 by L level. The (5) th row in FIG. 13 includes a first error correction mode for performing a first error correction process on the error correction block 41 in the row direction using the inner code parity 44, and an outer code parity 45. An error correction mode signal for switching between a second error correction mode in which a second error correction process is performed on the error correction block 41 in the column direction using the error correction block 41. The second error correction mode is indicated by an L level. ing. The (6) -th row in FIG. 13 is the output signal of the counter 14, which indicates that the timing is processing in the first error correction mode, and the output signal is processing in the second error correction mode. Are output alternately.
[0015]
The (7) -th row in FIG. 13 indicates a period in which the error detection processing is performed by the error detection unit 20 by the L level. The (8) -th row in FIG. 13 shows that, when an error is detected by the error detection unit 20, the timing T0 at which the error detection unit 20 outputs the reread instruction signal S0 to the controller 6 is changed from L level to H level. This is indicated by the timing of changing to the level.
[0016]
The (9) -th row in FIG. 13 shows that the address space number of the storage means 5 is the address N, N + 1, N + 2,... , And the data is sequentially written. In the (10) -th row in FIG. 13, a signal read from the DVD disk 1 and once stored in the storage device 5 is read by the first memory read / write unit 17, and error correction is performed by the error correction unit 16. After execution, the first memory read / write means 17 again delays the writing of the memory writing means 12 by a timing period of one error correction block unit, and stores the address space of the storage means 5 in error correction block units. The figure shows that numbers are accessed in the order of addresses N, N + 1, N + 2,... And are sequentially written. In the (11) th row in FIG. 13, the signal stored in the storage device 5 is read by the second memory read / write unit 21 after the error correction unit 16 has performed the error correction, and the error detection unit 20 reads the signal. After the error detection processing is performed, the second memory read / write unit 21 is again delayed from the writing of the memory writing unit 12 by a timing period of two error correction blocks, and stored in the error correction block unit. 5, the address space number 5 is accessed in the order of addresses N, N + 1, N + 2,... And is sequentially written.
[0017]
FIG. 13 shows that, as described above, first, the data of the sector number M detected from the DVD disk 1 that cannot be error-corrected writes an error correction block including the sector number M to the address N of the storage means 5. Next, the timing of each signal when error correction processing and error detection processing are performed on the data at the address N is shown.
[0018]
Next, the operation of the conventional DVD reproducing apparatus 100 will be described with reference to FIGS.
The signal recorded on the DVD disk 1 is binarized by the head amplifier 2 and then input to the demodulation means 11 in the error correction circuit 3. After demodulating the input signal (data), the demodulation unit 11 writes data to the storage unit 5 via the memory writing unit 12 and the bus 4 and also sends a sector unit timing signal to the timing generation unit 13. Output. The timing generation unit 13 generates a timing signal for each error correction block from the input timing signal for each sector, and outputs the timing signal as, for example, a timing signal based on an “L” level pulse.
[0019]
The counter 14 is initialized by the timing signal output from the timing generation unit 13, and thereafter alternately outputs, for example, "1" and "2" corresponding to the error correction mode. The sequencer 15 outputs two types of signals, and outputs, for example, an “L” level signal as a first type of signal during a period in which error correction processing is performed. As another type of signal, a signal for switching the error correction processing means 16 to perform the first error correction processing or the second error correction processing is output. When the first error correction processing is performed by the error correction processing means 16, for example, an “H” level is output. When the second error correction is performed, for example, an “L” level is output. The error correction processing means 16 performs error correction on the data in the storage means 5 according to two types of outputs from the sequencer 15 via the first memory read / write means 17.
[0020]
The error detecting means 20 accesses the address space in the storage means 5 holding the data after the error correction processing, via the second memory reading means 21, and executes the error detecting processing. For example, the address space to be accessed by the error correction unit 16 and the error detection unit 20 is switched in synchronization with the timing signal of the error correction block unit from the timing generation unit 13 and, as shown in FIG. Consider a case where the space holding the data after the correction processing is, for example, an address N. Then, the error detection unit 20 that performs error detection on the address space (N) using the error detection data (EDC) is next to the second error correction block unit timing period in which the error correction processing has started. The operation starts when the third error correction block unit timing period comes. As shown in the (7) th row of FIG. 13, when the period during which the error detection means 20 is performing the error detection operation for 16 sectors is set to, for example, the “L” level, the M sectors of the 16 sectors are used. Since an error is detected, an error detection signal S0 is output from the error detection means 20 to the controller 6 at a timing T0 as shown in the (8) th row of FIG.
[0021]
Upon receiving the error detection signal S0, the controller 6 outputs an instruction to the servo controller 7 based on the timing T0 at which the error detection signal S0 was input, to read out the error correction block including the sector in which the error was detected again, An error correction block including a sector in which an error has been detected under the control of the servo controller 7 is read from the DVD 1 again. Therefore, the error detection signal S0 indicates that an error has been detected, and includes an instruction to read out the error correction block including the sector in which the error has been detected again.
[0022]
By the way, the data output unit 22 sequentially reads and outputs the data held in the storage unit 5, but reads again the above-mentioned “error correction block including an erroneous sector”. In the error detection processing of the conventional DVD reproducing apparatus 100, as described above, the error detection signal S0 output from the error detection means 20 is output after the error correction processing by the error correction means 16 is completed. Since the signal is output only in the middle, the process of re-reading the error correction block including the erroneous sector by the error detection signal S0 is a time-consuming process. Therefore, when the operation of correcting the data takes a long time, it is determined that the error has disappeared, and the data that can be output is lost in the storage unit 5, and the data output may have to be stopped. .
[0023]
Further, as disclosed in Japanese Patent Application Laid-Open No. 9-180379, the error detection means 20 does not use the error detection data EDC to detect the error, and instead, as shown in the second row of FIG. When the interval of the timing signal in sector units is compared with the reference interval, and when it deviates from the reference interval, an error is detected to determine that there is an error in the main data 31 for each sector. Although the data is only deviated from the reference interval and is correctable by performing the correction processing by the error correction means 16 using the product-sum code of the DVD, the correction processing by the correction means 16 is performed. May be erroneously determined to be uncorrectable error data, and unnecessary data re-reading may be performed.
[0024]
[Problems to be solved by the invention]
As described above, the conventional error correction circuit 3 is configured to perform error detection for each of the sectors 30 (a to p) after the error correction processing of the entire error correction block 41 is completed. After a sector including uncorrectable data is written into the storage unit 5 by the read / write unit 17, a large time delay occurs until the error detection unit 20 detects an error in the sector data.
[0025]
For example, when reproducing data that cannot be corrected by the error correction means 16 of the conventional error correction circuit 3 of FIG. 12, the fact that the data is uncorrectable and has an error is determined by the error detection means 20 by the error correction block of FIG. It is detected during the third timing period of the unit. Therefore, the non-correctable data is re-read after the fourth timing period in error correction block units following the third timing period in error correction block units.
[0026]
Then, in order for the servo controller 7 to read the relevant sector data, the number of sectors from the currently read sector to the relevant sector to be returned increases to two error correction block units or more. In this case, since the intervals between the respective sectors are large, there is a problem that the control by the servo controller 7 becomes difficult, and a problem occurs that it takes time to establish the control. Further, since it takes time to establish the servo, there is a problem that data output from the conventional DVD reproducing apparatus is lost.
[0027]
An error correction circuit according to the present invention has been made in order to solve the above-described problem, and it is possible to prevent data loss due to a long time required for rereading control of data in which an error is detected, and to provide a DVD reproducing apparatus. It is an object of the present invention to provide an error correction circuit for stably controlling the error.
[0028]
[Means for Solving the Problems]
In order to achieve the above object, an error correction circuit of a disk reproducing apparatus according to the present invention is characterized in that a first error correction code serving as an inner code and a second error correction code serving as an outer code. Storage means for temporarily storing the read data when the data stored in the recording disk is read in units of error correction blocks by at least a head capable of reading data from the recording disk; Error correction means for performing a first error correction process using a first error correction code and a second error correction process using a second error correction code on error data to be corrected, Means for reading and writing data from the storage means in accordance with the instructions of the means, and at least reducing the read data and the position information of each sector in the error correction block of the data. A first memory read / write unit for outputting header information including the first and second error correction processes, a sequencer for outputting a control signal for switching between the first error correction process and the second error correction process to the error correction unit, and an odd and even number for switching the sequencer. And a counter for alternately outputting the control signal shown in FIG. 1 and a head on the recording disk 1 based on the data read from the recording disk and amplified by the head amplifier when the data stored on the recording disk is read in error correction block units. Track cross detecting means for detecting a case where a plurality of concentric tracks are crossed and outputting track cross detecting data, and track cross detecting data storing means for storing track cross detecting data by the track cross detecting means Read from the storage means by the first memory read / write means. A track cross detection data reading means for reading track cross detection data stored in the track cross detection data storage means based on the header information of the data; and at least track cross detection data read by the track cross detection data reading means. When reset means for resetting the sequencer and the counter and outputting track cross detection data, external notification means for outputting the track cross detection data output from the reset means to the outside, and when track cross detection data is received from the external notification means And a control unit for rereading the error correction block corresponding to the track cross detection data from the recording disk.
[0029]
According to a second aspect of the present invention, in the error correction circuit of the disk reproducing apparatus according to the first aspect, when a track cross is detected, the track cross detection means adds the data before and after the track cross detection data when the track cross is detected. The header information of the read data is output, the track cross detection data storage means stores the header information in addition to the track cross detection data, and the track cross detection data read means is stored by the first memory read / write means. The header information of the data read from the data is compared with the header information stored in the track cross detection data storage means to read out the track cross detection data, and the reset means reads the header information in addition to the track cross detection data. The external notification means outputs header information in addition to the track cross detection data. Control unit receives the header information in addition to the track cross detection data, the error correction block corresponding to the track crossing detection data, and identifies the received header information.
[0030]
According to a third aspect of the present invention, in the error correction circuit of the disk reproducing apparatus according to the first or second aspect, the track cross detection data storage means includes a number of flip-flops corresponding to the number of sectors that can be stored in the storage means. Characterized in that the shift register has
[0031]
According to a fourth aspect of the present invention, in the error correction circuit of the disk reproducing apparatus according to any one of the first to third aspects, each of the sectors read from the header information output by the first memory read / write means. Data ID detecting means for separating data of other data from other data, and detecting data recognition information (data ID) indicating an order in which the value increases or decreases by a fixed width in the correction block, and the data ID detecting means detects the data ID information. The first data ID storage means for storing the latest data ID and the new data ID, and outputting the currently stored data ID, and the second data ID from the latest data output from the first storage means. The second data ID storing means for storing the third data ID is compared with the order of each data ID stored in the first data ID storing means and the second data ID storing means. It is detected whether the data order is a direction intersecting one or more adjacent tracks from one track of the recording disk. If the data order is a direction intersecting, the intersecting direction and the first direction are determined. And a direction detecting means for outputting at least one of the data IDs stored in the second data ID storing means. The external notifying means further comprises a track crossing detection data input from the resetting means. The controller outputs a signal indicating the direction of the data order input from the direction detecting means, and when receiving the track crossing detection data and the signal indicating the direction of the data order from the external notification means, rereads from the recording disk. The direction of the error correction block to be made is specified by a signal indicating the direction of the data order.
[0032]
According to a fifth aspect of the present invention, in the error correction circuit of the disk reproducing apparatus according to the fourth aspect, the direction detecting means is arranged so that the data order intersects one track or more adjacent tracks from one track of the recording disk. It is characterized in that whether or not the direction is to be performed is detected based on whether or not the value of each data ID stored in the first data ID storage means and the value of each data ID stored in the second data ID storage means are continuous with a predetermined value difference. And
[0033]
According to a sixth aspect of the present invention, in the error correction circuit of the disk reproducing apparatus according to the fifth aspect, the direction detecting means is arranged so that a data order is shifted from one track of the recording disk to one or more adjacent tracks. If the directions intersect, whether the direction is on the inner circumference side is determined by calculating the difference between the values of the respective data IDs stored in the first data ID storage means and the second data ID storage means. , Is detected by the sign of the value.
[0034]
According to a seventh aspect of the present invention, in the error correction circuit of the disk reproducing apparatus according to the fifth or sixth aspect, the direction detecting means is arranged so that the data order is one or more adjacent tracks from one track of the recording disk. When the direction intersects with the direction, the number of tracks intersecting in that direction is calculated by calculating the difference between the values of the data IDs stored in the first data ID storage means and the second data ID storage means. It is characterized by detecting by the absolute value of the value.
[0035]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments.
[0036]
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of the error correction circuit according to the first embodiment of the present invention. In FIG. 1, portions having the same functions as those of the conventional error correction circuit 3 shown in FIG. 12 are denoted by the same reference numerals, and redundant description will be omitted.
[0037]
The main differences between the error correction circuit 50 of FIG. 1 and the error correction circuit 3 shown in FIG. 12 are the following points.
[0038]
(1) The track cross detecting means 51 is provided. When reading data stored in the recording disk 1 in units of error correction blocks, the track cross detecting means 51 reads data from the sector unit read from the recording disk 1 and amplified by the head amplifier 2 on the recording disk 1. Then, when a head (not shown) crosses a plurality of tracks formed concentrically, track cross detection data is output as S2.
[0039]
The waveform output from the head amplifier 2 when the head crosses a track is such that, for example, the waveform of a pulse signal every time the track crosses is generated according to the number of tracks crossing. Only the occurrence of a track cross and the duration of the track cross are required. Therefore, the track cross detecting means 51 generates the track cross detection data by shaping the waveform of the input pulse signal into one pulse signal so that the processing in the subsequent circuit becomes easy. When the head amplifier 2 detects the header information of the data in sector units before and after the detection of the track cross detection data, the track cross detection means 51 reads out the read data in that case in addition to the track cross detection data. The header information of the obtained data is output as S2.
[0040]
(2) Track cross detection data storage means 52 is provided. The track cross detection data storage unit 52 is, for example, a memory device, receives and stores the track cross detection data S2 by the track cross detection unit 51, and receives the sector synchronization signal St from the timing generation unit 13 and In response to a read request S4 from the track cross detection data reading means 53 described later, the requested track cross detection data is output as S5. When header information is received and stored together with the track cross detection data, the track cross detection data storage unit 52 also receives and stores the header information of the data as S2, and outputs it as S5.
[0041]
(3) The track cross detection data reading means 53 is provided. The track cross detection data reading means 53 sends the track cross detection data storage means 52 to the track cross detection data storage means 52 based on the sector-by-sector header information of the data read for error correction by the first memory read / write means 17. Then, a read request S4 is output, the track cross detection data stored in the track cross detection data storage means 52 is read as S5, and it is determined whether or not a track cross has occurred in the sector. When the track cross detection data reading means 53 determines that a track cross has occurred, the track cross detection data is output to the reset means 54 described later as S6. When reading the header information together with the track cross detection data, the track cross detection data reading means 53 also reads the header information as S5 and outputs it as S6.
[0042]
(4) The first memory read / write means 17 accesses the storage means 5 according to the instruction of the error correction means 16 and reads out the data to be corrected by the error correction means 16 in units of error correction blocks, and reads the corrected data. An output signal of header information for each sector in a block of data read when accessing the storage means 5 and a trigger signal S3 as a trigger signal for reading track cross detection data are written to the storage means 5 while writing to the storage means 5. It outputs to the detection data reading means 53.
[0043]
(5) The reset means 54 is provided. The reset unit 54 forcibly corrects an error when the track cross detection data reading unit 53 reads track cross detection data corresponding to a sector in a block of the data read when the storage unit 5 is accessed. In order to stop the operation, the sequencer 15 for controlling the error correction processing is reset by the reset signal S8, the counter 14 is reset by the reset signal S7, and the read track cross detection data (and header information) is set as S9, which will be described later. And output to the external notification means 55. If the header information is read together with the track cross detection data, the header information is also output to the external notification means 55 as S9.
[0044]
(6) An external notification unit 55 is provided. The external notification unit 55 receives the track cross detection data output as S9 when the reset is performed from the reset unit 54, and outputs it as S10 to the controller 6 which is a control unit outside the error correction circuit 50. When the header information is received together with the track cross detection data, the header information is also output to the controller 6 as S10.
[0045]
(7) When receiving the track cross detection data S10 from the external notification unit 55, the controller (control unit) 6 causes the error correction block corresponding to the track cross detection data to be re-read from the recording disk 1. Request to servo controller 7. When header information is also received together with the track cross detection data, an error correction block corresponding to the track cross detection data is specified by the received header information and read from the recording disk 1 again.
[0046]
In the present embodiment, for example, the timing at which the data of the second error correction block B2 is read from the recording disk 1 for each sector and the data of the first error correction block B1 stored in the storage means 5 are used for error correction. Therefore, if the read timing for each sector is synchronized, the error correction block is specified theoretically even if there is no header information of the sector unit data before and after the track cross detection data is detected in the above. It is possible to re-read from the recording disk 1.
[0047]
However, when the above two timings are not synchronized, that is, the timing at which the data of the second error correction block B2 from the recording disk 1 is read for each sector, and the timing of the first error correction stored in the storage means 5 If the timing of reading the data of the block B1 for each sector for error correction does not match and there is no correlation, the header information of the sector unit data before and after the detection of the track cross detection data is replaced with the corresponding track information. It is necessary to read the cross detection data.
[0048]
FIG. 2A is a diagram showing an operation when a head (not shown) crosses a track on the recording disk 1 when reading data stored on the recording disk 1 in error correction block units. FIG. 2B is a diagram illustrating a track cross signal when a track cross occurs in FIG.
[0049]
In FIG. 2A, Tr1 to Tr4 are concentrically formed on the recording disk 1 and are individual tracks on which information is recorded. Tr1 to Tr4 are collectively referred to as a track 1a. Reference numeral 1b denotes a head pickup for reading information recorded from the track 1a, and D1 denotes a direction in which the pickup 1b moves when a track cross occurs.
FIG. 2B shows track cross signals C1 to C4 generated each time the pickup 1b crosses a track when the pickup 1b in FIG. 2A moves in the direction D1.
[0050]
FIG. 3A is a diagram showing the timing of the sector synchronization signal St (ts1 to ts3) from the timing generation means 13, and FIG. 3B is a diagram showing the timing of the track cross signals C1 to C4. FIG. 3C is a diagram showing the timing of the track cross detection data CD1 output from the track cross detection means 51.
[0051]
The track cross signals C1 to C4 are generated by pulses with a very short interval as compared with the interval of the sector synchronization signals St (ts1 to ts3) in FIG. Therefore, the track cross detecting means 51 shapes the track cross signals C1 to C4 and outputs the track cross signals C1 to C1 as one track cross detection data CD1.
[0052]
FIG. 4A is a diagram showing the occurrence timings tb1 to tb3 of the error correction blocks B1 to B2 of the data read from the recording disk 1, and FIG. 4B is output from the timing generation means 13, for example. FIG. 4A is a diagram showing the synchronization timings ts1 to ts4 for each of the sectors S1 to S7 in each error correction block of FIG. 4A, and FIG. 4C is stored in the track cross detection data storage means 52. 4D is a diagram showing the timing of the track cross detection data CD1, and FIG. 4D is a diagram showing the timing of sector unit data read from the track cross detection data storage unit 52 by the track cross detection data reading unit 53. .
[0053]
For example, as shown in FIG. 4A, while the data of the error correction block B1 is read from the recording disk 1 and the memory writing unit 12 is writing the data to the storage unit 5, the data is written to the storage unit 5 as shown in FIG. It is assumed that a track cross occurs in the fourth sector S4 as shown in FIG. In this case, as shown in FIG. 4C, the track cross detection data CD1 is generated at the timing of the sector S4 and stored in the track cross detection data storage means 52.
[0054]
Next, when the data of the error correction block B2 starts to be read from the recording disk 1, the first memory read / write means 17 reads the data of the error correction block B1 from the storage means 5 according to the instruction of the error correction means 16, and reads the data of the sector. A timing signal is output to the track cross detection data reading means 53 so that the track cross detection data CD1 is read from the track cross detection data storage means 52 in order in units.
[0055]
When the track cross detection data reading means 53 reads the track cross detection data CD1 corresponding to the sector S4 of the error correction block B1, the reset means 54 instructs the reset means 54 to reset the sequencer 15 and the counter 14 at that timing, 55, the track cross detection data tc1 for rereading from the recording disk 1 is output. During the above operation, when the track cross detection data CD1 or the track cross detection data tc1 is output, the header information including the storage position information of the data in the recording disk 1 is also output.
[0056]
Next, with reference to FIG. 1 to FIG. 4, a description will be given of a difference between the operation of the error correction circuit of the present embodiment and the conventional operation.
[0057]
The data output read from the recording disk 1 is sent to the demodulating means 11 via the head amplifier 2 and also sent to the track cross detecting means 51 and monitored (S1). The data output sent to the demodulation means 11 is sequentially written to the storage means 5 by the memory writing means 12 and also sent to the timing generation means 13 to generate the sector synchronization timing signal St.
[0058]
On the other hand, if the head pickup cannot trace the track of the recording disk 1 and moves, for example, in the direction D1 in FIG. 2, the pickup crosses the track on which information is recorded. The track cross signals C1 to C4 as shown in (b) are generated and output (S1).
[0059]
The track cross signals C1 to C4 (S1) are detected by the track cross detection means 51, and as shown in FIG. It is shaped, sent to the track cross detection data storage means 52 (S2), and stored.
[0060]
The track cross detection data CD1 stored in the track cross detection data storage unit 52 is updated in sector units by the timing signal St for each sector from the timing generation unit 13. As described above, the track cross detection data CD1 is managed so as to be sequentially stored in the track cross detection data storage unit 52 for each sector.
[0061]
On the other hand, when the writing of the data of the error correction block B1 shown in FIG. 4A into the storage means 5 is completed by the memory writing means 12, the first memory read / write means 17 shown in FIG. At this time, the data for the error correction block B1 is read from the storage unit 5, and the error correction by the error correction unit 16 is performed. At this time, the first memory read / write unit 17 sends the timing signal and header information of the read sector to the track cross detection data reading unit 53 while reading the data of the storage unit 5 in sector units (S3).
[0062]
The track cross detection data reading means 53 requests the track cross detection data corresponding to the track cross detection data storage means 52 based on the sector timing and the header information (S3) received from the first memory read / write means 17 (S4). ) And read out (S5). When detecting a track cross, the track cross detection data reading means 53 notifies the reset means 54 of the track cross detection data and the header information (S6). The reset means 59 outputs a reset signal S7 to the counter 14 to stop the error correction operation, outputs a reset signal S8 to the sequencer 15, and sends track cross detection data together with header information to the external notification means 55. (S9). Upon receiving the track cross detection data and the header information (S9), the external notification means 55 sends the track cross detection data and the header information (S10) to the external controller 6.
[0063]
When the controller 6 receives the track cross detection data and the header information (S10), it recognizes that the servo has deviated, and re-applies the servo to the servo controller 7 in a correct operation. Is read again.
[0064]
The above-described series of operations is performed in the error correction circuit according to the first embodiment in accordance with the error correction process performed by the first memory read / write unit 17. Accordingly, the controller 6 can recognize that the servo has been deviated during the second timing period in units of error correction blocks shown in FIG. 13, so that the controller 6 performs the servo operation earlier than the conventional error correction circuit shown in FIGS. Reread control by the controller 7 can be performed.
[0065]
In this manner, the error correction circuit 50 of the present embodiment prevents data loss due to the time required for reread control of data in which an error is detected, and stably controls the DVD reproducing device 100. be able to.
[0066]
Further, in the above-described embodiment, as the data stored in the storage unit 5, the first error correction processing is performed on the error correction block 41 shown in FIG. 11 using the inner code parity 44. And the data having at least the second error correction code for performing the second error correction process using the outer code parity 45 have been described. However, in addition to the above, if the error detection data to be processed by the error detection means 20 is added data, the error data remaining after the error correction processing by the error correction Is detected using the error detection data, and the controller 6 can also re-read the error correction block including the error data detected by the error detection means 20 from the recording disk. .
[0067]
As described above, in the present embodiment, it is possible to detect that the head (pickup) at the time of reading the recording disk 1 crosses the track and read the corresponding data from the recording disk 1 again, so that an error is detected. Since it takes a long time to control the rereading of the data, it is possible to prevent the data from being lost, and to stably control the DVD reproducing apparatus.
[0068]
Embodiment 2 FIG.
In the first embodiment, the timing at which the data of the second error correction block B2 is read from the recording disk 1 for each sector and the data of the first error correction block B1 stored in the storage means 5 are used for error correction. For this reason, the track cross detection data storage means 52 in the error correction circuit stores the track cross detection data together with the track cross detection data so as to cope with not only the case where the reading timing for each sector is synchronized but also the case where the timing is not synchronized. A memory device or the like capable of storing header information including data position information has been assumed.
[0069]
However, for example, the timing at which the data of the second error correction block B2 is read from the recording disk 1 for each sector, and the data of the first error correction block B1 stored in the storage means 5 are read for each sector for error correction. If the read timing is the same, the error correction circuit can re-read the corresponding portion from the recording disk 1 only by using the detection data indicating whether or not there is a track cross for each sector. Even simple storage means other than the memory device can be applied. Embodiment 2 shows a case where a shift register is used as simple storage means other than a memory device.
[0070]
The main points in which the error correction circuit of the second embodiment differs from the error correction circuit 50 of the first embodiment shown in FIG. 1 are as follows.
[0071]
(8) The track cross detection data storage means 52 is a shift register having a number of flip-flops corresponding to the number of sectors that can be stored in the storage means 5.
[0072]
(9) Since the timing of the data for each sector read from the storage means 5 is the same as the timing of the data one error correction block before read from the recording disk 1, the error correction circuit of this embodiment is used. Only the detection of the track cross is performed without handling the position information and the like included in the header information.
[0073]
The position information of the data re-read from the recording disk 1 is read by the controller 6 and the servo controller 7 in accordance with the timing of the data for each sector in the error correction block read from the storage means 5. The data of the corresponding sector is read out again from the previous error correction block read out from.
[0074]
FIG. 5 is a block diagram showing the configuration of the track crossing detection data storage means in the error correction circuit according to the second embodiment of the present invention.
[0075]
5, 61 is a set-reset type flip-flop, C1 is track cross detection data detected in sector units, and 62 and 63 are track cross detection data C1. Is stored in the flip-flop.
[0076]
Other configurations are the same as those described in the first embodiment.
[0077]
Next, the operation of the track crossing detection data storage means in the error correction circuit of the present embodiment will be described.
[0078]
When the track cross detection data CD1 (S2) shown in FIGS. 3C and 4C is input to the set-reset type flip-flop 61 from the track cross detection means 51, for example, At the first rise, the flip-flop 61 is set.
[0079]
The set state of the flip-flop 61 is reset each time a sector synchronization signal St output from the timing generation unit 13 in sector units is input. However, at that time, the track cross detection data before resetting is output as a signal C1 to the flip-flop 62 connected adjacently.
[0080]
When the track cross detection data C1 is input to the flip-flop 62, the flip-flop 62 changes and maintains one of the two stable states to the other, and outputs the state signal. When the state signal of the flip-flop 62 is input to the flip-flop 63, the flip-flop 63 changes and maintains one of the two stable states to the other, and outputs the state signal. As described above, every time the sector synchronization signal is input, the state signal is transmitted to each flip-flop sequentially connected in the shift register.
[0081]
The number of flip-flops provided in the shift register is stored as the data cross detection data because it is only necessary to know whether or not it is necessary to reread each sector of the storage means 5 where data is stored. If there is only the number corresponding to the number of sectors of the means 5, the storage means 5 can be accessed.
[0082]
As described above, according to the present embodiment, a shift register having a number of flip-flops corresponding to the number of sectors that can be stored in the storage unit 5 is used as the track cross detection data storage unit 52 without using a memory or the like. Since the track cross information for each sector is managed, the circuit size of the error correction circuit can be reduced.
[0083]
Embodiment 3 FIG.
In the first and second embodiments described above, when the head at the time of reading of the recording disk 1 detects that the track has crossed, the corresponding data is read again from the recording disk 1 so that the data in which the error is detected is read again. However, since the direction of the track-crossed head was not detected, the controller 6 or the servo controller 7 detected the direction of the track-cross, which required time. . Therefore, for example, if the direction of the head that crossed the track can also be detected, it is possible to further reduce the data re-reading time compared to the first and second embodiments. In the following, a case will be described as a third embodiment where the head cross direction is also detected in addition to the head crossing track.
[0084]
FIG. 6 is a block diagram showing a configuration of the error correction circuit according to the third embodiment of the present invention.
The main points in which the error correction circuit 60 of FIG. 6 differs from the error correction circuit 50 shown in FIG. 1 are the following points.
[0085]
(10) The first memory read / write means 17 accesses the storage means 5 according to the instruction of the error correction means 16 and reads out the data to be corrected by the error correction means 16 in units of error correction, and reads the corrected data. In addition to writing to the storage means 5, the output signal S11 of header information for each sector in the block of data read when accessing the storage means 5 is output to the data ID detection means 56 described later.
[0086]
(11) Data ID detection means 56 is provided. The first data ID detection means 56 separates the read data from other data for each sector data from the output signal S11 of the header information of the storage means 5 input from the first memory read / write means 17, and In the block to be corrected, a data recognition information (data ID) portion indicating an order in which the value increases or decreases at a constant width is detected, and an output signal S12 of the data ID is output to a first data ID storage means 57 described later. I do.
[0087]
(12) The first data ID storage means 57 is provided. The first data ID storage means 57 stores the output signal S12 of the latest data ID detected and output by the first data ID detection means 56 and stores the output signal S12 of the new data ID. An output signal S13 of the currently stored data ID is output to a second data ID storage unit 58 described later, and a data ID newly stored by the output signal S12 is output as a data ID output signal S14. Output to the direction detecting means 59.
[0088]
(13) The second data ID storage means 58 is provided. The second data ID storage unit 58 stores the output signal S13 of the second latest data ID output from the first data ID detection unit 57, and stores the newly stored data ID by the output signal S13. The data ID is output to a direction detecting means 59 described later as an output signal S15.
[0089]
(14) A direction detecting means 59 is provided. The direction detection means 59 compares the order of both the output signal S14 of the data ID output from the first data ID storage means 57 and the output signal S15 of the data ID output from the second data ID storage means 58. Then, when the data order is not continuous due to a difference of a predetermined value, it is detected that the data order is discontinuous.
[0090]
Specifically, for example, when the data ID of each sector data is in ascending order that increases by one constant width, the value of the output signal S14 of the data ID output from the first data ID storage unit 57 And when the difference between the value of the output signal S15 of the data ID output from the second data ID storage means 58 is 1 and the value of the output signal S14 of the first data ID storage means 57 is larger. , The direction detecting means 59 does not output the output signal S16 because it determines that the direction is continuous. However, when the difference between the value of the output signal S14 and the value of the output signal S15 is not 1, the direction detection means 59 outputs the output signal S16 to the external notification means 55a in order to determine discontinuity.
[0091]
As described above, the data ID is information included in the header information for each sector in the block to be corrected, and indicates the order in which the value increases or decreases at a constant width in the block. Is not continuous, that is, discontinuous, means that an error has occurred in the data of the read correction block. In particular, in the case of the present embodiment, it is determined that a track cross has occurred in the data reading in a direction in which the data sequence crosses one or more adjacent tracks from one track of the recording disk.
[0092]
The direction detecting means 59 outputs at least the data ID received as the output signal S15 from the second data ID storage means 58 as the output signal S16.
[0093]
The discontinuity of the data order in the data reading can be detected by the fact that the position included in the header information of the data read according to the predetermined order is not, for example, one difference. The occurrence of the track cross can be detected from the fact that the position indicated by the header information is a position in a direction crossing one or more adjacent tracks from one track on the recording disk 1. it can.
[0094]
The first data ID storage means 57 and the second data ID storage means 58 determine whether the data order is a direction crossing one track or more adjacent tracks from one track of the recording disk 1. It can be detected based on whether or not the values of the stored data IDs are consecutive with a difference of a predetermined value.
[0095]
Further, when it is detected that the position of the read data is in the direction intersecting the track, it is detected whether the intersecting direction is the inner side or the outer side. The direction can be calculated by calculating the difference between the values of the data IDs stored in the first data ID storage means 57 and the second data ID storage means 58 and detecting the positive or negative value of the value.
[0096]
Specifically, for example, the values of the first data ID storage unit 57 and the second data ID storage unit 58 are compared, and when the difference is not 1, the first data ID storage unit 57 If the output value> the output value of the second data ID storage means 58, it indicates that a track cross has occurred in the inner circumferential direction. Conversely, if the difference is not 1, and the output value of the first data ID storage means 57 <the output value of the second data ID storage means 58, it indicates that a track cross has occurred in the outer peripheral direction. The direction detecting means 59 detects the direction in which the track cross has occurred as described above, and sends it to the external notification means 55a.
[0097]
In this case, for example, at least one of the data IDs stored in the first data ID storage unit 57 or the data IDs stored in the second data ID storage unit 58 is crossed. Output with positive and negative values indicating the direction.
[0098]
If the data order is a direction intersecting one track or more adjacent tracks from one track on the recording disk 1, the number of tracks intersecting in that direction is detected. The difference between the values of the data IDs stored in the ID storage means 57 and the second data ID storage means 58 can be calculated and detected by the absolute value of the value.
[0099]
For example, when a positive or negative value indicating the crossing direction is not calculated, the data ID stored in the first data ID storage unit 57 and the data stored in the second data ID storage unit 58 are stored. It is also possible to output both IDs and let the external controller 6 determine the crossing direction.
[0100]
(15) When receiving the output signal S16 (including the data ID) indicating that a track cross has occurred (being discontinuous) from the direction detecting means 59, the reset means 54a resets the counter 14 with the output signal S7. , And an output signal S8 for resetting the sequencer 15. Further, an output signal S9 (data ID indicating that a track cross (discontinuity) has occurred in the data ID detected for each sector is output to the external notifying means 55a. Is output together with the data ID.
[0101]
(16) When receiving the output signal S9 (including the data ID) from the resetting unit 54a, the external notification unit 55a outputs the track cross detection data and the data ID indicating discontinuity (or detection of an error). , As an output signal S10 to the controller 6. The output signal S10 is a signal similar to the error detection signal S0 output from the error detection means 20 to the controller 6, which indicates that a track cross has been detected due to discontinuous data, and that the track cross has been detected. The instruction content for causing the error correction block including the sector to be read again is included. That is, the output signal S10 includes, in addition to the track cross detection data and the data ID (header information), a positive / negative signal indicating the direction of the data order input from the direction detection means 59.
[0102]
(17) As described above, the controller 6 controls the servo controller 7 by instructing the DVD disk 1 to reproduce the error-corrected block in which the track cross is detected and to re-read the DVD disk 1, as well as the DVD reproducing apparatus. Although the control unit controls the operation of the whole 100, in the present embodiment, the output signal S10 is received from the external notification unit 55a in the same manner as when the error detection signal S0 is received from the error detection unit 20. In this case, the instruction to re-read from the DVD 1 is also issued. That is, when the controller 6 as the control unit receives the track cross detection data, the data ID (header information), and the positive / negative signal indicating the direction of the data order from the external notification unit 55a, the header information and the data order of the data order are received. It requests the servo controller 7 to re-read the error correction block containing the error data whose position and direction are specified by the positive and negative signals indicating the direction from the recording disk 1.
[0103]
FIG. 7 is a diagram showing the structure of a frame constituting one sector shown in FIG.
[0104]
As shown in FIG. 7, one sector has 13 lines, and each line is divided into two frames. Therefore, each one sector in the error correction block is composed of 26 frames from frame 0 to frame 25.
[0105]
FIG. 8 is a diagram showing the relationship between the synchronization timing in units of sectors shown in the (2) th row of FIG. 13 and the synchronization timing in units of frames shown in FIG.
[0106]
The sector synchronization timing ts1 shown in FIG. 8A coincides with the frame synchronization timing tf1 shown in FIG. 8B, and the data of the frame 0 in FIG. 7 is input / output at the frame synchronization timing tf1. Similarly, data of the frame 9 is input / output at the frame synchronization timing tf10, data of the frame 19 is input / output at the frame synchronization timing tf20, and data of the last frame 25 is input / output at the frame synchronization timing tf26. You. The next frame synchronization timing tf27 coincides with the sector synchronization timing ts2 of the next sector, and input / output is performed.
[0107]
FIG. 9 is a diagram showing the structure of a line (error correction line) including the header information shown in FIG. 10 from one sector composed of 13 lines shown in FIG.
[0108]
As shown in FIG. 9, the data ID (ID) exists in the four bytes (B1 to B4) located at the head of frame 0 in FIG. Being located at the beginning of frame 0 means that the data ID is located at the first four bytes of the sector. Also, since one block shown in FIG. 10 is composed of 16 sectors, in the error correction block 40 of FIG. 10B, out of the 208 lines, 1, 13, 25, 37, 49, 61, 73 out of 208 lines , 85, 97, 109, 121, 153, 145, 157, 169, and 181, the data ID of each sector is located in the first four bytes at the head of the 16 lines.
[0109]
In the above-mentioned data ID of the first four bytes (B1 to B4), the last one byte B4 indicates the order in which the sectors in any one block for which an error is to be corrected are sorted and arranged. Therefore, a value obtained by increasing the value from 0 to F by 1 (with a constant width) in hexadecimal notation is written. Therefore, “0” is written as the value of the last byte B4 in the data ID of the first sector of one block, and “1” is written as the value of the last byte B4 in the data ID of the next sector. The value of the last byte B4 is simply incremented by one for each sector, and "F" is written as the value of the last byte B4 in the data ID of the last sector. If the value of the last one byte B4 for each sector does not simply increase for each sector in the block, it means that data has not been read correctly.
[0110]
Next, the operation of the error correction circuit according to the second embodiment will be described.
[0111]
The operation of the error correction circuit according to the second embodiment described below is for the case where one error correction block is composed of 16 sectors like a DVD disk, and the error correction means 16 transmits the data via the first memory read / write means 17. In this case, the data is read from the storage means 5 to perform the correction processing. In that case, the error correction means 16 corrects the error for all 208 lines constituting the error correction block 40.
[0112]
When the first memory read / write means 17 starts reading / writing the line where the data ID shown in FIG. 9 exists, the header information at the head of the first line (line including frame 0) for each sector is output as the output signal S11. The data is output to the data ID detecting means 56. The data ID detecting means 56 detects the data ID located in the first 4 bytes of the header information output signal S11 and outputs it as an output signal S12, and stores the detected data ID value in the first data ID storage means 57. I do.
[0113]
When the error correction processing by the first memory read / write unit 17 proceeds and the data ID of the next sector is detected by the data ID detection unit 56, the data ID detection unit 56 stores the data ID in the first data ID storage unit 57. A new output signal S12 is output to update the set value to the value of the newly detected data ID. At this time, the first data ID storage means 57 uses the value of the immediately preceding data ID (the immediately preceding data ID of the latest data ID) stored as the output signal S13 as the second signal. It is sent to the data ID storage means 58.
[0114]
The direction detecting means 59 receives the output signals S14 and S15 of the stored data ID from the first data ID storing means 57 and the second data ID storing means 58, respectively. The difference between the value of the last byte B4 in the ID and the value of the last byte B4 in the data ID of the second data ID storage means 58 is compared, and the difference is 1 and the first If the value of the output signal S14 of the data ID storage means 57 is larger, the direction detection means 59 determines that the data is continuous and does not output the output signal S16. However, for example, when the difference between the value of the output signal S14 and the value of the output signal S15 is not 1, the direction detecting means 59 determines whether the sector indicated by the data ID in the first data ID In order to determine that the sector indicated by the data ID in the second data ID storage means 58 is discontinuous, an output signal S16 is output to the reset means 54a.
[0115]
The determination that the direction of the data ID is not continuous by the direction detecting means 59 means that the sectors are not continuously read from the block for correcting one error. In other words, this indicates that the servo by the servo controller 7 or the like is off, and that the tracks on the DVD disk 1 are not correctly traced. In this embodiment, in this case, in data reading, it is determined that a track cross in which the data order is a direction crossing one track or more adjacent tracks from one track of the recording disk has occurred.
[0116]
When receiving the output signal S16 from the direction detection means 59, the reset means 54a outputs output signals S17 and S18 for resetting the counter 14 and the sequencer 15, respectively, and interrupts the error correction operation by the error correction means 16.
[0117]
The reset unit 54a sends an output signal S9 to the external notification unit 55a, and the external notification unit 55a outputs an output signal S10 indicating that an error has been detected to the controller 6 that manages the servo.
[0118]
By receiving the output signal S10, the controller 6 can determine that a track cross is detected by reading a block including a sector indicated by the data ID therein. As a result, the controller 6 recognizes that the servo has deviated, so that the servo is reapplied so that the servo controller 7 performs a correct operation.
[0119]
Other operations are the same as those described in the first embodiment.
[0120]
As described above, in the present embodiment, when it is detected that a track cross has occurred during reading of a block for which an error is to be corrected, re-reading is performed using the direction detecting means 59 or the like described in the present embodiment. In order to improve the re-reading speed and correct other errors, the error detecting means 20 can be used to detect various errors stably as in the prior art and to reduce the re-reading speed from the recording disk. By improving, the data loss can be prevented, and the DVD reproducing apparatus 100 can be controlled stably.
[0121]
Further, in the above-described embodiment, the reset unit 54a outputs the discontinuity signal from the direction detection unit 59 and the first data ID storage unit 57 and the second data ID storage unit 58. The data ID stored in at least one of them has been received, and the received signal indicating discontinuity and the data ID have been output to the external notification means 55a as the output signal S9. However, for example, only the signal indicating discontinuity may be sent from the direction detecting means 59 to the reset means 54a, and the data ID may be output from the direction detecting means 59 to the external notification means 55a. .
[0122]
The data ID according to the present embodiment is information in header information arranged at the head of each of a plurality of sectors constituting a correction block, and is address information for accessing a corresponding portion of the storage unit 5. is there.
[0123]
In the above-described embodiment, if the output value of the first data ID storage unit 57> the output value of the second data ID storage unit 58, for example, the direction detection unit 59 performs track crossing in the inner circumferential direction. Has occurred, and conversely, if the output value of the first data ID storage means 57 <the output value of the second data ID storage means 58, it indicates that a track cross has occurred in the outer circumferential direction. In the case of a DVD two-layer disc, in the case of the oppositely recorded second layer, if the output value of the first data ID storage means 57 <the output value of the second data ID storage means 58, It indicates that a track cross has occurred, and conversely, if the output value of the first data ID storage means 57> the output value of the second data ID storage means 58, it indicates that a track cross has occurred in the outer circumferential direction. So Case may be a decision to the contrary.
[0124]
【The invention's effect】
As described above, according to the first and second aspects of the present invention, it is possible to detect that the head (pickup) crosses the track at the time of reading the recording disk and read the corresponding data from the recording disk again. , Since data errors can be detected earlier than error detection processing can detect data errors, it is possible to reduce the time required to shift to control for reading data again, and to control the rereading of data where errors are detected. Data can be prevented from being lost because it takes a long time. Therefore, it is possible to stably control a disk reproducing device such as a DVD reproducing device. To correct other errors, the conventional error detection means can be used to detect various errors stably as in the past, and to improve the data read speed from the recording disk. Can be prevented, and the DVD playback device can be stably controlled.
[0125]
According to the third aspect of the present invention, in addition to the effects described above, the track cross detection data storage means 52 has a number of flip-flops corresponding to the number of sectors that can be stored in the storage means 5 without using a memory or the like. Since track cross information for each sector is managed using the shift register, track cross detection data for each sector can be managed by the shift register, and the circuit size of the error correction circuit can be reduced.
[0126]
According to the present invention of claims 4 to 7, in addition to the above-described effects, in the case where it is detected that a track cross has occurred during reading of a block for which an error is to be corrected, the track is read using a direction detecting means or the like. Since the direction in which the cross has occurred is detected, the servo restart determination can be simplified, and the speed of rereading can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an error correction circuit according to a first embodiment of the present invention.
FIG. 2A is a diagram showing an operation when a head crosses a track on a recording disk when reading data stored on the recording disk in error correction block units, and FIG. FIG. 6 is a diagram showing a track cross signal when a track cross occurs in FIG.
3A is a diagram showing a timing of a sector synchronization signal from a timing generation unit, FIG. 3B is a diagram showing a timing of a track cross signal, and FIG. 3C is a diagram showing a timing output from the track cross detection unit; FIG. 6 is a diagram showing timing of track cross detection data.
FIG. 4A is a diagram showing an error correction block generation timing of data read from a recording disk, and FIG. 4B is a diagram showing a synchronization timing of each sector in each error correction block of FIG. (C) is a diagram showing the timing of the track cross detection data stored in the track cross detection data storage means, and (d) is a sector read from the track cross detection data storage means by the track cross detection data reading means. It is a figure showing the timing of the data of a unit.
FIG. 5 is a block diagram showing a configuration of a track cross detection data storage unit according to Embodiment 2 of the present invention.
FIG. 6 is a block diagram illustrating a configuration of an error correction circuit according to a third embodiment of the present invention.
FIG. 7 is a diagram showing a structure of a frame constituting one sector.
8 is a diagram illustrating a relationship between synchronization timing in units of a sector and synchronization timing in units of a frame illustrated in FIG. 7;
9 is a diagram showing a structure of a line (error correction line) including header information from one sector including 13 lines shown in FIG. 7;
FIG. 10 is a diagram illustrating a relationship between a data structure of a DVD and an error correction block.
FIG. 11 is a diagram showing a configuration of a unit block.
FIG. 12 is a block diagram showing a configuration of an error correction circuit of a conventional DVD reproduction device.
FIG. 13 is a timing chart showing operation timings of an error correction circuit in the conventional DVD reproducing apparatus shown in FIG.
[Explanation of symbols]
1 DVD disk, 2 head amplifier, 3, 50, 60 error correction circuit, 4 bus, 5 storage means, 6 controller (control unit), 7 servo controller, 11 demodulation means, 12 memory writing means, 13 timing generation means, 14 counter, 15 sequencer, 16 error correction means, 17 first memory read / write means, 20 error detection means, 21 second memory write means, 22 data output means, 23 data read means, 30 sectors, 31 main data, 32 header information, 33 error detection data EDC (Error Detection Code), 34 inner code parity (PI), 35 outer code parity (PO), 40 unit block, 41 error correction block, 44 inner code parity (PI), 45 Outer code parity (PO), 56 data ID detecting means, 57 first data ID storing means, 58 second data ID storing means, 54, 54a resetting means, 55, 55a external reporting means, 59 direction detecting means, 100 DVD playback device.

Claims (7)

The data stored on the recording disk to which the first error correction code serving as the inner code and the second error correction code serving as the outer code have been added is read at least by a head capable of reading data from the recording disk. Storage means for temporarily storing read data when reading in units of correction blocks;
A first error correction process using the first error correction code and a second error correction process using the second error correction code are performed on the error data included in the data. Error correction means;
A first means for reading and writing the data from the storage means in accordance with an instruction of the error correction means and outputting header information including at least the read data and position information of the data for each sector in the error correction block; Memory read / write means;
A sequencer for outputting a control signal for switching between the first error correction processing and the second error correction processing to the error correction means;
A counter that alternately outputs a control signal indicating an odd number and an even number to switch the sequencer,
When reading data stored in the recording disk in error correction block units, a plurality of heads are formed concentrically on the recording disk 1 from data read from the recording disk and amplified by a head amplifier. Track cross detection means for detecting a case where a track crosses and outputting track cross detection data; track cross detection data storage means for storing track cross detection data by the track cross detection means;
A track cross detection data reading unit that reads track cross detection data stored in the track cross detection data storage unit based on header information of data read from the storage unit by the first memory read / write unit;
When track cross detection data is read by the track cross detection data reading means, reset means for resetting at least the sequencer and the counter and outputting track cross detection data,
External notification means for outputting the track cross detection data output from the reset means to the outside,
A control unit that, when receiving the track cross detection data from the external notification unit, rereads an error correction block corresponding to the track cross detection data from the recording disk. Correction circuit. The track cross detection means, when a track cross is detected, outputs, in addition to the track cross detection data, header information of data read before and after the data,
The track cross detection data storage unit stores the header information in addition to the track cross detection data,
The track cross detection data reading unit compares header information of data read from the storage unit by the first memory read / write unit with header information stored in the track cross detection data storage unit, Read track cross detection data,
The reset means outputs the header information in addition to the track cross detection data,
The external notification means outputs the header information in addition to the track cross detection data,
The method according to claim 1, wherein the control unit receives the header information in addition to the track cross detection data, and specifies an error correction block corresponding to the track cross detection data by the received header information. An error correction circuit of the disk reproducing device according to the above. 3. The error correction circuit according to claim 1, wherein the track cross detection data storage unit is a shift register having a number of flip-flops corresponding to the number of sectors that can be stored in the storage unit. . From the header information output by the first memory read / write means, the read data for each sector is separated from other data, and the order in which the value increases or decreases by a constant width in the correction block is determined. Data ID detecting means for detecting the data recognition information (data ID)
First data ID storage means for storing the latest data ID detected by the data ID detection means and outputting the currently stored data ID when storing a new data ID;
A second data ID storage unit for storing the second latest data ID output from the first storage unit;
The order of each data ID stored in the first data ID storage means and the second data ID storage means is compared, and the data order is changed from one track of the recording disk to one or more adjacent tracks. It is detected whether the direction is an intersecting direction. If the data order is an intersecting direction, at least the intersecting direction and at least one of the data IDs stored in the first and second data ID storage means are detected. Direction detecting means for outputting one data ID,
The external notification unit, in addition to the track cross detection data input from the reset unit, outputs a signal indicating the direction of the data order input from the direction detection unit,
The control unit, when receiving the track cross detection data from the external notification unit and a signal indicating the direction of the data order, indicates an error correction block to be re-read from the recording disk and indicates the direction of the data order. 4. The error correction circuit according to claim 1, wherein the direction is specified by a signal. The direction detecting means determines whether or not the data order is a direction intersecting one track or more from one track of the recording disk with the first data ID storing means and the second data ID. 5. The error correction circuit according to claim 4, wherein the detection is performed based on whether or not the values of the respective data IDs stored in the storage means are continuous with a predetermined value difference. When the data order is a direction intersecting one or more adjacent tracks from one track of the recording disk, the direction detecting means determines whether or not the direction is on the inner peripheral side. 6. The disk reproducing apparatus according to claim 5, wherein a difference between the values of the data IDs stored in the data ID storage means and the second data ID storage means is calculated, and the difference is detected based on whether the value is positive or negative. Error correction circuit. If the data order is a direction intersecting one or more adjacent tracks from one track of the recording disk, the direction detecting means determines the number of tracks intersecting the direction by the first data ID. 7. The disk reproducing apparatus according to claim 5, wherein a difference between the values of the data IDs stored in the storage means and the second data ID storage means is calculated, and the difference is detected based on an absolute value of the value. Error correction circuit.

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