JP2004021096A - Active matrix type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the power consumption of an active matrix type display device. <P>SOLUTION: A drain line driver 1 and a gate line driver 2 have a plurality of level shifters 3. Individual level shifters 3 are operated in time division. Since shift registers 9 constituting the scanners of both drivers are connected to some level shifter 3, operation of most of the shift registers can be stopped. Since the number of shift registers 9 connected to each level shifter 3 is small, a buffer which has been conventionally required is made unnecessary and the power which has been consumed by the buffer can be reduced. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an active matrix display device having a switching element for each pixel, and more particularly to a driving circuit arranged around a display area.
[0002]
[Prior art]
Currently used display devices can be broadly classified into a passive matrix type and an active matrix type. Among them, the active matrix type display device is a type of display device in which a switching element is provided for each pixel, and a voltage corresponding to the image data of the pixel is applied to each pixel (or a current is applied) to perform display. It is.
[0003]
2. Description of the Related Art A liquid crystal display (LCD) is a display device in which liquid crystal is sealed between opposing substrates, a voltage is applied to pixel electrodes formed for each pixel, and display is performed by changing the transmittance of the liquid crystal. Active matrix type LCDs have become mainstream especially for monitor applications.
[0004]
In addition, an electroluminescence (EL) display device is a display device that performs display by passing a current from a pixel electrode formed for each pixel to an EL element, and an active matrix EL display device has been put into practical use. Research is prosperous.
[0005]
In particular, in the case of a so-called low-temperature polysilicon TFT in which a semiconductor layer of a thin film transistor (TFT) used for a switching element is manufactured without using a high-temperature process, various peripheral circuits can be integrally formed on a glass substrate. Therefore, the number of driving ICs connected to the periphery can be reduced, and the manufacturing cost can be reduced. The low-temperature polysilicon TFT can be used for various active matrix display devices such as a plasma display and a field effect display device (FED) in addition to the LCD and EL display devices.
[0006]
FIG. 5 is a conceptual diagram showing a conventional active matrix type LCD. An external control circuit 200 is connected to an LCD panel 100 on which various circuits are arranged on a glass substrate.
[0007]
The external control circuit 200 supplies various control signals, video signals, power supply voltage VDD, and the like for operating the LCD panel 100 to the LCD panel 100. The external control circuit 200 is a normal CMOS circuit, and operates at a low voltage of, for example, 3V, and the output control signal also has an amplitude of 3V.
[0008]
The display area 10 and various peripheral circuits are arranged on the LCD panel 100. In the display area 10, a plurality of pixel electrodes 11 arranged in a matrix, a plurality of drain lines 12 extending in a column direction, and a plurality of gate lines 13 extending in a row direction are arranged. A selection transistor 14 is arranged corresponding to each intersection. The drain of the selection transistor 14 is connected to the drain line 12, the gate is connected to the gate line 13, and the source is connected to the pixel electrode 11. Although not shown, each of the pixel electrodes 11 is provided with a color filter of one of the primary colors of RGB to perform color display.
[0009]
On the side of the display area 10, a drain line driver 21 is arranged on the column side, and a gate line driver 22 is arranged on the row side. A potential conversion circuit 30 is connected between the drain line driver 21, the gate line driver 22, and the external control circuit 200.
[0010]
Next, the operation of the active matrix display device will be described. The gate line driver 22 sequentially selects a predetermined gate line 13 from the plurality of gate lines 13, applies a gate voltage VG, and turns on the selection transistor 14 connected to the gate line 13. The gate line driver 22 selects the first gate line 13 according to the vertical start signal VST, and sequentially switches to and selects the next gate line 13 according to the vertical clock VCK.
[0011]
The drain line driver 21 sequentially selects a predetermined drain line 12 from the plurality of drain lines 12, and supplies an RGB video signal to the pixel electrode 11 through the drain line 12 and the selection transistor 14. The drain line driver 21 selects one or a plurality of drain lines 12 at a time. The drain line driver 21 selects the first drain line 12 according to the horizontal start signal HST, and sequentially switches to and selects the next drain line 12 according to the horizontal clock HCK.
[0012]
The vertical clock VCK and the horizontal clock HCK are generated by boosting the low-voltage clocks VCKL and HCKL having an amplitude of 3 V output from the external control circuit 200 to, for example, 12 V by the potential conversion circuit 30. Since many pixel electrodes 11 are connected to one drain line 12 and one gate line 13, the operation cannot be performed at a low voltage of about 3V. Therefore, the control signal supplied from the external control circuit 200 is boosted to a higher voltage of 12V. This is a means necessary for realizing the operation speed as a display device by using a TFT. The potential conversion circuit 30 includes a level shifter 31 for increasing a voltage and a buffer 32 for increasing a current driving capability. The level shifter 31 and the buffer 32 are arranged for each control signal to be boosted.
[0013]
FIG. 6 is a circuit diagram showing the drain line driver 21. The drain line driver 21 has a scanner 23 and a plurality of RGB selection circuits 24. The scanner 23 includes a plurality of shift registers 25, and a horizontal clock HCK obtained by boosting the control signal HCKL supplied from the external control circuit 200 by the potential conversion circuit 30 is input to each of the shift registers 25. The RGB selection circuit 24 includes three drain line selection transistors 26 each having an output connected to the gate of the shift register 25. The drain of each drain line selection transistor 26 is connected to one of the data lines 33RGB. The source of each drain line selection transistor 26 is connected to the drain line 12.
[0014]
The horizontal start signal HST is input to the first-stage shift register 25a. When the HST is input, the output of the output terminal Q of the shift register 25a becomes high for one cycle of the horizontal clock HCK. By the output of the shift register 25a, 26Ra, 26Ga, and 26Ba of the drain line selection transistor 26 are turned on, and the video signals of the data lines 33R, G, and B are supplied to the drain lines 12Ra, 12Ga, and 12Ba, respectively. The output of the shift register 25a is simultaneously input to the second-stage shift register 25b, and the output of the shift register 25b goes high for one cycle of the next horizontal clock HCK, turning on the selection transistors 26Rb, Gb, and Bb and turning on the data line. A 33 RGB video signal is supplied to the drain lines 12Rb, 12Gb, and 12Bb. Then, the output of the shift register 25b turns on the next shift register 25c. Hereinafter, similarly, the shift register 25 sequentially becomes high to sequentially select the drain lines 12 and supply the video signals to all the pixels.
[0015]
After all the drain lines 12 for one row are selected, the vertical clock VCK has the next cycle, the gate line driver 22 supplies the gate voltage VG to the next gate line 13, and the horizontal start signal HST is input again. Then, the output of the shift register 25a becomes high. The gate line driver 22 is also composed of a scanner.
[0016]
[Problems to be solved by the invention]
2. Description of the Related Art In recent years, with the spread of mobile phones and portable information terminals, demands for lowering the power of display devices have been increasing.
[0017]
On the other hand, the horizontal clock HCK and the vertical clock VCK are supplied to and drive the shift registers 25 in all stages of the drain line driver 21 and the gate line driver 22, respectively. For this reason, the conventional active matrix type display device requires a large current driving capability and inevitably consumes a large amount of power. In particular, the power consumption of the buffer 32 installed to ensure current driving capability is large.
[0018]
Therefore, an object of the present invention is to provide an active matrix display device with lower power consumption.
[0019]
[Means for Solving the Problems]
The present invention has been made to solve the above problems, and has a plurality of pixel electrodes arranged in a matrix, a plurality of gate lines extending in a row direction, and a plurality of drains extending in a column direction. A plurality of switching elements for supplying a video signal of a drain line to a pixel electrode in accordance with a gate signal of the gate line, and a drain line for sequentially selecting a predetermined drain line from the plurality of drain lines and supplying a video signal A drain line driver and / or a gate line driver in an active matrix display device having a driver and at least one of a gate line driver for sequentially selecting a predetermined gate line from a plurality of gate lines and supplying a gate signal. Has a plurality of level shifters, and at least some of the plurality of level shifters are provided only in a part of one vertical period or one horizontal period. Was created, each level shifter is an active matrix display device that sequentially operates overlap timing with each other.
[0020]
Further, a plurality of pixel electrodes arranged in a matrix, a plurality of gate lines extending in the row direction, a plurality of drain lines extending in the column direction, A plurality of switching elements for supplying a video signal of the drain line to the pixel electrode; a drain line driver for sequentially selecting a predetermined drain line among the plurality of drain lines and supplying a video signal; In an active matrix display device having at least one of a gate line driver for sequentially selecting a gate line and supplying a gate signal, the drain line driver and / or the gate line driver include a plurality of stages of shift registers, And a plurality of level shifters arranged corresponding to each other. Power is supplied in accordance with the sum, an active matrix display device voltage boosted by the level shifter is supplied to the drain line or / and the gate line.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a conceptual diagram showing an active matrix display device of the present invention. The same components as those of the conventional LCD are denoted by the same reference numerals as those of the conventional LCD of FIG.
[0022]
The external control circuit 200 and the display area 10 of the LCD panel 100 are exactly the same as those in the related art.
[0023]
On the side of the display area 10, the drain line driver 1 is arranged on the column side, and the gate line driver 2 is arranged on the row side. The basic operations of the drain line driver 1 and the gate line driver 2 are the same as those in the related art. That is, the gate line driver 2 selects the first gate line 13 according to the vertical start signal VST, and sequentially switches to the next gate line 13 according to the vertical clock VCK to supply the gate voltage VG. The drain line driver 1 selects the first drain line 12 according to the horizontal start signal HST, and sequentially switches to the next drain line 12 according to the horizontal clock HCK to supply the video signal.
[0024]
The feature of this embodiment is that the drain line driver 1 and the gate line driver 2 have level shift circuits 4 and 5. Each of the level shift circuits 4 and 5 has a plurality of level shifters 3, and the second and subsequent level shifters operate only in a part of one vertical period or one horizontal period, and the timings of the respective level shifters overlap each other. Operate sequentially.
[0025]
Hereinafter, the drain line driver 1 will be described in more detail. FIG. 2 is a circuit diagram showing the drain line driver 1. The drain line driver 1 has a plurality of shift registers 9, a level shift circuit 4, and a plurality of RGB selection circuits 24. The level shift circuit 4 has a plurality of level shifters 3. A voltage supply circuit 8 is connected between the second and subsequent level shifters 3 and the power supply VDD connected thereto. The voltage supply circuit 8 includes an OR circuit (hereinafter referred to as an OR circuit) 6 and a switch 7 that is turned on / off by an output of the OR circuit 6. The level shifter 3 in the first stage is always on, and the supply of voltage to the level shifters 3 in the second and subsequent stages is turned on and off by the voltage supply circuit 8, and is turned on only for a certain period. Each of the level shifter 3, the voltage supply circuit 8, the shift register 9, the RGB selection circuit 24, and the like have the same configuration. However, when they are markedly distinguished, they are expressed as 3a, 3b, 3c, and the like.
[0026]
The output of the shift register 9 is input to the shift register 9 of the next stage to constitute a scanner. The low-voltage clock HCKL having an amplitude of 3 V supplied from the external control circuit 200 or its inverted clock * HCKL is input to the shift register 9. The shift register 9 switches and outputs one after another every half cycle of the clock HCKL. The output of the shift register 9 is boosted by the level shifter 3 and supplied to the RGB selection circuit 24 as a horizontal clock HCK. The RGB selection circuit 24 is exactly the same as the conventional RGB selection circuit shown in FIG. 6, and connects the data line 33 and the drain line 12 according to the horizontal clock HCK.
[0027]
The voltage supply circuit 8 has an OR circuit 6 to which the horizontal clock HCK of the preceding stage and the succeeding stage is supplied, and the switch 7 is turned on by the output of the OR circuit 6. When the switch 7 is turned on, the level shifter 3 is connected to the power supply VDD, and can output the horizontal clock HCK by boosting the low voltage clock HCKL.
[0028]
Next, the operation of the drain line driver 1 will be described. First, the horizontal start signal HST is input to the first-stage shift register 9a and the OR circuit 6a. The shift register 9a is set by the horizontal start signal HST. Next, when the low-voltage clock HCKL goes high, the first-stage shift register 9a outputs the clock HCKa, and the boosted horizontal clock HCKa is supplied to the first-stage RGB selection circuit 24a, and the data lines 33R, G, B And the drain lines 12Ra, 12Ga, and 12Ba are connected to each other, and a video signal is supplied to the first-stage drain lines 12Ra, 12Ga, and 12Ba. The first-stage horizontal clock HCKa is supplied to the second-stage OR circuit 6b at the same time, the switch 7b is turned on by the output of the OR circuit 6b, and the second-stage level shifter 3b is connected to the power supply VDD. Thus, the second-stage level shifter 3b starts operating during the first-stage operation period, and stands by.
[0029]
Next, when the low voltage clock HCKL goes low, that is, when the inverted clock * HCKL goes high, the first-stage shift register 9a is reset, and the level shifter 3a stops outputting. Then, the shift register 9b outputs the voltage, the voltage is boosted by the already operated level shifter 3b, the second-stage clock HCKb is output, and the video signal is supplied to the second-stage drain lines 12Rb, 12Gb, and 12Bb. The clock HCKb is supplied to the third-stage OR circuit 6c at the same time, and the third-stage level shifter 3c is connected to the power supply VDD to be in a standby state.
[0030]
Next, when the low voltage clock HCKL goes high, the second-stage shift register 9b is reset, and the level shifter 3b stops outputting. Then, the shift register 9c outputs the signal, the voltage is boosted by the already operated level shifter 3c, the third-stage clock HCKc is output, and the video signal is supplied to the third-stage drain lines 12Rc, 12Gc, and 12Bc. The clock HCKc is simultaneously supplied to the fourth-stage OR circuit 6d, and the third-stage level shifter 3d is connected to the power supply VDD.
[0031]
Next, when the low-voltage clock HCKL goes low, the third-stage shift register 9c is reset, and the level shifter 3c stops outputting. As a result, there is no input to the second-stage OR circuit 6b, the switch 7b is turned off, the level shifter 3b is disconnected from the power supply VDD, and the operation stops. Then, the shift register 9c outputs the signal, the voltage is boosted by the already operated level shifter 3c, the third-stage clock HCKc is output, and the video signal is supplied to the third-stage drain lines 12Rc, 12Gc, and 12Bc. The clock HCKc is simultaneously supplied to the fourth-stage OR circuit 6d, and the third-stage level shifter 3d is connected to the power supply VDD.
[0032]
Thereafter, similarly, the n-stage level shifter 3 is operated by the clock HCK output from the (n-1) -th level shifter 3, and the shift register 9 connected thereto outputs the video signal to the drain line 12 to supply the video signal to the (n + 1) -th stage. When the output of the level shifter 3 is stopped, the switch 8 of the n-stage level shifter 3 is turned off. By repeatedly performing this operation, the drain lines 12 are sequentially selected, and video signals are supplied to all pixels.
[0033]
When all the drain lines 12 for one row are selected, the vertical clock VCK has the next cycle, the gate line driver 2 supplies the gate voltage VG to the next gate line 13, and the horizontal start signal HST is input again. , The output of the shift register 9a goes high. Like the drain line driver 1, the gate line driver 2 has a configuration including a plurality of level shifters 3 and a shift register 9.
[0034]
FIG. 3 shows an output timing chart of the present embodiment. The clock HCKa of the first stage goes high one unit time later than the period in which the horizontal start signal HST goes high, and the clock HCK goes high sequentially with a delay of one unit time. For example, the second-stage level shifter 3b operates during a period indicated by LS3b active in the drawing, that is, a period from when the output of the previous-stage level shifter 3a goes high to when the third-stage output clock HCKc goes low. Similarly, the level shifter 3 operates sequentially for one unit time before and after one horizontal period, that is, for a total of two unit times longer, and overlaps with the operation of the level shifters 3 in the preceding and succeeding stages, and operates during the other periods. To stop. In the case of a display device having one million pixels, several hundred levels of the level shifters 3 will be arranged, and only a part of the level shifters 3 which are in operation will be in operation. Therefore, the power consumption can be reduced as compared with the conventional case where the level shifter 31 corresponding to the boosting of all stages is operated.
[0035]
In addition, since the output of the level shifter 3 is supplied to only one RGB selection circuit 24, not so large current driving capability is required, and the buffer 32 need not be provided in the present embodiment. Therefore, the power consumption of the buffer 32 can be reduced.
[0036]
In particular, since the respective level shifters operate sequentially with their timings overlapped with each other, the level shifter 3 only needs to start operating one unit time after being connected to the power supply VDD. Can be. The level shifter 3 is cut off from the power supply VDD one unit time after the end of the operation period, so that the operation can be surely ended.
[0037]
Further, since the shift register 9 operates with the voltage of 3 V before boosting, power consumption in the shift register 9 can be reduced as compared with the case where the shift register 9 operates with the boosted clock as in the related art.
[0038]
Next, a second embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing the drain line driver 1 of the present embodiment. The present embodiment is different from the first embodiment in that the output of the level shifter 3 is supplied to its own OR circuit 6. In this embodiment, each level shifter 3 is connected to the power supply VDD by the output of the preceding level shifter 3, and is shut off from the power supply VDD when its own output stops. Therefore, as compared with the first embodiment, the time during which the power supply voltage is supplied to each level shifter 3 is further shortened, and the power consumption can be further reduced. However, in the present embodiment, since the power is shut off by its own output, the shut-off operation may become unstable.
[0039]
In the above-described embodiment, the connection to the power supply VDD is controlled by the output of the preceding stage and the subsequent stage. However, the connection may be controlled by the output of the level shifter of two or more stages. If the output is controlled by an earlier output, the period from the start of the operation of the level shifter to the output becomes longer, and the operation can be performed more stably. However, since the period during which the level shifter operates is correspondingly longer, power consumption is increased.
[0040]
Although the above-described embodiment has been described with the drain line driver 1, the embodiment can be applied to the gate line driver 2 in exactly the same manner. Since the drain line driver needs to be operated at a higher speed than the gate line driver, the power consumption caused by the operation of many shift registers is greatly increased. Therefore, the present invention is more effective when applied to a drain line driver than to a gate line driver. Compared with this, the effect of arranging the level shift circuit in the gate line driver is small. Of course, the gate line driver has the effect of arranging a plurality of level shifters, but the number of elements naturally increases as compared with the conventional arrangement of a potential conversion circuit using one level shifter and a buffer. An increase in the number of elements may lead to a decrease in yield. Therefore, a level shift circuit having a plurality of level shifters is arranged in the drain line driver having a greater effect, and the gate line driver is connected to the conventional potential conversion circuit including one level shifter and buffer described in the related art. Good to do.
[0041]
Each of the above embodiments has been described by exemplifying an LCD. However, the present invention is not limited to this, and can be used for various active matrix display devices such as an EL display device, a plasma display, and an FED.
[0042]
【The invention's effect】
As described above, according to the present invention, since a level shift circuit having a plurality of level shifters operating in a time-sharing manner with overlapping timings is provided, a circuit portion in which a drain line driver and / or a gate line driver does not operate is provided. Operation can be stopped, and power consumption can be reduced.
[0043]
In particular, among a plurality of shift registers constituting the drain line driver and / or the gate line driver, only the shift register connected to one scanner is operated, and the operation of the other shift registers is stopped. The operation of the register can be stopped, and power consumption can be significantly reduced.
[0044]
Furthermore, if the number of shift registers corresponding to one level shifter is 15 or less, the current drive capability of the level shifter does not become insufficient, so that there is no need to dispose a buffer and the power consumed by the buffer can be reduced. it can.
[0045]
Further, since the drain line driver needs to operate at a higher speed than the gate line driver, a more remarkable effect can be obtained by connecting a level shift circuit having a plurality of level shifters operating in a time-division manner to the drain line driver. Can be.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram of an active matrix display device of the present invention.
FIG. 2 is a circuit diagram showing a level shift circuit and a drain line driver according to the first embodiment of the present invention.
FIG. 3 is a timing chart according to the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing a level shift circuit and a drain line driver according to a second embodiment of the present invention.
FIG. 5 is a conceptual diagram of a conventional active matrix type display device.
FIG. 6 is a circuit diagram showing a conventional bell shifter and drain line driver.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Drain line driver 2 Gate line driver 3 Level shifter 4, 5 Level shift circuit 7 Shift register 10 Display area 12 Drain line 13 Gate line

Claims (2)

A plurality of pixel electrodes arranged in a matrix,
A plurality of gate lines extending in the row direction and arranged;
A plurality of drain lines extending in the column direction,
A plurality of switching elements for supplying a video signal of the drain line to the pixel electrode according to a gate signal of the gate line;
A drain line driver for sequentially selecting a predetermined drain line from among the plurality of drain lines and supplying a video signal, and a gate line driver for sequentially selecting a predetermined gate line from the plurality of gate lines and supplying a gate signal At least one of
In an active matrix display device having
The drain line driver and / or the gate line driver have a plurality of level shifters, and at least a part of the plurality of level shifters operates only in a part of one vertical period or one horizontal period. An active matrix display device, wherein the level shifters operate sequentially with timing overlapping each other. A plurality of pixel electrodes arranged in a matrix,
A plurality of gate lines extending in the row direction and arranged;
A plurality of drain lines extending in the column direction,
A plurality of switching elements for supplying a video signal of the drain line to the pixel electrode according to a gate signal of the gate line;
A drain line driver for sequentially selecting a predetermined drain line from among the plurality of drain lines and supplying a video signal, and a gate line driver for sequentially selecting a predetermined gate line from the plurality of gate lines and supplying a gate signal At least one of
In an active matrix display device having
The drain line driver and / or the gate line driver include a plurality of stages of shift registers and a plurality of stages of level shifters arranged corresponding to the respective shift registers.
The level shifter is supplied with power in accordance with a logical sum of outputs of the preceding and subsequent level shifters, and a voltage boosted by the level shifter is supplied to the drain line and / or the gate line. Matrix display device.

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