JP2004015409A - Semiconductor integrated circuit for communication and wireless communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for communication configuring a wireless communication system of a dual mode or over including the W-CDMA system wherein a step amplifier is employed for a gain control amplifier for amplifying a received signal, so as to make current consumption almost constant even when the gain is changed in response to the strength of the received signal, so as to extend the lifetime of a battery, that is, a standby time and a communicating time by one charging. <P>SOLUTION: The step amplifiers are employed for the gain control amplifiers (GCA, 241A, 241b, 243a, 243b) for amplifying the received signal, two pairs of the step amplifiers are provided and controlled for alternate use, on the occurrence of gain switching, the step amplifier not in use is selected to cancel offset, and the amplifier receiving the received signal is switched. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a communication semiconductor integrated circuit incorporating a variable gain signal amplifier circuit and a high gain amplifier circuit for amplifying a received signal in a wireless communication device, and a wireless communication device such as a mobile phone incorporating the communication semiconductor integrated circuit incorporating the communication semiconductor integrated circuit. About effective technology to apply.
[0002]
[Prior art]
2. Description of the Related Art In a wireless communication device (mobile communication device) such as a mobile phone or a mobile phone, a low-pass signal is amplified to a predetermined level that can be processed by a baseband circuit while removing noise and unnecessary frequency signals. -A filter and a gain control amplifier are used.
By the way, in a conventional GSM (Global System for Mobile Communication) or DCS (Digital Cellular System) type mobile phone, a gain control amplifier is generally a step-type amplifier that can switch the gain stepwise according to the level of a received signal. Is used. On the other hand, in a W-CDMA (Wideband Code Division Multiple Access) type mobile phone, a linear amplifier capable of linearly controlling a gain has been proposed as an amplifier for amplifying a received signal.
[0003]
[Problems to be solved by the invention]
When comparing the step-type amplifier and the linear-type amplifier, the power consumption of the linear-type amplifier varies greatly because the gain is changed by the current, whereas the current consumption of the step-type amplifier does not change much even if the gain is switched. A battery-powered system has the advantage of reducing battery consumption. Further, the linear amplifier has a disadvantage that the control range of the gain is narrower than that of the step amplifier, and in a region where the gain is high, the amplifier is saturated and the signal is distorted.
The reason that a linear amplifier is used in a W-CDMA mobile phone in spite of this problem is that a step-type amplifier needs to cancel the input DC offset of the amplifier every time the gain is switched. A major reason is that the CDMA system requires a continuous reception operation, and thus does not have time to cancel the DC offset. On the other hand, in a GSM or DCS mobile phone, a transmission mode and a reception mode are switched in a time unit (eg, 577 μsec) called a time slot, and a DC offset cancel operation is performed when switching between transmission and reception. Therefore, a step-type amplifier can be used.
[0004]
The inventors of the present invention have studied whether an amplifier for amplifying a received signal can be shared by both types in developing a dual-mode mobile phone of the W-CDMA system and the GSM system. Proved difficult to do. The present invention was born in the process of studying the use of a common receiving amplifier. As a technique similar to the invention of the present application, there is an invention disclosed in Japanese Patent Application Laid-Open No. 9-64666, but the purpose and conditions for switching the amplifier are different between the prior invention and the invention of the present application.
[0005]
An object of the present invention is to enable a step-type amplifier to be used as a gain control amplifier for amplifying a received signal in a communication semiconductor integrated circuit constituting a wireless communication system of dual mode or higher including a W-CDMA system. Thus, even if the gain is changed according to the strength of the received signal, the current consumption is made substantially constant even when the gain is changed, so that the mobile phone or the like using this can prolong the battery life, that is, the reception standby time and talk time by one charge. It is in.
Another object of the present invention is to provide a communication semiconductor integrated circuit capable of expanding a gain control range of a gain control amplifier for amplifying a received signal and improving a CN ratio, and a wireless communication system using the same. It is in.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0006]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.
That is, the first invention of the present application is a step-type gain control amplifier for amplifying a received signal in a communication semiconductor integrated circuit constituting a wireless communication system that performs continuous reception while changing a gain as in the W-CDMA system. Using an amplifier, two sets of the step-type amplifiers are controlled so that they are used alternately, and when a gain change occurs, the gain is switched by an unused step-type amplifier and offset cancellation is performed. The amplifier is configured to switch an amplifier to which a reception signal is input.
[0007]
According to the above-described means, since the step-type amplifier is used as the gain control amplifier, the current consumption can be made substantially constant even if the gain is changed according to the strength of the received signal, and two sets of step-type amplifiers are provided. In this case, the input of the received signal is switched after the gain is switched and the offset is canceled, so that it is possible to avoid the loss of the received data due to the offset canceling operation even when the reception is continuous.
[0008]
A second invention of the present application is a gain for amplifying a received signal in a communication semiconductor integrated circuit configuring a dual mode or higher wireless communication system including a mode for performing continuous reception while changing a gain, such as a W-CDMA system. A step-type amplifier is used as the control amplifier, and a plurality of filter circuits for removing unnecessary waves and noise are provided according to the frequency band of each mode, and the filter circuits are switched according to the selected mode, and gain switching and offset cancellation are performed. They are configured to be performed almost simultaneously. Here, the mode means a communication system having different multiplexing systems and modulation systems, such as the GSM system, the DCS system, and the W-CDMA system. Since the GSM system and the DCS system have the same multiplexing system and modulation system and differ only in the frequency band, the same mode is used in this specification.
[0009]
According to the above-described means, since the step-type amplifier is used as the gain control amplifier, the current consumption can be made substantially constant even when the gain is changed in accordance with the strength of the received signal. In the mode having the function of restoring the received data, the switching of the gain and the canceling of the offset during the reception allow the received data to be repaired even if it is lost, which hinders the reception operation. I can't.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Example 1)
FIG. 1 shows an example of the configuration of a receiving system circuit of a mobile phone according to a first embodiment, to which the present invention is preferably applied. Although not particularly limited, this embodiment is a preferred embodiment applied to a communication system such as a W-CDMA system which receives received signals continuously.
In FIG. 1, reference numeral 100 denotes an antenna for transmitting and receiving signal radio waves, 110 denotes a duplexer (divider) formed of a filter for separating a transmission signal and a reception signal, and 120 denotes a reception signal separated by the duplexer 110 without passing through an intermediate frequency. A direct conversion type receiving circuit for demodulating, amplifying and converting the signal to a baseband signal, and an oscillation circuit 130 for generating a high frequency oscillation signal φRF such as 4220 to 4340 MHz required for frequency conversion (down-conversion) of the received signal. Circuit.
[0011]
The receiving system circuit 120 of this embodiment divides the frequency of the oscillation signal φRF generated by the low noise amplifier (LNA) 121 and the oscillation circuit 130 and amplifies the signal received from the antenna 100 and has a phase of 90 °. A frequency dividing phase circuit 122 for generating two shifted quadrature signals, and a baseband signal I, Q of the audio frequency directly synthesized by synthesizing the received signal amplified by the LNA 121 and the signal divided by the frequency dividing circuit 122. (MIX) 123a and 123b for down-converting and demodulating the signal, and two sets of high-gain amplifiers having amplifiers (GCA) and low-pass filters (LPF) capable of controlling the gain and amplifying the demodulated signal to a predetermined level. 124a and 124b and demodulated signals from mixers (MIX) 123a and 123b are selectively input to either of the high gain amplifiers 124a or 124b. And a switch SWa2 and a switch SWb2 for controlling the operation of the switching circuit 125 and supplying the output of the high-gain amplifier on the selected side to a baseband circuit (not shown). The switching circuit 126 includes a switching circuit 126 and a control circuit 127 that controls switching of the switching circuits 125 and 126.
[0012]
The high gain amplifier (HGA-A) 124a includes a gain control amplifier circuit 241a for amplifying an I signal, a low pass filter 242a for band limitation, a gain control amplifier circuit 243a for a Q signal, and a low pass filter 244a. I have. Similarly to the high gain amplifier (HGA-B) 124a, the high gain amplifying section (HGA-B) 124b includes a gain control amplifier circuit 241b and a low-pass filter 242b for the I signal and a gain control amplifier circuit 243b and a low-pass filter 244b for the Q signal. ing. Each of the low-pass filters 244a and 242b is composed of a resistor, a capacitor, and the like. In a W-CDMA mobile phone, a band is set so as to pass a signal in a 2 MHz band.
[0013]
Although not shown in FIG. 1, a SAW filter for removing unnecessary waves from a signal received from the antenna 100 may be provided in a stage preceding the low noise amplifier (LNA) 121 in some cases. Although not particularly limited, in this embodiment, the reception system circuit 120, the oscillation circuit 130, and the transmission system circuit (not shown) are made of single crystal silicon except for external components such as a filter capacitor and a crystal unit. It is formed as a semiconductor integrated circuit on a single semiconductor substrate.
[0014]
FIG. 2 shows a more detailed configuration example of the high gain amplifiers 124a and 124b in FIG. As shown in FIG. 2, the high gain amplifying sections 124a and 124b include a plurality (for example, three) of gain control amplifiers GCA1, GCA2, and GCA3 and low-pass filters LPF1, LPF2, and LPF3 alternately arranged in series. It has a configuration in which an amplifier AMP having a fixed gain is connected to the last stage.
[0015]
The switches SW1, SW2, and SW3 for short-circuiting the input terminals when the offsets of the gain control amplifiers GCA1, GCA2, and GCA3 are cancelled, and the output potential difference between the gain control amplifiers GCA1, GCA2, and GCA3 corresponding to the respective gain control amplifiers. The DC offset of the output is set to "0" with respect to the differential input of the AD conversion circuits ADC1, ADC2, and ADC3 that convert to signals and the corresponding gain control amplifiers GCA1, GCA2, and GCA3 based on the comparison result by the AD conversion circuit. DA conversion circuits DAC1, DAC2, and DAC3 that provide such an input offset voltage are provided. The control circuit for controlling the AD conversion circuits ADC1 to ADC3 and the DA conversion circuits DAC1 to DAC3 to perform the offset canceling operation (calibration) may be received as a dedicated control circuit, but in this embodiment, the receiving system is used. The control circuit 127 that controls the entire circuit 120 is also configured to be used in common.
[0016]
In the calibration, the control circuit 127 first performs DC offset calibration of the first-stage gain control amplifier GCA1 based on a command (command) from the baseband circuit. After the completion of the step, calibration is performed in order of the third step and one step at a time.
[0017]
Also, although not particularly limited, the DC offset calibration of each stage is performed by comparing the differential outputs of the amplifiers GCA1, GCA2, and GCA3 by the AD conversion circuits ADC1, ADC2, and ADC3, and by the amplifiers by the DA conversion circuits DAC1, DAC2, and DAC3. A successive approximation method in which voltage application to GCA1, GCA2, and GCA3 is successively repeated is employed. The D / A conversion circuits DAC1, DAC2, and DAC3 are, for example, n types (n is a positive integer, for example, a value such as 6) having current values i, 2i, 4i, 8i,. By synthesizing the weight current in accordance with the n-bit input signal and converting it into a voltage, it is possible to select and output one from 2n voltage values.
[0018]
Then, based on the timing signal from the control circuit 127, the amplifier outputs of the AD conversion circuits ADC1, ADC2, and ADC3 are compared with the reference voltage, and the difference is input to the differential amplifier input by the DA conversion circuits DAC1, DAC2, and DAC3 according to the AD conversion result. Is repeated six times, for example, so that the calibration of the gain control amplifiers GCA1, GCA2, and GCA3 at each stage is executed. When the calibration is completed, the final DA input value necessary for setting the DC offset of each amplifier to “0” is stored in the register REG provided in the DA conversion circuits DAC1, DAC2, and DAC3, and the next calibration is performed. It is controlled so that the state is maintained until the time of the application.
[0019]
The applicant of the present invention has already filed several applications for the above-described calibration method of the gain control amplifier using the AD conversion circuit and the DA conversion circuit, and the calibration method itself is not directly related to the present invention. Therefore, illustration and description of a detailed circuit are omitted.
[0020]
FIGS. 3 and 4 show specific circuit examples of the step-type amplifier used as the gain control amplifiers GCA1, GCA2, and GCA3. In the gain control amplifier shown in FIG. 3, a plurality of resistors Re1, Re2,... Ren having different resistance values are provided in parallel between the emitter terminals of the pair of differential bipolar transistors Q1 and Q2. The switches SW11, SW12; SW21, SW22,..., SWn1 and SWn2 can be connected / disconnected. The resistors Re1, Re2,..., Ren may have the same resistance value. However, the resistors Re1, Re2,..., Ren may be formed so as to have a weight of, for example, n times 2, so that the gain varies depending on the combination of switches to be turned on. Can be.
[0021]
The gain control amplifier of FIG. 3 operates as an amplifier having a smaller gain as the value of the resistor connected between the emitter terminals of the differential bipolar transistors Q1 and Q2 is larger, and an amplifier having a larger gain as the value of the connected resistor is smaller. Works as Rc1 and Rc2 are collector resistors, and CI1 and CI2 are constant current sources. The switches SW11, SW12; SW21, SW22,..., SWn1, SWn2 are turned on and off by the control circuit 127 based on a command from the baseband circuit.
[0022]
The gain control amplifier shown in FIG. 4 has a plurality of pairs of differential bipolar transistors Q11, Q12; Q21, Q22,. Are connected to different resistors Re1, Re2,... Ren, and the emitters of transistors Q11, Q12; Q21, Q22... Qn1, Qn2 are connected through switches SW11, SW12; SW21, SW22. It is configured to be connectable / separable from CI1CI2.
[0023]
The gain control amplifier of FIG. 4 operates as an amplifier having a smaller gain as the value of the resistor connected between the emitter terminals of the bipolar transistor connected to the switch turned on, that is, the constant current sources CI1 and CI2, is reduced. Operate as an amplifier having a higher gain as the value of the resistor connected between the emitter terminals of the amplifiers is smaller. Rc1 and Rc2 are common collector resistors, and CI1 and CI2 are constant current sources. The switches SW11, SW12; SW21, SW22,..., SWn1, SWn2 are turned on and off by the control circuit 127 based on a command from the baseband circuit.
[0024]
Although not particularly limited, the baseband circuit and the control circuit 127 of the reception system circuit 120 are connected by, for example, a serial bus including three signal lines. On the other hand, a command code DATA, a clock CLK for providing the latch timing of the command, and an enable signal EN indicating that the data is valid are supplied, and the control circuit 127 is supplied at that time while the enable signal EN is at the valid level. The command code DATA is fetched in synchronization with the clock CLK, and the operation of the receiving circuit 120 is controlled based on the fetched command.
[0025]
FIG. 5 shows a specific circuit example of a step-type amplifier used as the gain control amplifiers GCA1, GCA2, and GCA3, and a DAC for calibration.
In FIG. 5, the transistors Qn1 and Qn2 are the transistors Q11 and Q12; Q21, Q22... Qn1 and Qn2 of the gain control amplifier GCA of FIG. 4, and the emitter resistance Re is the emitter resistance Re1, Re2. Ren is shown in a simplified manner, and the portion with reference numeral DACb is omitted because it is a circuit having the same configuration as the DACa portion. The DACa circuit and the DACb circuit in FIG. 5 function as one DA conversion circuit. In this embodiment, the current flowing through the transistors Q31, Q32, Q33,... Constituting the circuits of DACa and DACb is adjusted so that the potential difference between the outputs OUT1 and OUT2 becomes 0 when the inputs IN1 and IN2 are short-circuited. The value at that time is held in the register REG. Next, the timing of the switching of the gain and the timing of the offset cancel operation in the W-CDMA receiving system circuit of the present embodiment will be described with reference to FIG.
[0026]
FIG. 6 shows an example of timing control when the gain G in the high gain amplifying sections 124a and 124b changes in three stages, such as G1-G2-G3, according to the level of the received signal.
When the high gain amplifying unit 124a is amplifying the received signal with the gain G1 (the high gain amplifying unit 124b is inactive), the command CMD1 for switching the gain to G2 from the baseband circuit is supplied to the receiving system circuit 120. Then, a control signal (switching signal of the emitter resistance) for giving the total gain of the gain control amplifiers GCA1, GCA2, and GCA3 to G2 is given from the control circuit 127 to the high gain amplifying section 124b, and the switches SW11 and SW12 are provided. SW21, SW22 ... SWn1 and SWn2 are switched to change the gain (timing t1 in FIG. 6).
[0027]
Subsequently, when the command CMD2 for canceling the DC offset is supplied from the baseband circuit, the control circuit 127 controls the high gain amplifier 124b to execute the calibration of the gain control amplifiers GCA1, GCA2, and GCA3. A signal (control signal for an AD conversion circuit or the like) is supplied, and offset cancellation is performed (timing t2 in FIG. 6).
Thereafter, when a command CMD3 for switching the amplifier is supplied from the baseband circuit, a control signal (switch signal for switches SWa1, SWb1, SWa2, and SWb2) for switching the amplifier is sent from the control circuit 127 to the switching circuits 125 and 126. The received signals demodulated by the mixers 123a and 123b are supplied to the high gain amplifier 124a instead of the high gain amplifier 124a (timing t3 in FIG. 6).
[0028]
Then, when a command CMD4 for switching the gain from G2 to G3 is supplied from the baseband circuit to the reception system circuit 120, the control circuit 127 sends the gain control amplifiers GCA1, GCA2, and GCA3 to the high gain amplifying unit 124a. , A control signal (switching signal of the emitter resistance) for making the total gain G3 is given, and the states of switches SW11, SW12; SW21, SW22,... SWn1, SWn2 are switched to change the gain (FIG. 6). Timing t4).
[0029]
Subsequently, when the command CMD5 for canceling the DC offset is supplied from the baseband circuit, the control circuit 127 controls the high gain amplifier 124a to execute the calibration of the gain control amplifiers GCA1, GCA2, and GCA3. A signal (control signal for an AD conversion circuit or the like) is supplied, and offset cancellation is performed (timing t5 in FIG. 6).
Thereafter, when a command CMD6 for switching the amplifier is supplied from the baseband circuit, a control signal (switch signal for switches SWa1, SWb1, SWa2, SWb2) for switching the amplifier is sent from the control circuit 127 to the switching circuits 125 and 126. The received signals demodulated by the mixers 123a and 123b are supplied to the high gain amplifier 124b instead of the high gain amplifier 124b (timing t6 in FIG. 6).
[0030]
As described above, the case where the command is supplied three times from the baseband circuit to the receiving system circuit 120 when the gain is switched has been described. However, the control circuit 127 of the receiving system circuit 120 may have a timer circuit. As shown in FIG. 7, when a gain switching command CMD11 is supplied from the baseband circuit to the receiving system circuit 120, the receiving system circuit 120 automatically performs gain switching and calibration (timing t11). After that, when the amplifier switching command CMD12 is supplied from the baseband circuit to the receiving system circuit 120, the switching of the amplifiers by switching the switching circuits 125 and 126 (timing t12) can be performed.
[0031]
Further, when the gain is switched, the gain of the gain control amplifiers GCA1, GCA2, and GCA3 is switched by a first command supplied from the baseband circuit to the reception system circuit 120, and the calibration and switching circuit 125 is switched by the second command. , 126, and the gain control amplifiers GCA1, GCA2, and GCA3 are controlled by a single command supplied from the baseband circuit to the reception system circuit 120 when the gain is switched. The switching of the gain, the calibration, and the switching of the amplifier by the switching circuits 125 and 126 can be performed continuously.
[0032]
(Example 2)
FIG. 8 shows a configuration example of a receiving system circuit of a mobile phone according to a second embodiment to which the present invention is preferably applied. Although not particularly limited, this embodiment is a preferred embodiment applied to a dual-mode communication system capable of W-CDMA communication, GSM and DCS communication. 8, the same circuit blocks as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.
[0033]
In this embodiment, in order to enable dual-mode communication, a transmission / reception switch 140 for GSM and DCS is provided in addition to a duplexer (demultiplexer) 110 for separating transmission / reception signals of W-CDMA. ing. The reason why the transmission / reception changeover switch 140 is used for GSM and DCS signals is that transmission and reception are performed in a time-division manner with a time difference in the GSM and DCS methods, and the switches are cheaper. is there. The reason why a duplexer is used for signal separation in the W-CDMA system is that transmission and reception are simultaneously performed with signals having different frequencies in the W-CDMA system.
[0034]
The oscillation circuit 130 generates an oscillation signal φRF having a frequency such as 4220 to 4340 MHz when transmitting and receiving the W-CDMA system, and an oscillation signal φRF having a frequency such as 3700 to 3840 MHz when transmitting and receiving the GSM system. Further, at the time of transmission / reception of the DCS method, control is performed so as to generate an oscillation signal φRF having a frequency such as 3610 to 3760 MHz.
The receiving circuit 120 includes a low-noise amplifier (LNA) 121 for a W-CDMA reception signal and mixers 123a and 123b, as well as a low-noise amplifier (LNA) 128 for a GSM and DCS reception signal. , Mixers 129a and 129b are provided. The switching circuit 125 includes signal switching switches SWc1 and SWc2 for switching between a W-CDMA reception signal and a GSM or DCS reception signal, in addition to the amplifier switching switches SWa1 and SWb1. Further, in addition to low-pass filters 242b and 244b for W-CDMA reception signals, low-pass filters 242c and 244c for GSM and DCS reception signals and a switch SWc3 for filter switching are provided in high-gain amplification section 124b. , SWc4, SWc5, and SWc6. Other configurations are almost the same as those of the first embodiment shown in FIG.
[0035]
The state of each switch shown in FIG. 8 is a state when amplifying the GSM and DCS received signals. The GSM or DCS reception signals I and Q amplified by the LNA 128 and down-converted by the mixers 129a and 129b are supplied to the gain control amplifiers 241b and 243b via the switches SWc1 and SWc2 and SWa1 and SWb1 and amplified, and are amplified by the switch SWc3. , And SWc5, pass through the low-pass filters 242c and 244c, and are supplied from the switches SWc4 and SWc6 to the baseband circuit via the switching circuit 126. During the GSM and DCS reception operations, all switches are fixed and no switching is performed.
[0036]
The switches SWc1 and SWc2 and the switches SWc3, SWc4, SWc5, and SWc6 are configured to be controlled in conjunction with each other. When amplifying a W-CDMA reception signal (hereinafter, referred to as a W-CDMA mode), FIG. 8 is switched to the opposite side. Further, the switches SWa1 and SWb1 and the switches SWa2 and SWb2 are interlocked with each other and are controlled in the same manner as in the embodiment of FIG. That is, when the gain of the gain control amplifier is changed in the W-CDMA mode, the switches SWa1, SWb1 and SWa2, SWb2 are switched, and the signals from the mixers 123a, 123b are sent to the gain control amplifiers 241a, 243a or 241b, 243b. It is controlled so as to supply them alternately.
[0037]
FIG. 8 shows an embodiment in which low-pass filters 242b and 242c and 244b and 244c having different characteristics are prepared and switched by switches SWC3, SWc4, SWc5 and SWc6. As shown in FIG. 9, a received signal of W-CDMA or a received signal of GSM or DCS may be processed by changing characteristics by using some elements (capacitances) in common.
[0038]
In FIG. 9, (A) shows an example of a primary filter, in which a series on / off switch S1 and a capacitor C2 are connected in parallel with a capacitor C1 of a filter including a resistor R1 and a capacitor C1. . FIG. 9B shows an example of a secondary filter having a bipolar transistor Q0 and a constant current source CI0 connected to its emitter. Resistors R1 and R2 are connected in series between the input terminal and the base of the transistor Q0, and a capacitor C1 is connected between the base of Q0 and the ground point, and a series of on / off switches are connected in parallel with the capacitor C1. The switch S1 and the capacitor C2 are connected, a capacitor C3 is provided between a connection node of the resistors R1 and R2 and an output terminal (emitter of Q0), and an on / off switch S2-capacitor C4- Switch S3 is connected. In any of the filters, the cutoff frequency of the filter is changed by turning on or off the switch S1 or S1 to S3.
[0039]
FIG. 10 shows the operation timing of the variable gain amplifier when the strength of the received signal changes in the receiving system circuit of the second embodiment. In FIG. 10, (A) shows a change in received signal strength, (B) and (C) show reception operation timings in the GSM or DCS mode, and (D) to (F) show reception operation timings in the W-CDMA mode. Show. In FIG. 10, a hatched portion indicates a period during which a gain switching operation and a DC offset canceling (calibration) operation are performed. As shown in FIGS. 10B and 10C, in the GSM or DCS mode, the receiving operation is performed intermittently, so that the calibration can be performed without any trouble immediately before each receiving operation. In FIGS. 10B and 10C, “Rx” means a receiving operation, and “Mon” means a monitoring operation for detecting the strength of a received signal.
[0040]
On the other hand, as can be seen from FIG. 10 (D), continuous reception is performed in the W-CDMA mode. Therefore, as shown in FIGS. 10 (E) and (F), the periods T1 and T3 where the strength of the received signal is constant. In the above, one of the high gain amplifiers (HGA-A or HGA-B) operates at a constant gain GainA, GainC, and during the period T2 in which the strength of the received signal is changing, the high gain amplification on the A side and the B side is performed. The units (HGA-A and HGA-B) are operated alternately. Then, just before the switching of the amplifier, switching of the gain and calibration are performed.
FIG. 11 shows an example of the timing of the receiving operation during one frame period in the GSM or DCS mode in the receiving circuit of the second embodiment. In FIG. 11, "Tx" means a transmission operation.
[0041]
As shown in FIG. 11B, when the command CMD1 for switching the gain from the baseband circuit is supplied to the receiving system circuit 120, the control circuit 127 controls the high gain amplifying section (HGA-B) 124b for gain control. A control signal (switching signal of the emitter resistance in FIG. 3) for giving the total gain of the amplifiers GCA1, GCA2 and GCA3 to G2 is given, and the state of the switches SW11 and SW12; SW21, SW22... SWn1 and SWn2 is switched. Thus, the gain is changed (timing t1).
[0042]
Subsequently, when the command CMD2 for canceling the DC offset is supplied from the baseband circuit, the control circuit 127 calibrates the gain control amplifiers GCA1, GCA2, and GCA3 to the high gain amplifier (HGA-B) 124b. A control signal to be executed (a control signal of an AD conversion circuit or the like) is provided, and the offset is canceled (timing t2). Thereafter, the amplification of the received signal by the high gain amplifier (HGA-B) 124b is started (timing t3).
[0043]
The control timing in the GSM or DCS mode is not limited to the above, and the gain switching command CMD11 is supplied from the baseband circuit to the reception circuit 120 as shown in FIG. Then, the switching of the gain and the calibration (timing t11) are automatically performed on the side of the reception system circuit 120 as shown in FIG. 11 (E), and thereafter the amplification of the reception signal by the high gain amplifier (HGA-B) 124b. Is started (timing t12).
[0044]
FIG. 12 shows an example of a system configuration of the entire mobile phone to which the above embodiment is applied. As shown in FIG. 12, the receiving system circuit 120 is configured as a semiconductor integrated circuit (hereinafter, referred to as RF-IC) 200 on one semiconductor substrate together with the transmitting system circuit 150. The I and Q signals demodulated by the reception system circuit 120 of the RF-IC 200 are supplied to the baseband circuit 300.
The baseband circuit 300 converts a command code for switching the switches SWc1, SWc2, and the like in the switching circuit 125 of the second embodiment to RF by a mode switching signal MODE from the mode selection circuit 400 that determines the transmission / reception mode based on a key input signal or the like. Supply to the IC 200, or convert transmission data into I and Q signals and pass them to the RF-IC 200; The command from the baseband circuit 300 to the RF-IC 200 is not limited to the transmission of the command code, and a signal such as a control signal supplied from the control circuit 127 of the embodiment to each switch is directly transmitted to the baseband circuit. It is also possible to provide from 300. The mode selection circuit 400 may be a circuit that determines the mode according to the amount of data to be transmitted instead of the key input signal. In this case, the mode selection circuit 400 may be provided in the baseband circuit 300.
[0045]
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the spirit of the invention. Nor. For example, in any of the above embodiments, in the W-CDMA system, two high-gain amplifier circuits 124a and 124b are provided in order to increase the time required for offset cancellation, and are alternately provided each time the gain is changed. Although it has been described that switching is used, only one high-gain amplifier circuit may be provided. This is because a W-CDMA mobile phone is configured to have a function of restoring received data, so even if only one high gain amplifier circuit is used, gain switching and offset cancellation are performed at appropriate timing during reception. Is performed, even if a loss occurs in the received data, it can be repaired, so that the reception operation is not hindered.
[0046]
Further, in the above embodiment, the offset cancellation circuit is provided in each of the high gain amplifying sections for amplifying the reception signal. However, a common offset cancellation circuit is provided for a plurality of high gain amplifying sections, and the offset cancellation is performed in order. It is also possible to make it perform. Furthermore, in the embodiment, the receiving system circuit and the transmitting system circuit are formed on one semiconductor chip, but they may be formed on separate semiconductor chips. The configuration of the variable gain amplifier is not limited to the circuits shown in FIGS. 3 and 4, but may be other circuit types or MOSFETs.
[0047]
In the above description, the invention made by the present inventor is mainly used in a dual-mode mobile phone capable of performing communication by two systems, that is, the W-CDMA system and the GMS or DCS system, which are the fields of use which are the background of the invention, and the invention is used for the same. The case where the present invention is applied to an RF-IC as a semiconductor integrated circuit for communication has been described. However, the present invention is not limited to this, and EDGE (QGE) which performs QPSK modulation in which an amplitude shift is further added to a phase shift of GMSK modulation. The present invention can also be used for a triple mode configured to enable communication in a system called Enhanced Data Rates for GMS Evolution and a quad mode mobile phone to which another communication system is added.
[0048]
【The invention's effect】
The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.
That is, a step-type amplifier can be used as a gain control amplifier for amplifying a received signal in a communication semiconductor integrated circuit constituting a dual mode or higher wireless communication system including the W-CDMA system. In the mobile phone used, even if the gain is changed according to the intensity of the received signal, the current consumption is made substantially constant, and the battery life, that is, the reception standby time and talk time after one charge can be extended.
[0049]
Further, according to the present invention, it is possible to realize a communication semiconductor integrated circuit capable of expanding a gain control range of a gain control amplifier for amplifying a received signal and improving a CN ratio, and a wireless communication system using the same. it can.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a receiving system circuit of a mobile phone according to a first embodiment to which the present invention is preferably applied.
FIG. 2 is a block diagram illustrating a configuration example of a high gain amplifying unit of the reception system circuit of FIG. 1;
FIG. 3 is a circuit diagram showing a specific circuit example of a step-type amplifier used as a gain control amplifier of the reception system circuit of FIG. 1;
FIG. 4 is a circuit diagram showing another example of a circuit of a step-type amplifier used as a gain control amplifier of the reception system circuit of FIG. 1;
FIG. 5 is a circuit diagram showing a circuit example of a gain control amplifier and a calibration DAC circuit of the reception system circuit of FIG. 1;
FIG. 6 is a timing chart showing an example of control timing when a gain is changed in a high gain amplifying unit according to the level of a received signal.
FIG. 7 is a timing chart showing another example of the control timing when the gain is changed in the high gain amplifying unit according to the level of the received signal.
FIG. 8 is a block diagram illustrating a configuration example of a reception system circuit of a mobile phone according to a second embodiment that is preferable to which the present invention is applied.
FIG. 9 is a circuit diagram illustrating a configuration example of a low-pass filter included in the reception system circuit according to the embodiment;
FIG. 10 is a timing chart showing control timing in a receiving system circuit according to the second embodiment.
FIG. 11 is a timing chart showing a control timing at the time of amplifying a GSM or DCS reception signal in the reception system circuit of the second embodiment.
FIG. 12 is a block diagram illustrating a configuration example of a mobile phone suitable for applying the present invention.
[Explanation of symbols]
100 antenna
110 Duplexer
120 Receiver circuit
121,128 low noise amplifier circuit
122 frequency dividing circuit
123a, 123b, 129a, 129b Mixer
124a, 124b High gain amplifier
125, 126 switching circuit
127 control circuit
130 oscillation circuit
140 Transmission / reception switch
150 Transmission circuit
200 Communication semiconductor integrated circuit (RF-IC)
241a, 241b, 243a, 243b Gain control amplifier circuit
242a, 242b, 242c, 244a, 244b, 244c Low pass filter (LPF)
300 baseband circuit
400 mode selection circuit

Claims (12)

A gain control amplifier for amplifying the received signal, and an offset cancel circuit for canceling a DC offset of the gain control amplifier,
A communication semiconductor integrated circuit, wherein a signal transmitted in a discontinuous mode and a signal transmitted in a continuous mode can be amplified by the common gain control amplifier. 2. The communication semiconductor integrated circuit according to claim 1, wherein the gain control amplifier is configured to change its gain stepwise. The gain control amplifier, when amplifying a signal transmitted in a non-continuous mode, cancels the offset by the offset cancel circuit at a predetermined cycle, and amplifies a signal transmitted in a continuous mode. 3. The communication semiconductor integrated circuit according to claim 2, wherein the offset is canceled by the offset canceling circuit in accordance with a change in gain. The gain control amplifier includes two or more filters having different cutoff frequencies from each other, and switching means for switching one of these filters so that a received signal passes therethrough. The communication semiconductor according to any one of claims 1 to 3, wherein the filter is configured to be switched between when the signal is amplified and when the signal transmitted in the continuous mode is amplified. Integrated circuit. It is provided with two or more gain control amplifiers for amplifying a received signal, and an offset cancel circuit for canceling a DC offset of the gain control amplifier,
When a gain change occurs while a signal transmitted in a continuous mode is amplified by any one of the gain control amplifiers, a change in the gain of another gain control amplifier and the other change by the offset cancel circuit are performed. A semiconductor integrated circuit for communication, wherein the gain control amplifier to which the received signal is supplied is switched after the offset of the gain control amplifier is canceled to start an amplification operation. 6. The communication semiconductor integrated circuit according to claim 5, wherein the gain control amplifier is configured to change its gain stepwise. One of the two or more gain control amplifiers is configured so that a signal transmitted in a discontinuous manner and a signal transmitted in a continuous manner can be amplified by a common circuit. The communication semiconductor integrated circuit according to claim 6, wherein: The gain control amplifier includes two or more filters having different cutoff frequencies from each other, and switching means for switching one of these filters so that a received signal passes therethrough. 8. The communication semiconductor integrated circuit according to claim 7, wherein the filter is switched between when the signal is amplified and when the signal transmitted in the continuous mode is amplified. A gain control amplifier for amplifying a received signal and an offset canceling circuit for canceling a DC offset of the gain control amplifier, wherein the gain control amplifier shares a signal transmitted in a discontinuous mode and a signal transmitted in a continuous mode. A communication semiconductor integrated circuit configured to be able to amplify,
A baseband circuit that gives a command to select a reception signal to be amplified by the communication semiconductor integrated circuit,
When amplifying a signal transmitted in a discontinuous mode, a command for designating the gain of the gain control amplifier is issued at a predetermined cycle, and when amplifying a signal transmitted in a continuous mode, the gain control amplifier is used. A wireless communication system configured to give a command for designating the gain from the baseband circuit to the communication semiconductor integrated circuit at a timing corresponding to a change in the strength of a received signal. It comprises two or more systems of gain control amplifiers for amplifying received signals and an offset canceling circuit for canceling the DC offset of the gain control amplifiers, and amplifies a signal transmitted in a continuous system by any one system of gain control amplifiers. When a gain change occurs during the control, the gain control of receiving the received signal after the change of the gain of another gain control amplifier and the cancellation of the offset of the other gain control amplifier by the offset cancel circuit are completed. A communication semiconductor integrated circuit configured so that the amplifier is switched to start an amplification operation;
A baseband circuit that gives a command to select a reception signal to be amplified by the communication semiconductor integrated circuit,
When amplifying a signal transmitted in a discontinuous mode, a command for designating the gain of the gain control amplifier is issued at a predetermined cycle, and when amplifying a signal transmitted in a continuous mode, the gain control amplifier is used. A wireless communication system configured to give a command for designating the gain from the baseband circuit to the communication semiconductor integrated circuit at a timing corresponding to a change in the strength of a received signal. The command to execute the offset cancellation of the gain control amplifier by the offset cancel circuit is given from the baseband circuit to the communication semiconductor integrated circuit after the command for designating the gain of the gain control amplifier is given. The wireless communication system according to claim 9 or 10, wherein: A control signal for executing the offset cancellation of the gain control amplifier by the offset cancellation circuit is based on a command that specifies the gain of the gain control amplifier given to the communication semiconductor integrated circuit from the baseband circuit. The wireless communication system according to claim 9, wherein the wireless communication system is configured to be generated inside a semiconductor integrated circuit for use.

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