JP2004013719A - Updating circuit, and updating method of multiplexed nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method in which a plurality of nonvolatile memories are easily updated and the read check of the memories is easily performed when the plurality of the nonvolatile memories are multiplexed. <P>SOLUTION: An area which is continuous to the first nonvolatile memory 2a and the second nonvolatile memory 2b is divided on a single memory map, and the second nonvolatile memory 2b allocated on a backup area is updated. A system is started using a program updated on the second nonvolatile memory 2b which becomes a main area by replacing memory areas by selectors 6a and 6b, and then the first nonvolatile memory 2a newly allocated on the backup area is updated. Therefore, the first and second nonvolatile memories can be updated using a single CPU. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to updating a nonvolatile memory, and more particularly, to a multiplexed nonvolatile memory update circuit that updates each nonvolatile memory in a multiplexed configuration using a plurality of nonvolatile memories, and a multiplexed nonvolatile memory update circuit. And a method of updating a nonvolatile memory.
[0002]
[Prior art]
The CPU starts execution from the power-on reset vector. Therefore, an electronic device such as an LSI having a program to be activated from a reset vector often uses a built-in nonvolatile memory (Flash-ROM) to retain its contents even when the power is turned off. When such a program in the nonvolatile memory needs to be changed, the LSI is once removed from the printed circuit board and rewritten by a ROM writer or the like.
[0003]
An EEPROM used as a nonvolatile memory can be electrically rewritten. Therefore, in a configuration in which the EEPROM is built in the LSI together with the CPU, the contents of the nonvolatile memory can be changed by processing of the CPU. The update of the nonvolatile memory inside the LSI will be described. FIG. 12 is a flowchart showing the overall flow when updating the nonvolatile memory. It includes an erase step (step S1), a write step (step S2), a read check step (step S3), and a determination step (step S4).
[0004]
FIG. 13 is a flowchart showing the procedure of the erasing step (step S1). In the erasing step, an erase command is written to the command register of the nonvolatile memory (Step S11). As a result, all the data in the nonvolatile memory is erased (for example, the data is updated to 0xFF).
[0005]
FIG. 14 is a flowchart showing the procedure of the writing step (step S2). In the writing step, a write command is written to the command register of the nonvolatile memory (step S21), and then the address and data to be written are written (step S22). As a result, data is written to the specified address in the nonvolatile memory. Next, the address to be written is incremented (step S23). Until the address reaches the final address (step S24: No), the process returns to step S22 to update all data, and when the address reaches the final address (step S23). S24: Yes), ends the writing process.
[0006]
FIG. 15 is a flowchart showing the procedure of the read check step (step S3). In the read check step, a read / reset command is written to a command register of the nonvolatile memory (Step S31). As a result, the nonvolatile memory enters a normal state, and data can be read. Thereafter, the data is read and compared with the expected value (step S32).
[0007]
If the comparison result matches (step S32: OK), the address is incremented (step S33). Until the final address is reached (step S34: No), the process returns to step S32 to compare all data. When the address reaches the final address (step S34: Yes), the process ends normally (normal end). On the other hand, if the comparison results do not match (step S32: NG), the error counter 1 is incremented (step S35), and until the error counter 1 reaches a predetermined number (for example, 100) (step S36: No). Then, the process returns to step S32 to perform a retry. If the number of retries has reached a predetermined number (the error counter 1 is, for example, 100 times) (step S36: Yes), the error flag is set to "1", and the process ends abnormally (abnormal end).
[0008]
Thereafter, the process proceeds to the determination step S4 shown in FIG. If no error occurs in the read check step (step S3) and the error flag is “0” (step S5: No), rewriting is determined to be normal end (normal end), and the rewriting is terminated. On the other hand, if an error occurs in the read check step (step S3) and the error flag is “1” (step S5: Yes), the error counter 2 is updated (step S6), and the error counter is set to a predetermined value (for example, 10000 times). ) (Step S7: No), the process returns to the erasing step (Step S1). Then, redoing from the erase command is performed. If the redoing has reached a predetermined number of times (10000 times above) (step S7: Yes), it is determined that there is a physical error in the nonvolatile memory and rewriting is abnormally ended (abnormal end). Then, the update of the nonvolatile memory is completed.
[0009]
[Problems to be solved by the invention]
However, in a system having only one such non-volatile memory, if a permanent error occurs during the above-described non-volatile memory update and the non-volatile memory update program ends abnormally, the system is thereafter started up. It has the possibility of disappearing. For this reason, a method is considered in which the system can be started from the other non-volatile memory by multiplexing, such as using two non-volatile memories, even if updating of one non-volatile memory fails.
[0010]
In a configuration in which a plurality of such nonvolatile memories are arranged in a system, there is a demand for a method capable of efficiently performing the work of updating each nonvolatile memory and the work of performing a read check of each other's data. Further, since the LSI with the built-in CPU and nonvolatile memory is arranged on a printed circuit board and cannot be attached or detached, it is multiplexed while operating on the system while being mounted on the printed circuit board. There is a need for a method that can update the contents of a nonvolatile memory and perform a read check.
[0011]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made in consideration of the above problems, and has been made in consideration of the above circumstances. It is an object of the present invention to provide a circuit and a method for updating a memory.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the present invention divides an area into a main area and a backup area for a plurality of nonvolatile memories on a single memory map, Update. Thereafter, the memory area is replaced, the system is started by the update data of the old backup area which has become the main area, and another nonvolatile memory newly allocated to the backup area is updated.
[0013]
According to the present invention, a plurality of multiplexed nonvolatile memories can be sequentially updated using a single CPU. By multiplexing the programs stored in the nonvolatile memories allocated to the main area and the backup area, the system can be started using any one of the nonvolatile memories. Also, even if the system terminates abnormally during the update, the system can be restored.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of a multiplexed nonvolatile memory update circuit and method according to the present invention will be described in detail below with reference to the accompanying drawings. The present invention will be described on the premise of a configuration using two nonvolatile memories (Flash-ROM). Both of these non-volatile memories have the same data content, and are configured so that the mapping can be switched by setting.
[0015]
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration of an electronic device including a multiplexed nonvolatile memory according to a first embodiment of the present invention. In the LSI 1, a CPU (not shown) and first and second nonvolatile memories (Flash-ROM1, 2) 2a and 2b are built in, and the first and second nonvolatile memories 2a and 2b are built by the CPU. Are sequentially updated.
[0016]
FIG. 2 is a diagram showing a memory map accessed by the CPU. As shown in the figure, the main area A and the backup area B are secured as individual areas, are mapped so as to be continuous with each other on an address, and have the same data content. A memory area of the first nonvolatile memory 2a or the second nonvolatile memory 2b is allocated to the main area A and the backup area B, and the areas can be switched by selecting the selectors 6a and 6b. . The area C is a storage area for setting data of peripheral circuits such as a built-in RAM. Also, only one reset vector exists at a predetermined address on the main area A side.
[0017]
Under normal conditions, the CPU starts execution from the reset vector of the first nonvolatile memory 2a, which is the main area, and starts the system using only the data stored in the first nonvolatile memory 2a. Then, in the event of an abnormality, the execution can be started from the second nonvolatile memory 2b set on the backup area side.
[0018]
As shown in FIG. 1, a switching unit 3 for updating the first and second nonvolatile memories 2a and 2b is provided inside the LSI 1. The switching means 3 includes a setting holding memory 4 composed of a nonvolatile memory such as a Flash-ROM capable of holding a setting, and a circuit divided into two systems corresponding to the first and second nonvolatile memories 2a and 2b. Having. Each system is provided with decoders 5a and 5b, selectors 6a and 6b, and OR circuits 7a and 7b each composed of an OR gate. A holding circuit 8 is connected to an output of the setting holding memory 4.
[0019]
A watchdog timer 10 for detecting runaway of the CPU is connected to the setting holding memory 4. The watchdog timer 10 is periodically reset by the CPU during the updating process of the first and second nonvolatile memories 2a and 2b. When the watchdog timer 10 is not reset due to the runaway of the CPU, it generates an interrupt to the CPU or resets the CPU to detect runaway of the CPU.
[0020]
When the CPU write signal 20 is input from the CPU while the watchdog timer 10 is normally reset, the setting holding memory 4 outputs a write request signal 23 to the holding circuit 8. The holding circuit 8 is composed of a D-type flip-flop (DF / F). A write request signal 21 is input to a D terminal, and a reset signal 22 is input to a reset terminal. The holding circuit 8 outputs the switching signal 23 from the Q terminal while holding the write request signal 21, inverts and holds the switching signal 23 when the reset signal 22 is input, and outputs it from the Q terminal.
[0021]
The addresses at the time of updating the first and second nonvolatile memories 2a and 2b are input to the decoders 5a and 5b. Due to the two address decodings by the decoders 5a and 5b, the decoder 5a has access to the first nonvolatile memory 2a (or the second nonvolatile memory 2b) assigned to the main area A shown in FIG. , And the decoder 5b generates an access signal 24b indicating that the second nonvolatile memory 2b (or the first nonvolatile memory 2a) assigned to the backup area B has been accessed.
[0022]
The selectors 6a and 6b receive the access signals 24a and 24b, respectively, and select one of the inputs according to the input of the switching signal 23 to the select terminal S. These selectors 6a and 6b have their input terminals Q and L inverted and connected to each other, and when updating, either one of them is selected.
[0023]
Specifically, when the switching signal 23 is “0”, the first non-volatile memory 2a is allocated to the main area A when the access signal 24a becomes “1”, and when the access signal 24b becomes “1”, the main area A becomes A is assigned to the second nonvolatile memory 2b. On the other hand, when the switching signal 23 is “1”, the second nonvolatile memory 2b is allocated to the main area A when the access signal 24a becomes “1”, and the second nonvolatile memory 2b is allocated to the main area A when the access signal 24b becomes “1”. One nonvolatile memory 2a is allocated. As described above, by switching the selectors 6a and 6b, the assignment of the first and second nonvolatile memories 2a and 2b to the main area A and the backup area B can be switched. At the same time, the system is started from the first and second nonvolatile memories 2a and 2b allocated to the main area A.
[0024]
The output of the selector 6a is supplied as a selection signal 25a for controlling the first nonvolatile memory 2a via the OR circuit 7a. The output of the selector 6b is supplied as a control selection signal 25b to the second nonvolatile memory 2b via the OR circuit 7b. The parallel mode signal 27 is input to the OR circuits 7a and 7b. The parallel mode signal 27 is output from the CPU when the content comparison (read check) of the first and second nonvolatile memories 2a and 2b is performed simultaneously.
[0025]
Next, an update process of the first and second nonvolatile memories 2a and 2b according to the above configuration will be described. FIG. 3 is a flowchart showing a procedure for updating the multiplexed nonvolatile memory according to the first embodiment. When the nonvolatile memory is updated by the CPU provided inside the LSI, the watchdog timer 10 is activated to prevent erroneous writing of the nonvolatile memory due to runaway of the CPU. Next, the setting holding memory 4 receives a CPU write signal from the CPU and outputs a write request signal 21. Thereby, the holding circuit 8 outputs the switching signal 23, and the selectors 6a and 6b are switched. FIG. 4 is a diagram showing the rearrangement of the memory map. At this time, as shown in FIG. 4A, it is assumed that the second nonvolatile memory 2b is selected (assigned) to one system (the backup area B side) before the rearrangement.
[0026]
In this state, the CPU executes data update processing on the nonvolatile memory (second nonvolatile memory 2b) on the backup area B side (step S41). The updating process includes the above-described erasing process, a process of writing update data, and a read check process. In the writing step, data writing is performed from the update start address of the backup area B while incrementing the address. If an abnormality is detected in the read check step, it is determined that the update of the second nonvolatile memory 2b has failed, and a notification of a nonvolatile memory update error is made.
[0027]
FIG. 5 is a timing chart showing selection control of the first and second nonvolatile memories 2a and 2b according to the first embodiment. When the update processing of the second nonvolatile memory 2b ends normally, the CPU outputs the CPU write signal 20 again (FIG. 5A). As a result, the setting holding memory 4 holds the value obtained by inverting the original value, and outputs the inverted value to the holding circuit 8 as the write request signal 21 (step S42, FIG. 5B). Thus, after the rearrangement, as shown in FIG. 4B, the arrangement of the first and second nonvolatile memories 2a and 2b is switched.
[0028]
Thereafter, when the system is reset (step S43), the reset signal 22 is input to the holding circuit 8 (FIG. 5C). Correspondingly, the holding circuit 8 switches the switching signal 23 at the rise of the reset signal 22 (FIG. 5D). Thus, the access to the first and second nonvolatile memories 2a and 2b is switched, and the updated second nonvolatile memory 2b is allocated to the main area A.
[0029]
As a result, the CPU accesses the reset vector of the second nonvolatile memory 2b and starts executing the system (step S44). At this time, the first nonvolatile memory 2a is allocated to the backup area B. Then, an update process is performed on the first nonvolatile memory 2a (step S45). The update processing for the first non-volatile memory 2a is the same as the above-described update processing for the second non-volatile memory 2b, and the details are omitted.
[0030]
According to the above procedure, while the LSI 1 is mounted on the printed circuit board, the contents of the built-in first and second nonvolatile memories 2a and 2b are transferred to a single CPU built in the same LSI. The system can be updated sequentially by resetting the system. This makes it possible to easily update the LSI 1 without removing it from the printed circuit board.
[0031]
(Embodiment 2)
FIG. 6 is a block diagram illustrating a configuration of an electronic device including a multiplexed nonvolatile memory according to a second embodiment of the present invention. The second embodiment has a configuration in which a system reset is not required when updating a multiplexed nonvolatile memory. As in the first embodiment, the second embodiment is based on the premise that the LSI includes a CPU and two nonvolatile memories.
[0032]
As shown in the figure, the configuration of the second embodiment does not include the holding circuit 8 in the components of the switching unit 3. The output signal line of the setting holding memory 4 is directly connected to the select terminals S of the two selectors 6a and 6b.
[0033]
Next, an update process of the first and second nonvolatile memories 2a and 2b according to the above configuration will be described. FIG. 7 is a flowchart showing a procedure for updating a multiplexed nonvolatile memory according to the second embodiment. In the description using the same drawing, the description of the same processing content as in the embodiment is simplified.
[0034]
First, the watchdog timer 10 is started to prevent erroneous writing in the nonvolatile memory due to runaway of the CPU. Next, the setting holding memory 4 receives a CPU write signal from the CPU and outputs a write request signal 21. FIG. 8 is a diagram showing the rearrangement of the memory map. At this time, it is assumed that the second non-volatile memory 2b is selected (assigned) to one system (the backup area B side) before the rearrangement, as shown in FIG. 8A. Thereafter, a data update process is performed on the second nonvolatile memory 2b (step S51).
[0035]
In the read check step of the update process, the contents of the second nonvolatile memory 2b are read to confirm that the update has been performed reliably. Thereafter, it is confirmed that the application does not use the programs in the first and second nonvolatile memories 2a and 2b, and if so, the program is terminated, and the external interrupt and software used in the system are used. All interrupts are prohibited (step S52).
[0036]
FIG. 9 is a timing chart showing selection control of the first and second nonvolatile memories 2a and 2b according to the second embodiment. When the update processing of the second nonvolatile memory 2b ends normally, the CPU outputs the CPU write signal 20 again (FIG. 9A). As a result, the setting holding memory 4 holds the inverted value of the original value, and outputs the inverted value to the selectors 6a and 6b as the write request signal 21 (step S53, FIG. 9B). In the second embodiment, the write request signal 21 is used as the switching signal 23 (FIG. 9C) described in the first embodiment.
[0037]
Thus, after the rearrangement, as shown in FIG. 8B, the arrangement of the first and second nonvolatile memories 2a and 2b is switched. At this time, the write request signal 21 is inverted, the access to the first and second nonvolatile memories 2a and 2b is switched, the second nonvolatile memory 2b is selected, and the updated second nonvolatile memory 2b is selected. The memory 2b is allocated to the main area A.
[0038]
According to this configuration, the memory map can be switched without resetting the system. As a result, the CPU starts to access the updated second nonvolatile memory 2b, cancels the inhibition of the interrupt, and if the application uses the programs in the first and second nonvolatile memories 2a and 2b, Is permitted (step S54).
[0039]
At this time, the first nonvolatile memory 2a is allocated to the backup area B. Then, an update process is performed on the first nonvolatile memory 2a (step S55). The update processing for the first non-volatile memory 2a is the same as the above-described update processing for the second non-volatile memory 2b, and the details are omitted.
[0040]
In the updating method according to the second embodiment, a system reset is not required as compared with the updating method described in the first embodiment, and the first and second nonvolatile memories 2a and 2b are stored without stopping the system. It has the advantage that it can be updated. However, depending on the application operating on the system, a problem may occur when the BIOS programs and the like in the first and second nonvolatile memories 2a and 2b are replaced by rearrangement of the memory map in the middle. When such a program is provided, it is better to use the updating method (method of resetting the system when the memory map is switched) described in the first embodiment.
[0041]
According to the above procedure, the contents of the built-in first and second non-volatile memories 2a and 2b are transferred to a single CPU built in the same LSI 1 while the LSI 1 is mounted on a printed circuit board. And can be updated sequentially without using a system reset.
[0042]
Next, a description will be given of a data collation process after updating the non-volatile memories multiplexed by the updating method described in the first and second embodiments. This data collation processing can be executed by using the configuration of the OR circuits 7a and 7b and the comparator 30 shown in FIGS.
[0043]
After updating the first and second nonvolatile memories 2a and 2b, it is necessary to check whether the contents of the first and second nonvolatile memories 2a and 2b are the same. For this reason, after updating the first and second nonvolatile memories 2a and 2b, the contents are collated to determine a match. When the parallel mode signal 27 is supplied to the OR circuits 7a and 7b, the selection signals 25a and 25b are simultaneously supplied to the first and second nonvolatile memories 2a and 2b. Therefore, the CPU can read data from the first and second nonvolatile memories 2a and 2b at the same time by supplying the parallel mode signal 27 when executing the read check process.
[0044]
At this time, if the data sequentially read while incrementing the address is normally updated, the data is always stored in the first and second nonvolatile memories 2a and 2b respectively allocated to the main area A and the backup area B. Should match. This point is compared by the comparator 30 to detect a match. The CPU determines that the process has been completed normally if the match is detected in the data of all the addresses, and determines that the process has been abnormally ended (mismatch) if any part of the data does not match.
[0045]
According to the above configuration, even when the non-volatile memory is multiplexed, the data in both the main area A and the backup area B can be trusted, and the system using the non-volatile memory allocated to one area can be used. When the system cannot be activated, the system can be activated using the nonvolatile memory allocated to the other area, and the reliability of the system activation can be improved.
[0046]
In the configurations of Embodiments 1 and 2 described above, the configuration in which the CPU and the first and second nonvolatile memories 2a and 2b are incorporated in the same package of the LSI 1 has been described as an example. The present invention is not limited to packaging all of these inside the LSI 1, but also includes the CPU, the first and second non-volatile memories 2a and 2b, and the switching means 3 all composed of circuit elements of different packages. Only the parts can be made the same package, and the updating method described above can be applied to various aspects.
[0047]
(Embodiment 3)
FIG. 10 is a block diagram showing a circuit configuration of an electronic device including a multiplexed nonvolatile memory according to the third embodiment of the present invention. In the third embodiment, the multiplexed nonvolatile memory is updated using a dedicated ROM writer. As shown in the figure, the first and second nonvolatile memories 2a and 2b are configured to be able to simultaneously supply a parallel mode signal 27 for control from a dedicated ROM writer.
[0048]
FIG. 11 is a flowchart showing a procedure for updating a multiplexed nonvolatile memory according to the third embodiment. First, a chip circuit such as the LSI 1 shown in FIG. 10 is mounted on a dedicated ROM writer (not shown) (step S61). Next, a program to be updated is downloaded from an external PC (personal computer) or the like to a dedicated ROM writer (step S62).
[0049]
Next, the dedicated ROM writer activates the parallel mode signal 27 to select the first and second nonvolatile memories 2a and 2b at the same time, and the same for the first and second nonvolatile memories 2a and 2b at the same time. The program is written (step S63). As a result, the time required for updating can be reduced.
[0050]
After the update, the parallel mode signal 27 is activated to select the first and second nonvolatile memories 2a and 2b at the same time, and to read data from the first and second nonvolatile memories 2a and 2b at the same time. At this time, the data of one (first nonvolatile memory 2a) is output to the outside of the LSI 1, and the data of both nonvolatile memories 2a and 2b are compared by the comparator 30. As described above, the LSI 1 checks whether the updated data in the first and second nonvolatile memories 2a and 2b match, and outputs the result outside the LSI (step S64). As a result, even when the nonvolatile memories are multiplexed, the read check time can be performed in the same time as in the related art.
[0051]
The details of the read check are the same as the procedure shown in FIG. 12 described above. It is checked whether or not an error has occurred (step S65), and if there is no error (step S65: No), it is determined that the rewriting has been completed normally and the process ends. . On the other hand, if an error occurs during the read check (step S65: Yes), it is determined that the reading has been abnormally terminated (abnormal end). At the time of abnormal termination, the updating process including the erasing process is executed again.
[0052]
Since the above update procedure is an example using a dedicated ROM writer, when an existing ROM writer is used, there is no means for matching and comparing data in the multiplexed nonvolatile memory. In order to compare and match the data in the first and second nonvolatile memories 2a and 2b using the existing ROM writer in this manner, the data is serially read from the first and second nonvolatile memories 2a and 2b. You only have to check. For example, as shown in the memory map of FIG. 2, when the first and second nonvolatile memories 2a and 2b are continuously arranged in each area, the corresponding data in each of these areas is read-checked in address units. I do. Further, data obtained by continuously changing the address on the memory map may be determined to coincide with prescribed data. In this case, if the first and second non-volatile memories 2a and 2b are arranged continuously in each area, the data in each area can be sequentially read using an existing ROM writer.
[0053]
The first and second nonvolatile memories 2a and 2b and the setting holding memory 4 used in the first and second embodiments can be configured using an EEPROM. Thus, even after the LSI 1 is mounted on the printed circuit board, the first and second nonvolatile memories 2a and 2b can be updated by the built-in CPU any number of times. Further, the first and second nonvolatile memories 2a and 2b used in the third embodiment are not limited to the EEPROM, and after the step of erasing ultraviolet rays using the EPROM, the first and second nonvolatile memories 2a and 2b are used. Can be simultaneously updated and read checked. The number of nonvolatile memories used in each embodiment may be two or more, and one nonvolatile memory is allocated to the main area A, and a plurality of nonvolatile memories is allocated to the backup area B. Can be used.
[0054]
The updating method described above can be realized by executing a prepared program on a computer such as a personal computer or a workstation. This program is recorded on various recording media, and is executed by being read from the recording medium by a computer. The program may be a transmission medium that can be distributed via a network such as the Internet.
[0055]
(Supplementary Note 1) A nonvolatile memory updating circuit that includes a plurality of nonvolatile memories for storing a program and updates each nonvolatile memory.
Mapping means for forming a memory address formed by the plurality of nonvolatile memories by a main area having a reset vector of a CPU and a backup area, and forming one continuous address space by the main area and the backup area;
A main area set by the mapping means, and a switching means for allocating an area of each of the non-volatile memories to a backup area and controlling the areas to be interchangeable with each other;
Updating means for updating data in the nonvolatile memory assigned to the backup area,
A multiplexed nonvolatile memory update circuit, comprising:
[0056]
(Supplementary Note 2) The switching unit includes a holding unit that holds an assignment state of each of the nonvolatile memories to the main area and the backup area,
2. The multiplexed nonvolatile memory update circuit according to claim 1, wherein said holding means exchanges the assigned area based on a CPU write signal input at the time of update.
[0057]
(Supplementary note 3) The multiplexed nonvolatile memory according to any one of Supplementary notes 1 and 2, wherein the updating unit updates the data when a watchdog timer for detecting runaway of the CPU is activated. Update circuit for non-volatile memory.
[0058]
(Supplementary note 4) The multiplexed nonvolatile memory according to supplementary note 2, wherein the holding unit includes a nonvolatile memory that can electrically change a value without being affected by a power supply state and holds the changed state. Memory update circuit.
[0059]
(Supplementary Note 5) A nonvolatile memory updating circuit that includes a plurality of nonvolatile memories that store a program, and updates each nonvolatile memory.
A decoder for determining which area the CPU is accessing with respect to a main area having a reset vector of the CPU and a backup area;
A selector for allocating each of the non-volatile memories to the main area and the backup area, and controlling the allocated areas to be interchangeable based on an input of a selection signal;
A setting holding nonvolatile memory for holding and outputting an allocation state of each of the nonvolatile memories to the main area and the backup area, and inverting and holding a setting by input of a CPU write;
A holding circuit that outputs a holding output of the nonvolatile memory to the selector as a selection signal based on a system reset;
A CPU that updates data in a nonvolatile memory assigned to a backup area before and after the system reset,
A multiplexed nonvolatile memory update circuit comprising:
[0060]
(Supplementary Note 6) A nonvolatile memory update circuit that includes a plurality of nonvolatile memories for storing a program, and updates each nonvolatile memory.
A decoder for determining which area the CPU is accessing with respect to a main area having a reset vector of the CPU and a backup area;
A selector for allocating each of the non-volatile memories to the main area and the backup area, and controlling the allocated areas to be interchangeable based on an input of a selection signal;
A setting holding non-volatile memory for holding and outputting an allocation state of each of the non-volatile memories to the main area and the backup area, inverting and holding a setting by input of a CPU write, and outputting the setting as a selection signal to the selector;
A CPU for updating data in a nonvolatile memory assigned to a backup area before and after the CPU write,
A multiplexed nonvolatile memory update circuit comprising:
[0061]
(Supplementary note 7) The update circuit of the multiplexed nonvolatile memory according to any one of Supplementary notes 5 and 6, wherein each of the constituent circuits is packaged as a part of a single electronic circuit element. .
[0062]
(Supplementary note 8) The nonvolatile memory updating circuit according to any one of Supplementary notes 1 to 7, wherein each of the nonvolatile memories is formed of an EEPROM.
[0063]
(Supplementary Note 9) The multiplexed nonvolatile memories are configured to be able to simultaneously write / read data at the time of updating.
The multiplexed multiplexing device according to any one of Supplementary notes 1 to 8, further comprising a comparator for collating data read simultaneously from each of the nonvolatile memories, and configured to perform a match determination after updating each nonvolatile memory. Update circuit for nonvolatile memory.
[0064]
(Supplementary Note 10) A non-volatile memory updating method including a plurality of non-volatile memories for storing a program, and updating each of the non-volatile memories.
A mapping step of allocating a memory address of each of the nonvolatile memories to a main area having a reset vector of the CPU and a backup area, and forming one continuous address space by the main area and the backup area; A first update step of updating data in the nonvolatile memory allocated to the backup area set by the mapping step based on
Based on the system reset, the assignment of the main area and the backup area to each of the nonvolatile memories is exchanged with each other, and the system is started by the nonvolatile memory of the old backup area newly assigned to the main area. A second update process of updating data in another nonvolatile memory newly allocated to the backup area based on the exchange of the allocation based on the data;
A method of updating a multiplexed non-volatile memory, comprising:
[0065]
(Supplementary Note 11) A non-volatile memory update method including a plurality of non-volatile memories for storing a program, and updating each of the non-volatile memories.
A mapping step of allocating a memory address of each of the nonvolatile memories to a main area having a reset vector of the CPU and a backup area, and forming one continuous address space by the main area and the backup area; A first update step of updating data in the nonvolatile memory allocated to the backup area set by the mapping step based on
An area exchange step of exchanging the assignment of the main area and the backup area to each of the nonvolatile memories based on the CPU write again;
A second update step in which the system uses the nonvolatile memory of the old backup area newly assigned to the main area and updates data to another nonvolatile memory newly assigned to the backup area;
A method of updating a multiplexed non-volatile memory, comprising:
[0066]
(Supplementary note 12) The multiplexed multiplexing method according to supplementary note 11, wherein the area replacement step inhibits all interrupts used by the system, and is executed after the end of the program used by the application in the nonvolatile memory. How to update nonvolatile memory.
[0067]
【The invention's effect】
According to the present invention, a single memory map is divided into a main area and a backup area, an update is performed on the non-volatile memory allocated to the backup area, and the old backup area is replaced with the memory area and becomes the main area. Since the system is started by the update data and the other nonvolatile memory newly allocated to the backup area is updated, a plurality of multiplexed nonvolatile memories can be sequentially updated using a single CPU. The multiplexing structure in which the programs are stored in the non-volatile memories allocated to the main area and the backup area, respectively, enables the programs in the other non-volatile memories to be stored even if the system cannot be started using one non-volatile memory. The system used can be started. Further, the system can be restored even if the process ends abnormally during the update, so that the security of the system can be improved. Further, for updating, it is only necessary to sequentially update each non-volatile memory using one CPU, so that the circuit amount is small, and the circuit elements including the CPU and the non-volatile memory can be integrated into an LSI in a single package. And cost can be reduced. In addition, a plurality of nonvolatile memories can be updated while the LSI is mounted on the printed circuit board.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an electronic device including a multiplexed nonvolatile memory according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a memory map accessed by a CPU.
FIG. 3 is a flowchart showing a procedure for updating a multiplexed nonvolatile memory according to the first embodiment;
FIG. 4 is a diagram showing rearrangement of a memory map.
FIG. 5 is a timing chart showing selection control of first and second nonvolatile memories according to the first embodiment;
FIG. 6 is a block diagram illustrating a configuration of an electronic device including a multiplexed nonvolatile memory according to a second embodiment of the present invention.
FIG. 7 is a flowchart showing a procedure for updating a multiplexed nonvolatile memory according to the second embodiment;
FIG. 8 is a diagram showing rearrangement of a memory map.
FIG. 9 is a timing chart showing selection control of first and second nonvolatile memories according to the second embodiment;
FIG. 10 is a block diagram illustrating a circuit configuration of an electronic device including a multiplexed nonvolatile memory according to a third embodiment of the present invention.
FIG. 11 is a flowchart showing a procedure for updating a multiplexed nonvolatile memory according to the third embodiment;
FIG. 12 is a flowchart showing an entire flow at the time of updating a nonvolatile memory.
FIG. 13 is a flowchart illustrating a procedure of an erasing step.
FIG. 14 is a flowchart illustrating a procedure of a writing step.
FIG. 15 is a flowchart illustrating a procedure of a read check process.
[Explanation of symbols]
1 LSI
2a First nonvolatile memory
2b Second nonvolatile memory
3 Switching means
4 Setting holding memory
5a, 5b decoder
6a, 6b selector
7a, 7b OR circuit
8 Holding circuit
10 Watchdog timer
30 comparator

Claims (5)

A nonvolatile memory updating circuit that includes a plurality of nonvolatile memories for storing a program and updates each nonvolatile memory,
Mapping means for forming a memory address formed by the plurality of nonvolatile memories by a main area having a reset vector of a CPU and a backup area, and forming one continuous address space by the main area and the backup area;
A main area set by the mapping means, and a switching means for allocating an area of each of the non-volatile memories to a backup area and controlling the areas to be interchangeable with each other;
Updating means for updating data in the nonvolatile memory assigned to the backup area,
A multiplexed nonvolatile memory update circuit, comprising: The switching unit includes a holding unit that holds an allocation state of each of the nonvolatile memories to the main area and the backup area,
2. The multiplexed nonvolatile memory updating circuit according to claim 1, wherein said holding unit replaces the assigned area based on a CPU write signal input at the time of updating. 3. The multiplexed non-volatile memory according to claim 2, wherein the holding unit includes a non-volatile memory that can change a value electrically without being affected by a power supply state and holds the changed state. circuit. A method for updating a nonvolatile memory, comprising a plurality of nonvolatile memories for storing a program, and updating each nonvolatile memory,
A mapping step of allocating a memory address of each of the nonvolatile memories to a main area having a reset vector of the CPU and a backup area, and forming one continuous address space by the main area and the backup area;
A first updating step of updating data in the nonvolatile memory allocated to the backup area set by the mapping step based on a CPU write;
Based on a system reset, swapping the assignment of the main area and the backup area to each of the non-volatile memories, and starting the system with the non-volatile memory of the old backup area newly assigned to the main area;
A second updating step of updating data in another nonvolatile memory newly allocated to the backup area in a state where the allocation has been replaced based on the CPU write;
A method of updating a multiplexed non-volatile memory, comprising: A method for updating a nonvolatile memory, comprising a plurality of nonvolatile memories for storing a program, and updating each nonvolatile memory,
A mapping step of allocating a memory address of each of the nonvolatile memories to a main area having a reset vector of the CPU and a backup area, and forming one continuous address space by the main area and the backup area;
A first updating step of updating data in the nonvolatile memory allocated to the backup area set by the mapping step based on a CPU write;
An area exchange step of exchanging the assignment of the main area and the backup area to each of the nonvolatile memories based on the CPU write again;
A second update step in which the system uses the nonvolatile memory of the old backup area newly assigned to the main area and updates data to another nonvolatile memory newly assigned to the backup area;
A method of updating a multiplexed non-volatile memory, comprising:

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