JP2004007821A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shift circuit that is operable at a high speed with low power consumption without adopting a latch structure for level conversion. <P>SOLUTION: The level shift circuit is provided with a precharge circuit including two P type transistors P3, P4, and two N type transistors N3, N4. The precharge circuit precharges first and second nodes W1, W2 and a precharge control circuit 70 controls the precharging operations. A flip-flop circuit (level detection circuit) FF detects a level reduction of the nodes W1, W2. The switching level of the flip-flop circuit FF is set higher. Thus, when the level of the first or second node W1 or W2 reaches the switching level of the flip-flop circuit FF or below, the flip-flop circuit FF earlier detects the level and an output logic is changed. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a level shift circuit for converting a logic level, and more particularly, to a level shift circuit having a configuration for preventing a through current generated when a signal changes.

ラ ッ チ Conventionally, a latch type level shift circuit has been known as a level shift circuit. FIG. 32 shows a specific configuration of this level shift circuit. The level shift circuit shown in the figure includes two N-type transistors 51 and 52, two cross-coupled P-type transistors 53 and 54 whose gates are connected to the drains of the other, and first and second transistors. Inverters 55 and 56 are provided. The first inverter 55 inverts the input signal of the input terminal IN and operates with a low voltage source VDD of, for example, 1.5 V. The elements other than the first inverter 55 are high-voltage-side elements operated by a high-voltage source VDD3 such as 3.3 V. The two N-type transistors 51 and 52 are grounded and mutually connected. Complementary signals, that is, an input signal of the input terminal IN and an inverted signal of the input signal from the first inverter 55 are received. The two P-type transistors 53 and 54 have a source connected to the high voltage source VDD3, a drain connected to the drains of the N-type transistors 51 and 52, respectively, and the second inverter 56 includes one N-type transistor. The output side is connected to the connection point between the P-type transistor 52 and the P-type transistor 54, and the output side is connected to the output terminal OUT.

Next, the operation of the level shift circuit will be described. In the stationary state, for example, when the input signal is at the H (VDD) level and the inverted signal is at the L (VSS = 0 V) level, the N-type transistor 51 is ON, the N-type transistor 52 is OFF, the P-type transistor 53 is OFF, and P The type transistor 54 is in an ON state. In this state, a node W1 which is a connection point between one N-type transistor 51 and the P-type transistor 53 is at the L (VSS) level, and a node which is a connection point between the other N-type transistor 52 and the P-type transistor 54. W2 is at the H (VDD3) level. Since the transistors 51 and 53 and the transistors 52 and 54 are in a complementary relationship, no current flows in this stationary state.

(4) After that, when the input signal changes to the L (VSS) level and the operation is started, the N-type transistor 51 is turned off and the N-type transistor 52 is turned on as shown in FIG. Therefore, a through current I flows from the high voltage source VDD3 via the P-type transistor 54 and the N-type transistor 52 in the ON state, and the potential of the node W2 starts to decrease from the H (VDD3) level. When the potential of the node W2 drops below VDD3-Vtp (Vtp is the threshold voltage of the P-type transistor 53), the P-type transistor 53 starts to turn on, the potential of the node W1 rises, and the drain of the P-type transistor 54 The current decreases, and the potential of the node W2 further decreases.

Eventually, the potential of the node W1 becomes H (VDD3) level, the potential of the node W2 becomes L (0v) level, the through current stops flowing, the output logic is inverted by the second inverter 56, and the next input The state changes to a signal change waiting state. The case where the input signal changes from the H level to the L level has been described above. The same applies to the case where the input signal changes.

However, in the above-described conventional level shift circuit, since the through current flows through the P-type transistor 54 and the N-type transistor 52 during operation to change the potential of the node W2, the power consumption increases due to the flow of the through current. There was a disadvantage of doing so.

Therefore, conventionally, for example, Japanese Patent Application Laid-Open Nos. 10-190438 and 7-106946 propose a level shift circuit having a configuration in which a through current is cut off in accordance with a potential change of an output node W2. ing. FIG. 34 shows the configuration of this level shift circuit. The level shift circuit shown in FIG. 27 has current cutoff transistors 57 and 58 each composed of a P-type transistor between the high voltage source VDD3 and the two P-type transistors 53 and 54 in addition to the configuration shown in FIG. In addition, the potential of the node W1 is applied to the gate of one current cut-off transistor 57 via delay elements 59 and 60 composed of two inverters, and the gate of the other current cut-off transistor 58 has two delay elements. The potential of the node W2 is applied via 61 and 62. Further, a small latch 63 is connected to the two nodes W1 and W2, and the latch 63 has two P-type transistors 64 and 65, the sources of which are connected to the high voltage source VDD3 and the drains of which are connected to the high voltage source VDD3. Are respectively connected to the nodes W1, W2 and the gate of the other party.

In the conventional level shift circuit having the through current cutoff function, for example, when the input signal is at the H level, the potential of the node W2 is at the H (VDD3) level, and the current cutoff transistor 58 is turned off. The connection between the voltage source VDD3 and the P-type transistor 54 is cut off. Further, the potential of the node W1 is at the L (0v) level, the P-type transistor 53 and the current cutoff transistor 57 are ON, and the high voltage source VDD3 and the P-type transistor 53 are connected. When the input signal changes to the L level from this state, the connection between the node W1 and the ground is cut off by the OFF operation of the N-type transistor 51, and the node W2 is grounded by the ON operation of the N-type transistor 52. The potential of the node W2 decreases. The change in the potential drop is transmitted to the current cutoff transistor 58, but the transmission is delayed by a predetermined delay time by the two delay elements 61 and 62. During the delay time, the P-type transistor 53 is turned on by the decrease in the potential of the node W2, the high voltage source VDD3 is connected to the node W1, the potential of the node W1 is increased, and the P-type transistor 54 is turned off. After that, the current cutoff transistor 58 is turned on. Therefore, even if the N-type transistor 52 is turned on during this operation, a through current from the high voltage source VDD3 through the P-type transistor 54 and the N-type transistor 52 is cut off, so that power consumption is reduced. On the other hand, when the current cutoff transistor 57 is turned off with a delay of a predetermined time due to the rise in the potential of the node W1, the small latch 63 is connected to the node W2 in order to prevent the node W1 from entering a high impedance state and the output from becoming unstable. The internal P-type transistor 62 is turned on in response to the decrease in the potential of the node W1, the high voltage source VDD3 is connected to the node W1, and the node W1 is pulled up.

However, in the conventional level shift circuit having the through current cutoff function, the small latch 63 needs to have a sufficiently large gate length L so that it can operate even at a low voltage, and a large ON resistance of the transistor. However, since the operating current of the N-type transistors 51 and 52 is generally small, the driving capacity of the N-type transistors 51 and 52 is increased by the small latch 61, and the output terminal of the level shift circuit is changed based on a change in the logic level of the input signal. There is a disadvantage that the delay time until the change of the logic level of OUT becomes long.

Further, in the conventional level shift circuit having a through current cutoff function, the latch 63 is connected to the drains of the N-type transistors 51 and 52. It is necessary to make the potentials of the drains of the type transistors 51 and 52, that is, the potentials of the nodes W1 and W2, fully swing between the potential of the high voltage source VDD3 and the ground potential, which is another cause of increasing the delay time. . On the other hand, when the current capabilities of the N-type transistors 51 and 52 are increased so as to reduce the delay time, the size of the N-type transistors 51 and 52 increases. In particular, when the voltage of the low-voltage source VDD decreases, the value of the current flowing through the N-type transistors 51 and 52 decreases, and the size of the N-type transistors 51 and 52 further increases, resulting in an increase in area. Occurs.

SUMMARY OF THE INVENTION In view of the foregoing, an object of the present invention is to provide a level shift circuit having a through current cutoff function that operates at high speed and has a short delay time without disposing the small latch as in the related art.

To achieve the above object, the present invention provides a novel level shift circuit that does not have two cross-coupled transistors as a level shift circuit.

That is, in the level shift circuit according to the first aspect of the present invention, a complementary signal using the first voltage source as a power supply is input, one end is grounded, and the other end is connected to the first and second nodes, respectively. First and second transistors, a precharge circuit for precharging the first and second nodes to the potential of a second voltage source, and level detection for detecting a drop in potential of the first and second nodes And a precharge control circuit for controlling the precharge circuit.

According to a second aspect of the present invention, in the level shift circuit according to the first aspect, the level detection circuit includes a flip-flop circuit connected to the first and second nodes.

According to a third aspect of the present invention, in the level shift circuit according to the first or second aspect, when the level of the first and second nodes decreases, the switching level is set so that the potential decrease is detected earlier. It is characterized by being set high.

According to a fourth aspect of the present invention, in the level shift circuit according to the first or second aspect, the level detection circuit is configured such that a gate capacitance connected to the first and second nodes has a first and a second capacitance. It is characterized in that it is set small so that this potential drop occurs quickly when the potential of the node drops.

The invention according to claim 5 is the level shift circuit according to claim 1 or 2, wherein the precharge circuit connects the second voltage source to the first and second nodes; An intermittent circuit for interrupting and connecting between the first node and the ground and between the second node and the ground.

The invention according to claim 6 is the level shift circuit according to claim 5, wherein the supply circuit includes a first P-type transistor disposed between the second voltage source and the first node. , A second P-type transistor disposed between the second voltage source and the second node, and the cutoff circuit includes a second P-type transistor disposed between the first node and ground. 3 N-type transistors, and a fourth N-type transistor disposed between the second node and the ground.

According to a seventh aspect of the present invention, in the level shift circuit according to the first or fifth aspect, the first or second precharge control circuit performs one of the first and second OFF operations when the input signal does not change during a steady state. In a state where one of the first or second nodes connected to the transistor is precharged to the high voltage of the second voltage source, the connection between the second voltage source and one of the nodes in the precharged state is cut off. On the other hand, when the level of the input signal changes, the connection between the one node and the ground is cut off and the second voltage source is connected to the one node according to the level detection of the level detection circuit. The precharge circuit is controlled so as to precharge this one node to the high voltage of the second voltage source.

According to an eighth aspect of the present invention, in the level shift circuit according to the sixth aspect, the precharge control circuit controls the one of the first and second transistors that are in the OFF operation in a steady state when the input signal does not change. The corresponding one of the first or second P-type transistors is turned off and the corresponding one of the third or fourth N-type transistors is turned on. On the other hand, when the level of the input signal changes, the level detection circuit The one P-type transistor is turned on and the one N-type transistor is turned off in response to the level detection.

According to a ninth aspect of the present invention, in the level shift circuit according to the first or second aspect, a resistor connecting the second voltage source to the first node or the second node is provided when the input signal is stationary. It is characterized by having.

According to a tenth aspect of the present invention, in the level shift circuit according to the ninth aspect, the resistance value of the resistor is set so that a current value flowing from the second voltage source through its own resistor becomes substantially zero. It is characterized by being set to a resistance value.

According to an eleventh aspect of the present invention, in the level shift circuit according to the first aspect, the level detection circuit has a function of receiving a shutdown command signal and fixing an output logic when the first voltage source is shut down. It is characterized.

According to a twelfth aspect of the present invention, in the level shift circuit of the eleventh aspect, the level detection circuit can arbitrarily select an output logic to be fixed upon receiving a priority signal when the first voltage source is shut down. It is characterized by being.

According to a thirteenth aspect of the present invention, in the level shift circuit according to the first aspect, the level detecting circuit has an edge trigger configuration for detecting a potential drop of the first or second node when a clock signal changes. It is characterized.

According to a fourteenth aspect of the present invention, in the level shift circuit according to the first aspect, the test circuit receives a test signal in place of the input signal in a test mode, and the level detection circuit detects a potential drop corresponding to the test signal. It is characterized by having the function to do.

According to a fifteenth aspect of the present invention, in the level shift circuit according to the first aspect, the level detection circuit has a function of receiving a reset signal and resetting an output logic.

According to a sixteenth aspect, in the level shift circuit according to the first or fifteenth aspect, the level detection circuit has a function of receiving a set signal and setting an output logic.

According to a seventeenth aspect of the present invention, in the level shift circuit according to the first aspect, a function of receiving a control signal in addition to the input signal and changing an output of the level detection circuit to three states is provided. And

As described above, according to the first to seventeenth aspects of the present invention, the level detection circuit for detecting the potential drop of the first and second nodes is provided, and the switching level of the level detection circuit is set high. Therefore, when the potentials of the first and second nodes fall below the switching level of the level detection circuit, the level detection circuit detects the level and the output logic changes, so that the conventional logic is used. In addition, compared to a level shift circuit in which the output logic changes only when the potentials of the first and second nodes are fully swinged at a high voltage, the circuit operates with low power consumption and at high speed.

In particular, according to the fourth aspect of the invention, when the potentials of the first and second nodes decrease, the current flowing from the gates connected to the first and second nodes is small, and the potentials of these nodes decrease. Since the operation is performed earlier, the delay time is reduced, and the level shift circuit operates at high speed.

As described above, according to the level shift circuit of the present invention, the level detection circuit for detecting the decrease in the potential of the first and second nodes is provided, and the switching level of the level detection circuit is determined. Is set high, the level change can be detected at an early stage without waiting for the potentials of the first and second nodes to make a full swing at a high voltage, and a level shift circuit that operates at high speed with low power consumption is provided. it can.

In particular, according to the fourth aspect of the invention, since the reduction in the potentials of the first and second nodes is promoted, it is possible to provide a level shift circuit that operates at high speed with a reduced delay time.

Hereinafter, a level shift circuit according to an embodiment of the present invention will be described with reference to the drawings. First, a technique related to the present invention will be described first.

(Related technology of the present invention)
FIG. 1 is a diagram showing a specific configuration of a level shift circuit according to the related art of the present invention.

In the figure, IN is a signal input terminal, and INV0 is an inverter for inverting a signal input to the input terminal IN, and operates with a low voltage source (first voltage source) VDD of, for example, 1.5 V. . In the level shift circuit of FIG. 1, all the elements other than the inverter INV0 are high-voltage-side elements operated by a high-voltage source (second voltage source) VDD3 such as 3.3 V, for example.

In FIG. 1, N1 and N2 are a pair of N-type transistors, the sources of which are grounded. The input signal of the input terminal IN is input to the gate of one N-type transistor (first N-type transistor) N1, and the inverter INV0 is connected to the gate of the other N-type transistor (second N-type transistor) N2. Is input. P1 and P2 are a pair of P-type transistors, whose gates are cross-coupled to each other's drains, and whose drains are connected to the drains of the N-type transistors N1 and N2, respectively. The connection point between one of the P-type transistors (first P-type transistors) P1 and the first N-type transistor N1 is defined as a first node W1, and the other P-type transistor (second P-type transistor) P2 is defined as a connection point. A connection point with the N-type transistor N2 is defined as a second node W2.

Further, P3 and P4 are current interrupting transistors (current interrupting units) each including a pair of P-type transistors. The sources are connected to the high voltage source VDD3, and the drains are respectively connected to the sources of the P-type transistors P1 and P2. You. The connection point between the one current cut-off transistor (third P-type transistor) P3 and the first P-type transistor P1 is connected to a third node W3, and the other current cut-off transistor (fourth P-type transistor) P4 is connected to the third node W3. The connection point between the second P-type transistor P2 and the second P-type transistor P2 is defined as a fourth node W4. The second node W2 is connected to the gate of the one current cutoff transistor P3 via an inverter INV1, and the second node W2 is connected to the gate of the other current cutoff transistor P4 via an inverter INV1 and an inverter INV2. Node W2 is connected. The output terminal OUT is connected to the output side of the inverter INV2.

{Circle around (5)} In addition, P5 is a resistor composed of a P-type transistor whose gate is grounded, one end of which is connected to the third node W3, and the other end of which is connected to the fourth node W4.

The operation of the level shift circuit configured as described above will be described below.

{First, in a steady state where the potential of the signal at the input terminal IN is at the H (VDD) level, the N-type transistor N1 is ON and the P-type transistor P1 is OFF. Further, the N-type transistor N2 is OFF and the P-type transistor P2 is ON. The first node W1 is at 0 V, and the second node W2 is at the high voltage VDD3 potential (3.3 V). These operations are the same as those of the above-described conventional latch type level shift circuit. Further, one current cutoff transistor P3 is turned on and the other current cutoff transistor P4 is turned off by the potential (3.3 V) of the node W2. By turning on the one current cutoff transistor P3, the high voltage source VDD3 and the fourth node W4 are connected via the transistor (resistance) P5, and the fourth node W4 is pulled up to the high voltage of the high voltage source VDD3. Accordingly, the second node W2 is also pulled up to the high voltage of the high voltage source VDD3 via the P-type transistor P2 in the ON state. Therefore, the second and fourth nodes W2 and W4 are prevented from entering a high impedance state due to both the current cutoff transistor P4 and the N-type transistor N2 being in the OFF state. As a result, the logic of the output terminal OUT is fixed at the H (VDD3) level.

Next, when the input signal changes from the H (VDD) level to the L (VSS) level, the N-type transistor N2 is turned on. However, since the current cutoff transistor P4 is OFF, a through current does not flow from the high voltage source VDD3 through the P-type transistor P2 and the N-type transistor N2.

FIG. 2 shows the state of the current flowing immediately after the change of the input signal. In the figure, immediately after the input signal changes, the N-type transistor N2 is turned ON, so that the current Igp1 for discharging the gate capacitance Cgp1 of the P-type transistor P1 and the next-stage inverter Inv1 are provided at the second node W2. And a current Idp flowing from the high voltage source VDD3 through the current cutoff transistor P3, the resistor P5, and the P-type transistor P2. On the other hand, a current Idn flowing from the node W2 to the ground via the N-type transistor N2 flows out. Therefore,
Iginv + Igp1 = Idn-Idp
Holds. Here, the resistance value of the transistor (resistance) P5 is set to a sufficiently large value so that the through current ldp does not flow. This setting is performed in cooperation with the setting of the resistance values of the current cutoff transistor P3 and the P-type transistor P2 in the path through which the through current flows. With this setting, the current Idn is increased, and the currents Iginv and Igp1 are set smaller in order to ignore the through current Idp in the above equation and reduce the delay time by rapidly lowering the potential of the second node W2. Is good. That is, it is effective to set the gate capacitance Cgp1 of the P-type transistor P1 and the gate capacitance Cginv of the next-stage inverter Inv1 to be small.

Thereafter, when one P-type transistor P1 is turned on and the other P-type transistor P2 is turned off, and the logic of the latch unit is reversed, the output terminal is delayed by a predetermined delay time via the inverters INV1 and INV2. OUT is inverted to the L (0 V) level, one current cutoff transistor P3 is turned off, and the other current cutoff transistor P4 is turned on, and enters a state of waiting for the next input signal input change. Here, even if the current cutoff transistor P4 is turned on, the through current does not flow from the high voltage source VDD3 through these two transistors P4 and P2 because the P-type transistor P2 is already turned off. Further, even if both the current cutoff transistor P3 and the N-type transistor N1 are turned off, the current cutoff transistor P4 is turned on, so that the high voltage source VDD3 is connected to the third node W3 via the transistor (resistance) P5. Then, the fourth node W4 is pulled up to the high voltage of the high voltage source VDD3. Therefore, the first node W1 is also pulled up to the high voltage of the high voltage source VDD3 via the P-type transistor P1 in the ON state, and the first node W1 is prevented from entering the high impedance state.

Next, when the input signal changes from the L (VSS) level to the H (VDD) level, the N-type transistor N1 turns on. However, since the current cutoff transistor P3 is OFF, a through current does not flow from the high voltage source VDD3 via the P-type transistor P1 and the N-type transistor N1.

The state of the current flowing immediately after the change of the input signal is shown in FIG. In the drawing, immediately after the input signal changes, the N-type transistor N2 is turned off, so that the current -Igp1 for charging the gate capacitance Cgp1 of the P-type transistor P1 and the gate of the inverter Inv1 are supplied from the second node W2. The current -Iginv for charging the capacitance Cginv flows out, and the current Idp flows into the second node W2 from the high voltage source VDD3 via the current cutoff transistor P4 and the P-type transistor P2. Therefore,
Iginv + Igp1 = Idp
Holds. In order to shorten the delay time, it is desirable to increase the current Idp and set the current Igp1 and the current Iginv small. That is, it is effective to increase the sizes of the current cut-off transistor P4 and the P-type transistor P2 and reduce the gate capacitance of the next-stage inverter INV1.

From the above, the two P-type transistors P1 and P2 have an optimum value for matching the rise time and the fall time of the potential of the second node W2. In addition, when the size of the current cutoff transistors P3 and P4 is larger than those of the P-type transistors P1 and P2, the delay time can be further reduced.

In the related art, a resistor P5 connected to the third and fourth nodes W3 and W4 is arranged, and the resistor P5 prevents a high impedance state of the first and second nodes W1 and W2. The first and second nodes W1 and W2 do not require a conventional small latch. As a result, the drive capacity of each of the two N-type transistors N1 and N2 is reduced, so that the potential rise and fall speed of the second node W2 is increased, and the delay time is effectively reduced. In addition, since the N-type transistors N1 and N2 can be designed to have a small size and only the resistor 5 needs to be arranged instead of the conventional small latch, the layout area can be reduced.

The operation limit of the level shift circuit of the related art is that the resistance value of the transistor (resistance) P5 is very large,
VDD ≦ Vtn
(Vtn is the threshold voltage of the N-type transistors N1 and N2). Therefore, it is possible to increase the design margin.

(Modification)
4, 5, and 6 show modifications of the related technology.

FIG. 4 shows a modification of the arrangement position of the transistor (resistor) P5. According to the related art, when one P-type transistor (for example, P4) is in an OFF state, the other ON-state P-type transistor P3 is in an ON state, and the P-type transistor P3 is turned ON. Although the second and fourth nodes W2 and W4 are pulled up to the high voltage of the high voltage source VDD3, in the present modification, a pull-up resistor (first resistor) P51 of the nodes W1 and W3 and a node W2 , W4 and a pull-up resistor (second resistor) P52. These resistors are constituted by P-type transistors and are connected to the high voltage source VDD3. Then, a signal obtained by inverting a signal for controlling the transistors P3 and P4 (the potential of the second node W2 and the potential obtained by inverting this potential) so that the P-type transistors P3 and P4 are turned on when each of them is in the off state. Are used to control the P-type transistors (resistors) P51 and P52. The functions performed by the resistors P51 and P52 are the same as those of the resistor (transistor) P5 of the related art, and a description thereof will be omitted.

FIG. 5 is a further modification of the modification of FIG. That is, in the level shift circuit of FIG. 5, the resistors P51 and P52 for node pull-up are connected to the high voltage source VDD3 via the resistor P60 formed of a P-type transistor. The function of this modification is the same as that of the modification of FIG.

FIG. 6 shows a level shift circuit having a function of fixing the output logic when the internal low-voltage power supply is shut down. The level shift circuit shown in FIG. 6 is based on the level shift circuit shown in FIG. 1 and further includes an input terminal SD for receiving a low-voltage power supply shutdown command signal, a P-type transistor P65, and an N-type transistor N66. ing. The P-type transistor P65 is connected to the high voltage source VDD3 and the second node W2, and has a gate to which the shutdown command signal (L level) input to the input terminal SD is input. The N-type transistor N66 has a drain connected to the sources of the N-type transistors N1 and N2, a source grounded, and a gate to which a shutdown command signal of the input terminal SD is input.

Therefore, in the present modification, at the time of a low voltage power supply shutdown command, the N-type transistor 66 is turned off, the connection between the second node W2 and the ground is cut off, and the P-type transistor P65 is turned on. Node W2 is forcibly connected to the high voltage source VDD3, and the logic of the output terminal OUT can be fixed at the H (VDD3) level.

(Embodiment of the present invention)
Hereinafter, a level shift circuit according to an embodiment of the present invention will be described with reference to FIG.

FIG. 7 shows the overall configuration of the level shift circuit according to the present embodiment. The present embodiment is characterized in that the level conversion circuit does not employ a latch structure including two transistors having a gate connected to the other drain for level conversion as compared with the level shift circuit of the related art. The details will be described below.

In FIG. 7, IN is an input terminal, and INV0 is an inverter for inverting a signal input to the input terminal IN, and operates with a low voltage source (first voltage source) (VDD). In the level shift circuit of FIG. 7, all the elements other than the inverter INV0 operate on the high voltage source (second voltage source) VDD3.

In FIG. 7, N1 and N2 are a pair of N-type transistors receiving mutually complementary signals, and one N-type transistor (first transistor) N1 receives a signal of the input terminal IN at its gate, The other N-type transistor (second transistor) N2 receives at its gate the inverted signal from the inverter INV0. The sources of these N-type transistors N1 and N2 are grounded, and the drains are connected to the first and second nodes W1 and W2, respectively. Therefore, when one of the N-type transistors N1 or N2 is ON, the first or second node W1, W2 is grounded, and the potential of the first or second node W1, W2 is reduced to L (0v) level. Let it.

A precharge circuit B operates as a supply circuit 40 including a pair of P-type transistors P3 and P4, an intermittent circuit 50 including a pair of N-type transistors N3 and N4, and a resistor. And a P-type transistor P5. One P-type transistor (first P-type transistor) P3 has a source connected to the high-voltage source VDD3 and a drain connected to the first node W1. The other P-type transistor (second P-type transistor) P4 has a source connected to the high voltage source VDD3 and a drain connected to the second node W2. When one of the P-type transistors P3 or P4 is turned on, the high voltage source VDD3 is connected to the first or second node W1, W2, and the potential of the first or second node W1, W2 is changed to the high voltage source. It is precharged to a high voltage of VDD3.

In the precharge circuit B, one N-type transistor (third N-type transistor) N3 is disposed between the first node W1 and the N-type transistor N1 in FIG. (Fourth N-type transistor) N4 is arranged between the second node W2 and the N-type transistor N2. When these N-type transistors N3 and N4 are precharged by the P-type transistors P3 and P4, the corresponding first or second nodes W1 and W2 are connected to ground via the N-type transistors N1 and N2, respectively. To prevent Further, the P-type transistor P5 is connected to the drains (first and second nodes W1, W2) of the two P-type transistors P3, P4. In the P-type transistor P5, similarly to the related art, the high voltage source VDD3 is connected to the first or second node W1, W2, and the first and second nodes W1, W2 do not enter a high impedance state. So that it is arranged.

Further, A is a control circuit which detects that the first or second node W1, W2 has dropped to the L (0v) level and, after this detection, switches the first or second node W1, W2. It has a function of precharging to the H (VDD3) level. FIG. 8 shows the internal configuration of the control circuit A.

(8) The control circuit A in FIG. 8 includes a flip-flop circuit FF and a precharge control circuit 70 having two inverters INV1 and INV2. The flip-flop circuit (level detection circuit) FF has first and second two-input NAND circuits Nand1 and Nand2. The first NAND circuit Nand1 receives the potential of the first node W1 and the output signal of the second NAND circuit Nand2, and the second NAND circuit Nand2 receives the potential of the second node W2 and the first node W2. An output signal of NAND circuit Nand1 is received. The outputs of the first and second Nand circuits become the outputs of the flip-flop circuit FF. Therefore, when the first node W1 goes to L (0v) level, the output of the first NAND circuit Nand1 goes to H (VDD3) level and the output of the second NAND circuit Nand2 goes to L (0v) level. On the other hand, when the second node W2 goes to L (0v) level, the output of the second NAND circuit Nand2 is at H (VDD3) level, and the output of the first NAND circuit Nand1 is at L (0v) level. It becomes.

The precharge control circuit 70 of the control circuit A controls the precharge operation of the precharge circuit B. One inverter INV1 outputs the output of the first NAND circuit Nand1 of the flip-flop circuit FF. The precharge circuit B outputs the inverted signal to the gates of the P-type and N-type transistors P3 and N3 of the precharge circuit B. The other inverter INV2 receives and inverts the output of the second NAND circuit Nand2 of the flip-flop circuit FF, and outputs the inverted signal to the gates of the P-type and N-type transistors P4 and N4 of the precharge circuit B. .

Next, the operation of the level shift circuit according to the present embodiment will be described.

(4) In a steady state, the potentials of the first and second nodes W1 and W2 are both at the H (VDD3) level. When the input signal is at the H (VDD3) level, the N-type transistors N1 and N2 are turned ON and OFF, respectively, and the two outputs of the flip-flop circuit FF (the outputs of the first and second NAND circuits Nand1) are H ( VDD3) level and L (0v) level, and retains its logic. At this time, the N-type transistors N3 and N4 are OFF and ON, respectively, and the P-type transistors P3 and P4 are ON and OFF, respectively. The N-type transistors N1 and N3 and the N-type transistors N2 and N4 have complementary logic.

In the above state, for example, when the input signal changes from the H (VDD) level to the L (0v) level, the N-type transistor N2 is turned on. At this time, in the precharge circuit B, the N-type transistor N4 is in the ON state, but the P-type transistor P4 is in the OFF state. Therefore, the high voltage source VDD3 is grounded via these three transistors P4, N4, N2. No through-current flows through the circuit. In this case, a current as shown in FIG. 9 flows. That is, immediately after the input signal changes, the N-type transistor N2 is turned ON, so that the current Idn flowing from the second node W2 to the ground via the N-type transistors N4 and N2 flows out, and the second node W2 , A current Igand2 for discharging the gate capacitance Cgand2 of the second NAND circuit Nand2 in the flip-flop circuit FF, and a current Idp flowing through the P-type transistors P3 and P5 flow. Therefore,
Ignd2 = Idn-Idp
Holds. Here, if the through current Idp does not flow, that is, if the resistance value of the P-type transistor (resistance) P5 is sufficiently large, the through current Idp can be ignored. Therefore, in order to reduce the delay time by lowering the potential of the second node W2 quickly, it is preferable to set the current Idn to be large and the current Ignand2 to be small. Specifically, it is effective to set the gate capacitance Cgand2 of the NAND circuit Nand2 of the flip-flop circuit FF to be small. Further, since the current Idp is a current flowing through the two transistors P3 and P5, it is easy to keep this current value small.

Thereafter, the decrease in the potential of the second node W2 proceeds, the logic of the flip-flop circuit FF is reversed, the output of the NAND circuit Nand2 goes to the H (VDD3) level, and the output of the NAND circuit Nand1 goes to the L (0v) level. Since the N-type transistor N4 is turned off and the P-type transistor P4 is turned on, the second node W2 is precharged to the H (VDD3) level by the high voltage source VDD3. Since the precharge operation is performed by the P-type transistor P4, the speed is high. On the other hand, the P-type transistor P3 is turned off to stop precharging from the high voltage source VDD3 to the first node W1, and the N-type transistor N3 is turned on to turn off the first node W1. And waits for the next input signal change. In this state, since the high voltage of the high voltage source VDD3 is applied to the first node W1 via the P-type transistor P4 and the resistor P5 in the ON state, the potential of the first node W1 becomes the H (VDD3) level, The high impedance state of the first node W1 associated with the turning off of the P-type transistor P3 and the N-type transistor N1 is prevented.

動作 The operation when the input signal changes from the L (0 v) level to the H (VDD) level is the same as the above-described operation, and a description thereof will be omitted.

(4) Here, the switching levels of the two NAND circuits Nand1 and Nand2 of the flip-flop circuit FF are set high. Therefore, when the N-type transistors N1 and N2 are turned on, the potential of the corresponding first or second node W1 or W2 does not need to be fully swung from the H (VDD3) level to the L (0v) level, and the full swing is performed. As compared with the conventional level shift circuit which needs to be operated, higher speed operation with lower power consumption is possible.

Also, since the N-type transistors N1 and N2 need only drive only the gate capacitances of the corresponding NAND circuits Nand1 and Nand2 of the flip-flop circuit FF, the transistors N1 and N2 can be reduced in size. It is. Therefore, the layout area can be reduced.

The operation limit of the level shift circuit of the present embodiment is as follows, assuming that the resistance value of the P-type transistor (resistance) P5 is very large.
VDD ≧ Vtn
Therefore, it is possible to increase the design margin.

(First Modification)
10 and 11 show a first modification of the above embodiment. In the level shift circuit of FIG. 10, the control circuit A is configured by a small number of transistors. That is, as can be understood from comparison with the level shift circuit of FIG. 8, the two inverters INV1 and INV2 are omitted, and one of the P-type and N-type transistors P3 and N3 is controlled by the output of the NAND circuit Nand2. , And the other P-type and N-type transistors P4 and N4 are controlled by the output of the NAND circuit Nand1. Therefore, the level shift circuit in FIG. 10 can perform the same operation as the level shift circuit in FIG. 8 with a small number of transistors.

In the level shift circuit shown in FIG. 11, the flip-flop circuit is composed of two NOR circuits Nor1 and Nor2, and the inverters INV10 and INV11 are arranged in front of these NOR circuits. Further, like the level shift circuit of FIG. 10, the two inverters INV1 and INV2 of the precharge control circuit 70 are omitted. Therefore, in the level shift circuit of FIG. 11, the same operation as that of the level shift circuit of FIG. 8 is performed, and the drive capacity of the two NOR circuits Nor1 and Nor2 decreases due to the presence of the two inverters INV10 and INV11. Thus, the operation speed of the flip-flop circuit increases.

(Second Modification)
12 to 16 show a second modification of the above embodiment. In the level shift circuit of FIG. 12, when the low-voltage source VDD is shut down, a function of fixing the logic of the flip-flop circuit to the logic before the shutdown is added. Specifically, when a shutdown command signal (H (VDD3) level) is received at the terminal SD, the precharge circuit B is operated by the two NOR circuits Nor3 and Nor4 to cause the first and second nodes to operate. Both W1 and W2 are fixed at the H (VDD3) level, and the outputs of the two NAND circuits Nand1 and Nand2 of the flip-flop circuit are fixed.

Similarly, the level shift circuit in FIG. 13 has a function of fixing the logic of the flip-flop circuit to the logic before the shutdown when the low voltage source VDD is shut down. The difference from the level shift circuit of FIG. 12 is that the flip-flop circuit is composed of two NOR circuits Nor1 and Nor2, and that the terminal SD receives a shutdown command signal (H (VDD3) level). By the two NOR circuits Nor5 and Nor6, the outputs of the two NOR circuits Nor1 and Nor2 of the flip-flop circuit before the shutdown of the low-voltage source are turned on irrespective of the levels of the first and second nodes W1 and W2. This is fixed to logic. Further, in the level shift circuit of FIG. 13, the P-type transistor (resistor) P5 is turned off by the shutdown command signal (H (VDD3) level). This is to prevent a through current from flowing through, for example, the P-type transistor P3 and the N-type transistors N4 and N2 when these transistors are ON and the P-type transistor P5.

In the level shift circuit of FIG. 14, when the low-voltage source VDD is shut down, the logic of the flip-flop circuit is forcibly fixed to the L (0 V) level in the NAND circuit Nand1 and to the H (VDD3) level in the NAND circuit Nand2. It is. That is, the level shift circuit of FIG. 14 further adds an inverter INV12 to the level shift circuit of FIG. 12, and inverts the shutdown signal (H (VDD3) level) input to the terminal SD by the inverter INV12. Is input to the NAND circuit Nand2 of the flip-flop circuit, and the output of the NAND circuit Nand2 is fixed at the H (VDD3) level. The shutdown signal is supplied to the P-type transistor P3 and the N-type transistor N3 and the P-type transistor P4 and the N-type transistor N4 via the NOR circuits Nor3 and Nor4, and the potentials of the first and second nodes W1 and W2 become H ( VDD3) level.

In the level shift circuit of FIG. 15, the flip-flop circuit of the level shift circuit of FIG. 14 is configured by two NOR circuits Nor1 and Nor2 and two inverters INV10 and INV11. It has a configuration input to the NOR circuit Nor2. This level shift circuit also has the same function as the level shift circuit of FIG.

The level shift circuit of FIG. 16 is configured to have the same function as the level shift circuit of FIGS. 14 and 15 in another configuration. That is, an inverter INV12 and a NOR circuit Nor5, and inverters INV13 and INV14 are respectively arranged in front of two NAND circuits Nand1 and Nand2 which constitute a flip-flop circuit, and a shutdown signal from a terminal SD is input to the NOR circuit Nor5. It was done.

(Third Modification)
FIGS. 17 and 18 show a third modification of the above embodiment. These have a function of enabling the output logic of the level shift circuit to be arbitrarily switched when the low voltage source VDD is shut down. In the level shift circuit of FIG. 17, based on the configuration of FIG. 16, a NAND circuit Nand3 is arranged instead of the inverter INV14 of the level shift circuit of FIG. 16, another NAND circuit Nand4 is arranged, and a priority signal is received. A terminal PR is provided. The NAND circuit Nand4 receives a shutdown signal (H (VDD3) level) from the terminal SD and a priority signal from the terminal PR, and its output is input to the NAND circuit Nand3.

Therefore, in the level shift circuit of FIG. 17, when the shutdown signal is input, the priority signal to the terminal PR is changed to the H (VDD3) level and the L (0v) level, so that the output of the NAND circuit Nand3 is changed to the H level. By switching to the L level, the logic of the NAND circuit Nand2 of the flip-flop circuit can be switched between the H (VDD3) level and the L (0v) level. In this level shift circuit, the other NAND circuit Nand1 of the flip-flop circuit is always fixed at the H (VDD3) level.

In the level shift circuit of FIG. 18, the level shift circuit of FIG. 17 is improved so that the other NAND circuit Nand1 of the flip-flop circuit can be switched between the H (VDD3) level and the L (0v) level according to the priority signal. It was done. Specifically, an inverter INV15 and two NAND circuits Nand5 and Nand6 are separately arranged. To one NAND circuit Nand5, a priority signal from a terminal PR is input via the inverter INV15, and a shutdown signal (H (VDD3) level) is input from a terminal SD. The output of this NAND circuit Nand5 is input to another NAND circuit Nand6.

Therefore, in this level shift circuit, by changing the priority signal of the terminal PR between the H (VDD3) level and the L (0v) level, the output logic of the NAND circuits Nand5 and Nand6 is switched, and the NAND circuit of the flip-flop circuit is switched. The output logic of Nand1 can also be switched between the H (VDD3) level and the L (0v) level.

(Fourth modification)
19 to 21 show a fourth modification of the above embodiment. These are level shift circuits of the edge trigger type.

In the level shift circuit of FIG. 19, a first flip-flop circuit FF1 receiving the clock signal CLK and the potential of the first node W1, and a second flip-flop circuit receiving the clock signal CLK and the potential of the second node W2 FF2 and a third flip-flop circuit FF3 receiving the outputs of the flip-flop circuits FF1 and FF2.

In the level shift circuit of FIG. 19, when the clock signal CLK is at the L level, the first and second flip-flop circuits FF1 and FF2 are in a reset state, and the precharge circuit B is controlled by the NAND circuit Nand7 and the inverter INV15. The first and second nodes W1 and W2 are precharged to the high voltage of the high voltage source VDD3. Further, the third flip-flop circuit FF3 is in a level holding state. Thereafter, when the clock signal transits to the H level, the two P-type transistors P3 and P4 are turned off by the NAND circuit Nand7 and the inverter INV15 to stop the precharge, and the two N-type transistors N3 and N4. Turns on, the first or second node W1, W2 drops to the L (0v) level according to the level of the input signal at the terminal IN, and this is taken into the first or second flip-flop circuit FF1, FF2. Then, the logic of the flip-flop circuit FF3 is set. When the loading is completed, the precharge circuit B precharges the first and second nodes W1 and W2 again to the high voltage of the high voltage source VDD3 by the NAND circuit Nand7 and the inverter INV15.

FIG. 20 is an improvement of the level shift circuit of FIG. 19, in which two N-type transistors N3 and N4 of the level shift circuit of FIG. 19 are shared by one N-type transistor N5.

レ ベ ル The level shift circuit of FIG. 21 is a modification of the level shift circuit of FIG. That is, by disposing other N-type transistors N7 and N8 between the first and second nodes W1 and W2 and the N-type transistors N3 and N4, and controlling these N-type transistors by the clock signal CLK, When the clock signal CLK rises to the H level, these N-type transistors N7 and N8 are turned on to change the logic level of the first or second node W1 or W2 according to the input signal of the terminal IN. is there.

(Fifth Modification)
FIGS. 22 and 23 show a level shift circuit in which a test mode function is further added to the level shift circuit of the edge trigger type shown in FIG.

During the test, the level shift circuit of FIG. 22 turns off the two N-type transistors N10 and N11 by a test mode signal (L level) input to the terminal NT, and inputs the normal input signal (the input terminal IN). Input signals), the two N-type transistors N1 and N2 operating in accordance with the input signals are separated from the P-type transistors P3 and P4, and the test mode signal is inverted by an inverter INV16. The transistors N12 and N13 are turned on, and two N-type transistors N14 and N15 operating according to the test signal input to the terminal INT and the inverted signal of the inverter INV17 are connected to the P-type transistors P3 and P4. In the test mode, the first and second nodes W1 and W2 are supplied by the test signal at the terminal INT. It is obtained so as to change the logic level.

The level shift circuit in FIG. 23 is an improvement of the level shift circuit in FIG. That is, similarly to the N-type transistor N5 for grounding two N-type transistors N1 and N2 for normal use, an N-type transistor N16 for grounding two N-type transistors N14 and N15 for test mode is provided, and the terminal NT , The output of the NAND circuit Nand8 and the output of the NOR circuit Nor6 are controlled by the test mode signal (L level) input thereto, and the N-type transistor N5 for normal use is output to the output of the NAND circuit Nand8 of the precharge control circuit 70 at normal times. In the test mode, the N-type transistor N16 for the test mode is ON / OFF controlled in accordance with the output of the NOR circuit Nor6 of the precharge control circuit 70.

(Sixth modification)
24 and 25 show a sixth modification of the above embodiment.

The level shift circuit of FIG. 24 is obtained by further adding a reset function to the edge trigger type level shift circuit of FIG.

That is, in the level shift circuit of FIG. 24, the reset signal input to the reset terminal R is input to one NOR circuit Nor7 of the flip-flop circuit FF3 via the inverter INV18 to fix the output logic and to output the reset signal. To the NAND circuit Nand9, and the precharge circuit B precharges the first and second nodes W1 and W2 to the high voltage of the high voltage source VDD3.

The level shift circuit shown in FIG. 25 is obtained by further adding a set function to the level shift circuit shown in FIG. That is, in the level shift circuit of FIG. 25, the set signal input to the set terminal S is input to the other NOR circuit Nor8 of the flip-flop circuit FF via the inverter INV19, and the output logic is fixed and the set signal is To the NAND circuit Nand9, and the precharge circuit B precharges the first and second nodes W1 and W2 to the high voltage of the high voltage source VDD3.

(Seventh modification)
FIG. 26 shows a seventh modification of the above embodiment. The level shift circuit shown in the figure constitutes a tri-state level shift circuit.

That is, the level shift circuit of FIG. 26 creates a state of “H, H” in addition to “H, L” and “L, H” as a combination of the levels of the output terminals OUT1 and OUT2. Specifically, one more N-type transistor N17 is provided corresponding to the pair of N-type transistors N1 and N2, and one more P-type transistor P6 is provided corresponding to the pair of P-type transistors P3 and P4. Further, one N-type transistor N18 is further provided corresponding to the pair of N-type transistors N3 and N4. Further, a P-type transistor (resistance) P7 is provided corresponding to the P-type transistor (resistance) P5.

{Circle around (2)} Normally, the input signal of the terminal C is set to the L (0 V) level, the N-type transistor N18 is turned off, and the node W3 is held in the precharged state. In this state, the pair of N-type transistors N1 and N2 are turned ON or OFF through the NAND circuits Nand10 and Nand11 according to the input signal of the terminal IN and its inverted signal, and the control circuit 30 controls the logic of the pair of output terminals OUT1 and OUT2. The level is set to “H, L” or “L, H”. On the other hand, when controlling the logic levels of the output terminals OUT1 and OUT2 to “H, H”, the input signal of the terminal C is set to the H (VDD) level. As a result, the N-type transistor N17 is turned on, the node W3 is set to the L (0v) level, and the control circuit 30 changes the logic levels of the pair of output terminals OUT1 and OUT2 to "H, H" in response to the potential drop of the node W3. ”Is controlled. Incidentally, Nand12 in the figure constitutes a precharge control circuit 70 for controlling precharge of the nodes W1, W2, W3.

(Eighth Modification)
27 to 29 show an eighth modification of the above embodiment.

These level shift circuits are improved circuits for generating complementary signals input to a pair of N-type transistors N1 and N2 in the level shift circuit shown in FIG. That is, in the level shift circuit of FIG. 8, the delay time of the control circuit A is short, and the delay time required for a series of changes from the change of the input signal to the setting of the flip-flop circuit FF and the precharge to the high voltage VDD3. However, if the delay time is shorter than the delay time of the inverter INV0 on the low voltage VDD side, the first or second nodes W1 and W2 to be precharged may be erroneously discharged. That is, as shown in FIG. 31, when the state in which the input signal waveforms to the pair of N-type transistors N1 and N2 are both at the H level at the same time is long and the delay time of the control circuit A is short, the first and second , The nodes W1 and W2 are alternately discharged and precharged, and a pulse-like output waveform is erroneously output to the output terminal. In particular, when the input signal transitions from the H level to the L level, the input system is constituted by a high breakdown voltage transistor, the output system is constituted by a low breakdown voltage transistor, and the delay time is higher in the high breakdown voltage system than in the lower breakdown voltage system. It is considered that a malfunction occurs when the length is very long. In this modified example, in order to prevent this malfunction, one of the complementary signals to the pair of N-type transistors N1 and N2 must be changed to L level before the other of the complementary signals is set to H level. The configuration is such that one and the other of the complementary signals do not simultaneously go high.

The level shift circuit of FIG. 27 receives, instead of the inverter INV0 of FIG. 8, an inverter INV27, a delay circuit including two inverters INV28 and INV29, and the output of the inverter INV29 and the output of the first-stage inverter INV27. A complementary input signal is generated by the NOR circuit Nor27.

In the level shift circuit of FIG. 28, two inverters INV30 and INV31 and a flip-flop circuit FF4 generate a complementary input signal.

Further, in the level shift circuit of FIG. 29, complementary input signals are generated by two Schmitt circuits SchA and SchB, an inverter INV32, and a flip-flop circuit FF4, and as shown in FIG. The switching level of the circuit SchA is set low, and the switching level of the other Schmitt circuit SchB is set high.

In the above description, the level shift circuit that converts a low-voltage logic level to a high-voltage logic level has been described. However, the present invention is not limited to this. Needless to say, the same can be applied to a level shift circuit that converts the level into a level. In this case, the first voltage source becomes a high voltage source, and the second voltage source becomes a low voltage source.

As described above, according to the present invention, the level detection circuit for detecting the potential drop of the first and second nodes is provided, and the switching level of the level detection circuit is set to be high, so that the level of the first and second nodes is reduced. Since a level change can be detected early without waiting for the potential to make a full swing at a high voltage, it is useful as a level shift circuit or the like which operates with low power consumption and operates at high speed.

FIG. 2 is a diagram illustrating a configuration of a level shift circuit according to a related technique of the present invention. FIG. 4 is an explanatory diagram of a current flowing through the same level shift circuit when an input signal changes from H level to L level. FIG. 4 is an explanatory diagram of a current flowing through the same level shift circuit when an input signal changes from L level to H level. FIG. 11 is a diagram illustrating a modification of the arrangement position of the resistors in the level shift circuit according to the related art. FIG. 14 is a diagram illustrating another modified example of the same level shift circuit. FIG. 13 is a diagram illustrating a modification of the same level shift circuit, and illustrating a level shift circuit having a fixed output logic configuration when the internal power supply is shut down. FIG. 1 is a diagram illustrating a schematic configuration of a level shift circuit according to an embodiment of the present invention. FIG. 3 is a diagram showing a specific configuration of the same level shift circuit. FIG. 4 is an explanatory diagram of a current flowing through the same level shift circuit when an input signal changes from H level to L level. FIG. 11 shows a first modification of the embodiment of the present invention, and is a diagram in which a precharge control circuit provided in a level shift circuit is modified. FIG. 14 shows a first modification of the embodiment, and is a diagram in which a flip-flop circuit provided in a level shift circuit is modified. FIG. 13 is a diagram illustrating a second modification of the embodiment of the present invention, and illustrating a configuration of a level shift circuit having a function of fixing logic when a low-voltage source is shut down. FIG. 14 is a diagram illustrating another configuration of the level shift circuit according to the second modified example. FIG. 15 is a diagram illustrating still another configuration of the level shift circuit according to the second modified example. FIG. 14 is a diagram illustrating another configuration of the level shift circuit according to the second modification. FIG. 14 is a diagram illustrating still another configuration of the level shift circuit according to the second modified example. FIG. 14 is a diagram illustrating a third modification of the embodiment of the present invention and illustrating a configuration of a level shift circuit having a function of outputting a predetermined logic preferentially when a low-voltage source is shut down. FIG. 15 is a diagram illustrating another configuration of the level shift circuit according to the third modification. FIG. 14 is a diagram illustrating a configuration of an edge-triggered level shift circuit according to a fourth modification of the embodiment of the present invention. FIG. 21 is a diagram illustrating another configuration of the edge-triggered type level shift circuit according to the fourth modified example. FIG. 21 is a diagram illustrating still another configuration of the edge-triggered level shift circuit according to the fourth modified example. It is a figure showing the composition of the edge trigger type level shift circuit with the test mode function of the 5th modification of an embodiment of the invention. FIG. 14 is a diagram illustrating another configuration of an edge trigger type level shift circuit with a test mode function according to the modification. FIG. 14 is a diagram illustrating a configuration of an edge-triggered level shift circuit with a reset function according to a sixth modification of the embodiment of the present invention. It is a figure which shows the structure which added the set function to the edge trigger type level shift circuit with the reset function of the modification. FIG. 21 is a diagram illustrating a configuration of a tri-state level shift circuit according to a seventh modification of the embodiment of the present invention. FIG. 15 is a diagram illustrating a configuration of a level shift circuit according to an eighth modification of the embodiment of the present invention. FIG. 14 is a diagram illustrating another configuration of the level shift circuit according to the modification. FIG. 14 is a diagram illustrating still another configuration of the level shift circuit according to the modification. FIG. 3 is a diagram showing the operation of the same level shift circuit. FIG. 4 is a diagram illustrating an input waveform and an output waveform that can occur in the level shift circuit according to the embodiment of the present invention. FIG. 9 is a diagram illustrating a configuration of a conventional level shift circuit. FIG. 3 is a diagram illustrating a current flowing when the level shift circuit operates. FIG. 13 is a diagram illustrating a configuration of another conventional level shift circuit.

Explanation of reference numerals

IN input terminal VDD low voltage source (first voltage source)
VDD3 High voltage source (second voltage source)
N1 N-type transistor (first N-type transistor)
N2 N-type transistor (second N-type transistor)
P1 P-type transistor (first P-type transistor)
P2 P-type transistor (second P-type transistor)
P3 P-type transistor (third P-type transistor, current interrupt section)
P4 P-type transistor (fourth P-type transistor, current cutoff part)
P5 P-type transistor (resistance)
P51 P-type transistor (first resistor)
P52 P-type transistor (second resistor)
INV0, INV1, INV2 Inverter W1 First node W2 Second node W3 Third node W4 Fourth node A Control circuit B Precharge circuit FF Flip-flop circuit (level detection circuit)
Nand1, Nand2 NAND circuit 40 Supply circuit 50 Intermittent circuit 70 Precharge control circuit P3 P-type transistor (first P-type transistor)
P4 P-type transistor (second P-type transistor)
N3 N-type transistor (third N-type transistor)
N4 N-type transistor (fourth N-type transistor)
SD Shutdown terminal CLK Clock terminal NT Test mode terminal INT Test terminal R Reset terminal S Set terminal C Control terminal 30 Control circuit

Claims (17)

First and second transistors that are supplied with a complementary signal having the first voltage source as a power source, one end of which is grounded, and the other end of which is connected to the first and second nodes, respectively;
A precharge circuit for precharging the first and second nodes to a potential of a second voltage source;
A level detection circuit for detecting a drop in potential of the first and second nodes;
And a precharge control circuit for controlling the precharge circuit. The level detection circuit includes:
The level shift circuit according to claim 1, further comprising a flip-flop circuit connected to the first and second nodes. The level detection circuit includes:
3. The level shift circuit according to claim 1, wherein the switching level is set high so that the potential drop of the first and second nodes is detected early when the potential drops. The level detection circuit includes:
The capacitance of a gate connected to the first and second nodes is set to be small so that when the potentials of the first and second nodes decrease, the potential decreases quickly. Or the level shift circuit according to 2. The precharge circuit,
A supply circuit for connecting the second voltage source to the first and second nodes;
The level shift circuit according to claim 1, further comprising: an intermittent circuit that cuts off and connects between the first node and ground and between the second node and ground. The supply circuit includes:
A first P-type transistor disposed between the second voltage source and the first node; and a second P-type transistor disposed between the second voltage source and the second node. Type transistor,
The shutoff circuit,
A third N-type transistor disposed between the first node and ground; and a fourth N-type transistor disposed between the second node and ground. The level shift circuit according to claim 5. The precharge control circuit includes:
In a steady state where the input signal does not change, a state in which one of the first or second node connected to the one of the first or second transistor that is operating OFF is precharged to the high voltage of the second voltage source. Disconnecting the connection between the second voltage source and one of the nodes in the precharged state;
When the level of the input signal changes, the connection between the one node and the ground is cut off and the second voltage source is connected to the one node in response to the level detection of the level detection circuit. The level shift circuit according to claim 1, wherein the precharge circuit is controlled so as to precharge one node to a high voltage of a second voltage source. The precharge control circuit includes:
In a steady state in which the input signal does not change, one of the first or second P-type transistors corresponding to one of the first or second transistors operating OFF is turned off and the corresponding third or fourth P-type transistor is turned off. Turn on the N-type transistor,
7. The device according to claim 6, wherein when the level of the input signal changes, the one P-type transistor is turned on and the one N-type transistor is turned off in accordance with the level detection of the level detection circuit. Level shift circuit. The level shift circuit according to claim 1, further comprising: a resistor that connects the second voltage source to the first node or the second node when the input signal is stationary. The resistance value of the resistor is
The level shift circuit according to claim 9, wherein a high resistance value is set so that a current value flowing from the second voltage source via its own resistance becomes substantially zero. The level detection circuit includes:
The level shift circuit according to claim 1, wherein the level shift circuit has a function of receiving a shutdown command signal and fixing an output logic when the first voltage source is shut down. The level detection circuit includes:
The level shift circuit according to claim 11, wherein upon shutting down the first voltage source, a priority signal is received, and an output logic to be fixed can be arbitrarily selected. The level detection circuit includes:
2. The level shift circuit according to claim 1, wherein the level shift circuit has an edge trigger configuration for detecting a potential drop of the first or second node when a clock signal changes. 2. The level shift circuit according to claim 1, wherein the level shift circuit has a function of receiving a test signal instead of the input signal in a test mode, and detecting a potential drop corresponding to the test signal by the level detection circuit. The level detection circuit includes:
2. The level shift circuit according to claim 1, wherein the level shift circuit has a function of resetting output logic in response to a reset signal. The level detection circuit includes:
16. The level shift circuit according to claim 1, having a function of receiving a set signal and setting an output logic. The level shift circuit according to claim 1, wherein the level shift circuit has a function of changing an output of the level detection circuit into three states in response to a control signal in addition to the input signal.

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