JP2004007024A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2004007024A
JP2004007024A JP2003343960A JP2003343960A JP2004007024A JP 2004007024 A JP2004007024 A JP 2004007024A JP 2003343960 A JP2003343960 A JP 2003343960A JP 2003343960 A JP2003343960 A JP 2003343960A JP 2004007024 A JP2004007024 A JP 2004007024A
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film
resistor
heat
circuit board
chip
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Hiroyuki Sakai
酒井　啓之
Yoshito Ikeda
池田　義人
Toshimichi Ota
太田　順道
Kaoru Inoue
井上　薫
Katsunori Nishii
西井　勝則
Takayuki Yoshida
吉田　隆幸
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

<P>PROBLEM TO BE SOLVED: To prevent rapturing of a resistor film, related to a circuit board comprising the resistor film on a dielectric film, by eliminating a local thermal expansion at the dielectric film which is caused by generation of heat from the resistor. <P>SOLUTION: A heat dissipation conductor film 4 is provided on a BCB film 3 which is a dielectric film of a micro strip line, on which a resistor film 6 is formed through a silicone oxide film and a inter-layer insulating film 4 constituted by the silicone nitride film. The resistor sheet 6 is connected to a wiring conductor sheet 7. The heating of the resistor film 6 is quickly dispersed from the entire heat-dissipation conductor film 4 to a wide area, to suppress local thermal expansion of the BCB film 3. Thus the tensile stress and bending stress which the resistor film 6 receives are reduced to prevent rapture of the resistor film 6. <P>COPYRIGHT: (C)2004,JPO

Description

　本発明はマイクロストリップ線路を用いた回路基板、及びチップ実装を用いた半導体装置と実装方法に関するものであり、特に準ミリ波〜ミリ波領域で使用する高周波半導体装置およびその集積回路に関するものである。 The present invention relates to a circuit board using a microstrip line, a semiconductor device using a chip mounting, and a mounting method, and particularly to a high-frequency semiconductor device used in a quasi-millimeter wave to a millimeter wave region and an integrated circuit thereof. .

　近年、情報通信分野の進展は著しく、扱う周波数帯もマイクロ波帯からミリ波帯へとより高い周波数への展開が図られている。それに伴ってこれらの通信機器に用いられるトランジスタの高速化も著しく、最近ではヘテロ接合化合物半導体トランジスタなどで１００ＧＨｚを越えるカットオフ周波数をもつデバイスが実現されている。ところが、このようなマイクロ波〜ミリ波の高周波になると、トランジスタ特性もさることながら、回路実現のための実装方法が問題になる。たとえば実装工程を経た後に寄生容量や寄生インダクタンスが新たに生じることが多く、これらの寄生成分が通信機器に与える影響は周波数に比例して大きくなるため、高周波になればなるほどこれら寄生リアクタンス成分を小さく抑える必要がある。また、マイクロ波〜ミリ波の周波数帯を扱う通信機器においては、回路を構成する部材間に存在する接続要素等の寸法が波長に対して無視できない大きさとなるので、設計時には構成要素の物理的寸法を十分考慮する必要が生じる。また、当然のことながら、受動素子や線路などの回路部品には極めて正確な精度が要求される。 In recent years, the information and communication field has made remarkable progress, and the frequency bands to be handled are being expanded from microwave bands to millimeter wave bands to higher frequencies. Along with this, the speed of transistors used in these communication devices has been remarkably increased. Recently, devices having a cutoff frequency exceeding 100 GHz, such as heterojunction compound semiconductor transistors, have been realized. However, at such a high frequency of microwave to millimeter wave, not only the transistor characteristics but also the mounting method for realizing the circuit becomes a problem. For example, new parasitic capacitance and parasitic inductance often occur after the mounting process, and the effect of these parasitic components on communication equipment increases in proportion to the frequency.Therefore, the higher the frequency, the smaller these parasitic reactance components It needs to be suppressed. Also, in communication equipment that handles the frequency band from microwave to millimeter wave, the dimensions of the connection elements and the like existing between the members constituting the circuit are not negligible with respect to the wavelength. It is necessary to sufficiently consider dimensions. Of course, circuit components such as passive elements and lines require extremely accurate precision.

　このような問題に対処しながら、低コスト・高性能で、かつ応用範囲の広い準ミリ波〜ミリ波半導体集積回路を実現するための従来技術として、文献「電子情報通信学会1994年秋季大会講演論文集第39項」等に示されるＭＦＩＣ(Millimeter-wave Flip-chip IC)と呼ばれる技術が提案されている。この技術はマイクロバンプボンディング法（以下ＭＢＢ法と書く）とよばれるフリップチップ実装技術を用いて寄生効果を抑えたＩＣ（モジュール）技術であり、半導体プロセスの精密性・量産性を活かしながら設計自由度をも確保し、高性能なミリ波帯ＩＣを低コストで実現できるのが特徴である。 As a conventional technology for realizing a low cost, high performance, and versatile quasi-millimeter-wave to millimeter-wave semiconductor integrated circuit while addressing such problems, the literature "IEICE 1994 Autumn Conference Lecture A technique referred to as MFIC (Millimeter-wave Flip-chip IC) shown in, for example, Article 39 of the Transactions has been proposed. This technology is an IC (module) technology that uses a flip-chip mounting technology called the micro-bump bonding method (hereinafter referred to as the MBB method) to suppress parasitic effects, and allows design freedom while taking advantage of the precision and mass productivity of semiconductor processes. The feature is that a high performance millimeter wave band IC can be realized at low cost.

　図１３は、このＭＦＩＣの構造の一部を示す断面図である。同図において、符号と部材の関係は以下の通りである。５５０は回路基板、５００はＳｉ等の基板、５０１は基板５００の主面上に形成されたＡｕ膜からなる接地導体膜、５０２はＳｉＯ２膜からなる誘電体膜、５０３は誘電体膜５０２上に導電性材料を堆積した後パターニングして形成された第１の配線導体膜をそれぞれ示す。上記第１の配線導体膜５０３，接地導体膜５０１及び誘電体膜５０２によりマイクロストリップ線路が構成されている。なお、５０４は第１の配線導体膜５０３中の電極パッドを示す。また、回路基板５５０上の配線導体膜５０３中には、ＮｉＣｒからなる抵抗体膜５０９が介設されている。また、回路基板５５０上には、第１の配線導体膜５０３を下部電極とし、ＳｉＮからなる層間絶縁膜５１０を容量部とし、Ａｕからなる第２の配線導体膜５１１を上部電極とするＭＩＭ構造のキャパシタ５１２が形成されている。さらに、誘電体膜５０２の一部に形成されたバイアホールに上記第２の配線導体膜５１１を構成する金属が埋め込まれてなる埋め込み部材５１３が設けられており、この埋め込み部材５１３を介して第２の配線導体膜５１１が接地導体膜５０１に接続されている。 FIG. 13 is a sectional view showing a part of the structure of the MFIC. In the figure, the relationship between reference numerals and members is as follows. 550, a circuit substrate; 500, a substrate made of Si or the like; 501, a ground conductor film made of an Au film formed on the main surface of the substrate 500; 502, a dielectric film made of a SiO2 film; The first wiring conductor films formed by patterning after depositing a conductive material are shown. The first wiring conductor film 503, the ground conductor film 501, and the dielectric film 502 constitute a microstrip line. Reference numeral 504 denotes an electrode pad in the first wiring conductor film 503. In the wiring conductor film 503 on the circuit board 550, a resistor film 509 made of NiCr is provided. On the circuit board 550, an MIM structure in which the first wiring conductor film 503 is used as a lower electrode, the interlayer insulating film 510 made of SiN is used as a capacitor, and the second wiring conductor film 511 made of Au is used as an upper electrode. Are formed. Further, an embedding member 513 in which the metal constituting the second wiring conductor film 511 is embedded in a via hole formed in a part of the dielectric film 502 is provided. Two wiring conductor films 511 are connected to the ground conductor film 501.

　そして、回路基板５５０には、化合物半導体等で構成された高周波トランジスタを内蔵する半導体チップ５０８が主面側を下方に向けた状態でフリップチップ接続されている。すなわち、半導体チップ５０８の主面側には電極パッド５０７が設けられており、この電極パッド５０７と回路基板５５０上の電極パッド５０４とがマイクロバンプ５０６を介して接続されている。 {Circle around (5)} The circuit board 550 is flip-chip connected to a semiconductor chip 508 including a high-frequency transistor made of a compound semiconductor or the like with its main surface facing downward. That is, an electrode pad 507 is provided on the main surface side of the semiconductor chip 508, and the electrode pad 507 and the electrode pad 504 on the circuit board 550 are connected via the micro bump 506.

　なお、半導体チップ５０８と回路基板５５０との間には光硬化性絶縁樹脂５０５が介在しており、この光硬化性絶縁樹脂５０５により半導体チップ５０８が回路基板５５０上に固定され、かつ光硬化性絶縁樹脂５０５の収縮力によりマイクロバンプ５０６による接続状態が強固なものとなっている。このようなフリップチップ実装法はＭＢＢ法とよばれ、実装後のバンプの高さが数μｍ以下と非常に小さくでき、かつ信頼性が高いのが特徴である。 Note that a photocurable insulating resin 505 is interposed between the semiconductor chip 508 and the circuit board 550, and the semiconductor chip 508 is fixed on the circuit board 550 by the photocurable insulating resin 505, and the photocurable Due to the contraction force of the insulating resin 505, the connection state by the micro bumps 506 is strong. Such a flip-chip mounting method is called an MBB method, and is characterized in that the height of bumps after mounting can be extremely small to several μm or less, and the reliability is high.

　以上のように、ＭＦＩＣはＭＢＢ法によるフリップチップ実装技術を利用することにより、マイクロバンプ５０６の厚みを数μｍ以下にすることができるので、マイクロバンプ５０６が介在することによる寄生インダクタンスは極めて低いレベル（数ｐＨ）に抑えることができ、ミリ波帯においても十分使用できる。また、ＭＦＩＣ内のマイクロストリップ線路は半導体プロセスを用いて作製できるので、アルミナ基板等の上に印刷技術を応用して配線を行う通常のハイブリッドＩＣに比べてはるかに高精度のパターニングが実現できる。すなわち、図１３に示されるように、半導体プロセスでマイクロストリップ線路だけでなく抵抗体やＭＩＭキャパシタのような受動素子を基板上に集積することが可能である。さらに、同じく半導体プロセスを用いるＭＭＩＣ(Millimeter-wave Monoloithic IC)に比べても、ＭＦＩＣにおいては、受動回路を化合物半導体基板上ではなくＳｉ等の安価な基板上に形成できるので大幅な低コスト化が可能になる。 As described above, the MFIC can reduce the thickness of the micro-bump 506 to several μm or less by using the flip-chip mounting technology based on the MBB method. Therefore, the parasitic inductance due to the interposition of the micro-bump 506 is extremely low. (Several pH) and can be used sufficiently even in the millimeter wave band. Further, since the microstrip line in the MFIC can be manufactured by using a semiconductor process, patterning with much higher precision can be realized as compared with a normal hybrid IC in which wiring is performed by applying a printing technique on an alumina substrate or the like. That is, as shown in FIG. 13, it is possible to integrate not only microstrip lines but also passive elements such as resistors and MIM capacitors on a substrate in a semiconductor process. Furthermore, compared to the MMIC (Millimeter-wave Monoloithic IC) that also uses a semiconductor process, the MFIC allows a passive circuit to be formed on an inexpensive substrate such as Si instead of a compound semiconductor substrate, resulting in significant cost reduction. Will be possible.

　しかし、ＭＦＩＣでは薄膜誘電体膜を用いてマイクロストリップ線路を用いるために、マイクロストリップ線路の損失が比較的大きくなるという問題があった。そこで、文献「電子情報通信学会1996年総合大会講演論文集エレクトロニクス１巻第７８項」等に示されるように、マイクロストリップ線路を構成する誘電体膜５０２にＢＣＢ（ベンゾシクロブテン）等の有機膜を用いるという技術が提案されている。ＢＣＢは液状の原材料を基板表面にスピンコートしてベーキングするという簡単な工程で誘電体膜を容易に形成できる。しかも、ＢＣＢ膜の誘電損失はＣＶＤ等で作製したＳｉＯ２に比べて１桁近く低く、ＳｉＯ２より厚い膜（１０μｍ以上）が容易に作製できる。膜厚が厚ければ同一インピーダンスを実現する線路幅が広くなるので、線路の抵抗成分が小さくなり、損失が低減する。すなわち、ＢＣＢを用いることでＭＦＩＣ基板の生産性が大きく向上するだけでなく、誘電損失も導体損失も減らすことができ、ＭＦＩＣのマイクロストリップ線路の損失を大きく低減することができる。
特開平０７−０７４２８５号公報（要約） However, since the MFIC uses the microstrip line using the thin dielectric film, there is a problem that the loss of the microstrip line becomes relatively large. Therefore, as shown in the document “Electronic Information and Communication Engineers 1996 General Conference Proceedings of Electronics, Vol. 1, No. 78, Electronics”, etc., an organic film such as BCB (benzocyclobutene) is used for the dielectric film 502 constituting the microstrip line. There has been proposed a technique of using. BCB can easily form a dielectric film by a simple process of spin coating a liquid raw material on a substrate surface and baking. In addition, the dielectric loss of the BCB film is lower by almost one digit than that of SiO2 manufactured by CVD or the like, and a film (10 μm or more) thicker than SiO2 can be easily manufactured. If the film thickness is large, the line width for realizing the same impedance is widened, so that the resistance component of the line is reduced and the loss is reduced. That is, the use of BCB not only greatly improves the productivity of the MFIC substrate, but also can reduce the dielectric loss and the conductor loss, and can greatly reduce the loss of the microstrip line of the MFIC.
JP-A-07-074285 (abstract)

　しかしながら、ＢＣＢ膜等の有機樹脂膜を用いたＭＦＩＣによると上記の問題は解決できるが、以下に示すような新たな問題が発生する。 However, although the above problem can be solved by MFIC using an organic resin film such as a BCB film, the following new problem occurs.

　第１の問題は、抵抗体膜が断裂することである。ＭＦＩＣ基板上の抵抗体はＮｉＣｒ等の金属薄膜を所望の抵抗値になるようにパターンニングして形成されるが、その厚さは後述する理由により数１０ｎｍ〜数１００ｎｍと非常に薄い。一方、その下部にある有機樹脂は熱伝導率が低く、熱が逃げにくい性質を持っている。従って実使用状態で抵抗体膜に電流を流して抵抗が発熱した際、熱が逃げにくいため抵抗体下方の有機樹脂膜の温度が局部的に上昇する。この温度上昇により有機樹脂膜が熱膨張して厚みが増すために、薄く堅い抵抗体膜の発熱する中央部が下から押し上げられる形になり、つまり抵抗体膜が曲げ応力を受ける。また、一般的に有機樹脂の熱膨張率は大きいので、抵抗体が引っ張り応力を受ける。このような曲げ応力や引っ張り応力によって、抵抗体が断裂を起こしてしまうという問題があった。 The first problem is that the resistor film breaks. The resistor on the MFIC substrate is formed by patterning a metal thin film of NiCr or the like so as to have a desired resistance value, and its thickness is as thin as several tens nm to several hundreds nm for the reason described later. On the other hand, the organic resin at the lower part has a low thermal conductivity and has a property that heat is hard to escape. Therefore, when a current flows through the resistor film and the resistor generates heat in an actual use state, the heat is hard to escape and the temperature of the organic resin film below the resistor locally rises. The temperature rise causes the organic resin film to thermally expand and increase its thickness, so that the thin and rigid resistor film is heated up from below at the heat-generating central portion, that is, the resistor film receives bending stress. Further, since the thermal expansion coefficient of the organic resin is generally large, the resistor receives a tensile stress. There has been a problem that the resistor may be broken by such bending stress or tensile stress.

　我々の実験では、例えば厚みが２６μｍのＢＣＢ膜の上に大きさ５０μｍ×５０μｍ、厚さ１００ｎｍのＮｉＣｒ膜で抵抗体膜を形成した場合、わずか数ｍＡの電流を流すと断線してしまうことが分かった。抵抗体膜の膜厚を厚くすることで断裂を起こしにくくすることも考えられるが、そうすると抵抗体膜のシート抵抗値が小さくなってしまうため同じ抵抗値を実現するのに長いパターンが必要になる。ところが、抵抗体膜の長さがあまりに長くなるとインダクタンスなどの寄生成分の増加を招いてしまうので、膜厚増加には限度がある。 In our experiments, for example, when a resistor film is formed of a NiCr film having a size of 50 μm × 50 μm and a thickness of 100 nm on a BCB film having a thickness of 26 μm, disconnection may occur if a current of only a few mA flows. Do you get it. It is conceivable that increasing the thickness of the resistor film may make it less likely to break, but doing so will reduce the sheet resistance value of the resistor film, so a long pattern is required to achieve the same resistance value . However, if the length of the resistor film is too long, an increase in parasitic components such as inductance is caused.

　第２の問題も、有機樹脂膜の放熱性の悪さに起因する半導体チップの温度上昇の問題である。ＭＦＩＣのたとえばパワーアンプ等への応用を考えた場合、パワーアンプの最高電力値を上昇させるのに、半導体チップからの発熱をどれだけ放熱できるかが大きな鍵となるが、従来の半導体装置のごとくフェースダウンで実装された半導体チップの下方に熱伝導率が低い有機樹脂膜が存在していると、熱が放散せず、半導体装置チップの温度が過上昇して、トランジスタ等の特性を悪化させるおそれがあった。 {Circle around (2)} The second problem is that the temperature of the semiconductor chip rises due to poor heat dissipation of the organic resin film. When considering the application of the MFIC to, for example, a power amplifier, the key to increasing the maximum power value of the power amplifier is how much heat generated from the semiconductor chip can be radiated. If an organic resin film having low thermal conductivity is present below the semiconductor chip mounted face-down, heat will not be dissipated and the temperature of the semiconductor device chip will rise excessively, deteriorating the characteristics of transistors and the like. There was a fear.

　本発明の第１の目的は、抵抗体膜の発熱を効率よく放散させる手段を講じることより、抵抗の断裂のない、信頼性の高い回路基板を提供することにある。 A first object of the present invention is to provide a highly reliable circuit board free from resistance rupture by taking measures for efficiently dissipating heat generated by a resistor film.

　本発明の第２の目的は、ＭＦＩＣ基板の構成および実装方法を改良することにより、実装チップの放熱特性を向上させ、パワーアンプのように大電力を扱うことのできるＭＦＩＣを実現することにある。 A second object of the present invention is to improve the configuration and mounting method of an MFIC substrate, thereby improving the heat radiation characteristics of a mounted chip, and realizing an MFIC capable of handling large power like a power amplifier. .

　本発明の半導体装置は、少なくとも一部に接地用導体部を有する基板と、上記接地用導体部の上に形成された誘電体膜と、上記誘電体膜の上に形成され上記接地用導体部及び上記誘電体膜と共にマイクロストリップ線路を構成する配線導体膜とを有する回路基板と、半導体基板と、該半導体基板の主面上に形成された高周波トランジスタと、上記半導体基板の主面上に形成され上記高周波トランジスタに接続されるチップ側接地用電極及びチップ側信号用電極を有するとともに、上記主面を下方に向け上記チップ側信号用電極と上記回路基板の配線導体膜とが電気的に接続された状態で上記回路基板上に搭載される半導体チップとを備えるとともに、上記半導体チップの上記チップ側接地用電極と上記回路基板の上記接地用導体部との間を熱伝導可能に接続する放熱用部材を備え、上記放熱用部材は、上記接地導体部のうち上記チップ側接地用電極の下方となる領域の上で厚く形成された凸部と、上記チップ側接地用電極と上記凸部との間に介在するバンプとにより構成されており、上記誘電体膜は、上記支持体の周囲を取り囲むように形成されている。 A semiconductor device according to the present invention includes a substrate having a grounding conductor at least in part, a dielectric film formed on the grounding conductor, and the grounding conductor formed on the dielectric film. A circuit board having a wiring conductor film forming a microstrip line together with the dielectric film, a semiconductor substrate, a high-frequency transistor formed on a main surface of the semiconductor substrate, and a high-frequency transistor formed on a main surface of the semiconductor substrate And a chip-side grounding electrode and a chip-side signal electrode connected to the high-frequency transistor, and the chip-side signal electrode is electrically connected to the wiring conductor film of the circuit board with the main surface facing downward. A semiconductor chip mounted on the circuit board in a state in which the semiconductor chip is grounded, and between the chip-side grounding electrode of the semiconductor chip and the grounding conductor of the circuit board. A heat-radiating member connected so as to be conductively connected, wherein the heat-radiating member is formed thick on a region of the ground conductor below the chip-side grounding electrode; The dielectric film is formed by a bump interposed between the electrode and the projection, and the dielectric film is formed so as to surround the periphery of the support.

　これにより、半導体チップから生じた熱が放熱用部材を介してヒートシンクとなる接地導体部に逃される。したがって、半導体チップの下方にある誘電体膜が放熱性の低い材料で構成されている場合にも、誘電体膜や他の部材に悪影響を与えることがなく、信頼性の高いＭＦＩＣが得られる。 Thereby, the heat generated from the semiconductor chip is released to the ground conductor serving as a heat sink via the heat dissipation member. Therefore, even when the dielectric film below the semiconductor chip is made of a material having low heat dissipation, a highly reliable MFIC can be obtained without adversely affecting the dielectric film and other members.

　そして、上記放熱用部材を、上記接地導体部のうち上記チップ側接地用電極の下方となる領域の上で厚く形成された凸部と、上記チップ側接地用電極と上記凸部との間に介在するバンプとにより構成し、上記誘電体膜を、上記支持体の周囲を取り囲むように形成することにより、接地導体部の一部である凸部が放熱用部材として機能することになり、半導体チップから接地導体膜に直接的に熱が逃されるので、極めて高い放熱機能が得られる。 Then, the heat dissipating member is provided between the convex portion formed thickly on a region of the ground conductor portion below the chip-side grounding electrode, and between the chip-side grounding electrode and the convex portion. By forming the dielectric film so as to surround the periphery of the support, the convex portion, which is a part of the ground conductor portion, functions as a heat radiation member, and is formed by interposing bumps. Since heat is directly released from the chip to the ground conductor film, an extremely high heat dissipation function can be obtained.

　上記バンプはいずれも厚みが５μｍ以下であることにより、バンプの厚みが小さくなるので、熱の移動も速やかとなる。また、半導体チップの信号用電極と回路基板の配線導体膜との間をバンプで接続する場合には、信号接続用のバンプの厚みも５μｍ以下となり、寄生インダクタンスが無視できるほどに小さい半導体装置が得られる。 (4) Since the thickness of each of the bumps is 5 μm or less, the thickness of the bumps is reduced, so that the heat can be moved quickly. In the case where the signal electrode of the semiconductor chip and the wiring conductor film of the circuit board are connected by a bump, the thickness of the signal connection bump is also less than 5 μm, and a semiconductor device having a small parasitic inductance can be ignored. can get.

　本発明の回路基板によれば、抵抗体膜等の発熱性膜を有する回路基板又はこの回路基板を利用した半導体装置において、発熱性膜からの発熱を拡散させる手段を講じたので、発熱による局所的な誘電体膜の熱膨張が抑えられ、抵抗体膜の断裂を防止することができる。 According to the circuit board of the present invention, in a circuit board having a heat-generating film such as a resistor film or a semiconductor device using this circuit board, a means for diffusing heat from the heat-generating film is employed, so that local Thermal expansion of the dielectric film is suppressed, and the resistor film can be prevented from being broken.

　本発明の半導体装置によれば、回路基板上に半導体チップを搭載してなる半導体装置において、半導体チップから速やかに接地導体部へ放熱させる手段を講じたので、パワーアンプのように大電力を扱うＭＦＩＣを容易に実現することができる。 According to the semiconductor device of the present invention, in the semiconductor device in which the semiconductor chip is mounted on the circuit board, a means for quickly dissipating heat from the semiconductor chip to the ground conductor portion is employed, so that large power is handled like a power amplifier. MFIC can be easily realized.

　　（第１の実施形態）
　第１の実施形態は、放熱用導体膜によって発熱性膜で発生した熱を広い範囲に放散させるようにした回路基板の構造に関するものである。 (1st Embodiment)
The first embodiment relates to a structure of a circuit board that dissipates heat generated in a heat-generating film to a wide range by a heat-dissipating conductor film.

　図１（ａ）は、第１の実施形態に係る回路基板５０の一部を示す断面図である。図１（ａ）において符号と部材の関係は以下の通りである。１はＳｉやガラス等からなる基板、２は基板１の上に形成された例えばＡｕからなる接地導体膜、３はＢＣＢ（ベンゾシクロブテン）からなる第１の誘電体膜としてのＢＣＢ膜、４はＢＣＢ膜３の上にたとえばＴｉ，Ａｕを積層してなる放熱用導体膜、５は放熱用導体膜４の上に形成され後述の抵抗体膜と放熱用導電膜４とを電気的に絶縁するための例えばシリコン酸化膜からなる第２の誘電体膜としての層間絶縁膜、６は所定の抵抗値になるようにパターニングされた例えばＮｉＣｒからなる発熱性膜である抵抗体膜、７は例えばＴｉ，Ａｕを積層してなる配線導体膜である。上記配線導体膜７と、ＢＣＢ膜３と、層間絶縁膜５と、接地導体膜２とによりマイクロストリップ線路が構成されている。また、配線導体膜７と抵抗体膜６とは任意の２カ所において互いに接続されており、抵抗体膜６のうち配線導体膜との２つの接続部の間の領域が実質的に抵抗体Ｒ１として機能している。以下、この領域を実質抵抗部という。 FIG. 1A is a cross-sectional view showing a part of the circuit board 50 according to the first embodiment. In FIG. 1A, the relationship between reference numerals and members is as follows. Reference numeral 1 denotes a substrate made of Si or glass, etc., 2 denotes a ground conductor film formed of, for example, Au formed on the substrate 1, 3 denotes a BCB film as a first dielectric film made of BCB (benzocyclobutene), Is a heat dissipating conductor film formed by laminating, for example, Ti and Au on the BCB film 3, and 5 is formed on the heat dissipating conductor film 4 to electrically insulate a resistor film and a heat dissipating conductive film 4 described later. For example, an interlayer insulating film as a second dielectric film made of a silicon oxide film, 6 is a resistor film which is a heat-generating film made of, for example, NiCr patterned to have a predetermined resistance value, and 7 is, for example, This is a wiring conductor film formed by laminating Ti and Au. The wiring conductor film 7, the BCB film 3, the interlayer insulating film 5, and the ground conductor film 2 constitute a microstrip line. Further, the wiring conductor film 7 and the resistor film 6 are connected to each other at arbitrary two places, and the region between the two connection portions of the resistor film 6 and the wiring conductor film substantially corresponds to the resistor R1. Functioning as Hereinafter, this region is referred to as a substantial resistance portion.

　本実施形態では、抵抗体膜６の下方に薄い層間絶縁膜５を挟んで放熱用導体膜４が設けられているので、抵抗体膜６に電流が流れて発熱を生じた場合、この熱は放熱用導体膜４全体からその周囲に速やかに拡散されるため、ＢＣＢ膜３が局所的に急激な温度上昇することがない。すなわち、抵抗体膜６の下地膜となっているＢＣＢ膜３は熱伝導率が低いので、抵抗体膜６で発生した熱によってＢＣＢ膜３が局所的に加熱されると、その部分だけが急激に熱膨張するために抵抗体膜６に局部的に大きな応力（特に曲げ応力）が作用して、抵抗体膜６が断裂するおそれがある。しかし、本実施形態のごとく、抵抗体膜６の下方において層間絶縁膜５とＢＣＢ膜３との間に放熱用導体膜４を介在させることにより、抵抗体膜６から下方に伝導する熱が速やかに広範囲に拡散してしまうので、放熱性に乏しいＢＣＢ膜３への熱の局所集中を緩和することができ、ＢＣＢ膜３の局部的な熱膨張を抑制することができる。よって、抵抗体膜６に作用する曲げ応力等が小さくなり、抵抗体膜６の断裂を有効に防止することができる。 In this embodiment, since the heat dissipation conductor film 4 is provided below the resistor film 6 with the thin interlayer insulating film 5 interposed therebetween, when a current flows through the resistor film 6 to generate heat, this heat is generated. Since the heat dissipation conductor film 4 is quickly diffused from the whole to the periphery thereof, the temperature of the BCB film 3 does not locally rise sharply. That is, since the BCB film 3 serving as the base film of the resistor film 6 has a low thermal conductivity, when the BCB film 3 is locally heated by the heat generated in the resistor film 6, only that portion is sharply reduced. Due to thermal expansion, a large stress (particularly, bending stress) acts locally on the resistor film 6, and the resistor film 6 may be broken. However, as in the present embodiment, by disposing the heat dissipation conductor film 4 between the interlayer insulating film 5 and the BCB film 3 below the resistor film 6, the heat conducted downward from the resistor film 6 is quickly increased. Therefore, the local concentration of heat on the BCB film 3 having poor heat dissipation can be reduced, and the local thermal expansion of the BCB film 3 can be suppressed. Therefore, the bending stress or the like acting on the resistor film 6 is reduced, and the tearing of the resistor film 6 can be effectively prevented.

　本実施形態の効果を顕著にするために、つまり抵抗体膜６の熱を速やかに放熱用導体膜４に伝えるためには、層間絶縁膜５の厚さを電気的絶縁性を保てる範囲内でできる限り薄くしておくことが好ましい。また、層間絶縁膜５の厚みが薄いことは、層間絶縁膜５自体の熱膨張により抵抗体膜６にストレスを与えないためにも好ましい。 In order to make the effect of the present embodiment remarkable, that is, to quickly transmit the heat of the resistor film 6 to the heat-radiating conductor film 4, the thickness of the interlayer insulating film 5 must be set within a range where electrical insulation can be maintained. It is preferable to make it as thin as possible. Further, it is preferable that the thickness of the interlayer insulating film 5 is small in order not to apply stress to the resistor film 6 due to thermal expansion of the interlayer insulating film 5 itself.

　また、平面的に見たときの放熱用導体膜４の存在範囲は、抵抗体膜６の実質抵抗部と少なくとも一致する領域、できれば実質抵抗部を含みさらに広い領域であることが好ましく、放熱用導体膜４をこのように広く形成することによって、抵抗体膜６から発する熱を有効に放熱することができる。 In addition, it is preferable that the area where the heat-dissipating conductor film 4 is present in a plan view is a region that at least coincides with the substantial resistance portion of the resistor film 6, preferably a wider region including the substantial resistance portion. By thus forming the conductor film 4 wide, heat generated from the resistor film 6 can be effectively radiated.

　次に、図１（ｂ）は、第１の実施形態の変形例に係る回路基板５０の構造を示す断面図である。図１（ｂ）に示すように、基板１の上には、接地導体膜２と、ＢＣＢ膜３と、放熱用導体膜４と、層間絶縁膜５と、抵抗体薄膜６と、３つの部分７ａ，７ｂ，７ｃからなる配線導体膜７とが形成されている。これらの部材を構成する材料は図１（ａ）に示す回路基板５０についてすでに説明したものとほぼ同じであるが、層間絶縁膜５については、後述するキャパシタの容量を考慮して誘電率の高いシリコン窒化膜により構成することが好ましい場合もある。 Next, FIG. 1B is a cross-sectional view illustrating a structure of a circuit board 50 according to a modified example of the first embodiment. As shown in FIG. 1B, on a substrate 1, a ground conductor film 2, a BCB film 3, a heat dissipation conductor film 4, an interlayer insulating film 5, a resistor thin film 6, and three portions A wiring conductor film 7 composed of 7a, 7b, 7c is formed. The materials constituting these members are substantially the same as those already described for the circuit board 50 shown in FIG. 1A, but the interlayer insulating film 5 has a high dielectric constant in consideration of the capacitance of a capacitor described later. In some cases, it is preferable to use a silicon nitride film.

　図１（ｂ）に示す構造の特徴は、ＢＣＢ膜３の上において、放熱用導体膜４と配線導体膜７ｂとが埋め込み部材９を介して接続されており、放熱用導体膜４の一部が配線としても機能するように構成されている点と、配線導体膜７ｃを上部電極とし層間絶縁膜５を容量部とし放熱用導体膜４を下部電極とするキャパシタＣ１が構成されている点である。なお、上記図１（ａ）に示す回路基板５０の構造と同様に、放熱用導体膜４の上方において、層間絶縁膜５の上に抵抗体膜６が形成されており、両端でそれぞれ配線導体膜７ａ，７ｂに接続されている。 The structure shown in FIG. 1B is characterized in that the heat dissipation conductor film 4 and the wiring conductor film 7b are connected via the embedded member 9 on the BCB film 3, and a part of the heat dissipation conductor film 4 is formed. And a capacitor C1 in which the wiring conductor film 7c is used as an upper electrode, the interlayer insulating film 5 is used as a capacitor, and the heat dissipation conductor film 4 is used as a lower electrode. is there. As in the structure of the circuit board 50 shown in FIG. 1A, a resistor film 6 is formed on the interlayer insulating film 5 above the heat-dissipating conductor film 4 and wiring conductors are provided at both ends. It is connected to the films 7a and 7b.

　図１（ｃ）は、図１（ｂ）に示す回路基板５０の等価回路図である。図１（ｂ），１（ｃ）に示すように、配線導体膜７の２つの点Ｘ−Ｙ間に抵抗素子Ｒ１とキャパシタＣ１とが介設された構造となっている。 FIG. 1 (c) is an equivalent circuit diagram of the circuit board 50 shown in FIG. 1 (b). As shown in FIGS. 1B and 1C, a structure in which a resistance element R1 and a capacitor C1 are interposed between two points XY of the wiring conductor film 7 is provided.

　本実施形態では、放熱用導体膜４が抵抗体膜６の発熱を放散する機能を有するとともに、ある部分では配線として機能し、他のある部分ではキャパシタの下部電極として機能している。したがって、放熱用導体膜の利用用途の拡大を図ることができる。 In the present embodiment, the heat dissipation conductor film 4 has a function of dissipating heat generated by the resistor film 6, functions as a wiring in one part, and functions as a lower electrode of a capacitor in another part. Therefore, it is possible to expand use of the heat dissipation conductor film.

　なお、変形例を含む本実施形態では接地導体膜２の上に第１の誘電体膜としてＢＣＢ膜３を設けているが、本発明は斯かる実施形態に限定されるものではなく、ＢＣＢ膜３の代わりに、熱伝導率の低い材質例えば有機樹脂などからなる誘電体膜を設けた場合にも、放熱用導体膜を設けることにより、上方の発熱性膜の断裂を防止するという効果が得られる。これは、後述の各実施形態についても同様である。 In the present embodiment including the modification, the BCB film 3 is provided as the first dielectric film on the ground conductor film 2, but the present invention is not limited to such an embodiment, and the BCB film 3 is not limited thereto. In the case where a dielectric film made of a material having a low thermal conductivity, such as an organic resin, is provided instead of 3, the heat-radiating conductor film can be provided to prevent the upper heat-generating film from being broken. Can be This is the same for each embodiment described later.

　また、変形例を含む本実施形態及び後述の第２〜第５の実施形態において、発熱性膜は抵抗体として機能させるために設けたものに限定されるものではない。配線や電極として使用すべく設けた導体膜においても、材質や形状によって全体あるいは局部的に大きな熱を生じることがあり、その場合にも本発明の放熱用導体膜を設けることで、下地の局部的な熱膨張による当該導体膜自身の断裂を有効に防止することができる。 In addition, in the present embodiment including the modified examples and the second to fifth embodiments described later, the heat-generating film is not limited to the one provided to function as a resistor. Even in a conductor film provided for use as a wiring or an electrode, a large amount of heat may be generated as a whole or locally depending on the material and shape. This can effectively prevent the conductor film itself from being broken due to thermal expansion.

　さらに、変形例を含む本実施形態及び後述の第２の実施形態において、層間絶縁膜５が基板上の全面に形成されているが、必ずしも層間絶縁膜が全面に形成されている必要はなく、図１（ａ）に示す断面以外の部分において、配線導体膜７と、ＢＣＢ膜３と、接地導体膜２とによりマイクロストリップ線路が構成されていてもよいものとする。 Further, in the present embodiment including the modified example and the second embodiment described later, the interlayer insulating film 5 is formed on the entire surface of the substrate, but the interlayer insulating film is not necessarily formed on the entire surface. In a portion other than the cross section shown in FIG. 1A, a microstrip line may be constituted by the wiring conductor film 7, the BCB film 3, and the ground conductor film 2.

　また、後述の第２の実施形態においても同様であるが、抵抗体膜６と放熱用導体膜４との間に介設される層間絶縁膜５の材質は、シリコン酸化膜やシリコン窒化膜に限定されるものではない。ただし、この層間絶縁膜５（第２の誘電体膜）の材質は、第１の誘電体膜（ＢＣＢ膜３）よりも高い熱伝導率を有していることが好ましい。 The same applies to the second embodiment described later, but the material of the interlayer insulating film 5 interposed between the resistor film 6 and the heat dissipation conductor film 4 is a silicon oxide film or a silicon nitride film. It is not limited. However, the material of the interlayer insulating film 5 (second dielectric film) preferably has a higher thermal conductivity than that of the first dielectric film (BCB film 3).

　　（第２の実施形態）
　第２の実施形態は、発熱性膜からの熱を放熱用導体膜から広く拡散するとともに、熱伝導を利用してさらに効果的に熱を逃すようにした回路基板の構造に関するものである。 (Second embodiment)
The second embodiment relates to a structure of a circuit board in which heat from a heat-generating film is widely diffused from a heat-dissipating conductor film and heat is more effectively released by utilizing heat conduction.

　図２は、第２の実施形態に係る回路基板５０の一部を示す断面図である。図２に示すように、本実施形態に係る回路基板５０の構造は、上記第１の実施形態における図１（ａ）に示す回路基板５０の構造とほぼ同じであるが、本実施形態に係る回路基板５０の特徴は、放熱用導体膜８と接地導体膜２とが埋め込み部材８により接続されている点である。すなわち、ＢＣＢ膜３に形成された接続孔内に放熱用導体膜４を構成するＴｉ，Ａｕが埋め込まれており、この埋め込み部材８を介して放熱用導体膜４と接地導体膜２とが熱伝導率の高い材料からなる埋め込み部材８により接続されていることになる。図２に示す回路基板５０のその他の部分の構造は、図１（ａ）についてすでに説明した通りなので、図２については説明を省略する。 FIG. 2 is a cross-sectional view showing a part of a circuit board 50 according to the second embodiment. As shown in FIG. 2, the structure of the circuit board 50 according to the present embodiment is substantially the same as the structure of the circuit board 50 shown in FIG. A feature of the circuit board 50 is that the heat dissipation conductor film 8 and the ground conductor film 2 are connected by the embedded member 8. That is, Ti and Au constituting the heat dissipation conductor film 4 are buried in the connection holes formed in the BCB film 3, and the heat dissipation conductor film 4 and the ground conductor film 2 are thermally connected via the embedded member 8. The connection is established by the embedded member 8 made of a material having high conductivity. Since the structure of the other parts of the circuit board 50 shown in FIG. 2 has already been described with reference to FIG. 1A, the description of FIG. 2 is omitted.

　上述の第１の実施形態では、抵抗体膜６からの発熱を放熱用導体膜４全体から広い範囲に放散することでＢＣＢ膜３への熱の局所集中を防ぎ、局所的なＢＣＢ膜３の熱膨張を防止するものであったが、本実施形態では、上記第１の実施形態よりも一歩進んで、この熱をさらに迅速に外部に逃がしてしまうものである。すなわち、放熱用導体膜４がさらに大きなヒートシンクとなる接地導体膜２に接続されているため、放熱用導体膜４に伝わった熱は速やかにこのヒートシンクに逃がされ、抵抗体膜６付近のＢＣＢ膜３の温度上昇はほとんど起こらない。すなわち、基板１にＳｉや金属等の熱伝導率の高い材料を用いるといっそう効果的である。 In the above-described first embodiment, the heat generated from the resistor film 6 is radiated from the entire heat dissipation conductor film 4 to a wide range to prevent local concentration of heat on the BCB film 3. Although the thermal expansion is prevented, in the present embodiment, the heat proceeds one step further than in the first embodiment, and the heat is released to the outside more quickly. That is, since the heat dissipating conductor film 4 is connected to the ground conductor film 2 serving as a larger heat sink, the heat transmitted to the heat dissipating conductor film 4 is quickly released to the heat sink and the BCB near the resistor film 6 is removed. The temperature rise of the film 3 hardly occurs. That is, it is more effective to use a material having high thermal conductivity such as Si or metal for the substrate 1.

　　（第３の実施形態）
　第３の実施形態は、上述の第１，第２の実施形態における回路基板の構造よりも簡単な構造で、上述の第１，第２の実施形態と同等あるいはそれ以上の放熱効果を得るための回路基板の構造に関するものである。 (Third embodiment)
The third embodiment has a simpler structure than the structure of the circuit board in the first and second embodiments, and has a heat radiation effect equal to or higher than that of the first and second embodiments. And the structure of the circuit board.

　図３は、第３の実施形態に係る回路基板５０の一部を示す断面図である。図３において符号と部材の関係は、第１の実施形態における図１に示す関係と同様である。ただし、本実施形態では第１および第２の実施形態で用いた放熱用導体４も、これと抵抗体膜６を絶縁する層間絶縁膜５も設けられていない。つまり、ＢＣＢ膜３と抵抗体膜６及び配線導体膜７とは直接接触している。そして、本実施形態の特徴は、抵抗体膜６の直下方におけるＢＣＢ膜３の厚みが他に比べて薄くなった凹部１０が形成されており、この凹部１０におけるＢＣＢ膜３の上に抵抗体膜６が形成されている点である。すなわち、この薄くなった部分を介して抵抗体膜６の発熱を速やかに接地導体膜２に逃がすように構成されている。 FIG. 3 is a cross-sectional view showing a part of a circuit board 50 according to the third embodiment. In FIG. 3, the relationship between reference numerals and members is the same as the relationship shown in FIG. 1 in the first embodiment. However, in the present embodiment, neither the heat dissipation conductor 4 used in the first or second embodiment nor the interlayer insulating film 5 that insulates the heat dissipation conductor 4 from the resistor film 6 is provided. That is, the BCB film 3 is in direct contact with the resistor film 6 and the wiring conductor film 7. A feature of the present embodiment is that a recess 10 is formed in which the thickness of the BCB film 3 immediately below the resistor film 6 is smaller than that of the other portions, and the resistor 10 is formed on the BCB film 3 in the recess 10. The point is that the film 6 is formed. That is, the heat generation of the resistor film 6 is quickly released to the ground conductor film 2 through the thinned portion.

　本実施形態では、発熱性膜である抵抗体膜６と接地導体膜２とを近接させたことにより、第１、第２の実施形態において用いた放熱用導体膜の機能を接地導体膜２が果たすため、より簡単な構造で上記各実施形態と同様の効果を得ることができる。 In the present embodiment, since the resistor film 6 which is a heat-generating film and the ground conductor film 2 are brought close to each other, the function of the heat dissipation conductor film used in the first and second embodiments is changed by the ground conductor film 2. Therefore, effects similar to those of the above embodiments can be obtained with a simpler structure.

　本実施形態において、抵抗体膜６の直下方におけるＢＣＢ膜３の厚さは、熱が速やかに接地導体膜に伝わるようにできる限り薄いことが好ましい。また、抵抗体膜６の直下方におけるＢＣＢ膜３の厚みが薄いことにより、ＢＣＢ膜３の熱膨張した部分と熱膨張していない部分との厚みの差が小さくなるので、ＢＣＢ膜３の局部的な熱膨張によって抵抗体膜６が受ける曲げ応力等も低減される。 In the present embodiment, it is preferable that the thickness of the BCB film 3 immediately below the resistor film 6 be as thin as possible so that heat can be quickly transmitted to the ground conductor film. In addition, since the thickness of the BCB film 3 immediately below the resistor film 6 is small, the difference in thickness between the thermally expanded portion and the non-thermally expanded portion of the BCB film 3 becomes small. The bending stress applied to the resistor film 6 due to the thermal expansion is also reduced.

　　（第４の実施形態）
　第４の実施形態は、第３の実施形態と同様の効果を別の構成で実現しようとするものである。 (Fourth embodiment)
The fourth embodiment is intended to realize the same effect as the third embodiment with another configuration.

　図４は第４の実施形態に係る回路基板５０の一部を示す断面図である。図４に示すように、本実施形態の回路基板５０の構造は、上記第３の実施形態における図３に示す回路基板５０の構造において、抵抗体膜６の直下方におけるＢＣＢ膜３を除去するとともに、抵抗体膜６と接地導体膜２との間にシリコン窒化膜からなる層間絶縁膜１２を介在させたものである。すなわち、抵抗体膜６で発生した熱を層間絶縁膜１２を介して接地導体膜２に逃すようにしている。 FIG. 4 is a sectional view showing a part of a circuit board 50 according to the fourth embodiment. As shown in FIG. 4, the structure of the circuit board 50 of this embodiment is different from the structure of the circuit board 50 shown in FIG. 3 of the third embodiment in that the BCB film 3 immediately below the resistor film 6 is removed. In addition, an interlayer insulating film 12 made of a silicon nitride film is interposed between the resistor film 6 and the ground conductor film 2. That is, the heat generated in the resistor film 6 is released to the ground conductor film 2 via the interlayer insulating film 12.

　本実施形態では、第３の実施形態に比べ、発熱性膜である抵抗体膜６と接地導体膜２との間に層間絶縁膜１２のみを介在させているので、この層間絶縁膜１２を構成するための材料としてＢＣＢ膜３よりも熱伝導率の高い絶縁材料を選択して（本実施形態ではシリコン窒化膜）使用することで、第３の実施形態に係る回路基板５０の構造よりもさらに高い放熱効果を発揮することができる。また、層間絶縁膜１２の材質を自由に選ぶことができるため、より薄膜化が容易となり、この第２の誘電体膜を薄くすることにより第３の実施形態よりも効果的に放熱することが可能になる。 In this embodiment, as compared with the third embodiment, only the interlayer insulating film 12 is interposed between the resistor film 6 which is a heat-generating film and the ground conductor film 2. By selecting and using an insulating material having a higher thermal conductivity than the BCB film 3 (a silicon nitride film in the present embodiment) as a material for performing the process, the structure of the circuit board 50 according to the third embodiment is further improved. High heat dissipation effect can be exhibited. In addition, since the material of the interlayer insulating film 12 can be freely selected, it is easy to make the film thinner. By making the second dielectric film thinner, heat can be more effectively radiated than in the third embodiment. Will be possible.

　　（第５の実施形態）
　第５の実施形態は、発熱性膜である抵抗体膜の下方をトンネル状にすることにより熱放散機能を高めるようにした回路基板の構造に関する。図５（ａ）及び図５（ｂ）は、本実施形態における回路基板５０の２つのタイプを示す断面図である。いずれの場合にも、シリコン，ガラス等からなる基板１の上にＡｕ等からなる接地導体膜２が形成され、さらに接地導体膜２の上にＢＣＢ膜３が形成されている点は同じである。 (Fifth embodiment)
The fifth embodiment relates to a circuit board structure in which a heat dissipation function is enhanced by forming a tunnel below a resistor film that is a heat-generating film. FIGS. 5A and 5B are cross-sectional views showing two types of the circuit board 50 in the present embodiment. In either case, the ground conductor film 2 made of Au or the like is formed on the substrate 1 made of silicon, glass, or the like, and the BCB film 3 is formed on the ground conductor film 2 in the same manner. .

　ここで、図５（ａ）に示すタイプの回路基板５０においては、ＢＣＢ膜３の一部に凹部が形成され、抵抗体膜６は凹部を跨いで両端でＢＣＢ膜３に支持されるように形成されている。そして、抵抗体膜６は、その両端部において抵抗体膜の上にオーバーラップして形成されている配線導体膜７ａ，７ｂに接続されている。つまり、この２つの接続部の間の領域において抵抗体膜６の下方にトンネル部２０が形成されている。 Here, in the circuit board 50 of the type shown in FIG. 5A, a concave portion is formed in a part of the BCB film 3, and the resistor film 6 is supported by the BCB film 3 at both ends across the concave portion. Is formed. The resistor film 6 is connected to the wiring conductor films 7a and 7b formed on both sides of the resistor film so as to overlap with each other. That is, the tunnel portion 20 is formed below the resistor film 6 in a region between the two connection portions.

　また、図５（ｂ）のタイプの回路基板５０においては、抵抗体膜６がその両端部で配線導体膜７ａ，７ｂの上にオーバーラップするように形成されている。つまり、ＢＣＢ膜３の上面はフラットに形成されているが、抵抗体膜６の下方において配線導体膜の存在しない部分がトンネル部２０となっている。 In the circuit board 50 of the type shown in FIG. 5B, the resistor film 6 is formed so as to overlap the wiring conductor films 7a and 7b at both ends. In other words, the upper surface of the BCB film 3 is formed flat, but the portion below the resistor film 6 where no wiring conductor film exists is the tunnel portion 20.

　図５（ａ）及び図５（ｂ）に示す２つのタイプの回路基板５０のいずれにおいても、発熱性膜である抵抗体膜６の下方がトンネル部２０となっていて、ＢＣＢ膜３そのものが存在しないので、ＢＣＢ膜３の局部的な加熱による熱膨張が極めてわずかであり、かつ局部的な熱膨張が生じても抵抗体膜６がされによって曲げ応力等を受けることがない。したがって、ＢＣＢ膜３の局部的な熱膨張による抵抗体膜６の断裂を確実に防止することができる。 In each of the two types of circuit boards 50 shown in FIGS. 5A and 5B, the tunnel portion 20 is located below the resistor film 6 which is a heat-generating film, and the BCB film 3 itself is not used. Since it does not exist, the thermal expansion due to local heating of the BCB film 3 is extremely small, and even if local thermal expansion occurs, the resistor film 6 is not subjected to bending stress and the like. Therefore, the tearing of the resistor film 6 due to local thermal expansion of the BCB film 3 can be reliably prevented.

　次に、図６（ａ）〜図６（ｃ）を参照しながら、上記図５（ｂ）に示す回路基板５０の製造工程の概略的に説明する。 Next, the manufacturing process of the circuit board 50 shown in FIG. 5B will be schematically described with reference to FIGS. 6A to 6C.

　まず、図６（ａ）に示すように、Ｓｉ，ガラス等からなる基板１の上にＡｕ等を全面に堆積して接地導体膜２を形成し、接地導体膜２の全面上にＢＣＢ膜３を２６μｍ程度の厚みで形成する。そして、ＢＣＢ膜３の上にＡｕ等の膜を堆積した後これをパターニングして、所定の距離を隔てて２つの部分７ａ，７ｂに分かれる配線導体膜７を形成する。さらに、その上にフォトレジスト膜を堆積した後これをエッチバックして、２つの配線導体膜７ａ，７ｂの間に埋め込みフォトレジスト膜２１を残す。 First, as shown in FIG. 6A, a ground conductor film 2 is formed by depositing Au or the like on the entire surface of a substrate 1 made of Si, glass, or the like, and a BCB film 3 is formed on the entire surface of the ground conductor film 2. Is formed with a thickness of about 26 μm. Then, a film of Au or the like is deposited on the BCB film 3 and then patterned to form a wiring conductor film 7 divided into two portions 7a and 7b at a predetermined distance. Further, after a photoresist film is deposited thereon, it is etched back to leave a buried photoresist film 21 between the two wiring conductor films 7a and 7b.

　次に、図６（ｂ）に示すように、基板の全面上にＮｉＣｒ膜を堆積した後これをパターニングして、配線導体膜７ａ，７ｂ及び埋め込みフォトレジスト膜２１に跨る抵抗体膜６を形成する。このとき、抵抗体膜６は両端部で配線導体膜７ａ，７ｂに接続された状態となっている。 Next, as shown in FIG. 6B, a NiCr film is deposited on the entire surface of the substrate and then patterned to form a resistor film 6 extending over the wiring conductor films 7a and 7b and the buried photoresist film 21. I do. At this time, the resistor film 6 is connected to the wiring conductor films 7a and 7b at both ends.

　次に、図６（ｃ）に示すように、埋め込みフォトレジスト膜２１をリフトオフ法により選択的に除去することにより、抵抗体膜２０の下方にトンネル部２０を形成する。 Next, as shown in FIG. 6C, the tunnel portion 20 is formed below the resistor film 20 by selectively removing the buried photoresist film 21 by a lift-off method.

　なお、図５（ａ）のタイプの回路基板５０は、上記図６（ａ）〜６（ｃ）に示す製造工程とほぼ同様の製造工程によって形成される。すなわち、あらかじめＢＣＢ膜の一部に凹部を形成し、その凹部にフォトレジスト膜を埋め込んだ後、抵抗体膜を形成し、さらに、抵抗体膜の上に配線導体膜を形成するという手順により形成することができる。 The circuit board 50 of the type shown in FIG. 5A is formed by substantially the same manufacturing steps as those shown in FIGS. 6A to 6C. That is, a recess is formed in a part of the BCB film in advance, a photoresist film is buried in the recess, a resistor film is formed, and further, a wiring conductor film is formed on the resistor film. can do.

　　（第６の実施形態）
　第６の実施形態以下の実施形態は、回路基板上に半導体チップをフリップチップ実装するようにした半導体装置の構成において、半導体チップの放熱特性を向上するための構成に関するものである。 (Sixth embodiment)
Sixth Embodiment The following embodiments relate to a configuration for improving heat radiation characteristics of a semiconductor chip in a configuration of a semiconductor device in which a semiconductor chip is flip-chip mounted on a circuit board.

　図７は、第６の実施形態に係る半導体装置の一部を示す断面図である。図７において符号と部材の関係は以下の通りである。回路基板５０において、１はＳｉ，ガラス等からなる基板、２は基板１の上に形成された例えばＡｕからなる接地導体膜、３はＢＣＢ膜、１０４ａ、１０４ｂはボンディング用の電極パッドであり、中央の電極パッド１０４ｂは、図７に示す断面以外の部分において、誘電体膜３上のたとえばＴｉ，Ａｕの積層膜で構成される配線導体膜に接続されている。この配線導体膜は、誘電体膜３、接地導体膜２とともにマイクロストリップ線路を構成している。また、図中両端の電極パッド１０４ａは、ＢＣＢ膜３に形成された接続孔にＡｕ等の金属を埋め込んでなる埋め込み部材２００を介して接地導体膜２に接続されている。この埋め込み部材２００を介して電極パッド１０４ａと接地導体膜２とが電気的に接続されていると同時に、ＢＣＢ膜３上で電極パッド１０４ａが機械的にも安定に固定されている。 FIG. 7 is a sectional view showing a part of the semiconductor device according to the sixth embodiment. In FIG. 7, the relationship between reference numerals and members is as follows. In the circuit board 50, 1 is a substrate made of Si, glass or the like, 2 is a ground conductor film made of, for example, Au formed on the substrate 1, 3 is a BCB film, 104a and 104b are electrode pads for bonding, The central electrode pad 104b is connected to a wiring conductor film formed of a laminated film of, for example, Ti and Au on the dielectric film 3 at a portion other than the cross section shown in FIG. This wiring conductor film forms a microstrip line together with the dielectric film 3 and the ground conductor film 2. The electrode pads 104a at both ends in the figure are connected to the ground conductor film 2 via an embedding member 200 in which a metal such as Au is embedded in a connection hole formed in the BCB film 3. The electrode pad 104a and the ground conductor film 2 are electrically connected via the embedded member 200, and at the same time, the electrode pad 104a is mechanically and stably fixed on the BCB film 3.

　一方、回路基板５０上に搭載される半導体チップ１０８は大電力用トランジスタが内蔵されている。半導体チップ１０８には、接地用の電極パッド１０７ａと、回路基板５０上の受動素子との接続用の電極パッド１０７ｂが設けられており、この電極パッド１０７ａ，１０７ｂと回路基板５０上の電極パッド１０４ａ，１０４ｂとの間に、それぞれ接続用のマイクロバンプ１０６が介在している。そして、半導体チップ１０８は、マイクロバンプ１０６を介して、例えば図示はしていないが光硬化型樹脂の収縮力を利用したフリップチップ実装法により回路基板５０に接続されている。 On the other hand, the semiconductor chip 108 mounted on the circuit board 50 has a built-in high-power transistor. The semiconductor chip 108 is provided with an electrode pad 107a for grounding and an electrode pad 107b for connection with a passive element on the circuit board 50. The electrode pads 107a and 107b and the electrode pad 104a on the circuit board 50 are provided. , 104b are provided with micro bumps 106 for connection. The semiconductor chip 108 is connected to the circuit board 50 via the micro bumps 106 by, for example, a flip chip mounting method (not shown) using the contraction force of a photo-curable resin.

　本実施形態の特徴は、上記埋め込み部材２００，電極パッド１０４ａ及びマイクロバンプ１０６により、半導体チップ１０８で発生した熱を接地導体膜２に逃すための放熱用部材が構成されている点である。すなわち、本実施形態では、半導体チップ１０８の接地用の電極パッド１０７ａはマイクロバンプ１０６を介して基板上の電極パッド１０４ａに接続され、この電極パッド１０４ａは埋め込み部材２００を介して接地導体膜２に接続されているので、通電時の半導体チップ１０８からの発熱は、埋め込み部材２００を介して速やかに接地導体膜２に逃がされる。ＭＢＢ法で実装した場合、マイクロバンプ１０６の厚みは５μｍ以下程度に非常に薄くできるので、電極パッド１０７ａから接地導体膜２に至る経路全体の熱抵抗を小さくすることは容易であり、放熱効率は極めて良い。特に、基板をＳｉ等の放熱にすぐれた材料を用いることで、さらに効率よく放熱することが可能になる。このような構成とすることで、従来応用が難しいとされていたパワーアンプ等の大電力を扱う回路もＭＦＩＣで実現することが可能になる。パワーアンプに使用されるＧａＡｓ基板は放熱性が悪いことから、ＧａＡｓ基板上にパワートランジスタを搭載した半導体装置においては、従来ＧａＡｓ基板の裏面を冷却板に接続する構造を採っているが、本実施形態のように主面側の接地用電極パッド１０７ａを介して半導体チップ内の熱を接地用導体膜に逃す構成を採ることで、容易にＭＦＩＣ化を図ることができる。 The feature of the present embodiment is that the embedded member 200, the electrode pad 104a, and the microbump 106 constitute a heat dissipation member for releasing heat generated in the semiconductor chip 108 to the ground conductor film 2. That is, in this embodiment, the ground electrode pad 107a of the semiconductor chip 108 is connected to the electrode pad 104a on the substrate via the micro bump 106, and this electrode pad 104a is connected to the ground conductor film 2 via the embedded member 200. Since the connection is established, heat generated from the semiconductor chip 108 during energization is quickly released to the ground conductor film 2 via the embedded member 200. When mounted by the MBB method, the thickness of the micro-bumps 106 can be extremely thin, about 5 μm or less, so that it is easy to reduce the thermal resistance of the entire path from the electrode pad 107a to the ground conductor film 2, and the heat radiation efficiency is reduced. Very good. In particular, by using a material excellent in heat dissipation, such as Si, for the substrate, heat can be dissipated more efficiently. With such a configuration, a circuit that handles large power, such as a power amplifier, which has conventionally been considered difficult to apply, can be realized by the MFIC. Since a GaAs substrate used for a power amplifier has poor heat dissipation, a semiconductor device in which a power transistor is mounted on a GaAs substrate has conventionally adopted a structure in which the back surface of the GaAs substrate is connected to a cooling plate. By adopting a configuration in which heat in the semiconductor chip is released to the grounding conductor film via the grounding electrode pad 107a on the main surface side as in the embodiment, MFIC can be easily achieved.

　なお、図７に示す構造では、回路基板５０の埋め込み部材２００がマイクロバンプ１０６の直下方に位置しているが、本発明は斯かる構造に限定されるものではなく、埋め込み部材２００は回路基板５０の電極パッド１０４ａにさえ接続されいれば、熱伝導により半導体チップ１０８からの熱を接地導体膜に逃すことができる。 In the structure shown in FIG. 7, the embedding member 200 of the circuit board 50 is located immediately below the microbump 106, but the present invention is not limited to such a structure. As long as it is connected to the 50 electrode pads 104a, heat from the semiconductor chip 108 can be released to the ground conductor film by heat conduction.

　図８（ａ）は、マイクロバンプ１０６と埋め込み部材２００との中心の平面位置が食い違っている場合の回路基板５０の平面図である。このような構造でも、接地用の電極パッド１０４ａの下方に形成された埋め込み部材２００を介して、半導体チップ１０８の熱が接地導体膜１０２に逃されることがわかる。ただし、熱を効果的に逃すには、図８（ａ）に示すように、マイクロバンプ１０６と埋め込み部材２００とが平面的に見てオーバーラップしていることが好ましい。 FIG. 8A is a plan view of the circuit board 50 in a case where the center planar positions of the micro bumps 106 and the embedding members 200 are different from each other. It can be seen that even with such a structure, the heat of the semiconductor chip 108 is released to the ground conductor film 102 via the embedded member 200 formed below the ground electrode pad 104a. However, in order to effectively release the heat, as shown in FIG. 8A, it is preferable that the microbumps 106 and the embedding members 200 overlap in a plan view.

　なお、本実施形態及び後述の各実施形態において、信号用の電極パッド１０７ｂと回路基板５０上の信号用電極パッド１０４ｂとの間にはマイクロバンプ１０６が介在しているが、本発明の効果を発揮する上で両者間にマイクロバンプは必ずしも必要ではなく、直接電極パッド同士が接続されていてもよい。 In this embodiment and each of the following embodiments, the micro bumps 106 are interposed between the signal electrode pads 107b and the signal electrode pads 104b on the circuit board 50. The micro bumps are not necessarily required between the two in order to exhibit the effects, and the electrode pads may be directly connected to each other.

　また、図８（ｂ）は半導体チップ１０８の構造例を示す平面図である。同図に示されるように、パワートランジスタは、ゲート電極，ドレイン電極及びソース電極により構成されている。そして、図７中の電極パッド１０７ａは図８（ｂ）に示すソース電極に接続されるソースパッドであり、図７中の電極パッド１０７ｂは図８（ｂ）に示すドレイン電極に接続されるドレインパッドである。なお、ゲート電極に接続されるゲートパッドは図７には図示されていない。 FIG. 8B is a plan view showing a structural example of the semiconductor chip 108. As shown in the figure, the power transistor is composed of a gate electrode, a drain electrode and a source electrode. The electrode pad 107a in FIG. 7 is a source pad connected to the source electrode shown in FIG. 8B, and the electrode pad 107b in FIG. 7 is a drain pad connected to the drain electrode shown in FIG. It is a pad. The gate pad connected to the gate electrode is not shown in FIG.

　　（第７の実施形態）
　図９は、第７の実施形態に係る半導体装置の一部を示す断面図である。図９において符号と部材の関係は埋め込み部材兼バンプ２０１を除き図７と同じである。本実施形態では、ＢＣＢ膜３に形成された接続孔に埋め込む金属膜を厚めにしてＢＣＢ膜３の上面よりも上方に突出する埋め込み部材兼バンプ２０１を形成しておき、半導体チップ１０８をフリップ実装したときに、信号接続用の電極パッド１０７ｂがマイクロバンプを介して回路基板５０上の電極パッド１０４ｂに接続されると同時に、接地用の電極パッド１０７ａが埋め込み部材兼バンプ２０１に接続されるようにしたものである。すなわち、本実施形態では、この埋め込み部材兼バンプ２０１により、放熱用部材が構成されている。 (Seventh embodiment)
FIG. 9 is a cross-sectional view illustrating a part of the semiconductor device according to the seventh embodiment. In FIG. 9, the relationship between the reference numerals and members is the same as that of FIG. In the present embodiment, the metal film embedded in the connection hole formed in the BCB film 3 is made thicker to form an embedding member / bump 201 projecting above the upper surface of the BCB film 3, and the semiconductor chip 108 is flip-mounted. Then, the electrode pad 107b for signal connection is connected to the electrode pad 104b on the circuit board 50 via the micro-bump, and at the same time, the electrode pad 107a for ground is connected to the embedded member / bump 201. It was done. That is, in the present embodiment, the heat dissipation member is configured by the embedded member / bump 201.

　本実施形態では、上記第６の実施形態における埋め込み部材２００，電極パッド１０４ａ及びマイクロバンプ１０７ａが一体化された埋め込み部材兼バンプ２０１を設けた構造となっているので、第６の実施形態と同様の効果をより簡易なプロセスで得ることができる。 The present embodiment has a structure in which the embedded member 200, the electrode pad 104a, and the micro-bump 107a are integrated with the embedded member 200 and the bump 201 of the sixth embodiment, so that the structure is the same as that of the sixth embodiment. Can be obtained with a simpler process.

　なお、電極パッド１０７ｂ−１０４ｂ間に設けるマイクロバンプ１０６を弾力性のある材料で構成することにより、半導体チップ１０８と回路基板５０との間の３カ所における接触を確保するための各部の高さの調整は容易となる。 The micro bumps 106 provided between the electrode pads 107b and 104b are made of a resilient material, so that the height of each part for ensuring contact between the semiconductor chip 108 and the circuit board 50 at three places is secured. Adjustment becomes easy.

　　（第８の実施形態）
　図１０は、第８の実施形態に係る半導体装置の一部を示す断面図である。図１０において符号と部材の関係は放熱・接地用支持体２１０を除き図７と同じである。本実施形態では、接地導体膜２のうち半導体チップ１０８の接地用の電極パッド１０７ａの下方となる部分の上に、接地と放熱のための導電性材料からなる支持体２１０を形成する。そして、この支持体２１０を形成した後、ＢＣＢ膜３を塗布する。支持体２１０の厚みをＢＣＢ膜３と電極パッド１０４ｂとの合計厚みと同じ程度にしておくことで、他の電極と同時にマイクロバンプを介してフリップチップ実装できる。 (Eighth embodiment)
FIG. 10 is a sectional view showing a part of the semiconductor device according to the eighth embodiment. In FIG. 10, the relationship between the reference numerals and members is the same as that of FIG. In the present embodiment, a support 210 made of a conductive material for grounding and heat dissipation is formed on a portion of the grounding conductor film 2 below the grounding electrode pad 107a of the semiconductor chip 108. Then, after forming the support 210, the BCB film 3 is applied. By setting the thickness of the support 210 to be approximately the same as the total thickness of the BCB film 3 and the electrode pads 104b, flip chip mounting can be performed simultaneously with other electrodes via micro bumps.

　本実施形態では、横断面積の大きい導電性材料からなる支持体２１０を設けることで、第６および第７の実施形態よりもさらに強固で安定なチップの支持と熱放散が可能になる。 In this embodiment, by providing the support 210 made of a conductive material having a large cross-sectional area, it is possible to more firmly and stably support the chip and dissipate heat as compared with the sixth and seventh embodiments.

　　（第９の実施形態）
　図１１は、第９の実施形態に係る半導体装置の一部を示す断面図である。図１１において符号と部材の関係は接地導体膜２の凸部２１１を除き図１０と同じである。本実施形態では、半導体チップ１０８の接地用電極パッド１０７ａの下方となる部分に凸部２１１を有する接地導体膜２を形成した後、接地導体膜２の凸部２１１の周囲にＢＣＢ膜３を塗布する。 (Ninth embodiment)
FIG. 11 is a sectional view showing a part of the semiconductor device according to the ninth embodiment. In FIG. 11, the relationship between the reference numerals and the members is the same as that in FIG. In the present embodiment, after the ground conductor film 2 having the protrusion 211 is formed in a portion below the ground electrode pad 107 a of the semiconductor chip 108, the BCB film 3 is applied around the protrusion 211 of the ground conductor film 2. I do.

　本実施形態では、第６の実施形態における埋め込み部材２００または第８の実施形態における放熱・接地用の支持体２１０を、より簡易な方法で実現するものである。すなわち、本実施形態では放熱・接地用支持体が必要となるべき部分の接地導体膜を予め厚く形成しておき、これを放熱・接地用支持体として用いることにより、第６の実施形態における接続孔及び埋め込み部材の形成工程や、第８の実施形態における開口及び支持体を形成する工程が不要となるので、第６、第８の実施形態と同様の効果を、より簡単なプロセスで実現できる。 In the present embodiment, the embedded member 200 in the sixth embodiment or the heat radiation / grounding support 210 in the eighth embodiment is realized by a simpler method. That is, in this embodiment, the grounding conductor film in the portion where the heat dissipation / grounding support is required is formed in advance to be thick, and this is used as the heat dissipation / grounding support. Since the step of forming the hole and the embedded member and the step of forming the opening and the support in the eighth embodiment are not required, the same effects as in the sixth and eighth embodiments can be realized by a simpler process. .

　　（第１０の実施形態）
　図１２は第１０の実施形態に係る半導体装置の一部を示す断面図である。図９において符号と部材の関係は以下の通りである。１はＳｉやガラス等からなる基板、２は基板１の上に形成された例えばＡｕからなる接地導体膜、３はＢＣＢ膜、３１はＢＣＢ膜３の一部に形成された開口部、１０３はＢＣＢ膜３上に例えばＴｉ，Ａｕを積層して形成された配線導体膜である。上記配線導体膜１０３，誘電体膜３及び接地導体膜２によりマイクロストリップ線路が構成されている。また、１０４ｂはＢＣＢ膜３の上に形成された電極パッドであり、配線導体膜１０３に接続されている。 (Tenth embodiment)
FIG. 12 is a sectional view showing a part of the semiconductor device according to the tenth embodiment. In FIG. 9, the relationship between reference numerals and members is as follows. Reference numeral 1 denotes a substrate made of Si or glass, 2 denotes a ground conductor film made of, for example, Au formed on the substrate 1, 3 denotes a BCB film, 31 denotes an opening formed in a part of the BCB film 3, and 103 denotes The wiring conductor film is formed by stacking, for example, Ti and Au on the BCB film 3. The wiring conductor film 103, the dielectric film 3, and the ground conductor film 2 constitute a microstrip line. Reference numeral 104 b denotes an electrode pad formed on the BCB film 3, and is connected to the wiring conductor film 103.

　ここで、本実施形態の特徴は、主面上に高周波トランジスタやパワートランジスタを有する半導体チップ１０８が、主面を上方に向けた状態で回路基板５０上に搭載されており、半導体チップ１０８と回路基板５０との間を接続するための配線接続用チップ２２０がフェースダウンで回路基板５０上にフリップチップ接続されている点である。すなわち、半導体チップ１０８の裏面と回路基板５０の接地導体膜２とが接しており、半導体チップ１０８内のトランジッスタに接続される信号用の電極パッド１０７ｂが半導体チップ１０８の主面側に形成されている。配線接続用チップ２２０は例えば半導体により構成されていて、配線接続用チップ２２０の上には、配線導体膜２２１と、この配線導体膜２２１に接続される電極パッド２２２ａ，２２２ｂとが設けられている。そして、回路基板５０上の信号用の電極パッド１０４ｂと配線接続用チップ２２０上の電極パッド２２２ｂとの間、及び半導体チップ１０８上の信号用の電極パッド１０７ｂと配線接続用チップ２２０上の電極パッド２２２ａとの間は、マイクロバンプ１０６を介してそれぞれ接続されている。すなわち、回路基板５０上の電極パッド１０４ｂと半導体チップ１０８上の電極パッド１０７ｂが、配線接続用チップ２２０上の配線導体膜２２１を利用して接続されていることになる。 Here, a feature of the present embodiment is that a semiconductor chip 108 having a high-frequency transistor or a power transistor on a main surface is mounted on a circuit board 50 with the main surface facing upward. The point is that the wiring connection chip 220 for connecting to the substrate 50 is flip-chip connected on the circuit substrate 50 face down. That is, the back surface of the semiconductor chip 108 is in contact with the ground conductor film 2 of the circuit board 50, and the signal electrode pads 107 b connected to the transistors in the semiconductor chip 108 are formed on the main surface side of the semiconductor chip 108. I have. The wiring connection chip 220 is made of, for example, a semiconductor. On the wiring connection chip 220, a wiring conductor film 221 and electrode pads 222a and 222b connected to the wiring conductor film 221 are provided. . The signal electrode pad 104b on the circuit board 50 and the electrode pad 222b on the wiring connection chip 220, and the signal electrode pad 107b on the semiconductor chip 108 and the electrode pad on the wiring connection chip 220 222a are connected via the micro bumps 106, respectively. That is, the electrode pads 104b on the circuit board 50 and the electrode pads 107b on the semiconductor chip 108 are connected using the wiring conductor film 221 on the wiring connection chip 220.

　本実施形態では、熱を発生する半導体チップ１０８が接地導体膜２に直接接しているので、半導体チップ１０８で発生する熱の放熱効果を大幅に向上させることができる。しかも、半導体チップ１０８と回路基板５０上の配線導体膜１０３とは、フリップチップ実装される配線接続用チップ２２０を介して接続されているので、インダクタとなるワイヤを使用する必要もなくなり、フリップチップ接続による優れた高周波特性を得ることができる。また、配線接続用チップ２２０上の配線２２１は、回路基板５０の接地導体膜２に対しマイクロストリップ線路を構成しているので、ワイヤボンドやリボンボンドで電極を接続するのとは異なり、ＭＦＩＣの特徴であるインピーダンスの乱れのない良好な高周波接続が可能になる。一方、配線導体膜２２１のインピーダンスは、ＢＣＢ膜３の厚み、マイクロバンプ１０６の厚み等を考慮することによって設計できる。特に、ＭＢＢ法のようなマイクロバンプの厚みの小さいフリップチップ実装技術を用いることで、より正確な設計が可能になる。 In the present embodiment, since the semiconductor chip 108 that generates heat is in direct contact with the ground conductor film 2, the heat radiation effect of the heat generated in the semiconductor chip 108 can be significantly improved. Moreover, since the semiconductor chip 108 and the wiring conductor film 103 on the circuit board 50 are connected via the wiring connection chip 220 mounted on the flip chip, it is not necessary to use a wire serving as an inductor, and the flip chip is not required. Excellent high-frequency characteristics can be obtained by connection. Further, since the wiring 221 on the wiring connecting chip 220 forms a microstrip line with respect to the ground conductor film 2 of the circuit board 50, unlike the case where electrodes are connected by wire bonding or ribbon bonding, Good high-frequency connection without characteristic disturbance of impedance becomes possible. On the other hand, the impedance of the wiring conductor film 221 can be designed by considering the thickness of the BCB film 3, the thickness of the micro bumps 106, and the like. In particular, by using a flip chip mounting technique with a small thickness of the micro bumps such as the MBB method, a more accurate design becomes possible.

　なお、本実施形態では設けていないが、半導体チップ１０８中にＰＨＳ（バイアホールに金属を埋め込んだヒートシンク）を形成すればさらに高い放熱効果を得ることができる。 Although not provided in the present embodiment, a higher heat dissipation effect can be obtained by forming a PHS (heat sink in which a metal is buried in a via hole) in the semiconductor chip 108.

　なお、本実施形態では配線接続用チップ２２１上には配線導体膜２２１のみを設けたが、この配線接続用チップ２２１上に小信号トランジスタやマッチング回路等を搭載することで、より高機能なＭＦＩＣが実現できる。 In the present embodiment, only the wiring conductor film 221 is provided on the wiring connection chip 221. However, by mounting a small signal transistor, a matching circuit, and the like on the wiring connection chip 221, a more sophisticated MFIC Can be realized.

　本発明は、特に、準ミリ波〜ミリ波領域で使用する高周波半導体装置およびその集積回路に利用することができる。 The present invention can be applied particularly to a high-frequency semiconductor device used in a quasi-millimeter wave to millimeter wave region and an integrated circuit thereof.

第１の実施形態に係る回路基板の一部を示す断面図，その変形例に係る回路基板の一部を示す断面図及びその等価回路図である。FIG. 4 is a cross-sectional view illustrating a part of a circuit board according to the first embodiment, a cross-sectional view illustrating a part of a circuit board according to a modification example thereof, and an equivalent circuit diagram thereof. 第２の実施形態に係る回路基板の一部を示す断面図である。FIG. 6 is a cross-sectional view illustrating a part of a circuit board according to a second embodiment. 第３の実施形態に係る回路基板の一部を示す断面図である。FIG. 11 is a cross-sectional view illustrating a part of a circuit board according to a third embodiment. 第４の実施形態に係る回路基板の一部を示す断面図である。It is sectional drawing which shows a part of circuit board concerning 4th Embodiment. 第５の実施形態に係るブリッジ上の抵抗体を設けた２種類の半導体装置の一部を示す断面図である。It is sectional drawing which shows a part of 2 types of semiconductor devices which provided the resistor on the bridge which concerns on 5th Embodiment. 第５の実施形態のうちの１つの回路基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of one circuit board of 5th Embodiment. 第６の実施形態に係る半導体装置の一部を示す断面図である。FIG. 14 is a cross-sectional view illustrating a part of a semiconductor device according to a sixth embodiment. 第６の実施形態に係る半導体装置の埋め込み部材とマイクロバンプとの中心位置をずらせた変形例に係る半導体装置及び半導体チップの平面図である。FIG. 18 is a plan view of a semiconductor device and a semiconductor chip according to a modification in which the center positions of the embedded member and the microbump of the semiconductor device according to the sixth embodiment are shifted. 第７の実施形態に係る半導体装置の一部を示す断面図である。FIG. 14 is a cross-sectional view illustrating a part of a semiconductor device according to a seventh embodiment. 第８の実施形態に係る半導体装置の一部を示す断面図である。FIG. 14 is a cross-sectional view illustrating a part of a semiconductor device according to an eighth embodiment. 第９の実施形態に係る半導体装置の一部を示す断面図である。FIG. 14 is a cross-sectional view illustrating a part of a semiconductor device according to a ninth embodiment. 第１０の実施形態に係る半導体装置の一部を示す断面図である。FIG. 14 is a cross-sectional view illustrating a part of a semiconductor device according to a tenth embodiment. 従来のＭＦＩＣの一部を示す断面図である。It is sectional drawing which shows a part of conventional MFIC.

符号の説明Explanation of reference numerals

　１　　基板
　２　　接地導体膜（接地導体部）
　３　　ＢＣＢ膜（誘電体膜）
　４　　放熱用導体膜
　５　　層間絶縁膜
　６　　抵抗体膜（発熱性膜）
　７　　配線導体膜
　８　　埋め込み導体部
　１０　凹部
　１２　層間絶縁膜
　２０　トンネル部
　２１　埋め込みフォトレジスト膜
　５０　回路基板
　１０４ａ　接地用電極パッド
　１０４ｂ　信号用電極パッド
　１０５　　光硬化性樹脂
　１０６　　マイクロバンプ
　１０７ａ　接地用電極パッド
　１０７ｂ　信号用電極パッド
　１０８　　半導体チップ
　１１１　　上部電極
　２００　　埋め込み部材
　２０１　　埋め込み部材兼バンプ
　２１０　　支持体
　２１１　　凸部
　２２０　　配線接続用チップ
　２２１　　配線導体膜
　２２２ａ，２２２ｂ　電極パッド 1 substrate 2 ground conductor film (ground conductor part)
3 BCB film (dielectric film)
4 Heat dissipation conductor film 5 Interlayer insulation film 6 Resistor film (heat-generating film)
REFERENCE SIGNS LIST 7 wiring conductor film 8 buried conductor portion 10 concave portion 12 interlayer insulating film 20 tunnel portion 21 buried photoresist film 50 circuit board 104 a grounding electrode pad 104 b signal electrode pad 105 photocurable resin 106 microbump 107 a grounding electrode pad 107 b signal Electrode pad 108 semiconductor chip 111 upper electrode 200 embedding member 201 embedding member / bump 210 support 211 convex portion 220 wiring connection chip 221 wiring conductor film 222a, 222b electrode pad

Claims (4)

少なくとも一部に接地用導体部を有する基板と、上記接地用導体部の上に形成された誘電体膜と、上記誘電体膜の上に形成され上記接地用導体部及び上記誘電体膜と共にマイクロストリップ線路を構成する配線導体膜とを有する回路基板と、
　半導体基板と、該半導体基板の主面上に形成された高周波トランジスタと、上記半導体基板の主面上に形成され上記高周波トランジスタに接続されるチップ側接地用電極及びチップ側信号用電極を有するとともに、上記主面を下方に向け上記チップ側信号用電極と上記回路基板の配線導体膜とが電気的に接続された状態で上記回路基板上に搭載される半導体チップとを備えるとともに、
　上記半導体チップの上記チップ側接地用電極と上記回路基板の上記接地用導体部との間を熱伝導可能に接続する放熱用部材を備え、
　上記放熱用部材は、
　上記接地導体部のうち上記チップ側接地用電極の下方となる領域の上で厚く形成された凸部と、
　上記チップ側接地用電極と上記凸部との間に介在するバンプとにより構成されており、
　上記誘電体膜は、上記支持体の周囲を取り囲むように形成されていることを特徴とする半導体装置。 A substrate having at least a portion of a grounding conductor, a dielectric film formed on the grounding conductor, and a microstructure formed on the dielectric film together with the grounding conductor and the dielectric film; A circuit board having a wiring conductor film constituting a strip line,
A semiconductor substrate, a high-frequency transistor formed on the main surface of the semiconductor substrate, a chip-side ground electrode and a chip-side signal electrode formed on the main surface of the semiconductor substrate and connected to the high-frequency transistor; A semiconductor chip mounted on the circuit board in a state in which the chip-side signal electrode and the wiring conductor film of the circuit board are electrically connected with the main surface facing downward,
A heat-dissipating member that connects the chip-side grounding electrode of the semiconductor chip and the grounding conductor of the circuit board so as to be able to conduct heat,
The heat dissipating member,
A convex portion thickly formed on a region of the ground conductor portion below the chip-side grounding electrode,
It is constituted by a bump interposed between the chip-side grounding electrode and the convex portion,
A semiconductor device, wherein the dielectric film is formed so as to surround the support. 　請求項１記載の半導体装置において、
　上記バンプはいずれも厚みが５μｍ以下であることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device, wherein each of the bumps has a thickness of 5 μm or less. 　請求項１又は２記載の半導体装置において、
　上記誘電体膜は、有機樹脂により構成されていることを特徴とする半導体装置。 The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the dielectric film is made of an organic resin. 　請求項３記載の半導体装置において、
　上記誘電体膜は、ＢＣＢ（ベンゾシクロブテン），ポリイミド及びアクリルのうち少なくともいずれか１つにより構成されていることを特徴とする半導体装置。 The semiconductor device according to claim 3,
The semiconductor device, wherein the dielectric film is made of at least one of BCB (benzocyclobutene), polyimide, and acrylic.
JP2003343960A 2003-10-02 2003-10-02 Semiconductor device Pending JP2004007024A (en)

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JP28794596A Division JP3490851B2 (en) 1996-10-30 1996-10-30 Circuit board

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199206A (en) * 2009-02-24 2010-09-09 Nissan Motor Co Ltd Semiconductor device
EP3024026A1 (en) * 2014-11-07 2016-05-25 MediaTek Inc. Semiconductor package
WO2018123480A1 (en) * 2016-12-28 2018-07-05 タツタ電線株式会社 Heat dissipation board, heat dissipation circuit structure, and method for manufacturing same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199206A (en) * 2009-02-24 2010-09-09 Nissan Motor Co Ltd Semiconductor device
EP3024026A1 (en) * 2014-11-07 2016-05-25 MediaTek Inc. Semiconductor package
US9972593B2 (en) 2014-11-07 2018-05-15 Mediatek Inc. Semiconductor package
US10312210B2 (en) 2014-11-07 2019-06-04 Mediatek Inc. Semiconductor package
WO2018123480A1 (en) * 2016-12-28 2018-07-05 タツタ電線株式会社 Heat dissipation board, heat dissipation circuit structure, and method for manufacturing same
JPWO2018123480A1 (en) * 2016-12-28 2019-10-31 タツタ電線株式会社 Heat dissipation board, heat dissipation circuit structure, and manufacturing method thereof
US10893603B2 (en) 2016-12-28 2021-01-12 Tatsuta Electric Wire & Cable Co., Ltd. Heat dissipation substrate, heat dissipation circuit structure body, and method for manufacturing the same

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