JPH10505466A - Microwave / millimeter wave circuit structure and a manufacturing method thereof having a flip-chip installed the discrete elements - Google Patents

Microwave / millimeter wave circuit structure and a manufacturing method thereof having a flip-chip installed the discrete elements

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Publication number
JPH10505466A
JPH10505466A JP50586297A JP50586297A JPH10505466A JP H10505466 A JPH10505466 A JP H10505466A JP 50586297 A JP50586297 A JP 50586297A JP 50586297 A JP50586297 A JP 50586297A JP H10505466 A JPH10505466 A JP H10505466A
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Prior art keywords
substrate
circuit
microwave
millimeter wave
interconnection network
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JP50586297A
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ペリー・エー マクドナルド、
メーラン マットルービアン、
ローレンス・エー ラルソン、
デイビッド・ビー レンシュ、
Original Assignee
エイチイー・ホールディングス・インコーポレーテッド・ドゥーイング・ビジネス・アズ・ヒューズ・エレクトロニクス
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Priority to US499,800 priority Critical
Priority to US08/499,800 priority patent/US5629241A/en
Application filed by エイチイー・ホールディングス・インコーポレーテッド・ドゥーイング・ビジネス・アズ・ヒューズ・エレクトロニクス filed Critical エイチイー・ホールディングス・インコーポレーテッド・ドゥーイング・ビジネス・アズ・ヒューズ・エレクトロニクス
Priority to PCT/US1996/011144 priority patent/WO1997002733A2/en
Publication of JPH10505466A publication Critical patent/JPH10505466A/en
Application status is Pending legal-status Critical

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Abstract

(57)【要約】 マイクロ波/ミリメートル波回路構造は、セラミックでも半導体でもない低コストの誘電性基板(2)、好ましくはデュロイド基板上の相互接続ネットワーク(10)にフリップチップ設置することによってディクリートな回路素子を支持する。 (57) Abstract: Microwave / millimeter wave circuit structure, low cost nor the semiconductor in the ceramic dielectric substrate (2), di preferably by flip chip installed in the interconnection network of Duroid substrate (10) supporting the cleat circuit elements. 高い動作周波数のために必要とされる基板ネットワーク上での回路素子とコンタクトパッド(14)との正確な整列は、相互接続ネットワークを酸化し(20)、非酸化材料(14′)で形成されたコンタクトパッドを設け、パッドに対してぬれ性のはんだバンプを設けることによって容易にされる。 Precise alignment between the circuit element and the contact pads on the substrate network (14) required for the high operating frequency oxidizes interconnection network (20), it is formed in a non-oxidizing material (14 ') the contact pads provided with, is facilitated by providing a wettability of the solder bump against the pad. その代りに、フリップチップ上のコンタクトバンプは、相互接続ネットワーク上のパッシベーション層における対応する開口を通して正確に位置されることもできる。 Instead, contact bumps on the flip chip can also be positioned accurately through opening corresponding in passivation layer on the interconnect network. 薄い回路基板は良好にフリップチップを設置するには柔らかすぎるため、回路基板には補助基板が積層される。 Thinner circuit board too soft to properly install a flip chip, the circuit board auxiliary substrate is laminated. 一方の面にアンテナが、他方の面に回路が設けられている2つの回路基板が一緒に積層される自己整列したアンテナアプリケーションにおいて、基板の間の金属製接地平面も補強機能を助ける。 Antenna on one surface thereof, in other antenna applications with self-aligned two circuit board circuit is provided on a surface are laminated together, a metal ground plane between the substrate also help reinforcing function.

Description

【発明の詳細な説明】 フリップチップ設置されたディスクリートな素子を有するマイクロ波/ミリメートル波回路構造およびその製造方法発明の背景 発明の分野本発明は、マイクロ波/ミリメートル波回路に関し、特に、ディスクリートな回路素子を使用するこの波長範囲の回路構造に関する。 BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present microwave / millimeter wave circuit structure and manufacturing method invention has a flip-chip installed the discrete element relates microwave / millimeter wave circuit, in particular, discrete a circuit structure of the wavelength range to be used for circuit elements. 従来技術の説明マイクロ波/ミリメートル波のスペクトルは、一般的に300MHzにおける約1mから300GHzにおける約1mmまで延在するものとして定義され、スペクトルのミリメートル波部分は約30乃至300GHzに及んでいる。 Spectrum of the prior art described microwave / millimeter wave is generally defined as extending from about 1m in 300MHz to approximately 1mm in 300 GHz, millimeter wave portion of the spectrum is up to about 30 to 300 GHz. マイクロ波/ミリメートル波回路は、電話送信、電子レンジ、レーダ等の多数のアプリケーションと、衝突防止レーダ、ミリメートル波画像システム、盲点レーダ、市外交換、道路表面監視用レーダを含む自動車における使用のために開発されてきた。 Microwave / millimeter wave circuit, telephone transmission, and numerous applications such as a microwave oven, radar, collision avoidance radar, millimeter wave imaging system, blind spot radar, toll switch, for use in motor vehicles, including a road surface monitoring radar It has been developed. それらは一般的に、回路板基板にワイヤ接合されたディスクリートな素子を有するハイブリッド回路として、あるいは能動回路素子が受動素子と同じウエハ上に集積されるモノリシックマイクロ波集積回路(MMIC)として構成される。 They are generally constructed as a monolithic microwave integrated circuit as a hybrid circuit having a circuit board substrate to the wire bonded discrete elements, or the active circuit elements are integrated on the same wafer on a passive element (MMIC) . 衝突防止レーダ等のマイクロ波装置の開発はMMICの使用に依存してきたが、幾つかの要因によってMMICの製造がディスクリートな装置の製造よりも相当に高価になってしまう。 Although the development of the microwave devices such as anti-collision radar have relied on the use of MMIC, the production of MMIC becomes considerably more expensive than the manufacture of discrete devices by several factors. MMICは、ディスクリートな装置よりもかなり大きく、従って、半導体ウエハ上で多くの面積を占め、チップのコストはその寸法に大きく依存する。 MMIC is considerably greater than the discrete devices, therefore, occupies a large area on the semiconductor wafer, the cost of the chip is highly dependent on its size. また、 MMICの製造の複雑さのために、ディスクリートな装置で容易に達成できる8 0%以上の生産効率とは対照的に、それらの典型的な生産効率は15%乃至30 %程度のものである。 Further, due to the complexity of manufacturing the MMIC, in contrast to the readily 80% or more of production efficiency that can be achieved with discrete devices, their typical production efficiency of the order of 15% to 30% is there. 例えば、7.6cm(3インチ)のウエハから約14,0 00個の実用的なディスクリートな装置が得られることと比較して、MMICは約400個である。 For example, in comparison with the practical discrete devices from the wafer about 14,0 00 pieces of 7.6 cm (3 inches) is obtained, MMIC is about 400. “裏返し”されたチップの回路面に導電性コンタクト“バンプ”が設けられ、 そのバンプを介してチップが電気的および機械的に回路板に接着されるフリップチップ接合技術の使用は、H.Sakai 氏等による参照文献“A Novel Millimeter-W ave IC on Si Substrate Using Flip-Chip Bonding Technology”(IEEE MTT-S Digest,1994,pages 1763-1766)に開示されている。 "Turn" chips circuit surface conductive contact "bumps" are provided on the use of flip-chip bonding technology chip through the bump is bonded to electrically and mechanically circuit board, H.Sakai disclosed in Mr. like references "a Novel Millimeter-W ave IC on Si Substrate Using Flip-Chip Bonding Technology" by (IEEE MTT-S Digest, 1994, pages 1763-1766). この文献において、ミリメートル波ヘテロ接合トランジスタは、シリコン基板上に形成されたマイクロストリップラインに接合されたフリップチップである。 In this document, millimeter wave heterojunction transistor is flip-chip bonded to the microstrip line formed on a silicon substrate. しかしながら、シリコンは、ミリメートル波周波数において非常に高い損失を有する。 However, silicon has a very high loss in millimeter-wave frequencies. これらの損失を克服するために、Sakai 氏等は、マイクロストリップラインの製造に使用するためにシリコン基板上に9マイクロメートルの厚さのSiO を堆積した。 To overcome these losses, Sakai said etc. were deposited SiO 2 of 9 micrometers thick on a silicon substrate for use in the manufacture of the microstrip line. しかしながら、60GHzの場合の50オームの伝送ラインに対する損失は依然として0. However, the loss for the transmission line of 50 ohms in the case of 60GHz is still zero. 55dB/mmであり、それは低損失の整合素子、パワー結合器、およびカプラに対して高すぎる。 A 55 dB / mm, it is the matching element with low losses, power combiner, and too high for the coupler. 実際に、回路は60GHzではなく20GHzで試験動作するように作られており、それはおそらく高い周波数での過剰な伝送ラインの損失のためである。 In fact, the circuit is made to test operation at 20GHz rather than 60 GHz, it is probably due to the loss of excessive transmission lines at high frequencies. さらに、低い周波数の場合に通常回路板に使用されるシリコンならびにセラミック材料はかなり高価である。 Further, silicon and ceramic materials normally used for the circuit board in the case of the low frequency is fairly expensive. Sakai 氏等はまた、加熱しない絶縁樹脂の使用に基づいたバンプ技術も提案した。 Sakai said etc. also bump technology was also proposed based on the use of heated without insulating resin. これによって結果的に装置の配置の正確度が比較的低くなり、それはマイクロ波/ミリメートル波回路に関わる高い周波数において重要な要因である。 This results in accuracy is relatively low placement of the device, it is an important factor at high frequencies involved in the microwave / millimeter wave circuit. 実際に、ハイブリッド回路ではなくMMICに移行する主要な理由は、ハイブリッド回路は各回路を手動で調整する必要があるため結果的にコストが高くなるからであり、この処理は多くの時間を必要とし、また高価である。 Indeed, the primary reason for migrating the MMIC not a hybrid circuit, a hybrid circuit is because eventually the cost since it is necessary to adjust each circuit manually increases, this process requires a lot of time , also it is expensive. 周波数が高い程、整合素子(伝送ライン)の長さは短くなり、回路の性能はラインの長さおよび装置の配置における変化に対してより感応するようになる。 The higher the frequency, the length of the matching element (transmission line) is shortened, performance of the circuit becomes more sensitive to changes in the arrangement of the length and device lines. フリップチップ設置は、 主に装置の設置位置におけるわずかな変化が回路性能にとって重要でない低い周波数で使用される。 Flip chip installation, a slight change in the installation position of the main device is used at a low frequency not critical to circuit performance. しかしながら、マイクロ波/ミリメートル波の範囲において、装置の配置および取付けの正確度は、低コストの回路およびシステムの達成にとって非常に重要である。 However, in the microwave range / millimeter wave, the placement and attachment of the accuracy of the device is very important for achieving low-cost circuits and systems. Sakai 氏等は、たったの16マイクロメートルの伝送ライン幅に対して5.5マイクロメートルのチップ整列の正確度を達成しているが、 ライン幅に関してそのように低い配置正確度は、再現可能な回路性能を達成するためのミリメートル波周波数では許容不可能であると考えられてきた。 Sakai said etc., although to achieve the accuracy of the 5.5 micrometer tip positioning relative to the transmission line width of only 16 micrometer, such low placement accuracy with respect to the line width, reproducible in millimeter wave frequencies to achieve the circuit performance it has been considered to be unacceptable. Sakai 氏等によって使用された比較的損失が高く高価なシリコン基板と対照的に、低コストであり、損失レベルが低いデュロイド基板あるいは別の類似したプラスティックタイプの基板が開発されてきた。 In contrast relatively loss was used as high as expensive silicon substrate by Sakai Mr. like, low cost, the substrate loss levels are low Duroid substrate or another similar plastic types have been developed. デュロイド(Duroid)は、ドープされたテフロン(商標名)組成物(テフロンの化学式はPTFEである)に対するRogers社の商標である。 Duroid (Duroid) is doped Teflon (trade name) composition (chemical formula Teflon is PTFE) is a trademark of Rogers Corporation against. 低損失のプラスティックタイプの基板は、その両面上に金属被覆することによって廉価で入手でき、低損失の伝送ラインを製造するためにSakai 氏等によるSiO および2つの金属層の堆積を必要としない。 Substrate plastic type low loss, available inexpensive by metallization on both sides, do not require the deposition of SiO 2 and two metal layers by Sakai Mr. like to produce a transmission line of low loss . しかしながら、デュロイド基板は比較的柔らかく、それ故にそれらの上にディスクリート装置をワイヤ接合することは困難である。 However, Duroid substrate is relatively soft, it is difficult to thus wire bonding discrete devices on them. 低い周波数では、これらの基板は、デュロイド基板上に設置されるパッケージの内側にワイヤ接合されたディスクリートなトランジスタ等の、先にパッケージされた素子を使用するマイクロ波回路に対して使用される。 At low frequencies, these substrates is used for a microwave circuit using discrete transistors or the like which is inside the wire bonding of the package to be installed in Duroid substrate, the elements that are packaged previously. しかしながら、部品のパッケージ寄生が高すぎて、この試みはミリメートル波周波数では実行することができない。 However, the package parasitic components is too high, this approach can not be run on millimeter wave frequencies. また、約600マイクロメートル以下の厚さのデュロイド基板は非常にフレキシブルであるので、信頼できる自動的フリップチップ設置ができない。 Further, since Duroid substrate thickness of less than about 600 micrometers is a very flexible, can not trusted automatically flip chip installation. それ故に、MMICは通常アルミナ等の非常に硬い基板上にフリップチップ設置される。 Therefore, MMIC is flip chip installed usually very hard substrates such as alumina. 従って、所望されたような低コストであるにも関わらず、デュロイド基板は高い周波数のMMICのフリップチップ設置には適切でない。 Therefore, despite the low cost, as desired, Duroid substrate not suitable for flip chip installation of high frequency MMIC. 発明の概要本発明は、廉価であり、現在使用可能なMMIC技術よりも高い生産効率を達成するが、過剰な損失、ライン幅に関する装置配置の正確度の欠如、およびSaka i 氏等による試みのような比較的コストの高い基板の使用を回避するマイクロ波/ミリメートル波回路構造およびそれに関連した製造方法を提供することを目的としている。 The present invention is inexpensive, but to achieve a high production efficiency than currently available MMIC technology, excessive loss, lack of accuracy of the apparatus configurations for line width, and Saka i due attempt Mr. and its object is to provide a manufacturing method microwave / millimeter wave circuit structure and associated avoids the use of relatively costly substrate such as. これらの目的は、セラミックおよび半導体ではなく、低損失プラスティックであることが好ましい誘電性基板を使用するマイクロ波/ミリメートル波回路構造を使用して達成され、そこにおいて、ディスクリートな回路素子が基板にフリップチップ設置され、基板上の相互接続ネットワークによって電気的に相互接続される。 These objects, rather than the ceramic and semiconductor, be achieved using a microwave / millimeter wave circuit structure is using the preferred dielectric substrate is a low loss plastic, in which, discrete circuit elements flipped substrate is the chip installed, are electrically interconnected by an interconnection network on the substrate. 相互接続された回路素子間の間隔は、マイクロ波/ミリメートル波範囲内の電気信号と調和し、また、基板上のコンタクトパッドと自己整列するはんだバンプをチップ上で使用することにより高度に正確な装置の配置が達成され、手動で調整させる必要がなくなる。 Spacing between interconnected circuit elements, in harmony with electrical signals in the microwave / millimeter wave range and highly accurate by using a solder bump to the contact pads and self-aligned on the substrate on the chip placement of the device is achieved, it is not necessary to adjust manually. 好ましい実施形態において、相互接続ネットワークの表面は酸化され、一方、 基板のコンタクトパッドは非酸化材料から形成され、それらはニッケル/金であることが好ましい。 In a preferred embodiment, the surface of the interconnection network is oxidized, while the contact pads of the substrate is formed from a non-oxidizing material, it is preferred that they are nickel / gold. 酸化された表面によって、はんだバンプがそこに流動することが阻止され、それによって、バンプおよびそれらの関連した回路が基板のパッド上で正確に自己整列することが強化される。 The oxidized surface, is prevented to be fluidized therein the solder bumps, thereby it is enhanced to the bumps and their associated circuitry to accurately self-aligned on the substrate pad. ミリメートル波周波数での動作を最適にするために、隣接したバンプ間の間隔は約125マイクロメートル以下であり、パッドの幅は約50マイクロメートル以下である。 For optimum operation at millimeter wave frequencies, the interval between adjacent bumps is not more than about 125 micrometers, the width of the pad is less than or equal to about 50 micrometers. 回路素子の配置の正確度を高めるための別の方法として、基板がパッシベーション層で被覆され、そこにおいて、バンプ位置に開口が形成され、バンプが各開口を貫通して下部の相互接続ネットワークと接触している。 Another method for increasing the accuracy of the arrangement of circuit elements, the substrate is coated with a passivation layer, in which an opening is formed in the bump position, contacts the lower portion of the interconnection network bumps through each aperture doing. 約600マイクロメートル以下の薄いプラスティック基板に必要な剛性を与えるために、低コストの補強基板が主基板に接着されることが好ましい。 To provide the necessary stiffness about 600 micrometers or less thin plastic substrate, a low-cost reinforcing substrate is preferably bonded to the main substrate. 小型のトランシーバ装置は、2つのデュロイド基板の一方がトランシーバ回路を支持し、 デュロイド基板の他方がそれら基板を通してトランシーバ回路と接続され、回路基板よりも低い誘電定数を有していることが好ましいアンテナを支持している状態でそれらを背中合わせに積層することによって構成されることができる。 Small transceiver devices, one of the two Duroid substrate supporting the transceiver circuit, the other Duroid substrate is connected to the transceiver circuit through them board, the antenna preferably has a lower dielectric constant than the circuit board they can be configured by laminating the back-to-back in a state where the supporting. 2つの基板の間の金属層は、接地平面および補強層の二重機能を行い、別個の補強基板がフリップチップ回路上に設けられてもよい。 Metal layer between two substrates, performs a dual function of the ground plane and the reinforcing layer, separate reinforcing substrate may be provided on the flip chip circuitry. 本発明のこれらおよびその他の特徴および利点は、添付図面と共に以下の詳細な説明から当業者に明らかとなる。 These and other features and advantages of the present invention will become apparent from the following detailed description in conjunction with the accompanying drawings to those skilled in the art. 図面の簡単な説明図1、図2、および図3は、フリップチップ回路上でのバンプコンタクトの製造における連続したステップを示す部分的断面図である。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1, Figure 2, and Figure 3 is a partial sectional view showing a sequence of steps in the manufacture of the bump contacts on the flip-chip circuitry. 図4は、相互接続基板上に設けられたフリップチップを示す部分的断面図である。 Figure 4 is a partial sectional view showing a flip chip provided interconnection substrate. 図5は、非酸化バンプコンタクトパッドを支持する酸化鉛と相互接続した基板の部分的断面図である。 Figure 5 is a partial cross-sectional view of the substrate interconnected and lead oxide for supporting the non-oxidized bump contact pads. 図6は、非酸化バンプコンタクトパッドを支持する酸化鉛と相互接続した基板の平面図である。 Figure 6 is a plan view of a substrate on which interconnected with lead oxide to support the non-oxidized bump contact pads. 図7は、バンプコンタクト開口を有するパッシベーション層および強化背面体を含む本発明による回路基板の斜視図である。 Figure 7 is a perspective view of a circuit board according to the invention comprising a passivation layer and reinforcing the rear body having a bump contact opening. 図8は、1対の回路チップが基板にフリップチップ設置されている状態の図7 の回路基板の断面図である。 8, a pair of circuit chips is a cross-sectional view of the circuit board of FIG. 7 in a state that is flip-chip placed on the substrate. 図9は、一方の面においてフリップチップトランシーバ回路を有し、他方の面においてアンテナを有する二重基板構造の斜視図である。 Figure 9 is the one side has a flip-chip transceiver circuits is a perspective view of a dual substrate structure having an antenna on the other surface. 図10は、図9の構造に設けられたフリップチップおよびビームリードチップを示す断面図である。 Figure 10 is a sectional view showing a flip chip, and beam lead chip provided on the structure of FIG. 図11は、図9の二重基板構造の形成に使用される2つの基板の断面図である。 Figure 11 is a cross-sectional view of two substrates to be used in the formation of a double substrate structure of FIG. 図12は、二重アンテナ/回路基板のアンテナ側を示す斜視図である。 Figure 12 is a perspective view showing an antenna side of the dual antenna / circuit board. 図13は、図12の構造の回路側を示す斜視図である。 Figure 13 is a perspective view showing the circuit side of the structure of FIG. 12. 実施例本発明は、ディスクリートな能動回路素子を本発明による基板にフリップチップ設置することによってマイクロ波/ミリメートル波回路の信頼性およびコストを改良する。 EXAMPLES The present invention improves the reliability and cost of the microwave / millimeter wave circuit by flip chip placed on the substrate according to the present invention the discrete active circuit elements. 本発明によって、この高い周波数範囲において他の方法では禁止要因となると思われる臨界的な整列の問題が克服される。 The present invention, the critical alignment problems in other ways seems to be inhibited factors are overcome in this high frequency range. 図1乃至3において、フリップチップ装置上での接合パッドの形成が示されている。 1 through 3, the formation of bonding pads on the flip chip device is shown. 図1において、InPあるいはGaAs等の半導体から形成されたフリップチップ2がその回路面が上方を向いた状態で示されているが、回路自体は図示されていない。 In Figure 1, the flip chip 2 formed of a semiconductor such as InP or GaAs is shown with its circuit surface facing upward, the circuit itself is not shown. チップの回路面は、パターン化されて開口を有するフォトレジスト4で被覆されており、その開口中にコンタクトパッド6 が回路と接続した状態で形成されている。 Circuit surface of the chip and patterned is coated with a photoresist 4 having an opening, the contact pads 6 are formed in a state of being connected to the circuit during the opening. 回路の相互接続のために使用されたAuと共に、パッドは典型的にTi/Pt/AuあるいはNi/Auから形成されている。 With Au used for circuit interconnections, pads are typically formed from Ti / Pt / Au or Ni / Au. その後、フォトレジストの開口の上部部分において、(すず/鉛等の合金から作られた)はんだコンタクト“バンプ”8 がめっきされる。 Thereafter, the upper portion of the opening of the photoresist, (tin / made from an alloy such as lead) solder contact "bumps" 8 is plated. コンタクトバンプそれ自体は新しくなく、それらは例えばSakai 氏等による上述の参照文献において開示されており、そこにおいて、はんだバンプ装置が基板に設けられる際の正確度は、マイクロ波/ミリメートル波回路には不適切である。 Contact bump itself not new, they are disclosed in the above references, for example by Sakai Mr. like, in which, the accuracy at which the solder bumps device is provided on the substrate, the microwave / millimeter wave circuit it is inappropriate. 本発明によって、自動システムによる冗長な整列の必要なしに(125マイクロメートルの伝送ラインの幅で)約2マイクロメートル程度の正確度で整列させる、より正確な装置の配置が提供される。 The present invention, an automated system without the need for redundant alignment by (the width of the transmission line 125 micrometers) are aligned at about 2 micrometer order accuracy, placement more accurate device is provided. 一度、はんだバンプ8 がめっきされると、フォトレジストが図2に示されているように取除かれる。 Once the solder bumps 8 are plated, the photoresist is removed as shown in FIG. マイクロ波/ミリメートル波周波数と両立させるために、 バンプは典型的に25マイクロメートルの高さおよび50マイクロメートルの幅を有し、いずれにしても約100マイクロメートルを越えない幅を有し、所定の装置における隣接したバンプ間の間隔は典型的に約150マイクロメートルに維持される。 In order to satisfy both the microwave / millimeter wave frequencies, bump typically has a width of height and 50 micrometers 25 micrometers, a width not exceeding about 100 micrometers Anyway, predetermined the spacing between adjacent bumps in the apparatus is maintained at typically about 150 micrometers. これは、高さおよび幅が75マイクロメートルであり、隣接したバンプ間の間隔が250乃至375マイクロメートルである典型的な従来のフリップチップのバンプの寸法と対照をなす。 This height and width is 75 micrometers, in contrast to the dimensions of the spacing between adjacent bumps is 250 to 375 micrometers typical bump of a conventional flip chip. フォトレジストの除去の後、バンプ8 は、図3に示されているようにある程度平坦な輪郭になるように予備溶融される。 After removal of the photoresist, the bump 8 is pre-melted to become somewhat flat contour as shown in Figure 3. 錫鉛はんだには、220℃の予備溶融温度が適切である。 Tin-lead in the solder, pre-melting temperature of 220 ° C. is appropriate. その後、チップは裏返しにされ、以下に説明されるような特有の特性を有する特別な基板12上に設置される。 Thereafter, the chip is upside down, it is placed on a special substrate 12 having the unique properties as described below. この基板は、典型的にパターン化された銅のネットワークである金属被覆された相互接続ネットワークをその上部表面上で支持し、そのネットワークの1対のリード線10は図4に示されている。 The substrate is typically an interconnection network which is metallized is patterned copper networks supported on its upper surface, the lead wire 10 of the pair of the network is shown in Figure 4. パッド14は所望された接触位置で基板の金属被覆上に設けられ、基板のパッド14は一般的にチップのパッド6 に類似している。 Pad 14 is similar desired contact location is provided on the metal coating of the substrate, the pad 14 of the substrate is generally pads 6 of the chip. チップが所定の位置に置かれたとき、はんだパッド8 は加熱され、それらが接着するように再溶融され、基板パッド14との電気的接続が形成される。 When chips are placed in a predetermined position, the solder pads 8 are heated, they are re-melted to adhere, electrical connection between the substrate pads 14 are formed. 必要な熱は、装置を対流式炉内に配置し、 高温のガスをチップ上に流すか、あるいは加熱ランプを使用する等の従来の技術によって供給されることができる。 Necessary heat is to place the device in a convection oven, can be a high-temperature gas is supplied by conventional techniques such as the use of flow or, alternatively heat lamp on the chip. 加熱処理中に、はんだの表面張力によってバンプが基板のパッド14と自己整列するようになる。 During the heat treatment, the bumps by the surface tension of the solder is such that the self-aligned with the pad 14 of the substrate. これは、必要とされる高レベルの配置正確度を得るのに有効である。 This is effective to obtain a placement accuracy of the high level required. 配置の正確度は、酸化可能な基板の金属被覆をその金属被覆上の非酸化コンタクトパッドと組合わせることによってさらに改良される。 The accuracy of placement is improved further by combining the metal coating of oxidizable substrate a non-oxidized contact pads on the metal coating. この構造は、図5および図6に示されている。 This structure is illustrated in FIGS. 基板の金属被覆10は銅等の通常の材料から形成され、一方、コンタクトパッド14′は酸化しない(あるいは金属被覆よりも実質的に高い温度で酸化する)材料から形成される。 The metal coating 10 of the substrate is formed from conventional materials such as copper, on the other hand, the contact pads 14 '(oxidize at temperatures substantially higher than or metallization) which is not oxidized is formed from a material. この目的には、金層18によって被覆されたニッケル層16が好ましく、チタン、プラチナおよび金を積層した層も使用されることができる。 For this purpose, the nickel layer 16 is preferably coated with a gold layer 18, titanium can also be used a layer formed by laminating a platinum and gold. 基板が加熱されて金属被覆10の上に酸化物層20が形成されるが、コンタクトパッド14′上には形成されない。 Although the substrate is heated with an oxide layer 20 on the metal coating 10 is formed, not formed on the contact pad 14 '. その後、はんだバンプが基板のコンタクトパッド14′上に再溶融されたとき、その周囲の金属被覆の酸化物20は、 はんだが金属被覆上に流れることを防ぎ、それは、酸化物によってはんだがぬれ性でない表面を有するようになるからである。 Thereafter, when the solder bumps are re-melted on the contact pad 14 'of the substrate, the oxide 20 surrounding the metallization prevents the flow solder on the metal coating, it is wetting solder resistance by oxide This is because so having a surface not. すなわち、パッドははんだに優先的にぬれ性の表面を与え、それによってはんだバンプのパッドへの自己整列が増強され、フリップチップを基板上に正確に配置することができる。 That is, the pad provides a preferentially wetting of the surface to the solder, thereby self-aligned to the solder bump pad is enhanced, it is possible to accurately place the flip chip on a substrate. 適切な錫鉛はんだの再溶融温度の範囲は180℃乃至250℃である。 Range remelting temperature suitable tin-lead solder is 180 ° C. to 250 ° C.. 装置の正確な配置を確実にするための別の実施形態が図7および図8に示されている。 Another embodiment to ensure accurate placement of the device is shown in FIGS. この実施形態における基板は、特別な利点を提供し、以下に詳細に説明されるようなセラミックでなく半導体でもない誘電性材料の比較的薄い層22であり、補強基板24によって背面を支持されている。 The substrate in this embodiment, provides particular advantages, relatively thin layer 22 of dielectric material nor the semiconductor rather than ceramic, such as described in detail below, is supported the back by the reinforcing board 24 there. 基板全体は、基板22に接着するポリイミドであることが好ましい薄いパッシベーション層26で被覆されている。 The entire substrate is coated it is preferred thin passivation layer 26 is a polyimide that adheres to the substrate 22. 小さい開口28のアレイはパッシベーション層を通して形成され、種々のフリップチップ2 のコンタクトバンプ8 に対して所望された位置に対応する。 Array of small openings 28 are formed through the passivation layer, corresponding to the desired position relative to contact bumps 8 of the various flip chip 2. 開口28はコンタクトバンプよりもわずかに大きいだけであり、それによって、バンプとパッシベーション層26の下部の基板22上の金属被覆(図示されていない)との間で正確な整列を助ける。 Opening 28 is only slightly larger than the contact bumps, thereby helping the accurate alignment between the metallization on the lower substrate 22 of the bumps and the passivation layer 26 and (not shown). このタイプのパッシベーション層は、従来フリップチップと共に使用されているが、マイクロ波/ミリメートル波動作のために必要とされる正確度の高い装置の配置を提供するためではない。 This type of passivation layer has been used with a conventional flip chip, but not to provide an arrangement of high accuracy equipment required for the microwave / millimeter wave operation. 種々のフリップチップに対する相互接続ネットワークが形成される主要基板22 は、セラミックでなく半導体でもない誘電性材料で構成され、それはデュロイドであることが好ましい。 Interconnection network main board is formed 22 for various flip chip is formed of a dielectric material nor the semiconductor rather than ceramic, it is preferably Duroid. 上述のように、デュロイドは廉価であるが、一般的にフリップチップに適用するにはフレキシブル過ぎると考えられてきた。 As described above, Duroid is less expensive, the generally applicable to flip-chip has been considered too flexible. 本発明は、 低コストのプラスティック基板であるために低コストであるという利益を享受するが、フリップチップ技術と調和するように基板構造を変更する。 The present invention enjoys the benefit of being inexpensive because a plastic substrate of low cost, to change the substrate structure to match the flip chip technology. デュロイドは通常、フリップチップ設置に十分な剛性を有していない約600マイクロメートル以下の厚さの基板にはそのような変更が必要である。 Duroid is typically the substrate of about 600 micrometers in thickness that does not have sufficient rigidity to flip chip installation is required such changes. 同様に、通常フリップチップに適用されるものとしては考えられない合成樹脂ベースの材料等の別の低コストの材料がデュロイドの代りに使用されることができるが、デュロイドが最も好ましいものである。 Similarly, usually can be another low-cost material such as the material of the synthetic resin base unthinkable as applied to a flip chip is used instead of Duroid, those Duroid is most preferred. フリップチップを設置するには薄すぎるデュロイド基板に対して、デュロイド基板22によって電気回路から分離され、それ故にフリップチップ設置基板に関連した電気特性を有する必要のない材料の補強基板24が設けられる。 Against Duroid substrate too thin to install the flip chip, it is electrically isolated from the circuit by Duroid board 22, thus reinforcing substrate 24 need not material having electrical characteristics associated with the flip chip installation substrate is provided. これによって補強基板に使用できる可能性のある材料の範囲が広くなり、任意の所定のアプリケーションのために選択された特定の材料は、一般的にそのコスト、その剛性特性、およびそれが装置にいくらかの電気的機能を供給するかどうかに依存する。 This wider range of possible materials that can be used for reinforcing the substrate, the particular material selected for any given application, typically its cost, somewhat to the stiffness properties, and it apparatus an electrical function depends on whether the supply of. この目的に対して好ましい補強基板は、表面板の製造に通常使用されている工業規格プラスティックであるFR4およびポリイミドである。 Preferred reinforcing substrate for this purpose is the FR4 and polyimide is an industry standard plastic which are usually employed in the manufacture of surface plates. デュロイド基板および補強基板は、それらの間に接合用接着剤30を用いて加熱/加圧処理を通して一緒に積層されることが好ましい。 Duroid substrate and the reinforcing substrate is preferably laminated together through heating / pressurizing treatment using the bonding adhesive 30 therebetween. 積層温度は、一般的に約250℃乃至300℃ である。 Lamination temperature is typically about 250 ° C. to 300 ° C.. 図9において、本発明の別の実施形態が示されており、そこにおいて、2つのデュロイド基板が一緒に積層され、両側の面上に回路素子が設けられた2面の高い周波数の装置が形成される。 9, there is shown another embodiment of the present invention, in which two Duroid substrate are laminated together, the apparatus of the high frequency two surfaces circuit element is provided on both side faces forming It is. 伝送ライン、バイアス回路、アンテナおよびパワー結合器等の受動回路素子は、低コストで一方あるいは両方の基板上に直接製造されることができる。 Transmission lines, the bias circuit, the antenna and the passive circuit elements of the power combiner and the like, can be produced directly in one or both of the substrates at a low cost. そのような受動回路素子の製造には微細な幾何学およびリソグラフィのステップが必要とされず、結果的に低コストで大量生産されることができる。 Not required steps fine geometry and lithography in the manufacture of such passive circuit elements can be mass-produced at consequently lower cost. トランジスタ、バラクタ、PINスイッチおよびダイオードミキサ等のディスクリートな能動素子ならびにキャパシタおよび抵抗器等の別の受動素子は、フリップチップ技術を使用して単面あるいは両面の低コストの基板に付け加えられることができる。 Transistors, varactor, another passive element of the active element and the capacitor and resistor, etc. discrete, such as PIN switch and diode mixer, can be added using the flip chip technique to a single surface or both surfaces of a low-cost substrate . 図9に示されている実施形態において、一方の基板32はアンテナ34を支持し、他方の基板36はアンテナと関連したトランシーバ回路を支持している。 In the embodiment shown in Figure 9, one of the substrates 32 supporting the antenna 34, the other substrate 36 supports a transceiver circuit associated with the antenna. この回路は、基板上に直接形成されたインダクタ38、伝送ライン40 、およびコンタクトパッド42等の受動素子と、フリップチップ設置によって固定されたパワーHEMT(電子移動度トランジスタ)44、バラクタ46、低雑音HE MT48、HBT(ヘテロ接合バイポーラトランジスタ)50、PINダイオード52 等の能動素子と、フリップチップ設置によって取付けられたキャパシタ54および抵抗器57等の付加的な受動素子とを含んでいる。 This circuit includes an inductor 38 which is directly formed on the substrate, and passive elements such as a transmission line 40 and the contact pads 42, the power HEMT (electron mobility transistor) 44 that is fixed by flip chip installation, the varactors 46, low-noise HE MT48, a HBT (heterojunction bipolar transistor) 50, an active element such as a PIN diode 52, and an additional passive elements such as capacitors 54 and a resistor 57 mounted by flip-chip installation. 銅であることが好ましい接地平面56は、2つの基板を分離する。 Preferably a copper ground plane 56 separates the two substrates. 接地平面は銅で形成されることが好ましく、トランシーバ回路とその下部のアンテナとの間の通信が所望される位置において開口58のアレイ(図10参照)でパターン化され、接地平面においてこれらの開口を含む連続した誘電体通路を介してアンテナとその関連した回路との間で高い周波数の信号が送信される。 Ground plane is preferably formed of copper, at a position where communication is desired between the transceiver circuitry and its lower part of the antenna is patterned with an array of apertures 58 (see FIG. 10), the openings in the ground plane high frequency signal between the antenna and its associated circuitry are transmitted over a continuous dielectric path including. 図10において、上部基板36上の対応するパッドに設けられたフリップチップパッケージ60が1つだけ示されている。 10, a flip chip package 60 provided in the corresponding pads on the upper substrate 36 is shown only one. また、ビームリードパッケージ62が示されており、それはフリップチップに類似しているが、その下部の回路表面上でコンタクトバンプを使用するのではなく、その縁部の周囲で導電リング64を使用する。 Further, a beam lead package 62 is shown, although it is similar to the flip chip, rather than using the contact bumps on the circuit surface of the lower, using a conductive ring 64 around its edges . ビームリード装置は、フリップチップと類似した方法で設置され、本発明の目的のためにフリップチップと等しいと考えられることができる。 Beam lead devices are installed in a manner similar to flip-chip, it can be considered equal to the flip chip for the purposes of the present invention. 図11において、積層される前の2つのデュロイド基板32および36が示されている。 11, two Duroid substrate 32 and 36 before being stacked is shown. そのような基板は、通常両面に金属被覆層が設けられており、基板32および36上の上部および下部金属被覆層は、それぞれ32a,32b および36a,36b として示されている。 Such substrates typically have a metal coating layer is provided on both sides, upper and lower metallization layer on the substrate 32 and 36 are shown respectively 32a, 32b and 36a, as 36b. 2つの基板が一緒に積層される前に、金属層36b がエッチングされて取除かれる。 Before the two substrates are laminated together, the metal layer 36b is removed by etching. アンテナ34は金属被覆層32b からパターン化され、トランシーバ回路のための相互接続ネットワークは金属被覆層36a からパターン化され、内部金属被覆層32a は基板36の金属被覆されていない表面に融着されて接地平面56 を形成する。 Antenna 34 is patterned from metallization layer 32b, the interconnection network for the transceiver circuit is patterned from metallization layer 36a, an internal metallization layer 32a is fused to the surface which is not metallized substrate 36 forming a ground plane 56. 2つの基板を接合する前に、金属被覆層32a に接地平面の開口部58 が形成される。 Before joining the two substrates, the opening 58 of the ground plane metallization layer 32a is formed. 接合膜(典型的にPTFE接合膜である)が、融着処理中にこれらの開口を充填する。 Bonding film (typically a PTFE bonding film) is filled these openings during fusing process. 接地平面として機能するのに加えて、融着された金属被覆32a および36b は基板全体を補強し、それによって、図7および図8に示されているような補強基板がない場合よりも薄くすることができる。 In addition to functioning as a ground plane, fused metal coating 32a and 36b are to reinforce the entire substrate, thereby thinner than without the reinforcing substrate as shown in FIGS. 7 and 8 be able to. しかしながら、付加的な剛性が必要である場合、種々の電気素子のために補強基板に空洞部を残した状態で、補強基板を回路基板36上に加えることができる。 However, where necessary additional rigidity, while leaving a cavity in the reinforcing substrate for various electrical elements, may be added to the reinforcing substrate on the circuit board 36. 2つの基板32および36はまた、所望されるならば、異なる誘電定数を有して製造されることができる。 The two substrates 32 and 36, if desired, can be manufactured with different dielectric constants. 内蔵式アンテナのアプリケーションの場合、アンテナ基板32の誘電定数が低いと、アンテナから放射されたフィールドが基板内に制限されることを防ぎ、一方、回路基板36の誘電定数が高いと、その伝送ラインに要求される長さが減少される。 For the built-in antenna applications, the low dielectric constant of the antenna substrate 32, field radiated from the antenna is prevented from being limited in the substrate, whereas, when the high dielectric constant of the circuit board 36, the transmission line the required length is reduced to. 異なる誘電定数を有するデュロイドタイプの材料は容易に入手することができる。 Duroid type of materials with different dielectric constants can be easily obtained. 図12および図13において、図9に示された内蔵式アンテナ装置の特定の実施形態が示されており、図12においてはアンテナアレイ66が設けられた状態で示され、図13においては対向面に回路が設けられた状態で示されている。 12 and 13, there is shown a particular embodiment of the built-in antenna device shown in FIG. 9, 12 is shown with the antenna array 66 is provided, facing surface 13 circuit is shown in a state provided. この特定の場合において、基板は約7.5×10cmであり、アンテナ基板32および回路基板36はそれぞれ125マイクロメートルおよび250マイクロメートルの厚さを有し、これらの寸法の全ては、特定のアプリケーションに依存して変化することができる。 In this particular case, the substrate is about 7.5 × 10 cm, the antenna substrate 32 and the circuit board 36 has a thickness of each 125 micrometers and 250 micrometers, all of these dimensions, specific application it is possible to vary depending on. 各アンテナは、アンテナ入力端部68a と整列した接地平面56における開口(図示されていない)を通して反対側のトランシーバ回路と通信する。 Each antenna is in communication with the opposite side of the transceiver circuit through the opening (not shown) in the ground plane 56 aligned with the antenna input end 68a. 図13に示されている反対側のトランシーバ回路は、基板の反対側の異なるそれぞれのアンテナと接続される5個の端子70と、端子70と5:1のパワー結合器74との間の接続を切換えるPINダイオードスイッチ72とを含んでいる。 The opposite side of the transceiver circuit shown in FIG. 13, the five terminals 70 connected with the respective antenna of different opposite side of the substrate, the terminal 70 5: connection between the power combiner 74 1 and a PIN diode switch 72 for switching. パワー結合器74は増幅器76,78に接続され、増幅器76はミキサ80と82との間で信号を供給している。 The power combiner 74 is connected to an amplifier 76, the amplifier 76 supplies a signal to and from the mixer 80 and 82. 電圧制御発振器(VCO)84は、基準周波数信号を周波数逓倍器86 に供給し、その出力は増幅器78と共にミキサ80および82に接続されている。 Voltage controlled oscillator (VCO) 84 is the reference frequency signal is supplied to a frequency multiplier 86, the output of which is connected to a mixer 80 and 82 with amplifier 78. 増幅器76から出ている向かい合ったミキサ端子は、同位相(I)チャンネル88および直角位相(Q)チャンネル90である。 Mixer terminals facing emanating from the amplifier 76 is in phase (I) channel 88 and quadrature (Q) channel 90. このタイプのアンテナは、衝突防止レーダ等の自動車のアプリケーションに特に有効である。 This type of antenna is particularly useful in automotive applications such as anti-collision radar. 本発明は、従来の高い周波数の構造の不所望な寄生効果なしに、マイクロ波およびミリメートル波装置のための低コストで信頼度の高い回路構造を提供する。 The present invention, without undesirable parasitic effects of the structure of a conventional high frequency, to provide high circuit structure reliability at low cost for microwave and millimeter wave device. 本発明の特定の実施形態が図示および説明されてきたが、多数の変更および修正された実施形態が当業者によって行われる。 While particular embodiments of the present invention have been shown and described, the embodiment has been numerous changes and modifications will occur to those skilled in the art. そのような変更および修正された実施形態は、添付された請求の範囲に定められた本発明の意図および技術的範囲から逸脱せずに行われることができる。 Such changes and modified embodiments may be made without departing from the spirit and scope of the invention as defined in the appended claims.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 マクドナルド、 ペリー・エー アメリカ合衆国、カリフォルニア州 91320、ニューベリ・パーク、ロス・ビエ ントス 257 (72)発明者 レンシュ、 デイビッド・ビー アメリカ合衆国、カリフォルニア州 91320、サウザンド・オークス、キャピタ ン 811 (72)発明者 ラルソン、 ローレンス・エー アメリカ合衆国、カリフォルニア州 92014、デル・マー、メルカド・ドライブ 13771 ────────────────────────────────────────────────── ─── front page of the continuation (72) inventor McDonald, Perry er United States, California 91320, Newbury Park, Los Bie Santos 257 (72) inventor Renshu, David Bee United States, California 91320, Thousand Oaks, capital emissions 811 (72) inventor Larsson, Lawrence er United States, California 92014, del Mar, Mercado drive 13771

Claims (1)

  1. 【特許請求の範囲】 1. [Claims] 1. セラミックでなく、半導体でもない誘電性基板と、 前記基板上の電気的相互接続ネットワークと、 前記基板にフリップチップ設置され、前記相互接続ネットワークによって電気的に相互接続され、相互接続された回路素子間の間隔がマイクロ波/ミリメートル波の範囲の少なくとも一部の波長で電気信号と調和している複数のディスクリートな回路素子とを具備しているマイクロ波/ミリメートル波回路構造。 Not ceramic, a dielectric substrate nor the semiconductor, electrical interconnection network on said substrate, is flip-chip mounted on the substrate are electrically interconnected by said interconnection network, between interconnected circuit elements Microwave / millimeter wave circuit structure spacing is provided with a plurality of discrete circuit elements are in harmony with the electrical signal in at least part of the wavelength range of the microwave / millimeter wave. 2. 2. 前記ディスクリートな回路素子の少なくとも幾つかは、前記相互接続ネットワークと電気的に接触し、機械的に接着される多数のバンプを含み、隣接したバンプの間の間隔は150マイクロメートル程度である請求項1記載の回路構造。 At least some of said discrete circuit elements, the interconnection network and in electrical contact includes a number of bumps are mechanically bonded, claims spacing between adjacent bumps is approximately 150 micrometers circuit structure 1 according. 3. 3. 前記相互接続ネットワークは酸化された表面を有する酸化金属を具備し、さらに、前記酸化金属上のバンプ位置において非酸化導電性パッドのアレイを具備し、前記バンプは各パッドに接着されることを特徴とする請求項1または2記載の回路構造。 Comprising a metal oxide wherein the interconnection network having a surface oxidized, further characterized in that said at bump positions on the metal oxide comprises an array of non-oxidized conductive pads, the bump is bonded to the pads circuit structure of claim 1 or 2 wherein the. 4. 4. 前記誘電性基板は約600マイクロメートル以下の厚さを有しており、さらに、前記誘電性基板に接着された補強基板を具備している請求項1、2、3のいずれか1項記載の回路構造。 It said dielectric substrate has a thickness of less than or equal to about 600 micrometers, further, in any one of claims 1, 2 and 3 are provided with a reinforcing substrate bonded to the dielectric substrate circuit structure. 5. 5. 前記構造は、トランシーバ基板上にトランシーバ回路を具備し、さらに、一方の面にアンテナが形成され、トランシーバ基板と背中合わせに接着されたアンテナ基板を具備し、前記アンテナは前記基板を通して前記トランシーバ回路と接続されている請求項1、2、3、4のいずれか1項記載の回路構造。 The structure comprises a transceiver circuit on the transceiver substrate, further, is on one side the antenna is formed, comprises an antenna substrate adhered back to back and the transceiver substrate, wherein the antenna connected to the transceiver circuit through the substrate circuit structure of any one of claims 1, 2, 3, 4 being. 6. 6. マイクロ波/ミリメートル波回路構造の製造方法において、 電気的相互接続ネットワークと前記ネットワーク上の各位置における導電性コンタクトパッドのアレイを有するセラミックおよび半導体ではない誘電性基板を設け、パッドの寸法および前記パッド間の間隔はマイクロ波/ミリメートル波の範囲の少なくとも一部の信号波長と調和するものであり、 複数のディスクリートな回路素子を設け、その回路素子は前記基板上の各コンタクトパッド位置と対応する接触位置を有し、 前記回路素子の接触位置を前記基板上の各コンタクトパッドに機械的および電気的に接続するコンタクトバンプで前記回路素子を前記基板にフリップチップ設置し、それによって、前記回路素子の設置中に前記コンタクトパッドをそれらの各バンプと自己整列 The method of manufacturing a microwave / millimeter wave circuit structure, an electrical interconnection network and the dielectric substrate are not ceramic and semiconductor having an array of conductive contact pads at each position on the network is provided, the dimensions of the pad and the pad the spacing between are those consistent with at least a portion of the signal wavelength in the range of microwave / millimeter wave, a plurality of discrete circuit elements provided, contacts the circuit elements corresponding to each contact pad position on the substrate position has, the circuit elements a contact position of the circuit element in contact bumps that mechanically and electrically connected to the contact pads on the substrate by flip-chip mounted on the substrate, whereby the circuit elements wherein the contact pads self-aligning and each of them bumps during installation せることを含むマイクロ波/ミリメートル波回路構造の製造方法。 Method for producing a microwave / millimeter wave circuit structure comprising causing. 7. 7. 前記バンプは、前記基板上に前記回路素子を設置する前に前記回路素子上で予備溶融され、前記設置中に再溶融されるはんだバンプを含んでいる請求項6記載の製造方法。 The bump, the pre melted on the circuit elements prior to installing the circuit element, a manufacturing method of including a solder bump is melted again and claim 6 wherein in said installed on the substrate. 8. 8. 前記相互接続ネットワークは酸化可能な材料から形成され、前記パッドは非酸化材料から形成され、さらに、前記回路素子を前記基板に設置するに先立って前記相互接続ネットワークの表面を酸化するステップを含んでいる請求項6または7記載の製造方法。 Said interconnection network is formed from an oxidizable material, the pad is formed of a non-oxide material, further comprises the step of oxidizing the surface of said interconnection network prior to installing the circuit element to said substrate claim 6 or 7 the method according located. 9. 9. 前記コンタクトバンプははんだバンプとして前記回路素子上に設けられ、前記回路素子は前記バンプを前記パッド上に流動させることによって前記基板上に取付けられ、前記相互接続ネットワークの酸化表面によって前記はんだバンプが前記表面上に流れることが阻止され、それによって前記バンプおよびそれらの関連した回路を前記パッド上で自己整列させる請求項8記載の製造方法。 The contact bumps provided on the circuit element as a solder bump, the circuit element is mounted on said substrate by flowing said bumps onto said pads, the solder bump is the by oxidation surface of said interconnection network is prevented from flowing on the surface, whereby the bumps and a manufacturing method of claim 8, wherein the self-aligning their associated circuitry on the pad.
JP50586297A 1995-07-07 1996-07-01 Microwave / millimeter wave circuit structure and a manufacturing method thereof having a flip-chip installed the discrete elements Pending JPH10505466A (en)

Priority Applications (3)

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US499,800 1995-07-07
US08/499,800 US5629241A (en) 1995-07-07 1995-07-07 Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same
PCT/US1996/011144 WO1997002733A2 (en) 1995-07-07 1996-07-01 Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same

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EP0782766A3 (en) 1997-11-19
CA2198088A1 (en) 1997-01-30
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US5629241A (en) 1997-05-13
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DE69637906D1 (en) 2009-06-04
US5757074A (en) 1998-05-26
WO1997002733A3 (en) 1997-08-21
CA2198088C (en) 2001-05-15
EP0782766A2 (en) 1997-07-09
WO1997002733A2 (en) 1997-01-30

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