JP2004006985A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plan by which the number of manufacturing processes of an MTCMOS structure constituted of a completely depleted transistor having a back gate electrode can be reduced sufficiently. <P>SOLUTION: In a method of manufacturing a MISFET (metal insulator semiconductor field-effect transistor) constituted of a completely depleted transistor formed in a semiconductor layer provided on a support substrate through an insulating film, particularly, a method of manufacturing a completely depleted MISFET provided with a back gate in a support substrate, the number of masks used is reduced by forming channels and the back gate by using a common mask and the number of processes is reduced by performing ion implantation of p and n dopants in an overlapping way. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a method of manufacturing a fully depleted MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a semiconductor layer provided on a supporting substrate via an insulating film, and more particularly to a fully depleted MISFET having a back gate provided on the supporting substrate. MISFET manufacturing method.

Field-effect transistors (FETs) formed using SOI (Silicon on Insulator), a semiconductor layer formed on an insulating film (hereinafter referred to as SOI silicon layer), are low power consumption devices such as LSIs for portable information terminals, and high-speed CPUs. It is expected to be applied to high-speed operation circuits. In particular, a transistor in which the SOI silicon layer in the channel region is completely depleted (hereinafter referred to as a fully depleted transistor) has an advantage that a problem relating to a substrate floating effect in a partially depleted transistor is reduced.

Conventionally, as a circuit technology, a high-threshold transistor is inserted into a power supply line of a low-threshold logic circuit block as a switch, so that high-speed operation by the low-threshold circuit and switching of the high-threshold transistor are achieved. There has been proposed a technology that realizes a reduction in power consumption by reducing the threshold voltage, increases a sub-threshold leakage current at the time of OFF due to a decrease in threshold, and suppresses an increase in power consumption due to the increase. Hereinafter, the threshold refers to the threshold of the gate voltage. This MTCMOS (Multi-Threshold-Voltage CMOS) technology is expected to realize low-voltage and high-speed circuit operation when combined with SOI devices.

However, when the MTCMOS structure is formed by using a fully-depleted transistor having a back gate, there is a problem that the number of manufacturing steps increases.

As a manufacturing method for reducing the number of processes, for example, as disclosed in Patent Document 1, by performing ion implantation repeatedly with three photoresist patterns for channel implantation, four different threshold n-type Examples of forming a MOSFET are known.

However, this conventional example is a manufacturing method considering only one MOSFET, and the number of steps in the CMOS process has not been sufficiently reduced.

As described above, no sufficient measure for reducing the number of processes has been taken with respect to the increase in the number of manufacturing processes of the MTCMOS structure including the fully-depleted transistors having the back gate electrode.
JP 9-27553 A

An object of the present invention is to provide a manufacturing method for forming an MTCMOS structure with a small number of manufacturing steps.

The present invention provides a step of forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer which are insulated and separated from each other on a buried insulating film on a semiconductor substrate of a first conductivity type; By implanting a second conductivity type impurity twice using a mask, a first back gate electrode is formed in the semiconductor substrate under the first semiconductor layer, and a second back gate electrode is formed in the semiconductor substrate under the second semiconductor layer. Forming a first impurity region for the back gate electrode under the third and fourth semiconductor layers, and using the first to fourth semiconductor layers as first to fourth impurity layers of a second conductivity type; Ion implantation of impurities of the second conductivity type using the second mask to increase the impurity concentration of the second conductivity type of the first and fourth impurity layers to the second conductivity type of the second and third impurity layers. A step of making the impurity concentration higher than that of By implanting the first conductivity type impurity twice, a third back gate electrode is provided in the first impurity region below the third semiconductor layer and a fourth back gate electrode is provided below the fourth semiconductor layer. Forming a gate electrode, setting the third and fourth impurity layers to a first conductivity type, and making the impurity concentration of the third impurity layer higher than that of the fourth impurity layer; A semiconductor device manufacturing method including a step of forming a semiconductor device in each of the fourth to fourth impurity layers.

The second invention of the present application is the method of manufacturing a semiconductor device according to the first invention of the present application, wherein the semiconductor device has a channel region, a gate insulating film, and a gate electrode.

The third invention of the present application is the method for manufacturing a semiconductor device according to the first invention of the present application, wherein the first to fourth semiconductor layers have the same thickness.

According to the present invention, an MTCMOS structure including a fully-depleted transistor having a back gate can be manufactured with a small number of steps.

According to the present invention, it is possible to provide a method for manufacturing an MTCMOS structure with a small number of manufacturing steps in a fully depleted transistor having a back gate electrode.

Hereinafter, embodiments will be described with reference to the drawings.

(1st Embodiment)
The device parameter setting method of the present embodiment is an effective method for minimizing threshold variation in the MTCOS structure.
FIG. 1 is a schematic sectional view of the semiconductor device according to the first embodiment. 1 is a support substrate, 2 is a buried insulating film, 3 is an interlayer insulating film, 4 is an element isolation region, 5 and 5 'are gate side wall insulating films, 6 and 6' are gate insulating films, and 7 and 7 'are source / drain. Regions 8, 8 'are gate electrodes, 9, 10 are contact electrodes to the back gate electrode, 11 and 12 are channel regions of the same conductivity type, and 13 and 14 are back gate electrodes. The contacts to the gate, source, and drain are omitted. The features of the semiconductor device according to the present embodiment are that the thickness and the conductivity type of the SOI silicon layer (channel region) are the same, and in the case of two fully-depleted transistors having different thresholds, the channel concentration is low and the back gate is low. A transistor with a higher voltage has a lower threshold voltage, and a transistor with a higher channel concentration and a lower back gate voltage has a higher threshold voltage.

Next, a device parameter setting method according to the present embodiment will be described.

FIG. 2 shows an impurity in a channel region in which the variation in the threshold value becomes minimum with respect to a set gate voltage threshold value (hereinafter simply referred to as a threshold value) in a fully depleted transistor obtained by a device parameter setting method described later. 4 is a graph showing a relationship between a concentration (hereinafter, referred to as a channel concentration) and a back gate voltage. Here, a single-crystal silicon layer having a thickness of 20 nm as the channel regions 11 and 12 which are SOI silicon layers, a silicon oxide film having a thickness of 30 nm as the buried insulating film 2, and a silicon film having a thickness of 3 nm as the gate insulating film 6. An oxide film, 1 × 10 ²⁰ cm ⁻³ n-type polysilicon (polycrystalline silicon) as a gate electrode, and the support substrate 1 is made of n-type silicon to electrically separate the back gate electrodes 13 and 14. The gate electrodes 13 and 14 were modeled on n-type MOSFETs made of p-type silicon.

(2) As is clear from the graph of FIG. 2, the combination of the channel concentration and the back gate voltage that minimizes the variation in the threshold value with respect to the set threshold value is determined as one set. Thus, when forming the MTCMOS structure, which is the object of the present invention, it is necessary to set the channel concentration and the back gate voltage according to each set threshold value.

For example, when the threshold value of the FET1 in FIG. 1 is set to 0.1 V and the threshold value of the FET2 is set to 0.4 V in this calculation, in this calculation, the channel concentration and the back gate voltage of the FET1 are 1.2 × 10 ¹⁷ cm ⁻³ , −0.8V, and 2.4 × 10 ¹⁷ cm ⁻³ , −3V for FET2.

That is, as shown in Figure 2, to the threshold to be set, the threshold variation is minimized, the impurity concentration N _A and the back gate voltage V _G2 of the same conductivity type as the channel regions 11 and 12 is determined. At this time, the thickness of the SOI silicon layer is the same, and the thresholds are different. For example, when setting device parameters of two fully depleted transistors, the lower the channel concentration and the higher the back gate voltage, the lower the threshold. In contrast, a transistor having a higher channel concentration and a lower back gate voltage is a transistor having a higher threshold value.

Hereinafter, a device parameter setting method will be described. In calculating the relationship shown in the graph of FIG. 2, a formula ("Electrical characterization of Silicon-on-Insulator Materials and Devices", by Sorin Cristloveanu and Sheng S. Li) expressing the threshold value of a fully depleted transistor is used. , Kluwer Academic Publishers, (1995)). Furthermore, in order to consider the quantum effect in the calculation of the threshold value, reference (MJ van Dort et al., IEDM91 p495, (1991)), (JW Slotboom et al., IEEE trans. Electron
Devices, vol.ED024, No.8, pp.1123-1125, (1977)), ("Quantum Mechanics for Device Physics" by David K. Ferry, translated by Yosuke Nagaoka et al., Maruzen, (1996)) I referred to what is being done.

Figure 3 is a graph showing the relationship between the silicon film thickness t _Si and the threshold value V _t of the SOI layer of the fully depleted transistor. Here, in the model used in the calculation of FIG. 2, the impurity concentration of the channel region is 1 × 10 ¹⁷ cm ⁻³ , and the back gate voltage V _G2 is −1 V.

The threshold value of the fully depleted transistor can be controlled by the back gate voltage, and the threshold value is determined by the surfaces of the channel regions 11 and 12 that are in contact with the buried insulating film 2 (hereinafter referred to as back surfaces). Is determined by the electronic state at. That is, the threshold value can be changed from the accumulation state to the inversion state by the back gate voltage, and the threshold value is substantially constant in the accumulation state and the inversion state.

In FIG. 3, the threshold value when the back surface is in the accumulation state is represented by Vt, acc, and the threshold value when the back surface is in the inversion state is represented by Vt, inv. (In the hatched area in the figure).

As shown in FIG. 3, when the thickness of the buried insulating film is t _box = 100 nm, the threshold value decreases almost linearly with decreasing the thickness of the SOI silicon film. However, when the buried insulating film thickness t _box = 30 nm, the threshold value has a minimum value with respect to the SOI silicon film thickness as indicated by the arrow. At this time, the threshold sensitivity to the fluctuation of the SOI silicon film thickness is minimized, and the variation in the threshold value to the SOI silicon film thickness is minimized.

This is because the potential of the back surface is restricted to the potential of the back gate by capacitive coupling due to the thin buried insulating film. Since the potential difference between the surface and the back surface is almost constant at all times, the surface electric field Es at the time of the threshold increases as the SOI becomes thinner. Therefore, since the threshold value is highly dependent on the surface electric field, the effect that the threshold value has a minimum point and increases with the SOI thinning appears.

FIG. 2 is a graph in which the conditions of the channel concentration and the back gate voltage at which the threshold variation is minimized are extracted with the SOI silicon film thickness and the buried insulating film thickness set in advance. In the description of the present embodiment, as shown in FIG. 2, the SOI silicon film thickness is set to 20 nm and the buried insulating film thickness is set to 30 nm. Other film thickness conditions can be set as long as the value has a minimum value with respect to the SOI film thickness.

Next, the threshold value calculation formula used in the present embodiment will be described.

Relationship between the gate voltage V _G1 and the surface potential of the fully depleted transistor can be expressed by the following equation.

　ここで、Φ_S1、Φ_S2はそれぞれチャネル領域11および12のゲート絶縁膜6に接した表面、埋め込み絶縁膜3に接した表面におけるフェルミポテンシャルである。Φ_MS1はゲート絶縁膜6側のゲート電極8との仕事関数差、Q_OX1はゲート絶縁膜6中の固定電荷密度、C_OX1はゲート絶縁膜6のキャパシタンス、Q_inv1はチャネル領域11、12におけるチャネルの反転層電荷である。そして、Q_deplはチャネル領域４での空乏層電荷を表し、電子の電荷量ｑ、チャネル領域11、12の不純物密度N_A、チャネル領域11、12の膜厚t_siを用いて−qN_At_siで表される。また、フェルミポテンシャルΦ_Fはシリコンの真性キャリア密度n_i、ボルツマン定数k、温度T、電子の電荷量（単位素電荷）qを用いて、

Here, Φ _S1 and Φ _S2 are Fermi potentials on the surfaces of the channel regions 11 and 12 in contact with the gate insulating film 6 and on the surface in contact with the buried insulating film 3, respectively. Φ _MS1 is the work function difference between the gate insulating film 6 and the gate electrode 8, Q _OX1 is the fixed charge density in the gate insulating film 6, C _OX1 is the capacitance of the gate insulating film 6, and Q _inv1 is the channel region 11, 12. This is the inversion layer charge of the channel. Then, Q _depl represents the depletion charge in the channel region 4, -qn _A t using electron charge amount q, the impurity concentration N _A of the channel regions 11 and 12, the thickness t _si of the channel regions 11 and 12 It is represented by _si . The Fermi potential Φ _F is calculated using the intrinsic carrier density n _i of silicon, the Boltzmann constant k, the temperature T, and the electron charge (unit elementary charge) q.

で表される。またキャパシタンスは、例えばチャネル領域11、12の場合、シリコンの誘電率ε_Si、膜厚t_Siを用いて、Ｃ_Si＝ε_Si／ｔ_Siで表される。

Is represented by In the case of the channel regions 11 and 12, for example, the capacitance is represented by C _Si = ε _Si / t _Si using the dielectric constant ε _{Si of silicon} and the thickness t _Si .

In the present invention, the case where the back surface which can be threshold-controlled by the back gate voltage is in a depleted state is used. The threshold value at this time is expressed by the following equation from equation (1).

　ここで、Vtはしきい値。V_FB1、V_FB2はゲート絶縁膜6側、埋め込み絶縁膜2側のフラットバンド電圧。C_ox2は埋め込み絶縁膜２のキャパシタンス。V_G2はバックゲート電圧を表し、back surfaceが蓄積状態から反転状態までの範囲の条件で有効である。

Here, Vt is the threshold. V _FB1 and V _FB2 are flat band voltages on the gate insulating film 6 side and the buried insulating film 2 side. _Cox2 is the capacitance of the buried insulating film 2. V _G2 represents the back gate voltage, and is effective under the condition that the back surface ranges from the accumulation state to the inversion state.

Next, the derivation of FIG. 2 will be described.

よ り From equation (3), the threshold sensitivity to the SOI film thickness is expressed by the following equation.

　式(4)でしきい値感度が最低となるのは０となるときである。そこで、式(3)および式(4)であらかじめSOIシリコン膜厚および埋め込み絶縁膜厚、ならびにチャネル濃度とバックゲート電圧以外のパラメータを設定する。そして式(3)に所望のしきい値V_tを設定する。以上の式(3)、式(4)より、所望のしきい値でしきい値感度を最小にするチャネル濃度Ｎ_Aとバックゲート電圧Ｖ_G2を求めることができる。

In equation (4), the threshold sensitivity becomes minimum when it becomes zero. Therefore, parameters other than the SOI silicon film thickness and the buried insulating film thickness, and the channel concentration and the back gate voltage are set in advance by the equations (3) and (4). And set the desired threshold V _t in equation (3). Or of formula (3), the equation (4), it is possible to obtain the channel concentration N _A and the back gate voltage V _G2 to minimize threshold sensitivity desired threshold.

In the present embodiment, in order to obtain the channel concentration and the back gate voltage shown in FIG. 2, the equation (3) is directly used as the threshold equation for simplifying the operation. Therefore, at the time of parameter derivation, calculation taking into account the quantum effect is not performed. In order to perform more accurate calculations, numerical calculations including quantum effects are required.

で は In the above model calculation, the calculation was performed when n-type polysilicon was used for the n-type MISFET as the gate electrode. When a metal such as tungsten (W), aluminum (Al), or titanium nitride (TiN) is used for the gate electrode, the threshold value becomes higher than that of the polysilicon gate. Therefore, it is necessary to apply a substrate bias positively to lower the threshold value. However, in CMOS, a forward bias is applied to the back gate formed by the n-type silicon layer of the p-type MISFET, and a current flows between the back gate electrodes. . When the substrate bias is positively applied as described above, the back gate of the n-type MISFET is formed of an n-type silicon layer, and the back gate of the p-type MISFET is formed of a p-type silicon layer, thereby preventing conduction between the back gate electrodes. be able to.

Next, a method of considering the surface quantum effect in the threshold value calculation will be described. In this calculation, the following equation was used as the increase amount of the surface band bending due to the surface quantization correction of the surface potential.

　つまり式(5)は、伝導体E_cから最低エネルギー準位E₀へのシフトE₀-E_c、高濃度のチャネル不純物添加によるバンドギャップの縮小（bandgap narrowing）効果DE_g、そして量子論による表面電荷密度が最大となる位置のシフトDzによる表面電位の変化E_sDzから構成されている。

That equation (5) is shifted E ₀ -E _c to the lowest energy level E ₀ from conductor E _c, high density reduction of the band gap by the channel doping of the (bandgap narrowing) effect DE _g and by quantum theory, It consists of the change E _s Dz of the surface potential due to the shift Dz of the position where the surface charge density becomes maximum.

Next, equation (5) will be described. The shift amount E ₀ −E _c to the lowest energy level E ₀ is

　ここで、ｈはプランク定数、ｍはキャリアの有効質量を表す。また、E_sは表面電界を示し、次式で表される。

Here, h represents Planck's constant, and m represents the effective mass of the carrier. Also, E _s denotes the surface electric field is expressed by the following equation.

　また、bandgap narrowing効果DE_gは、次式で表される。

The bandgap narrowing effect DE _g is represented by the following equation.

　E_sDzの近似式は、次式で表される。

The approximate expression of E _s Dz is represented by the following expression.

　以上、式(1)〜(9)を考慮して得られたしきい値のSOI膜厚依存性が図３である。

FIG. 3 shows the SOI film thickness dependence of the threshold value obtained in consideration of the equations (1) to (9).

実 験 From the results of experiments performed by the present inventors, it has been found that there is an offset in the actually measured threshold value as compared with the theoretical calculation in this case. This is probably because fixed charges exist on the SOI silicon side of the buried insulating film, or an increase in the effective thickness of the buried insulating film due to, for example, depletion of the back gate electrode. In designing device parameters, it is possible to minimize the variation in threshold value by considering these offsets. For example, fixed charge density, buried insulation It is preferable to grasp the effective film thickness of the film and design a device parameter that minimizes the threshold variation.

As described above, the device parameter setting method according to the present embodiment is an effective method for minimizing threshold value variation.
(Second embodiment)
The second embodiment shows the relationship among the back gate voltage, the back gate insulating film thickness, and the channel concentration that minimizes the threshold variation, and shows that these three conditions are not related to the thickness of the SOI silicon layer. . We also show that the theoretical calculation is consistent with the actual device.

The threshold of a fully depleted transistor is described in the literature (HK. Lim and JG Fossum, "Threshold Voltage of Thin-Film Silicon-on-Insulator (SOI) MOSFET's," IEEE Trans. Electron Devices, vol. 30, pp. 1244 -1251, 1983.), and is represented by equation (10).

　ここで、Φ_Fはチャネル領域のフェルミポテンシャル、V_FB1及びV_FB2はゲート電極及びバックゲート電極のフラットバンド電圧、C_ox1、C_ox2及びC_Siはゲート絶縁膜、埋め込み絶縁膜及び空乏化したSOIシリコン層の各容量、N_it1及びN_it2はゲート絶縁膜側及び埋め込み絶縁膜側のSOIシリコン層の界面におけるバンドギャップ中の界面準位密度を表す。また、ゲート絶縁膜側及び埋め込み絶縁膜側のSOIシリコン層界面中の固定電荷密度についてはフラットバンド電圧に含めて考慮する。そして、以下に述べるバックゲート電圧V_G2は埋込み絶縁膜側のSOIシリコン層（裏面）が空乏状態でバックゲート電圧によりしきい値制御可能である範囲にあることとする。

Here, Φ _F is the Fermi potential of the channel region, V _FB1 and V _FB2 are the flat band voltages of the gate electrode and the back gate electrode, and C _ox1 , C _ox2 and C _Si are the gate insulating film, the buried insulating film, and the depleted SOI. The respective capacitances of the silicon layer, N _it1 and N _it2 , represent the interface state density in the band gap at the interface between the SOI silicon layer on the gate insulating film side and the buried insulating film side. Further, the fixed charge density at the interface between the SOI silicon layer on the gate insulating film side and the buried insulating film side is taken into account in the flat band voltage. The back gate voltage _VG2 described below is in a range where the threshold can be controlled by the back gate voltage when the SOI silicon layer (back surface) on the buried insulating film side is depleted.

Hereinafter, using the equation (10), the design region in which the threshold variation due to the variation in the thickness of the SOI silicon layer is minimized, that is, in the relationship between the threshold and the thickness of the SOI silicon layer, the threshold is determined to be minimum. The following conditions are shown.

Condition threshold can be a minimum is obtained by differentiating equation (10) with a thickness t _Si of the SOI silicon layer, represented by the formula (11).

(Equation 11)
C _ox2 (C _ox2 + _{qN it2} ) (2Φ _F + V _FB2 + _{qN it2} / C _ox2 −V _G2 )> _{qN A} ε _Si (11)
Here, N _A is the channel impurity density, epsilon _Si represents the dielectric constant of the SOI silicon layer.

FIG. 4 shows the thickness dependence of the threshold value of the SOI-MOSFET depending on the thickness of the SOI silicon layer, based on the measurement results and the theory including the expression (10) and the surface quantum effect described in the first embodiment. The result of theoretical calculation by calculation is shown.

The transistor used for the measurement had a gate oxide film thickness of 108 nm, a back gate oxide film (buried oxide film) of 5.6 nm, and a channel concentration of 1.2 × 10 ¹⁷ cm ^-3 regardless of the SOI film thickness. In the n-type MOSFET, the gate electrode is a p-type silicon layer to which Boron is added at 1 × 10 ¹⁷ cm ⁻³ , and the back gate electrode is n-type Poly silicon. The interface state density at the interface of the SOI silicon layer between the gate oxide film and the buried oxide film is 1 × 10 ¹¹ cm ⁻² eV ⁻¹ . The points in FIG. 4 show the actual measurement results.

On the other hand, the line in FIG. 4 shows the result of theoretical calculation. The conditions for matching with the measured results were as follows: the gate insulating film thickness was 119 nm, the negative fixed charge in the buried insulating film was 4 × 10 ¹¹ cm ^-2 , except for the buried insulating film thickness of 5.6 nm and the channel impurity density. Is 2 × 10 ¹⁷ cm ⁻³ and the impurity density of the p-type gate electrode is 1 × 10 ¹⁷ cm ⁻³ , which is within the error range of the measured value. This indicates that the theoretical calculation of Expression (10) is in good agreement with the measured value.

In FIG. 4, the back gate voltage at which the variation in the threshold value is minimum is at -0.4 and -0.8 V. At 0 V, the threshold value decreases monotonously as the thickness of the SOI silicon layer becomes thinner. ing. Then, in FIG. 4, each value of the device parameter when the threshold value becomes minimum satisfies the conditional expression of Expression (11).

Hereinafter, an example of the range of the device parameter obtained from Expression (11) will be described. FIG. 5 shows a region of the back gate voltage where the variation in the threshold value with respect to the thickness of the back gate oxide film (buried oxide film) can be minimized. FIG. 5 shows the case where the channel concentration is 1 × 10 ¹⁷ cm ⁻³ . It is possible to minimize threshold variation within a voltage range (in the direction of the arrow) smaller than the back gate voltage shown by the line in FIG.

{Circle over (2)} FIG. 6 shows a region of the back gate voltage that can minimize the variation in the threshold with respect to the channel concentration. In FIG. 6, the back gate insulating film thickness was 10 nm (solid line) and 30 nm (dotted line), and the concentration of the back gate electrode was the same as the channel concentration. It is possible to minimize the threshold variation within a range of the back gate voltage smaller than the back gate voltage of each line in FIG.

FIGS. 5 and 6 do not consider the interface state and the fixed charge. Therefore, in an actual device, the back gate voltage application range may change due to these effects. If the back gate voltage is within the range as shown in FIG. 5 or FIG. 6, it is possible to control the threshold fluctuation with respect to the thickness of the SOI silicon layer to a minimum.

As described above, if the device parameters of the fully-depleted transistor satisfy Expression (11), the variation in threshold voltage with respect to the thickness of the SOI silicon layer can be minimized.
(Third embodiment)
The third embodiment aims at simplifying the manufacturing process in realizing the MTCMOS device structure including the fully-depleted transistor having the back gate shown in the first embodiment.

FIGS. 7 to 13 are schematic cross-sectional views of main steps according to the first embodiment of the present invention. As shown in FIG. 7, a p-type silicon substrate as the support substrate 1, a silicon oxide film with a thickness of about 30 nm as the buried insulating film 2, and p-type silicon films with SOI layers 11, 12, 15, and 16 of about 20 nm, for example, An SOI substrate made of a silicon layer is used. An element isolation region 4 is formed on the SOI substrate to form a transistor region. Since the method of manufacturing the SOI substrate and the method of forming the element isolation region are not essential in the present invention, they are not particularly described here.

Next, ion implantation for the back gate electrode and ion implantation for the channel are performed using the first photoresist mask 17 as shown in FIG. In the first photoresist mask 17, the back gate electrodes 18 and 19 of the p-type MOSFET, the region 20 for electrical isolation between the substrate and the back gate of the n-type MOSFET, and the pattern for channel ion implantation are formed. I do.

After the formation of the photoresist mask 17, ion implantation is performed with an n-type dopant such as phosphorus at an acceleration voltage of about 70 KeV so that the peak impurity concentration in the substrate 1 is about 1 × 10 ¹⁷ to 10 ²⁰ cm ^−3. Back gate electrode regions 18 and 19 and an electrode separation region 20 are formed on a support substrate 1 made of silicon.

Next, as shown in FIG. 9, the same photoresist mask 17 is used to add an n-type dopant such as phosphorus to the SOI silicon layers 11, 12, 15, and 16 at an acceleration voltage of about 20 KeV and an impurity concentration of about 1 × 10 ¹⁷ cm ^−3. The ion implantation is performed so that

(4) The above-described ion implantation of the n-type back gate electrodes 18 and 19 and the n-type channel is performed using the same photoresist mask 17, thereby simplifying the manufacturing process. The back gate electrode may be formed by first performing ion implantation of the channel, which is the reverse of the order of the above-described ion implantation process.

Subsequently, as shown in FIG. 10, an n-type dopant such as phosphorus is ion-implanted into the SOI silicon layers 12 and 15 serving as channel regions using the second photoresist mask 21 at an acceleration voltage of about 20 KeV. The impurity concentration is adjusted to be about 2.5 × 10 ¹⁷ cm ⁻³ together with the implantation. In FIG. 10, (n +) is used to indicate that the n-type impurity density of the SOI silicon layers 12 and 15 is increased.

Next, as shown in FIG. 11, ion implantation of the back gate electrodes 23 and 24 of the n-type MOSFET and the channel is performed using the third photoresist mask 22.

In other words, ions of a p-type dopant such as boron are implanted into the substrate 1 at an acceleration voltage of about 20 KeV so that the peak impurity concentration of boron becomes about 2 × 10 ¹⁷ cm ⁻³ to about 2 × 10 ²⁰ cm ⁻³ . At this time, p-type back gate electrode regions 23 and 24 are formed in the n-type electrode separation region 20.

Then, as shown in FIG. 12, a p-type dopant such as boron is applied to the SOI silicon layers 11 and 12 serving as channel regions at an acceleration voltage of about 10 KeV and an impurity density of boron is 3.5 with the same third photoresist mask 22. Ion implantation is performed so as to be about × 10 ¹⁷ cm ⁻³ .

So far, the SOI silicon layers 11 and 12 contain n-type impurities of about 1 × 10 ¹⁷ cm ⁻³ and 2.5 × 10 ¹⁷ cm ⁻³ , respectively. The region is formed, and the channel concentration of the SOI silicon layers 11 and 12 becomes 2.5 × 10 ¹⁷ cm ^-3 and 1 × 10 ¹⁷ cm ^-3 , and the SOI silicon region having a different channel concentration by one ion implantation of the p-type dopant. Has been realized.

Then, as shown in FIG. 13, a gate electrode 8 and a source / drain region 7 are formed, and a p-type MOSFET having a higher threshold, a p-type MOSFET having a lower threshold, a threshold To form an MTCMOS structure including an n-type MOSFET having a high threshold voltage and an n-type MOSFET having a low threshold value. In this structure, it is desirable that the contact to the back gate electrode be made from the SOI side through an element isolation and buried insulating film.

Similar to the above first photoresist mask, ion implantation of the back gate and channel of the n-type MOSFET is performed using the same third photoresist mask. This reduces the number of masks and the number of steps. Note that the order of the ion implantation step may be reversed, and the back gate electrode may be formed by first performing ion implantation of the channel.

で は In the present embodiment, two n-type and p-type MOSFET fully depleted transistors having different threshold values have been described, but the present invention is not limited to this. Further, the arrangement of the structure is not limited to that shown in the drawing. Although the manufacturing steps other than the main steps are not particularly described, for example, a silicon oxide film may be formed on the surface as a protective film, and a photoresist may be formed and ion implantation may be performed thereon.

As described in the first embodiment, the back gate voltage of the n-type MISFET may be positively applied in order to lower the threshold value, for example, when a metal gate is formed. As described above, in the CMOS structure, when the back gate voltage is forward-biased between the back gate electrodes, it is necessary to change the structure of the back gate electrode in order to prevent conduction between the back gates. That is, for example, in the structure of FIG. 13, when a positive voltage is applied to the back gate of the n-type MISFET and a negative voltage is applied to the back gate of the p-type MISFET, the thyristor structure causes a forward conduction state. Therefore, as shown in FIG. 14, the back gate of the n-type MISFET is made of n-type silicon (21 ', 24'), and the back gate of the p-type MISFET is made of p-type silicon (18 ', 19'). The back gate voltage for setting the threshold value varies with this, but can be easily estimated by calculation.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to the above embodiments.

For example, as a method for forming the insulating film, a method for forming an oxide film by thermal oxidation, a method for forming an oxide film by injecting oxygen with low acceleration energy of about 30 keV, a method for depositing a silicon oxide film, A method of depositing a silicon nitride film, a method of combining these methods, or a method of thermally nitriding a silicon oxide film or forming a nitrided oxide film for oxidizing a silicon nitride film may be used. In addition, other methods for converting silicon into a silicon oxide film or a silicon nitride film, such as a method of implanting oxygen ions into deposited silicon or a method of oxidizing deposited silicon, may be used.

In addition, a silicon nitride film, a tantalum oxide film, a titanium oxide film, a ferroelectric film such as strontium titanate, barium titanate, and lead zirconium titanate, a monolayer film of a paraelectric film, or a composite thereof is formed on these insulating films. It is also possible to use a membrane.

Although not specifically mentioned in the above-described embodiment, the element isolation includes trench isolation, STI (shallow trench isolation), LOCOS element isolation film, recessed (Recessed) LOCOS, improved LOCOS method, Alternatively, for example, a mesa-type isolation or a field shield isolation excluding the SOI in a region to be an element isolation may be used, or these may be combined.

Further, in the above-described specific example, p-type Si is used for the SOI layer, but n-type Si, GaAs, or InP may be used instead.

Further, where only the n-type MISFET is described in the specific example, a p-type MISFET may be applied. In this case, the n-type in the above embodiment is replaced with the p-type and the p-type is replaced with the n-type. As for the species, As, P, Sb, etc. may be read as any of In, B, etc., and for ion implantation, As, P, Sb may be read as any of In, B, BF2.

Further, the gate electrode is made of polycrystalline silicon, single crystal silicon, porous (porous) silicon, amorphous silicon, SiGe mixed crystal, SiC mixed crystal, GaAs, W, Ta, Ti, Hf, Co, Pt, Pd, TiN. Metal or silicide can be used. Further, these may have a laminated structure.

Further, in the above-described embodiment, only the structure in which the semiconductor layer is flat is mentioned. However, the thickness of the source / drain region may be larger than that of the channel region. For example, a recessed channel (Recessed channel) structure may be used. The silicon layer in the channel region may be thinned by etching or sacrificial oxidation, or a silicon layer may be formed in the source / drain, such as an elevated source / drain structure. May be deposited to make the film thicker than the channel region.

Further, in addition to the above-described structure, a partially depleted transistor formed of, for example, a thick silicon layer may be formed on the same substrate, or by reducing the channel concentration in the same silicon layer as the above-described structure. The resulting partially depleted transistor may be formed. Alternatively, the structure may be such that the MISFET is formed on the same substrate on which the above-described structure is formed, but at a place where the buried insulating film is partially removed and bulk silicon is formed.

In this embodiment, two different threshold values are set in the MTCMOS structure in the present embodiment. However, the present invention is not limited to the two threshold values, and other threshold values may be set. .

In addition, various modifications can be made without departing from the spirit of the present invention.

The above embodiment has the effects described below.

First, according to the above-described embodiment, it is possible to set a desired threshold value while keeping the threshold value fluctuation due to the fluctuation of the SOI silicon film thickness, which is a problem in the fully depleted transistor, almost at a minimum.

回路 Further, it is possible to configure a circuit on which the threshold variation is almost minimized with desired different thresholds, on an SOI substrate having the same SOI silicon film thickness. Therefore, it is possible to form an MTCMOS structure with less variation in threshold value for SOI film thickness fluctuation and more uniform characteristics than before.

As described above, in the MTCMOS structure having a small threshold variation, in the high threshold transistor used as a power switch, the threshold variation is suppressed, and the sub-threshold which occurs when the threshold voltage varies to the low threshold side is reduced. An increase in power consumption due to an increase in leakage current can be kept small. In addition, low-threshold transistors used in logic circuit blocks reduce variations in delay time in logic circuits, such as suppressing an increase in delay time due to a decrease in current driving capability caused by an increase in threshold value. Since it can be maintained, the present invention can realize a high-speed and stable circuit operation with small variation in power consumption.

Further, in the formation of MTCMOS formed of a fully depleted transistor having a back gate, the number of masks can be reduced by using a common mask for the channel and the back gate.

(4) In order to set a plurality of different thresholds, the technique of overlapping the implantation of impurity ions is used to facilitate adaptation to a channel and back gate common mask. As a result, the back gate electrodes of all the MISFETs of the same conductivity type can be formed with one mask, so that the occurrence of a short circuit of the back gate electrode due to misalignment or the like can be prevented.

{Circle around (4)} The n- or p-type impurity having a higher concentration is implanted into the channel region containing the p- or n-type impurity to change the attribute of the channel region. That is, by simultaneously implanting n-type or p-type impurities into channel regions containing p-type or n-type impurities having different concentrations in advance, it becomes possible to form n-type or p-type channel regions having different concentrations. . This is an effective manufacturing method for reducing the number of steps in forming the MTCMOS.

Also, due to the features of this manufacturing process, for example, when forming a pMISFET after forming an nMISFET first, the pMISFET channel region contains p-type impurities at substantially the same concentration as the p-type impurity in the nMISFET channel region. May be.

In addition, since the mask pattern is used for both the channel and the back gate, it is necessary to perform ion implantation for forming an impurity region for electrically isolating the back gate. Therefore, the impurity is also contained in the element isolation region. May be deposited at the separation / silicon interface.

As described above, according to the present embodiment, the number of masks is reduced by forming the channel and the back gate with the common mask, and the number of steps is reduced by repeatedly ion-implanting p and n dopants. As described above, the manufacturing method of the present embodiment has great industrial advantages.

FIG. 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. 4 is a graph showing a relationship between a threshold value, a channel concentration, and a back gate voltage of a fully depleted transistor obtained by the device parameter setting method according to the embodiment. Graph showing the relationship between the silicon film thickness t _Si and the threshold value V _t of the SOI layer of the fully depleted transistor. 9 is a graph showing actual measurement results and theoretical calculation results regarding the film thickness dependence of the threshold of the SOI-MOSFET according to the second embodiment depending on the film thickness of the SOI silicon layer. 9 is a graph showing a region of a back gate voltage that can minimize threshold variation when a channel concentration is constant according to the second embodiment. 9 is a graph showing a region of a back gate voltage in which a variation in threshold can be minimized when a back gate oxide film is fixed according to the second embodiment. FIG. 13 is a schematic process cross-sectional view illustrating a main part manufacturing process according to the third embodiment. FIG. 13 is a schematic process cross-sectional view illustrating a main part manufacturing process according to the third embodiment. FIG. 13 is a schematic process cross-sectional view illustrating a main part manufacturing process according to the third embodiment. FIG. 13 is a schematic process cross-sectional view illustrating a main part manufacturing process according to the third embodiment. FIG. 13 is a schematic process cross-sectional view illustrating a main part manufacturing process according to the third embodiment. FIG. 13 is a schematic process cross-sectional view illustrating a main part manufacturing process according to the third embodiment. FIG. 13 is a schematic process cross-sectional view illustrating a main part manufacturing process according to the third embodiment. FIG. 14 is a schematic sectional view illustrating a modification of FIG. 13.

Explanation of reference numerals

FET1, FET2 Fully depleted transistors
1,1 'support substrate
2 Buried insulating film
3 interlayer insulating film
4 Element isolation area
5,5 'gate sidewall area
6,6 'gate insulating film
7,7 'source / drain region
8,8 'gate electrode
9,10 Back gate contact electrode
11, 12 channel area
13, 14 Back gate electrode
15, 16 channel area
17 First photoresist mask
18, 18 ', 19, 19' back gate electrode
20 Electrode separation area
21 Second photoresist mask
22 Third photoresist mask
23, 23 ', 24, 24' back gate electrode

Claims (3)

Forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer which are insulated and separated from each other on a buried insulating film on a semiconductor substrate of the first conductivity type;
By implanting the second conductivity type impurity twice using the first mask, a first back gate electrode is formed in the semiconductor substrate under the first semiconductor layer, and is formed under the second semiconductor layer. A second back gate electrode has a first impurity region formed below the third and fourth semiconductor layers, and the first to fourth semiconductor layers are first to fourth impurity layers of a second conductivity type. Process and
The second conductive type impurity is ion-implanted using the second mask to increase the second conductive type impurity concentration of the first and fourth impurity layers to the second conductive type impurity of the second and third impurity layers. A step of making the concentration higher than the impurity concentration;
A third back gate electrode is formed in the first impurity region under the third semiconductor layer by ion-implanting the first conductivity type impurity twice using the third mask. A fourth back gate electrode is formed under the layer, and the third and fourth impurity layers are of the first conductivity type, and the impurity concentration of the third impurity layer is higher than the impurity concentration of the fourth impurity layer. Process and
A method of manufacturing a semiconductor device, comprising: forming a semiconductor device on each of the first to fourth impurity layers. 2. The method according to claim 1, wherein the semiconductor device has a channel region, a gate insulating film, and a gate electrode. 2. The method according to claim 1, wherein the first to fourth semiconductor layers have the same thickness.

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