JP2004146847A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a SOI (silicon-on-insulator) element which enables the threshold to be set properly and its high-speed operation to be performed. <P>SOLUTION: In this semiconductor device, a plurality of island-shaped silicon layers are formed as an element region on an insulating layer. The element region includes a plurality of MIS (metal insulator semiconductor) type field-effect transistors, having n type channel provided with gate electrodes 88, 89 consisting of p-type silicon. Ge or Sn, is included in a gate electrode 89 of at least one MIS field-effect transistor among the plurality of MIS field-effect transistors, and Ge or Sn is not included in the gate electrode 88 of the other transistor among the plurality of MIS field-effect transistors. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a MOSFET having a thin film SOI structure and a method for manufacturing the same.

Thin-film SOI (Silicon-On-Insulator) elements, for example, SOI transistors formed on insulating films, have recently attracted attention as devices of the 0.1 μm generation.

薄膜 Since the thin film SOI element is electrically insulated from the underlying semiconductor substrate by the insulating film, it has a great advantage that the parasitic capacitance is small. Further, it is known that there is an advantage such as resistance to soft errors for the same reason.

Further, in the case where the SOI layer is completely depleted due to the thinning of the SOI layer, it is possible to easily achieve an improvement in operation speed, a reduction in power consumption, and an improvement in switching characteristics due to an increase in mobility (mobility). Can be. It is also reported that the reduction in threshold voltage Vth (so-called short channel effect) due to miniaturization of the channel length is smaller than that of a MOSFET formed in a bulk. (Non-Patent Document 1)
Further, in the thin film SOI element of the 0.1 μm generation, low power consumption is indispensable, and the power supply voltage is expected to be about 1V. To achieve this, it is of utmost importance to set the thresholds of the devices appropriately.

However, there is a problem that it is difficult to set a threshold value in a thin film SOI element, which makes circuit design difficult. In order to solve this, in the conventional method, the threshold value is adjusted by increasing the impurity concentration of the channel region. However, this method has a disadvantage that the increase in mobility, which is a major feature of the thin film SOI element, is lost.

On the other hand, in order to suppress power consumption during standby in the thin film SOI element, good subthreshold characteristics are indispensable. Originally, an excellent subthreshold characteristic is expected as a feature of the SOI element. However, when the element is actually manufactured, the subthreshold characteristic is deteriorated.

FIG. 7 shows the IV characteristics of the SOI device manufactured by the present inventors. The horizontal axis is the gate voltage, and the vertical axis is the drain current. A hump is observed in a region where the drain current rises, and an increase in the drain current is confirmed on the low gate voltage side. That is, it is clear that the threshold value of the element is lowered and the subthreshold characteristics are deteriorated.

FIG. 8 is a cross-sectional view of a thin-film SOI device for explaining the deterioration of the subthreshold characteristic. Reference numeral 213 denotes an element isolation region formed by the LOCOS method, and a region 215a having a smaller thickness than the channel region 215 of the original SOI layer is formed below the bird's beak region. 211 is a silicon substrate, 212 is a buried silicon oxide film, and 214 is a gate electrode.

As described above, when the region 215a is formed, a parasitic transistor having a low threshold value exists in this portion, and the threshold value of the entire transistor becomes lower than that of the original transistor due to the operation of the parasitic transistor. . That is, when a gate voltage is applied, a current first flows through the parasitic transistor, and then a current flows through the original transistor.
The hump characteristic shown in FIG. A detailed analysis of this phenomenon is shown in Non-Patent Document 2, for example.
M. Yoshimi et al., IEICE Trans., Vol. E74, p. 337, 1991 IEEE, Transactions on Electron Devices, vol. 39, p. 874, 1992.

As described above, in the conventional thin film SOI element, it is indispensable to adjust the threshold setting for circuit design, and to achieve this, the impurity concentration of the channel is increased. It was difficult to achieve the original ultra-high speed.

Further, it is necessary to achieve good subthreshold characteristics in order to suppress power consumption during standby and the like. However, in the conventional thin-film SOI element, a hump (bump) is observed, and the threshold value of the element is lowered. There is a problem that the subthreshold characteristic is deteriorated.

The present invention has been made in view of the above circumstances, and has as its object to provide a thin-film SOI device in which a threshold can be appropriately set and high-speed operation is possible.

According to the present invention, a plurality of island-shaped silicon layers are formed as an element region on an insulating layer, and the element region includes a plurality of n-channel MIS field effect transistors having a gate electrode made of p-type silicon. The gate electrode of at least one of the plurality of MIS field effect transistors includes Ge or Sn, and the gate electrodes of the other plurality of MIS field effect transistors include Provided is a semiconductor device which does not contain Ge or Sn.

Further, in the present invention, a plurality of island-shaped silicon layers are formed as element regions on an insulating layer, and the element region includes a storage element region in which a plurality of storage elements are formed and a circuit for controlling operation of the storage element. The storage device region and the circuit region each include a formed MIS field-effect transistor of an n-type channel having a gate electrode made of p-type silicon, and the MIS included in the circuit region. Wherein the gate electrode of the field effect transistor includes Ge or Sn, and the gate electrode of the MIS field effect transistor included in the storage element region does not include Ge or Sn. provide.

In the two present inventions, the following embodiments are preferable.
(1) The concentration of Ge or Sn contained in the gate electrode of the MIS field effect transistor is 1 × 10 ²⁰ cm ⁻³ or more.
(2) The silicon layer further includes a p-channel MIS field-effect transistor having a gate electrode made of p-type silicon, and the gate electrode of the MIS field-effect transistor includes Ge or Sn. thing.
(3) The circuit region includes a p-channel MIS field-effect transistor having a gate electrode made of p-type silicon, and the gate electrode of the MIS field-effect transistor includes Ge or Sn.
(4) The concentration of Ge or Sn contained in the gate electrode of the MIS field-effect transistor of the p-type channel is 1 × 10 ²⁰ cm ⁻³ or more.
(5) The source region of the MIS field-effect transistor of the n-type channel contains Ge or Sn.
(6) The concentration of Ge or Sn contained in the source region of the MIS field-effect transistor of the n-type channel is 1 × 10 ²⁰ cm ⁻³ or more.

Further, as a method of manufacturing such a semiconductor device of the present invention, a plurality of island-shaped p-type silicon layers are formed as element regions on an insulating layer, and the element regions are provided with a gate electrode made of p-type silicon. Forming a gate insulating film on the p-type silicon layer, and forming a gate electrode made of p-type silicon on the gate insulating film. Forming a first mask pattern on the conductive film, and selectively introducing Ge or Sn into the conductive film using the first mask pattern; Removing the first mask pattern, forming a second mask pattern on the conductive film, and etching the second mask pattern using Ge or Sn by using the second mask pattern. Processing the introduced conductive film and the conductive film not incorporating these into respective gate electrode shapes, and introducing an n-type impurity into the p-type silicon layer using the second mask pattern to form a source / drain. Forming a region, and a method for manufacturing a semiconductor device.

Furthermore, as another manufacturing method, a semiconductor device in which a storage element region including a plurality of storage elements and a circuit region including a circuit controlling operation of the storage element are formed in a p-type silicon layer formed over an insulating layer Forming a gate insulating film on the p-type silicon layer; forming a conductive film of p-type silicon on the gate insulating film to be a gate electrode; Forming a first mask pattern on the portion to be the storage element region, and selectively introducing Ge or Sn into the portion of the conductive film to be the circuit region using the first mask pattern; Removing the first mask pattern; forming a second mask pattern on the conductive film; and etching the storage element region and the circuit by etching using the second mask pattern. Processing the conductive film in a region into the shape of a gate electrode; and introducing n-type impurities into the p-type silicon layer in the storage element region and the circuit region using the second mask pattern to form a source / drain. Forming a region, and a method for manufacturing a semiconductor device.

In the two present inventions, the step of introducing Ge or Sn may be a step of ion-implanting Ge or Sn such that the peak concentration in the conductive film is 1 × 10 ²⁰ cm ⁻³ or more. preferable.

According to the present invention, the semiconductor device includes a plurality of MIS field-effect transistors of an n-channel having a gate electrode made of p-type silicon, and at least one MIS field-effect transistor of the plurality of MIS field-effect transistors. Since the gate electrode of the MIS-type field effect transistor contains Ge or Sn, and the gate electrodes of the other MIS field-effect transistors do not contain Ge or Sn, the n-type channel whose gate electrode contains Ge or Sn is used. The threshold voltage (Vth) of the MIS field-effect transistor can be made lower than that of the MIS field-effect transistor, and a plurality of MIS field-effect transistors having different Vth can be formed.

In an SOI MOSFET, particularly a fully depleted SOI MOSFET, it is difficult to set Vth to a desired value by changing the impurity concentration of the channel region of the SOI layer. Vth can be controlled depending on whether Ge or Sn is introduced or not, and the problem in circuit design of a fully depleted SOI MOSFET can be overcome.

For example, in a memory cell portion of a dynamic RAM, a MOSFET having a high Vth is required to reduce leakage current, and p-type silicon into which Ge or Sn is not used is used as a gate. On the other hand, in the peripheral circuit section that controls the memory operation, Vt
A MOSFET having a low h is required, and p-type silicon into which Ge or Sn is introduced is used as a gate.

Further, when p-type silicon into which Ge or Sn is introduced is used as the gate electrode of the MIS field-effect transistor of the p-type channel, the Fermi level of the gate approaches the center of the band gap as compared with the case where Ge or Sn is not introduced. . Therefore, the amount of ions implanted into the channel for obtaining an appropriate Vth can be reduced. In addition, the same gate material as the gate of the n-channel MIS field-effect transistor can be used, and the conductivity of the gate can be changed between the conventional n-channel and p-channel MIS field-effect transistors. The manufacturing process can be simplified as compared with the first embodiment.

Also, if Ge or Sn is introduced into the source region, the band gap can be narrowed, thereby effectively accumulating holes in the channel, which is the main cause of the substrate floating effect in the n-type channel SOI MOSFET. Can be prevented.

According to the present invention, it is possible to provide an SOI element in which a threshold can be appropriately set and high-speed operation can be performed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(1st Embodiment)
First, before describing this embodiment, the problems of the thin-film SOI transistor will be described again.

In a thin-film SOI transistor, particularly a fully-depleted SOI MOSFET in which the SOI layer is completely depleted, it is difficult to set Vth to a desired value by changing the impurity concentration of the channel region of the SOI layer, which is a problem in circuit design. Become. The analytical expression of Vth is given by the following expression.

Vth = VFB + 2φB + QB / Cox (1)
Here, VFB is the flat band voltage, φB is the Fermi potential, QB is the surface potential, φs is the amount of charge in the depletion layer at 2φB, and Cox is the capacitance of the gate insulating film.

ＭＯＳＦＥＴ In a MOSFET formed in a normal semiconductor substrate bulk, QB can be controlled by changing the impurity concentration of the channel region to set Vth to a desired value. However, in a fully-depleted SOI MOSFET, it is difficult to control QB because the SOI layer is thin. The analytical expression of QB of the fully depleted SOI MOSFET is given by the following expression.

QB = q × NSOI × TSOI (2)
Here, q is the elementary charge amount, NSOI is the impurity concentration of the channel region of the SOI layer, and TSOI is the thickness of the SOI layer. That is, in the fully depleted SOI MOSFET, since the SOI layer is thin and the TSOI is small, it is difficult to control QB to a desired value by changing the impurity concentration NSOI of the channel region. For this reason, it is difficult to set Vth to a desired value by changing the impurity concentration NSOI of the channel region of the SOI layer.

However, in the LSI circuit design, MOSFETs having different Vths may be required. For example, in a memory cell portion of a dynamic RAM, a MOSFET having a high Vth is required to reduce leakage current, while in a peripheral circuit portion controlling a memory operation, a MOSFET having a low Vth is required for high-speed operation. That is, particularly in a fully depleted SOI MOSFET, it is difficult to set Vth to a desired value by changing the impurity concentration NSOI of the channel region of the SOI layer, which is a problem in circuit design.

According to the invention of this embodiment, a plurality of n-channel MIS field-effect transistors having a gate electrode made of p-type silicon are included, and at least one MIS field-effect transistor of the plurality of MIS field-effect transistors is included. Since the gate electrode of the field effect transistor contains Ge or Sn, and the gate electrodes of the other MIS field effect transistors do not contain Ge or Sn, the gate electrode contains Ge or Sn. The threshold voltage (Vth) of the n-channel MIS field-effect transistor can be lower than that of the n-channel MIS field-effect transistor, so that a plurality of MIS field-effect transistors having different Vth can be formed. it can.

{For example, by introducing Ge into the p-type polycrystalline silicon gate, the band gap is narrowed by 0.3 eV as compared with the case where Ge is not introduced (broken line), as shown by the solid line in the band diagram of FIG. As a result, the work function of the p-type polycrystalline silicon gate changes, and the flat band voltage VFB changes according to the equation of Vth shown in (1). Therefore, a fully depleted SOI MOSFET different in Vth by 0.3 V can be realized depending on whether or not Ge is introduced into the p-type polycrystalline silicon gate.

As described above, in the SOI MOSFET, particularly the fully depleted SOI MOSFET, it is difficult to set Vth to a desired value by changing the impurity concentration of the channel region of the SOI layer. Vth can be controlled depending on whether Ge or Sn is introduced into the silicon gate, and SOI MOSFETs (particularly, fully depleted SOI
MOSFET) circuit design problems can be overcome.

The invention of this embodiment is particularly effective for a semiconductor integrated circuit having a dynamic RAM. For example, in a memory cell portion of a dynamic RAM, a MOSFET having a high Vth is required to reduce leakage current, and p-type silicon into which Ge or Sn is not used is used as a gate. On the other hand, in a peripheral circuit section for controlling a memory operation, a MOSFET having a low Vth is required for high-speed operation, and p-type silicon into which Ge or Sn is introduced is used as a gate.

FIG. 1 is a sectional view showing the structure of an SOI MOSFET of the present invention according to the present embodiment. As a gate of the n-channel SOI MOSFET, a p-type polycrystalline silicon gate 88 into which Ge is not introduced and a p-type polycrystalline silicon gate 89 into which Ge is introduced are formed. The Vth of the SOI MOSFET having the gate 88 into which Ge is not introduced can be increased by 0.3 V as compared with the Vth of the SOI MOSFET having the gate 89 into which Ge is introduced. Therefore, depending on whether or not Ge is introduced into the p-type polycrystalline silicon gate, it becomes possible to realize a fully-depleted SOI MOSFET whose Vth differs by 0.3 V. The above problems can be overcome. Note that such an effect can be obtained even if Sn is used instead of Ge.

FIG. 4 is a process sectional view illustrating the method for manufacturing the thin-film SOI device shown in FIG. 1 are given the same reference numerals. First, a buried oxide film 82 having a thickness of 100 nm is formed on a p-type (100) silicon substrate 81 by a known SIMOX technique. At this time, a single crystal silicon film (hereinafter referred to as an SOI film) is formed on the surface. Next, the SOI film is thinned to 50 nm by thermal oxidation and wet etching using NH ₄ F. Thereafter, an oxide film 83 for element isolation is formed by a known selective oxidation technique to electrically isolate adjacent elements.

Next, BF ₂ ions were applied to the formation region of the n-channel MOSFET at an acceleration voltage of 20 keV,
P-type SOI layers 84 and 85 are formed by ion implantation at a dose of 5 × 10 ¹¹ cm ⁻² . On the other hand, an n-type SOI layer 86 is formed in the formation region of the p-channel MOSFET by ion-implanting As at an acceleration voltage of 40 keV and a dose of 5 × 10 ¹¹ cm ⁻² .

Thereafter, a gate oxide film 87 is formed with a thickness of 7 nm, and polycrystalline silicon 88 doped with phosphorus (P) is deposited with a thickness of 0.3 μm, and then a resist film is formed as shown in FIG. By using 101 as a mask, Ge is ion-implanted at an acceleration voltage of 100 keV and a dose of 3 × 10 ¹⁵ cm ⁻² to form a polycrystalline silicon layer 102 containing Ge. Here, Sn may be ion-implanted instead of Ge to form a polycrystalline silicon layer containing Sn.

Next, after removing the resist film 101, as shown in FIG. 4B, a CVD oxide film is deposited to a thickness of, for example, 0.3 μm, and then a polycrystalline silicon 88 containing no Ge is formed by a well-known patterning technique. The gate electrode 88, the gate electrodes 89 and 90 including Ge, and the oxide films 103, 104 and 105 located on the gate electrodes 88 and 90 by patterning the polycrystalline silicon layer 102 containing To form Further, a resist film 106 is formed on the n-type SOI layer (p-channel MOSFET formation region) 86, and As ions are implanted at an acceleration voltage of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² to form n-type source / drain regions. 92 and 93 are formed.

Next, after the resist film 106 is removed, as shown in FIG. 4C, the formation region of the n-channel MOSFET is masked with the resist film 107, and then BF ₂ ions are accelerated at a voltage of 30 keV and a dose of 5 × 10 5. P-type source / drain regions 91 are formed by ion implantation at ¹⁵ cm ⁻² , and annealing is performed at 850 ° C. for 30 minutes. Then, after forming an interlayer insulating film by a well-known technique, a contact is formed, and a wiring is formed to form an element.

In the present embodiment, since the p-type silicon into which Ge (or Sn) is introduced is used as the gate electrode 90 of the MIS field-effect transistor having the p-type channel, the gate is compared with the case where Ge (or Sn) is not introduced. Fermi level approaches the center of the band gap. Therefore, the amount of ions implanted into the channel for obtaining an appropriate Vth can be reduced. In addition, the same gate material as that of the gate of the MIS field-effect transistor of the n-type channel can be used, and the conductivity of the gate can be changed in the conventional MIS field-effect transistor of the n-type channel and the p-type channel. The manufacturing process can be simplified as compared with the first embodiment.
(Second embodiment)
FIG. 5 is a process sectional view illustrating the method for manufacturing the thin-film SOI device of the present embodiment. 1 are given the same reference numerals.

As shown in FIG. 5, in the As ion implantation for forming the n-type source / drain regions 92 and 93 of the first embodiment of FIG. 4B, Ge is accelerated at a voltage of 30 keV and a dose of 10 ^15. By ion implantation at cm ⁻² , n-type source / drain regions 111 and 112 containing Ge are formed, respectively. Next, a p-type source / drain region is formed by a well-known technique, an interlayer insulating film is formed, a contact is formed, and a wiring is formed to form an element.

The device according to the second embodiment can realize a fully depleted SOI MOSFET whose Vth differs by 0.3 V depending on whether or not Ge is introduced into the p-type polycrystalline silicon gate, as in the first embodiment. Thus, it was possible to overcome a problem in circuit design of a fully depleted SOI MOSFET.

Furthermore, according to the present embodiment, if Ge is introduced into the source region, the band gap can be narrowed, and as a result, a hole in the channel of the hole that is a main cause of the substrate floating effect in the n-type channel SOI MOSFET can be obtained. Accumulation can be effectively prevented. That is, as shown in FIG. 3, when the band gap of the source region becomes narrower (solid line), the energy barrier between the channel and the source decreases, and the hole current flowing into the source increases exponentially with the decrease of the energy barrier. To increase. As a result, holes can be prevented from accumulating in the channel, and the drain breakdown voltage in the off region can be improved by, for example, 1 V or more compared to a normal element in which Ge is not implanted. Note that Sn (tin), which is an atom that narrows the band gap of silicon, may be used instead of Ge, and the above effects can be obtained.
(Third embodiment)
FIG. 6 is a process sectional view illustrating the method for manufacturing the thin-film SOI device of the present embodiment. 1 are given the same reference numerals.

First, similarly to FIG. 4A of the first embodiment, a polycrystalline silicon layer 102 containing Ge is formed, and after removing the resist film 101, polycrystalline silicon containing no Ge is formed by a well-known patterning technique. The gate electrode 88 and the gate electrodes 89 and 90 containing Ge are formed by patterning the polycrystalline silicon layer 102 containing 88 and Ge. Further, as shown in FIG. 6A, a resist film 106 is formed on the n-type SOI layer (p-channel MOSFET formation region) 86, and P is ionized at an acceleration voltage of 30 keV and a dose of 10 ¹³ cm ⁻² . The implantation forms an n-type source / drain region 131 and a lightly doped n-type LDD (lightly doped drain) region 132.

Next, as shown in FIG. 6B, after depositing a CVD oxide film 133 on the entire surface to a thickness of, for example, 0.5 μm, a p-type polysilicon gate electrode containing no Ge is formed by a well-known patterning technique. The formation region of the n-channel MOSFET and the formation region of the p-channel MOSFET having 88 are covered with the CVD oxide film 133. Further, after depositing a CVD nitride film on the entire surface to a thickness of, for example, 0.5 μm, anisotropic etching is performed, and a p-type polycrystalline silicon gate electrode 89 containing Ge of an n-channel MOSFET is formed with a CVD oxide film 134. Cover.

Next, As is ion-implanted at an acceleration voltage of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² , and Ge is ion-implanted at an acceleration voltage of 30 keV and a dose of 10 ¹⁵ cm ⁻² to obtain an n-type source containing Ge. Forming a drain region 135; Thereafter, the CVD oxide film 133 on the formation region of the n-channel MOSFET and the formation region of the p-channel MOSFET having the p-type polysilicon gate electrode 88 not containing Ge is removed by etching. Further, a p-type source / drain region is formed by a well-known technique, an interlayer insulating film is formed, a contact is formed, and a wiring is formed to form an element.

<< The device according to the present embodiment can realize a fully depleted SOI MOSFET whose Vth differs by 0.3 V depending on whether Ge is introduced into the p-type polycrystalline silicon gate, as in the first embodiment. Further, similarly to the second embodiment, in the n-channel MOSFET having the p-type polycrystalline silicon gate electrode 89 containing Ge, Ge is introduced into the n-type source / drain regions, so that Ge is introduced. The drain breakdown voltage in the off region was improved by 1 V as compared with the device in which the source region was formed. Further, in the n-channel MOSFET having the p-type polycrystalline silicon gate electrode 88 containing no Ge, the junction leak current could be reduced because Ge was not introduced into the n-type source / drain region 131. .

In the first to third embodiments, Ge is introduced into the polycrystalline silicon gate by ion implantation, but Ge may be introduced by solid phase diffusion. The above manufacturing steps shown in the second and third embodiments, As, Ge, BF ₂ n-type source and drain regions 92,93,111,112 by ion implantation of ions, and p-type source and drain regions 91 In order to prevent the above ions from entering the gate electrodes 89 and 90 containing Ge and the gate electrode 88 not containing Ge, the CVD oxide film 105 was used as a mask material. As the mask material, a metal silicide film may be used instead of the CVD oxide film 105. If a metal silicide film is used, gate resistance can be reduced, and a high-speed semiconductor device can be realized.

Note that the present invention is not limited to the method of the above-described embodiment. For example, the SOI layer is formed by a SIMOX method in which oxygen ions are implanted into a silicon substrate, but the SOI layer may be formed by monocrystallizing a polycrystalline silicon film on a silicon oxide layer by a laser beam annealing technique. Good. Alternatively, an SOI layer may be formed by bonding silicon substrates together via a silicon oxide film. In addition, various modifications can be made without departing from the spirit of the present invention.

FIG. 2 is a cross-sectional view showing the structure of the thin-film SOI device according to the first embodiment of the present invention. FIG. 4 is a band diagram when Ge is introduced (solid line) and when Ge is not introduced (dashed line). FIG. 3 is a band diagram in the channel direction when Ge is introduced into the source (solid line) and when Ge is not introduced into the source (dashed line). FIG. 2 is a process cross-sectional view illustrating a method for manufacturing the thin-film SOI element of FIG. 1. FIG. 9 is a process cross-sectional view illustrating a method for manufacturing the thin-film SOI device according to the second embodiment of the present invention. FIG. 13 is a process cross-sectional view illustrating the method of manufacturing the thin-film SOI device according to the third embodiment of the present invention. FIG. 9 is a characteristic diagram showing electric characteristics of a conventional thin film SOI element. FIG. 11 is a cross-sectional view illustrating the structure of a conventional thin-film SOI element.

Explanation of reference numerals

88 ... p-type polycrystalline silicon gate not introducing Ge 89 ... p-type polycrystalline silicon gate introducing Ge

Claims (11)

A plurality of island-shaped silicon layers are formed as element regions on the insulating layer, and the element regions include a plurality of n-channel MIS field-effect transistors having a gate electrode made of p-type silicon. The gate electrode of at least one of the MIS field effect transistors includes Ge or Sn, and the gate electrodes of the other plurality of MIS field effect transistors include Ge or Sn. A semiconductor device which is not included. A plurality of island-shaped silicon layers are formed as element regions on an insulating layer, and the element region is a storage region in which a plurality of storage elements are formed and a circuit region in which a circuit for controlling operation of the storage elements is formed. And the storage element region and the circuit region each include an n-channel MIS field-effect transistor having a gate electrode made of p-type silicon, and include a MIS field-effect transistor included in the circuit region. A semiconductor device, wherein the gate electrode contains Ge or Sn, and the gate electrode of the MIS field effect transistor contained in the storage element region does not contain Ge or Sn. 3. The semiconductor device according to claim 1, wherein the concentration of Ge or Sn contained in the gate electrode of the MIS field effect transistor is 1 × 10 ²⁰ cm ⁻³ or more. The silicon layer further includes a p-channel MIS field-effect transistor having a gate electrode made of p-type silicon, and the gate electrode of the MIS field-effect transistor includes Ge or Sn. 3. The semiconductor device according to claim 1, wherein: The circuit region includes a p-channel MIS field-effect transistor having a gate electrode made of p-type silicon, and the gate electrode of the MIS field-effect transistor includes Ge or Sn. The semiconductor device according to claim 2. 6. The semiconductor device according to claim 5, wherein the concentration of Ge or Sn contained in the gate electrode of the p-type MIS field-effect transistor is 1 × 10 ²⁰ cm ⁻³ or more. 3. The semiconductor device according to claim 1, wherein Ge or Sn is contained in a source region of the MIS field-effect transistor having the n-type channel. 8. The semiconductor device according to claim 7, wherein the concentration of Ge or Sn contained in the source region of the n-type MIS field-effect transistor is 1 × 10 ²⁰ cm ⁻³ or more. A plurality of island-shaped p-type silicon layers are formed as element regions on an insulating layer, and the element regions include a plurality of n-channel MIS field-effect transistors having a gate electrode made of p-type silicon. Forming a gate insulating film on the p-type silicon layer; forming a conductive film made of p-type silicon on the gate insulating film to be a gate electrode; Forming a first mask pattern on the conductive film, selectively introducing Ge or Sn into the conductive film using the first mask pattern, removing the first mask pattern, A second mask pattern is formed thereon, and the conductive film to which Ge or Sn is introduced and the conductive film to which Ge or Sn are not introduced are etched by using the second mask pattern. And a step of forming a source / drain region by introducing an n-type impurity into the p-type silicon layer using the second mask pattern. Manufacturing method of a semiconductor device. A method for manufacturing a semiconductor device, comprising: forming, in a p-type silicon layer formed on an insulating layer, a storage element region including a plurality of storage elements and a circuit region including a circuit for controlling operation of the storage element, Forming a gate insulating film on the p-type silicon layer, forming a conductive film made of p-type silicon on the gate insulating film and serving as a gate electrode, Forming a first mask pattern on the substrate, selectively introducing Ge or Sn into a portion of the conductive film to be the circuit region using the first mask pattern, and removing the first mask pattern. Forming a second mask pattern on the conductive film, and using the second mask pattern to etch the conductive film in the storage element region and the circuit region into a gate electrode. And forming a source / drain region by introducing an n-type impurity into the p-type silicon layer in the storage element region and the circuit region using the second mask pattern. A method for manufacturing a semiconductor device, comprising: 11. The method according to claim 9, wherein the step of introducing Ge or Sn is a step of ion-implanting Ge or Sn such that the peak concentration in the conductive film is 1 × 10 ²⁰ cm ⁻³ or more. The manufacturing method of the semiconductor device described in the above.

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