JP2004004904A - Correction method for figure pattern for semiconductor device, and manufacturing method for the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a correction method for a figure pattern for a semiconductor device and a manufacturing method for a semiconductor device, which can suppress increase in chip area, while resolving the hindrance of securing of gate extruding amount which is brought about by a corner-rounding phenomenon at miniaturization. <P>SOLUTION: This correction method for a figure pattern for a semiconductor device, which does not influence the concave-shaped diffused layer corresponding part of a figure pattern for a semiconductor device, and another pattern that exists near a gate includes a process 102, which detects the concave-shaped diffused layer corresponding part, and a process 103 which corrects the concave-shaped diffused layer corresponding part or a transistor gate corresponding part, which protrudes from the concave-shaped diffused layer corresponding part, so as to secure projection of the gate from the concave-shaped diffused layer corresponding part with respect to the corner-rounding phenomenon. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for correcting a figure pattern for a semiconductor device and a method for manufacturing a semiconductor device, which deform a figure pattern for a mask used for manufacturing a semiconductor device or the like in advance so that a transfer image close to a desired design pattern is obtained. It is about.
[0002]
[Prior art]
2. Description of the Related Art In manufacturing a current semiconductor device or the like, a photolithography process of transferring a mask graphic pattern of a semiconductor device to a resist material on a semiconductor substrate using an exposure light source is an essential process. In recent years, the miniaturization of semiconductor manufacturing processes has been progressing at a pace faster than the reduction of the wavelength of the light source for exposure. As a result, a situation in which a photolithography process for transferring a dimension equal to or smaller than the wavelength of the exposure light source has to be performed has been forced. This causes a problem of a difference between the designed mask graphic pattern and the transferred graphic pattern.
[0003]
One of the phenomena of such a difference is corner rounding. Due to this phenomenon, the concavo-convex shape designed as a mask figure pattern recedes after transfer. If these occur in the convex gate portion of the transistor or the concave diffusion layer portion where the gate protrudes, it hinders securing the amount of protrusion of the gate from the diffusion layer. This causes conduction between the source and the drain of the transistor, which leads to an increase in the current of the power supply as a semiconductor product, and in the worst case, an operation failure. Of course, as a semiconductor product, measures must be taken to prevent these.
[0004]
An example of a countermeasure against the hindrance of securing the gate protrusion amount caused by the corner rounding phenomenon, which has been conventionally performed, will be described with reference to the drawings. FIGS. 21 and 22 show an example in which no countermeasures are taken to prevent the gate protrusion amount from being secured. In the mask figure pattern shown in FIG. 21, the transistor gate 511 protrudes from the diffusion layer 513, but no countermeasures are taken against obstruction of securing the gate protrusion amount after transfer due to the corner rounding phenomenon. Therefore, another pattern 512 can be arranged. However, in the post-transfer mask figure pattern shown in FIG. 22, there is a problem that the gate protrusion recedes due to the corner rounding phenomenon and the source and drain of the diffusion layer are short-circuited.
[0005]
FIG. 23 and FIG. 24 show an example of a conventional countermeasure for preventing the gate protrusion amount from being secured. As a conventional countermeasure shown in FIG. 23, as a countermeasure, a point where it is likely that the protrusion amount of the gate after transfer is likely to be impaired due to the corner rounding phenomenon is detected in the mask figure pattern design stage, and the gate protrusion amount is increased on the mask figure pattern. Was given. Therefore, in the mask figure pattern after transfer shown in FIG. 24, an appropriate gate protrusion amount is ensured even after the gate protrusion has receded due to the corner rounding phenomenon.
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional configuration, since the amount of gate protrusion is increased on the mask graphic pattern, other patterns 512 cannot be arranged in the increased space. In other words, the other patterns 512 in FIG. 21 that could be arranged when no countermeasures against obstruction of securing the gate protrusion amount were taken are eliminated in FIG. 23 after the countermeasures. This is an obstacle to effectively utilizing the space and keeping the chip area small.
[0007]
On the other hand, the size of the chip area is the largest factor that determines the chip cost, and can be said to be the most important in developing a competitive chip. The present invention solves the above-mentioned conventional problems, and solves the problem of securing the gate protrusion amount caused by the corner rounding phenomenon at the time of miniaturization, while suppressing the increase in the chip area while suppressing the increase in the chip area. It is an object of the present invention to provide a method for correcting the above and a method for manufacturing a semiconductor device.
[0008]
[Means for Solving the Problems]
The method for correcting a graphic pattern for a semiconductor device according to claim 1 is a method for correcting a graphic pattern for a semiconductor device that does not affect a portion corresponding to a concave diffusion layer of the graphic pattern for a semiconductor device and another pattern existing near a gate. A step of detecting a portion corresponding to the concave diffusion layer, and a portion corresponding to the concave diffusion layer and the concave diffusion layer so as to secure the protrusion of the gate from the portion corresponding to the concave diffusion layer against the corner rounding phenomenon. Correcting at least one of the transistor gate equivalent parts protruding from the corresponding part.
[0009]
According to the method of correcting a graphic pattern for a semiconductor device according to claim 1, in order to eliminate the obstruction of securing the amount of gate protrusion caused by the corner rounding phenomenon, a portion corresponding to a concave diffusion layer on a mask graphic pattern for a semiconductor device. In the portion corresponding to the transistor gate projecting from the above, the reduction correction of the diffusion layer or the enlargement correction of the transistor gate has been performed, thereby eliminating the obstruction of securing the gate protrusion amount caused by the corner rounding phenomenon occurring after the photolithography process. be able to.
[0010]
Moreover, in order to solve this problem, the problem of increasing the chip area, which has conventionally occurred, is not caused, so that it can greatly contribute to the development of a competitive chip. In addition, by taking measures that focus on the inhibition of securing the gate protrusion amount, adverse effects such as an increase in the amount of data caused by the solution are minimized, and the problem in mask fabrication does not occur.
[0011]
According to a second aspect of the present invention, there is provided a method of correcting a graphic pattern for a semiconductor device according to the first aspect, wherein the step of correcting the portion corresponding to the concave diffusion layer performs reduction correction on the bottom side of the concave portion. It includes a logical operation step. According to the method for correcting a graphic pattern for a semiconductor device according to the second aspect, the same effect as that of the first aspect can be obtained.
[0012]
According to a third aspect of the present invention, there is provided the method of correcting a figure pattern for a semiconductor device according to the first aspect, wherein the step of correcting the portion corresponding to the concave diffusion layer is performed at a position near the both ends of the bottom of the concave portion and the bottom adjacent to the bottom. On the other hand, reduction correction is performed, and includes a graphic pattern correcting step and a logical operation of the graphic pattern. According to the third aspect of the present invention, there is provided the same effect as that of the first aspect.
[0013]
According to a fourth aspect of the present invention, in the method for correcting a figure pattern for a semiconductor device according to the first aspect, the step of correcting the transistor gate protruding from the portion corresponding to the concave diffusion layer includes the step of correcting the edge of the side adjacent to the edge of the transistor gate. The enlargement correction is performed on the vicinity of both ends of the side, and includes a deviation measurement step of two types of graphic patterns, a correction step of the graphic patterns, and a logical operation step of the graphic patterns.
[0014]
According to the method for correcting a graphic pattern for a semiconductor device according to the fourth aspect, the same effect as that of the first aspect is obtained. According to a fifth aspect of the present invention, in the method for correcting a figure pattern for a semiconductor device according to the first aspect, the step of correcting the transistor gate equivalent portion protruding from the concave diffusion layer equivalent portion includes the steps of: Enlargement correction is performed on the vicinity of both ends of an edge adjacent to the edge of the gate equivalent portion. The two types of figure pattern shift measurement step, the figure pattern side movement step, and the figure pattern correction step And a logic operation step of the graphic pattern.
[0015]
According to the fifth aspect of the present invention, there is provided an effect similar to that of the first aspect.
[0016]
According to a sixth aspect of the present invention, there is provided a method of correcting a semiconductor device graphic pattern according to the first aspect, wherein at least a portion corresponding to a concave diffusion layer or a portion corresponding to a transistor gate protruding from a portion corresponding to a concave diffusion layer. And a corrected photography step.
[0017]
According to the method of manufacturing a semiconductor device of the sixth aspect, the same effect as that of the first aspect is obtained.
[0018]
According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including a photographing step in which a bottom side of a concave portion is reduced and corrected by the method of correcting a figure pattern for a semiconductor device according to the second aspect.
[0019]
According to the method of manufacturing a semiconductor device according to the seventh aspect, the same effect as that of the first aspect is obtained.
[0020]
According to a eighth aspect of the present invention, there is provided a method of correcting a semiconductor device graphic pattern according to the third aspect, wherein the photo is reduced and corrected for the vicinity of both ends of the bottom of the concave portion and the bottom adjacent to the bottom. It includes a graphic process.
[0021]
According to the method of manufacturing a semiconductor device according to the eighth aspect, the same effect as that of the first aspect is obtained.
[0022]
According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fourth aspect, comprising the step of correcting a pattern adjacent to an edge of a transistor gate corresponding portion protruding from a concave diffusion layer corresponding portion. This includes a photographing process in which enlargement correction is performed on the vicinity of both ends of the edge.
[0023]
According to the method of manufacturing a semiconductor device of the ninth aspect, the same effect as that of the first aspect is obtained.
[0024]
According to a tenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the fifth aspect, wherein the edge of the transistor gate equivalent portion protruding from the concave diffusion layer equivalent portion and the transistor gate equivalent portion are formed by the semiconductor device graphic pattern correcting method. This includes a photography process in which enlargement correction is performed on the vicinity of both ends of the side of the side adjacent to the side.
[0025]
According to the method of manufacturing a semiconductor device of the tenth aspect, the same effect as that of the first aspect is obtained.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 shows a process of correcting a mask figure pattern for a semiconductor device according to the first embodiment of the present invention.
[0027]
The mask graphic pattern 101 shown in FIG. 1 is input to the concave diffusion layer detecting step 102, and thereafter, optical proximity effect correction (hereinafter referred to as Optical Proximity) for correcting the difference between the designed mask graphic pattern and the transferred graphic pattern. Through an OPC step 103 for performing a correction (abbreviated as OPC), a post-OPC mask figure pattern 104 is output.
[0028]
FIG. 2 is a detailed description of the concave diffusion layer detection step 102. As shown in FIG. 2, an edge moving step (reduction) 201, a correction step (reduction) 202, a logical operation step (subtraction) 203, and an interval measurement step 204 are performed on the diffusion layer graphic pattern, and a concave diffusion layer is formed. To detect. This constitutes a method for extracting a concave pattern figure applied to the concave diffusion layer detecting step 102.
[0029]
3A is subjected to a side movement of a predetermined amount A in a side moving step (reduction) 201, and the figure pattern shown in FIG. 3B is output. The diffusion layer graphic pattern is corrected (reduced) by a predetermined amount A in a correction step (reduction) 202, and the graphic pattern shown in FIG. 3C is output. The graphic patterns of FIGS. 3B and 3C are subjected to a logical operation (subtraction) in a logical operation step (subtraction) 203, and the graphic pattern of FIG. 3D is output. The graphic pattern shown in FIG. 3D is subjected to an interval measurement in the interval measuring step 204, and the graphic pattern shown in FIG. The graphic pattern shown in FIG. 3E is a detection result of the concave diffusion layer.
[0030]
FIG. 4 shows a logical operation step 301 which is a detailed step of the OPC step 103 in the first embodiment of the present invention. In the logical operation step (subtraction) 301, the diffusion layer graphic pattern shown in FIG. 5A is subjected to a logical operation (subtraction) with the graphic pattern shown in FIG. And the graphic pattern shown in FIG. 5C is output.
[0031]
Note that the correction amount in the OPC step 103 can be controlled by changing the predetermined amount A used in the side moving step (reduction) 201 and the correction step (reduction) 202. 6 and 7 show graphic patterns corrected by the method for correcting a mask graphic pattern for a semiconductor device according to the first embodiment of the present invention. Numeral 1 denotes a portion corresponding to a concave diffusion layer, 2 denotes a gate, and 3 denotes another pattern.
[0032]
After the transfer, the corrected mask figure pattern for a semiconductor device shown in FIG. 6 becomes a figure pattern in which a gate protrusion amount can be secured and other patterns 3 can be arranged as shown in FIG. Therefore, by manufacturing a semiconductor device by a photolithography process using the corrected semiconductor device mask figure pattern, it is possible to eliminate the obstruction of securing the gate protrusion amount caused by the corner rounding phenomenon occurring after the photolithography process.
[0033]
Moreover, in order to solve this problem, the problem of increasing the chip area, which has conventionally occurred, is not caused, so that it can greatly contribute to the development of a competitive chip. In addition, by taking measures that focus on the inhibition of securing the gate protrusion amount, adverse effects such as an increase in the amount of data caused by the solution are minimized, and the problem in mask fabrication does not occur.
[0034]
(Embodiment 2)
FIG. 8 shows a part of a method of correcting a mask figure pattern for a semiconductor device according to the second embodiment of the present invention. The second embodiment can be realized by replacing the OPC process 103 of the first embodiment with the OPC process shown in FIG. The graphic pattern shown in FIG. 3D generated in the concave diffusion layer detection step 102 is corrected (enlarged) by a predetermined amount C in a correction step (enlargement) 401 shown in FIG. The graphic pattern shown in b) is output. Further, in a logical operation step (subtraction) 402, a logical operation (subtraction) is performed between the graphic pattern shown in FIG. 9A and the graphic pattern shown in FIG. 9B, and the graphic pattern shown in FIG. The pattern is output.
[0035]
Note that the amount of correction in the OPC process 103 can be controlled by changing the predetermined amount C used in the correction process (enlargement) 401. FIGS. 10 and 11 show graphic patterns corrected by the semiconductor device mask graphic pattern correction method according to the second embodiment. After the transfer, the corrected semiconductor device mask figure pattern shown in FIG. 10 becomes a figure pattern in which a gate protrusion amount can be secured and other patterns 3 can be arranged as shown in FIG.
[0036]
(Embodiment 3)
FIG. 12 shows a part of a method of correcting a mask figure pattern for a semiconductor device according to the third embodiment of the present invention. The third embodiment can be realized by replacing the OPC process 103 of the first embodiment with the OPC process shown in FIG. The deviation pattern between the diffusion layer graphic pattern and the transistor gate graphic pattern shown in FIG. 13A is measured in a deviation measuring step 501, and the figure pattern shown in FIG. Is output. Further, the graphic pattern shown in FIG. 13A is corrected (enlarged) by a predetermined amount E in a correction step (enlargement) 502, and the graphic pattern shown in FIG. 13B is output. The graphic pattern shown in FIG. 13A is corrected (enlarged) by a predetermined amount F in a correction step (enlargement) 502, and the graphic pattern shown in FIG. 13C is output. Next, in a logical operation step (integration) 503, a logical operation step (integration) 503 of the graphic pattern shown in FIG. 13B and the transistor gate graphic pattern shown in FIG. The graphic pattern shown in (d) is output. Further, in a logical operation step (integration) 503, a logical operation step (integration) of the figure pattern shown in FIG. 13C and the figure pattern of the transistor gate shown in FIG. ) Is output. Then, in a logical operation step (subtraction) 504, a logical operation step (subtraction) is performed on the graphic pattern shown in FIG. 13D and the graphic pattern shown in FIG. A graphic pattern is output. The graphic pattern shown in FIG. 13F is subjected to a predetermined amount of G correction (expansion) in a correction step (enlargement) 505, and the graphic pattern shown in FIG. Finally, in a logical operation step (summing) 506, a logical operation (summing) is performed between the figure pattern shown in FIG. 13G and the figure pattern of the transistor gate shown in FIG. The graphic pattern shown in (h) is output.
[0037]
The predetermined amount D used for the deviation measuring step 501, the predetermined amount E used for the correction step (enlargement) 502, the predetermined amount F used for the correction step (enlargement) 502, and the predetermined amount G used for the correction step (enlargement) 505 vary. By doing so, the amount of correction in the OPC step 103 can be controlled. 14 and 15 are graphic patterns corrected by the semiconductor device mask graphic pattern correction method according to the third embodiment.
[0038]
After the transfer, the corrected semiconductor device mask figure pattern shown in FIG. 14 becomes a figure pattern in which a gate protrusion amount can be secured and other patterns 3 can be arranged as shown in FIG.
(Embodiment 4)
FIG. 16 shows a part of a method of correcting a mask figure pattern for a semiconductor device according to the fourth embodiment of the present invention. The fourth embodiment can be realized by replacing the OPC process 103 of the first embodiment with the OPC process shown in FIG.
[0039]
The transistor gate graphic pattern shown in FIG. 17A is subjected to side movement (enlargement) by a predetermined amount H in a side movement step (enlargement) 601 to output the graphic pattern shown in FIG. 17B. The transistor gate graphic pattern shown in FIG. 17A is corrected (enlarged) by a predetermined amount H in a correction step (enlargement), and the graphic pattern shown in FIG. 17C is output. Next, in a logical operation step (subtraction) 603, a logical operation (subtraction) is performed between the graphic pattern shown in FIG. 17B and the graphic pattern shown in FIG. The pattern is output. Further, in the logical operation step (integration) 604, the correction amount in the correction step (enlargement) is set to a predetermined amount H in the same procedure as the deviation measurement step 501 and the correction step (enlargement) 502 in FIG. A logical operation (integration) of the graphic pattern shown in FIG. 17E and the graphic pattern shown in FIG. 17D is performed, and the graphic pattern shown in FIG. 17F is output. Further, the graphic pattern shown in FIG. 17F is subjected to correction (enlargement) by a predetermined amount I in a correction step (enlargement) 605, and the graphic pattern shown in FIG. Finally, in a logical operation step (summing) 606, a logical operation (summing) is performed between the figure pattern shown in FIG. 17G and the figure pattern of the transistor gate shown in FIG. The graphic pattern shown in (h) is output.
[0040]
Note that the predetermined amount H used in the side moving step 601, the predetermined amount H used in the correction step (enlargement) 602, the predetermined amount H used when generating FIG. 605, and the predetermined amount I used in the correction step (enlargement) 605 vary. By doing so, the amount of correction in the OPC step 103 can be controlled. FIGS. 18 and 19 show graphic patterns corrected by the semiconductor device mask graphic pattern correction method according to the fourth embodiment of the present invention.
[0041]
After the transfer, the corrected figure pattern of the semiconductor device mask shown in FIG. 18 becomes a figure pattern in which a gate protrusion amount can be secured and other patterns 3 can be arranged as shown in FIG. In the pattern graphic extracting method according to the present invention, the side moving (reducing) step and the correcting (reducing) step in the concave diffusion layer detecting step are changed to a side moving (enlarging) step and a correcting (enlarging) step. Thus, it can be applied as a step of detecting a convex shape.
[0042]
FIG. 20 shows a method of extracting a convex figure pattern corresponding to FIG. 20 (a) is a convex figure pattern, FIG. 20 (b) is a figure pattern subjected to side movement in a side movement (enlargement) step, and FIG. 20 (c) is correction in a correction (enlargement) step. FIG. 20 (d) is a figure pattern obtained by performing a logical (subtraction) operation of the figure patterns of FIG. 20 (b) and FIG. 20 (c), and FIG. This is a graphic pattern that has been measured and is output at locations at intervals equal to or less than a predetermined amount, and is a detection result of the graphic pattern.
[0043]
In the present invention, not only one of the concave diffusion layer equivalent portion and the transistor gate equivalent portion protruding from the concave diffusion layer equivalent portion is corrected but also, for example, from the first embodiment to the fourth embodiment. The step of correcting both of them may be performed by combining any of the embodiments.
[0044]
【The invention's effect】
According to the method of correcting a graphic pattern for a semiconductor device according to claim 1, in order to eliminate the obstruction of securing the amount of gate protrusion caused by the corner rounding phenomenon, a portion corresponding to a concave diffusion layer on a mask graphic pattern for a semiconductor device. In the portion corresponding to the transistor gate projecting from the above, the reduction correction of the diffusion layer or the enlargement correction of the transistor gate has been performed, thereby eliminating the obstruction of securing the gate protrusion amount caused by the corner rounding phenomenon occurring after the photolithography process. be able to.
[0045]
Moreover, in order to solve this problem, the problem of increasing the chip area, which has conventionally occurred, is not caused, so that it can greatly contribute to the development of a competitive chip. In addition, by taking measures that focus on the inhibition of securing the gate protrusion amount, adverse effects such as an increase in the amount of data caused by the solution are minimized, and the problem in mask fabrication does not occur.
[0046]
According to the method for correcting a graphic pattern for a semiconductor device according to the second aspect, the same effect as that of the first aspect can be obtained.
[0047]
According to the third aspect of the present invention, there is provided the same effect as that of the first aspect.
[0048]
According to the method for correcting a graphic pattern for a semiconductor device according to the fourth aspect, the same effect as that of the first aspect is obtained.
[0049]
According to the fifth aspect of the present invention, there is provided an effect similar to that of the first aspect.
[0050]
According to the method of manufacturing a semiconductor device according to the sixth to tenth aspects, the same effect as the first aspect is obtained.
[Brief description of the drawings]
FIG. 1 is a process chart for correcting a mask figure pattern for a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a detailed process diagram of a concave diffusion layer detection process 102;
3A is a diagram illustrating a diffusion layer pattern according to the first embodiment, FIG. 3B is a pattern after movement (reduction) of a side, FIG. 3C is a pattern after correction (reduction), and FIG. ) Is a figure pattern after a logical operation (subtraction), and (e) is a diffusion layer figure pattern of a detection result.
FIG. 4 is a detailed process diagram of an OPC process 103 of FIG. 1 in the first embodiment.
5A is a diagram illustrating a diffusion layer pattern according to the first embodiment, FIG. 5B is a diagram after a concave diffusion layer is detected, and FIG. 5C is a diagram after OPC.
FIG. 6 is an OPC graphic pattern according to the first embodiment.
FIG. 7 is a graphic pattern after OPC transfer according to the first embodiment;
FIG. 8 is a partial process diagram of a method of correcting a mask figure pattern for a semiconductor device according to a second embodiment of the present invention.
9A is a diagram illustrating a diffusion layer pattern in the second embodiment, FIG. 9B is a figure after correction (enlargement), and FIG. 9C is a figure after OPC.
FIG. 10 is an OPC graphic pattern according to the second embodiment.
FIG. 11 is a graphic pattern after OPC transfer according to the second embodiment. .
FIG. 12 is a partial process diagram of a method of correcting a mask figure pattern for a semiconductor device according to a third embodiment of the present invention.
13A is a figure pattern after displacement measurement in the third embodiment, FIG. 13B is a figure pattern after correction (enlargement), FIG. 13C is a figure pattern after correction (enlargement), and FIG. ) Is a figure pattern after logical operation (integration), (e) is a figure pattern after logical operation (integration), (f) is a figure pattern after logical operation (subtraction), and (g) is a figure pattern after correction (enlargement). The graphic pattern (h) is a graphic pattern after a logical operation (summation).
FIG. 14 is an OPC graphic pattern according to the third embodiment.
FIG. 15 shows a graphic pattern after OPC transfer according to the third embodiment.
FIG. 16 is a partial process diagram of a method of correcting a mask figure pattern for a semiconductor device according to a fourth embodiment of the present invention.
17A is a diagram illustrating a transistor gate pattern pattern according to the fourth embodiment, FIG. 17B is a diagram pattern after edge movement (enlargement), FIG. 17C is a diagram pattern after correction (enlargement), and FIG. ) Is the figure pattern after the logical operation (subtraction), (e) is the figure pattern after the correction (enlargement), (f) is the figure pattern after the logical operation (subtraction), and (g) is the figure after the correction (enlargement) The pattern (h) is a figure pattern after a logical operation (summation).
FIG. 18 is an OPC graphic pattern according to the fourth embodiment.
FIG. 19 is a graphic pattern after OPC transfer according to the fourth embodiment.
20A and 20B show a graphic extraction method of a convex graphic pattern in a detection step corresponding to FIG. 3, wherein FIG. 20A is a convex graphic pattern, FIG. 20B is a graphic pattern after moving (enlarging) a side, and FIG. ) Is a figure pattern after correction (enlargement), (d) is a figure pattern after logical operation (subtraction), and (e) is a diffusion layer figure pattern as a detection result.
FIG. 21 shows a graphic pattern in a conventional example.
FIG. 22 is a graphic pattern after transfer in a conventional example.
FIG. 23 is a diagram showing a conventional pattern for taking measures to ensure the amount of protrusion of a transistor gate.
FIG. 24 is a diagram showing a conventional pattern for taking measures to ensure the amount of protrusion of a transistor gate after transfer.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Diffusion layer equivalent part 2 Gate equivalent part 3 Other pattern 101 Mask figure pattern 102 Concave diffusion layer detection step 103 OPC step 104 Post OPC mask figure pattern 201 Side moving step (reduction)
202 Correction process (reduction)
203 Logical operation process (subtraction)
204 Interval measurement step 301 Logical operation step (subtraction)
401 Correction process (enlarge)
402 Logical operation step (subtraction)
501 Shift measurement process 502 Correction process (enlargement)
503 Logical operation process (integration)
504 logical operation process (subtraction)
505 Correction process (enlarge)
506 Logical operation process (summing)
601 Side moving process (enlarge)
602 Correction process (enlarge)
603 Logical operation step (subtraction)
604 Logical operation process (integration)
605 Correction process (enlarge)
606 Logical operation process (summing)
511 transistor gate 512 other pattern 513 diffusion layer

Claims (10)

A method of correcting a figure pattern for a semiconductor device which does not affect a concave diffusion layer equivalent part of a figure pattern for a semiconductor device and another pattern present near a gate, wherein the step of detecting the part corresponding to the concave diffusion layer is provided. A recessed diffusion layer-equivalent portion and a transistor gate equivalent portion projecting from the concave-shaped diffusion layer-equivalent portion so as to secure the projection of the gate from the concave diffusion layer-equivalent portion against a corner rounding phenomenon. Correcting a figure pattern for a semiconductor device. 2. The method according to claim 1, wherein the step of correcting the portion corresponding to the concave diffusion layer performs a reduction correction on the bottom of the concave portion, and includes a logical operation step of the graphic pattern. The step of correcting the portion corresponding to the concave diffusion layer is a step of performing reduction correction on the base of the concave portion and the vicinity of both ends of the base adjacent to the base. 2. The method according to claim 1, further comprising a logical operation step. The step of correcting the transistor gate protruding from the portion corresponding to the concave diffusion layer performs enlargement correction on the vicinity of both ends of the edge adjacent to the edge of the transistor gate. 2. The method for correcting a figure pattern for a semiconductor device according to claim 1, further comprising a step of measuring a pattern shift, a step of correcting a figure pattern, and a step of performing a logical operation of the figure pattern. The step of correcting the transistor gate equivalent portion protruding from the concave diffusion layer equivalent portion is performed near the both ends of the edge adjacent to the edge of the transistor gate equivalent portion and the edge adjacent to the edge of the transistor gate equivalent portion. 2. The semiconductor device according to claim 1, wherein enlargement correction is performed, and the method includes a step of measuring a shift of two types of graphic patterns, a step of moving the sides of the graphic patterns, a step of correcting the graphic patterns, and a step of performing a logical operation of the graphic patterns. A method of correcting a figure pattern for a device. 2. A photographing step in which at least one of a concave diffusion layer equivalent part and a transistor gate equivalent part protruding from the concave diffusion layer equivalent part is corrected by the method for correcting a graphic pattern for a semiconductor device according to claim 1. And a method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device, comprising: a photography step of reducing and correcting a bottom of a concave portion by the method for correcting a graphic pattern for a semiconductor device according to claim 2. 4. A method for manufacturing a semiconductor device, comprising: a photographing process in which a reduction process is performed on the bottom of a concave portion and the vicinity of both ends of the bottom adjacent to the bottom by the method of correcting a figure pattern for a semiconductor device according to claim 3. In the method for correcting a figure pattern for a semiconductor device according to claim 4, enlargement correction is performed on the vicinity of both ends of the edge adjacent to the edge of the transistor gate equivalent portion projecting from the concave diffusion layer equivalent portion. A method for manufacturing a semiconductor device including a photography step. 6. The method according to claim 5, wherein the edge of the transistor gate corresponding portion protruding from the concave diffusion layer corresponding portion and the edge adjacent to the transistor gate corresponding portion are adjacent. A method of manufacturing a semiconductor device including a photography process in which enlargement correction is performed on the vicinity of both ends.

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